From patchwork Wed Jun 4 00:15:13 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 894026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 54E842C3251; Wed, 4 Jun 2025 00:18:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748996284; cv=none; b=C+M0H+dVTqzDNOJAwUamUQ+LHs7F/q6nf9A8Kn9RswU3uXro5zQGGBh10cZLqFImGGcL6lRggx8eOuZS42jQKqQbz+SW6xUTMc5spXuJr1r44XTWSz2W9iBss4P7Y3/VbGm9Ja4WiqkNclOAaO6EV6fdoT+4nrqqsFqugqtbGgM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748996284; c=relaxed/simple; bh=WlIPLmc/FFq62iCagksYCp6qUw2SVgS1XlRC8UQ86RY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=sKyuxoiVc1gPnhbA8BF8hsxsawgHMc4wfZ6/G+bv6GkG9XpyiCAMj/SLpnqzZkkiiT5Y627bcaNqhof24piPDVWPsLgaDxLVEOsxyqVq6pa6f8eWgfFJ4M0o0gENgubwvY+6Cj7nK+e9vgPuyOlQoiuifuuwGB9FLfJ+gy0qlmg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=OjQ+g6WJ; arc=none smtp.client-ip=198.175.65.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="OjQ+g6WJ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1748996283; x=1780532283; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=WlIPLmc/FFq62iCagksYCp6qUw2SVgS1XlRC8UQ86RY=; b=OjQ+g6WJBQCa9ERHE2/SiWMwYo2BG1zBVjbmzVCp0b+BMe++NJxY4mlv smFnycGz/oGGX2Fvnz8CeCStZ2zPIiagZEVeR93dNNChm/up74ns85Vi8 5Aqqw/dhWh3tRokmUj/2Wgc11PeHarBjf9I6abl37EIlGth1x4xR3yjX2 f/S8H3mfJybjjjNZt2AG10qrxvIQQ+OgtCxvbn8BTc0ZNVkA0/dcTg4kU u76Dro0JYD2AQj9TFf3T8a/opJnxFf6oluXM2y5v7U0v/jGMxCdkhO0cz p0h1uce0rQBeNE8GLhPGi3xkMMG8IPH1MOUnY57Ua+Jsnz0aBx5ko67lq A==; X-CSE-ConnectionGUID: plUX8MMAQ4a6KsMt258sew== X-CSE-MsgGUID: E6Q0aKIMRa2EgP7VvPWeqw== X-IronPort-AV: E=McAfee;i="6700,10204,11453"; a="62112927" X-IronPort-AV: E=Sophos;i="6.16,207,1744095600"; d="scan'208";a="62112927" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2025 17:18:01 -0700 X-CSE-ConnectionGUID: Zq9LiRrKR3O6C1R9Li/Tcw== X-CSE-MsgGUID: bFGiFZfiSz6RUM6oQ5bwdA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,207,1744095600"; d="scan'208";a="149904451" Received: from unknown (HELO [172.25.112.21]) ([172.25.112.21]) by fmviesa005.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2025 17:18:00 -0700 From: Ricardo Neri Date: Tue, 03 Jun 2025 17:15:13 -0700 Subject: [PATCH v4 01/10] x86/acpi: Add a helper functions to setup and access the wakeup mailbox Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250603-rneri-wakeup-mailbox-v4-1-d533272b7232@linux.intel.com> References: <20250603-rneri-wakeup-mailbox-v4-0-d533272b7232@linux.intel.com> In-Reply-To: <20250603-rneri-wakeup-mailbox-v4-0-d533272b7232@linux.intel.com> To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley , "Rafael J. Wysocki" Cc: Saurabh Sengar , Chris Oo , "Kirill A. Shutemov" , linux-hyperv@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, "Ravi V. Shankar" , Ricardo Neri , Ricardo Neri X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748996287; l=3940; i=ricardo.neri-calderon@linux.intel.com; s=20250602; h=from:subject:message-id; bh=WlIPLmc/FFq62iCagksYCp6qUw2SVgS1XlRC8UQ86RY=; b=OSOBVCV+0Em4QTXbhjXb/J+EoNF3QP2p8VNGT+Z1LJIjU5aqld4VELjoZBgn0IIhZe3X1dnhU RLgOMPg89OeB0PxRnPZNQq4Rn4RhHYRc1rNAB9P0ffvz9luLB5rKlNx X-Developer-Key: i=ricardo.neri-calderon@linux.intel.com; a=ed25519; pk=NfZw5SyQ2lxVfmNMaMR6KUj3+0OhcwDPyRzFDH9gY2w= In preparation to move the functionality to wake secondary CPUs up out of the ACPI code, add two helper functions. The function acpi_setup_mp_wakeup_mailbox() stores the physical address of the mailbox and updates the wakeup_secondary_cpu_64() APIC callback. There is a slight change in behavior: now the APIC callback is updated before configuring CPU hotplug offline behavior. This is fine as the APIC callback continues to be updated unconditionally, regardless of the restriction on CPU offlining. The function acpi_madt_multiproc_wakeup_mailbox() returns a pointer to the mailbox. Use this helper function only in the portions of the code for which the variable acpi_mp_wake_mailbox will be out of scope once it is relocated out of the ACPI directory. The wakeup mailbox is only supported for CONFIG_X86_64 and needed only with CONFIG_SMP=y. Signed-off-by: Ricardo Neri --- Changes since v3: - Squashed the two first patches of the series into one, both introduce helper functions. (Rafael) - Renamed setup_mp_wakeup_mailbox() as acpi_setup_mp_wakeup_mailbox(). (Rafael) - Dropped the function prototype for !CONFIG_X86_64. (Rafael) Changes since v2: - Introduced this patch. Changes since v1: - N/A --- arch/x86/include/asm/smp.h | 3 +++ arch/x86/kernel/acpi/madt_wakeup.c | 20 +++++++++++++++----- 2 files changed, 18 insertions(+), 5 deletions(-) diff --git a/arch/x86/include/asm/smp.h b/arch/x86/include/asm/smp.h index 0c1c68039d6f..77dce560a70a 100644 --- a/arch/x86/include/asm/smp.h +++ b/arch/x86/include/asm/smp.h @@ -146,6 +146,9 @@ static inline struct cpumask *cpu_l2c_shared_mask(int cpu) return per_cpu(cpu_l2c_shared_map, cpu); } +void acpi_setup_mp_wakeup_mailbox(u64 addr); +struct acpi_madt_multiproc_wakeup_mailbox *acpi_get_mp_wakeup_mailbox(void); + #else /* !CONFIG_SMP */ #define wbinvd_on_cpu(cpu) wbinvd() static inline int wbinvd_on_all_cpus(void) diff --git a/arch/x86/kernel/acpi/madt_wakeup.c b/arch/x86/kernel/acpi/madt_wakeup.c index f36f28405dcc..4033c804307a 100644 --- a/arch/x86/kernel/acpi/madt_wakeup.c +++ b/arch/x86/kernel/acpi/madt_wakeup.c @@ -37,6 +37,7 @@ static void acpi_mp_play_dead(void) static void acpi_mp_cpu_die(unsigned int cpu) { + struct acpi_madt_multiproc_wakeup_mailbox *mailbox = acpi_get_mp_wakeup_mailbox(); u32 apicid = per_cpu(x86_cpu_to_apicid, cpu); unsigned long timeout; @@ -46,13 +47,13 @@ static void acpi_mp_cpu_die(unsigned int cpu) * * BIOS has to clear 'command' field of the mailbox. */ - acpi_mp_wake_mailbox->apic_id = apicid; - smp_store_release(&acpi_mp_wake_mailbox->command, + mailbox->apic_id = apicid; + smp_store_release(&mailbox->command, ACPI_MP_WAKE_COMMAND_TEST); /* Don't wait longer than a second. */ timeout = USEC_PER_SEC; - while (READ_ONCE(acpi_mp_wake_mailbox->command) && --timeout) + while (READ_ONCE(mailbox->command) && --timeout) udelay(1); if (!timeout) @@ -227,7 +228,7 @@ int __init acpi_parse_mp_wake(union acpi_subtable_headers *header, acpi_table_print_madt_entry(&header->common); - acpi_mp_wake_mailbox_paddr = mp_wake->mailbox_address; + acpi_setup_mp_wakeup_mailbox(mp_wake->mailbox_address); if (mp_wake->version >= ACPI_MADT_MP_WAKEUP_VERSION_V1 && mp_wake->header.length >= ACPI_MADT_MP_WAKEUP_SIZE_V1) { @@ -243,7 +244,16 @@ int __init acpi_parse_mp_wake(union acpi_subtable_headers *header, acpi_mp_disable_offlining(mp_wake); } + return 0; +} + +void __init acpi_setup_mp_wakeup_mailbox(u64 mailbox_paddr) +{ + acpi_mp_wake_mailbox_paddr = mailbox_paddr; apic_update_callback(wakeup_secondary_cpu_64, acpi_wakeup_cpu); +} - return 0; +struct acpi_madt_multiproc_wakeup_mailbox *acpi_get_mp_wakeup_mailbox(void) +{ + return acpi_mp_wake_mailbox; } From patchwork Wed Jun 4 00:15:14 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 895262 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7FB9D6AA7; Wed, 4 Jun 2025 00:18:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748996285; cv=none; b=Dq9QdoumhRc+g0+MbnX3BjyR7UcYzQsFnwFYIA1StDyJfrsf8J0/v69b9Ire5uP5Tx1rMoZshbLiZWhrMklzgi0l4Ay7SaL8DgQJFgzdoiwUxKsjzMyB6AfJLCFOA0rlKKxgLsKzeowu/CnK84ySCRd8OdzJ3MdG3KDJMjTsBtM= ARC-Message-Signature: i=1; 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d="scan'208";a="149904454" Received: from unknown (HELO [172.25.112.21]) ([172.25.112.21]) by fmviesa005.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2025 17:18:00 -0700 From: Ricardo Neri Date: Tue, 03 Jun 2025 17:15:14 -0700 Subject: [PATCH v4 02/10] x86/acpi: Move acpi_wakeup_cpu() and helpers to smpwakeup.c Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250603-rneri-wakeup-mailbox-v4-2-d533272b7232@linux.intel.com> References: <20250603-rneri-wakeup-mailbox-v4-0-d533272b7232@linux.intel.com> In-Reply-To: <20250603-rneri-wakeup-mailbox-v4-0-d533272b7232@linux.intel.com> To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley , "Rafael J. Wysocki" Cc: Saurabh Sengar , Chris Oo , "Kirill A. Shutemov" , linux-hyperv@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, "Ravi V. Shankar" , Ricardo Neri , Yunhong Jiang , Ricardo Neri X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748996287; l=9450; i=ricardo.neri-calderon@linux.intel.com; s=20250602; h=from:subject:message-id; bh=pPl7b6XtSmseHCkcheCWPHAL+avH9O3JDG2Rt0uU5Cw=; b=1CCcC47E8CEf8V9oEUfYfQ2PLhaqmKAjC4IoI7CWqbrsBCxPy6I600CaJjUQDi5DwST4QzLSO TFA/jgJvaoLBYkCri6ifvEz4vr70dPsF1WtSmu1lHdmWpzLhFz5Sym3 X-Developer-Key: i=ricardo.neri-calderon@linux.intel.com; a=ed25519; pk=NfZw5SyQ2lxVfmNMaMR6KUj3+0OhcwDPyRzFDH9gY2w= The bootstrap processor uses acpi_wakeup_cpu() to indicate to firmware that it wants to boot a secondary CPU using a mailbox as described in the Multiprocessor Wakeup Structure of the ACPI specification. The platform firmware may implement the mailbox as described in the ACPI specification but enumerate it using a DeviceTree graph. An example of this is OpenHCL paravisor. Move the code used to setup and use the mailbox for CPU wakeup out of the ACPI directory into a new smpwakeup.c file that both ACPI and DeviceTree can use. No functional changes are intended. Co-developed-by: Yunhong Jiang Signed-off-by: Yunhong Jiang Signed-off-by: Ricardo Neri --- Changes since v3: - Create a new file smpwakeup.c instead of relocating it to smpboot.c. (Rafael) Changes since v2: - Only move to smpboot.c the portions of the code that configure and use the mailbox. This also resolved the compile warnings about unused functions that Michael Kelley reported. - Edited the commit message for clarity. Changes since v1: - None. --- arch/x86/Kconfig | 7 ++++ arch/x86/kernel/Makefile | 1 + arch/x86/kernel/acpi/madt_wakeup.c | 76 ---------------------------------- arch/x86/kernel/smpwakeup.c | 83 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 91 insertions(+), 76 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index cb0f4af31789..82147edb355a 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1113,6 +1113,13 @@ config X86_LOCAL_APIC depends on X86_64 || SMP || X86_UP_APIC || PCI_MSI select IRQ_DOMAIN_HIERARCHY +config X86_MAILBOX_WAKEUP + def_bool y + depends on OF || ACPI_MADT_WAKEUP + depends on X86_64 + depends on SMP + depends on X86_LOCAL_APIC + config ACPI_MADT_WAKEUP def_bool y depends on X86_64 diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile index 99a783fd4691..8f078af42a71 100644 --- a/arch/x86/kernel/Makefile +++ b/arch/x86/kernel/Makefile @@ -94,6 +94,7 @@ apm-y := apm_32.o obj-$(CONFIG_APM) += apm.o obj-$(CONFIG_SMP) += smp.o obj-$(CONFIG_SMP) += smpboot.o +obj-$(CONFIG_X86_MAILBOX_WAKEUP) += smpwakeup.o obj-$(CONFIG_X86_TSC) += tsc_sync.o obj-$(CONFIG_SMP) += setup_percpu.o obj-$(CONFIG_X86_MPPARSE) += mpparse.o diff --git a/arch/x86/kernel/acpi/madt_wakeup.c b/arch/x86/kernel/acpi/madt_wakeup.c index 4033c804307a..a7e0158269b0 100644 --- a/arch/x86/kernel/acpi/madt_wakeup.c +++ b/arch/x86/kernel/acpi/madt_wakeup.c @@ -2,12 +2,10 @@ #include #include #include -#include #include #include #include #include -#include #include #include #include @@ -15,12 +13,6 @@ #include #include -/* Physical address of the Multiprocessor Wakeup Structure mailbox */ -static u64 acpi_mp_wake_mailbox_paddr __ro_after_init; - -/* Virtual address of the Multiprocessor Wakeup Structure mailbox */ -static struct acpi_madt_multiproc_wakeup_mailbox *acpi_mp_wake_mailbox; - static u64 acpi_mp_pgd __ro_after_init; static u64 acpi_mp_reset_vector_paddr __ro_after_init; @@ -127,63 +119,6 @@ static int __init acpi_mp_setup_reset(u64 reset_vector) return 0; } -static int acpi_wakeup_cpu(u32 apicid, unsigned long start_ip) -{ - if (!acpi_mp_wake_mailbox_paddr) { - pr_warn_once("No MADT mailbox: cannot bringup secondary CPUs. Booting with kexec?\n"); - return -EOPNOTSUPP; - } - - /* - * Remap mailbox memory only for the first call to acpi_wakeup_cpu(). - * - * Wakeup of secondary CPUs is fully serialized in the core code. - * No need to protect acpi_mp_wake_mailbox from concurrent accesses. - */ - if (!acpi_mp_wake_mailbox) { - acpi_mp_wake_mailbox = memremap(acpi_mp_wake_mailbox_paddr, - sizeof(*acpi_mp_wake_mailbox), - MEMREMAP_WB); - } - - /* - * Mailbox memory is shared between the firmware and OS. Firmware will - * listen on mailbox command address, and once it receives the wakeup - * command, the CPU associated with the given apicid will be booted. - * - * The value of 'apic_id' and 'wakeup_vector' must be visible to the - * firmware before the wakeup command is visible. smp_store_release() - * ensures ordering and visibility. - */ - acpi_mp_wake_mailbox->apic_id = apicid; - acpi_mp_wake_mailbox->wakeup_vector = start_ip; - smp_store_release(&acpi_mp_wake_mailbox->command, - ACPI_MP_WAKE_COMMAND_WAKEUP); - - /* - * Wait for the CPU to wake up. - * - * The CPU being woken up is essentially in a spin loop waiting to be - * woken up. It should not take long for it wake up and acknowledge by - * zeroing out ->command. - * - * ACPI specification doesn't provide any guidance on how long kernel - * has to wait for a wake up acknowledgment. It also doesn't provide - * a way to cancel a wake up request if it takes too long. - * - * In TDX environment, the VMM has control over how long it takes to - * wake up secondary. It can postpone scheduling secondary vCPU - * indefinitely. Giving up on wake up request and reporting error opens - * possible attack vector for VMM: it can wake up a secondary CPU when - * kernel doesn't expect it. Wait until positive result of the wake up - * request. - */ - while (READ_ONCE(acpi_mp_wake_mailbox->command)) - cpu_relax(); - - return 0; -} - static void acpi_mp_disable_offlining(struct acpi_madt_multiproc_wakeup *mp_wake) { cpu_hotplug_disable_offlining(); @@ -246,14 +181,3 @@ int __init acpi_parse_mp_wake(union acpi_subtable_headers *header, return 0; } - -void __init acpi_setup_mp_wakeup_mailbox(u64 mailbox_paddr) -{ - acpi_mp_wake_mailbox_paddr = mailbox_paddr; - apic_update_callback(wakeup_secondary_cpu_64, acpi_wakeup_cpu); -} - -struct acpi_madt_multiproc_wakeup_mailbox *acpi_get_mp_wakeup_mailbox(void) -{ - return acpi_mp_wake_mailbox; -} diff --git a/arch/x86/kernel/smpwakeup.c b/arch/x86/kernel/smpwakeup.c new file mode 100644 index 000000000000..e34ffbfffaf5 --- /dev/null +++ b/arch/x86/kernel/smpwakeup.c @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include +#include +#include +#include +#include +#include +#include + +/* Physical address of the Multiprocessor Wakeup Structure mailbox */ +static u64 acpi_mp_wake_mailbox_paddr __ro_after_init; + +/* Virtual address of the Multiprocessor Wakeup Structure mailbox */ +static struct acpi_madt_multiproc_wakeup_mailbox *acpi_mp_wake_mailbox; + +static int acpi_wakeup_cpu(u32 apicid, unsigned long start_ip) +{ + if (!acpi_mp_wake_mailbox_paddr) { + pr_warn_once("No MADT mailbox: cannot bringup secondary CPUs. Booting with kexec?\n"); + return -EOPNOTSUPP; + } + + /* + * Remap mailbox memory only for the first call to acpi_wakeup_cpu(). + * + * Wakeup of secondary CPUs is fully serialized in the core code. + * No need to protect acpi_mp_wake_mailbox from concurrent accesses. + */ + if (!acpi_mp_wake_mailbox) { + acpi_mp_wake_mailbox = memremap(acpi_mp_wake_mailbox_paddr, + sizeof(*acpi_mp_wake_mailbox), + MEMREMAP_WB); + } + + /* + * Mailbox memory is shared between the firmware and OS. Firmware will + * listen on mailbox command address, and once it receives the wakeup + * command, the CPU associated with the given apicid will be booted. + * + * The value of 'apic_id' and 'wakeup_vector' must be visible to the + * firmware before the wakeup command is visible. smp_store_release() + * ensures ordering and visibility. + */ + acpi_mp_wake_mailbox->apic_id = apicid; + acpi_mp_wake_mailbox->wakeup_vector = start_ip; + smp_store_release(&acpi_mp_wake_mailbox->command, + ACPI_MP_WAKE_COMMAND_WAKEUP); + + /* + * Wait for the CPU to wake up. + * + * The CPU being woken up is essentially in a spin loop waiting to be + * woken up. It should not take long for it wake up and acknowledge by + * zeroing out ->command. + * + * ACPI specification doesn't provide any guidance on how long kernel + * has to wait for a wake up acknowledgment. It also doesn't provide + * a way to cancel a wake up request if it takes too long. + * + * In TDX environment, the VMM has control over how long it takes to + * wake up secondary. It can postpone scheduling secondary vCPU + * indefinitely. Giving up on wake up request and reporting error opens + * possible attack vector for VMM: it can wake up a secondary CPU when + * kernel doesn't expect it. Wait until positive result of the wake up + * request. + */ + while (READ_ONCE(acpi_mp_wake_mailbox->command)) + cpu_relax(); + + return 0; +} + +void __init acpi_setup_mp_wakeup_mailbox(u64 mailbox_paddr) +{ + acpi_mp_wake_mailbox_paddr = mailbox_paddr; + apic_update_callback(wakeup_secondary_cpu_64, acpi_wakeup_cpu); +} + +struct acpi_madt_multiproc_wakeup_mailbox *acpi_get_mp_wakeup_mailbox(void) +{ + return acpi_mp_wake_mailbox; +} From patchwork Wed Jun 4 00:15:15 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 894025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D23F379F5; Wed, 4 Jun 2025 00:18:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748996285; cv=none; b=JIpVniCEmn15C9vJzfNB4bB1a5842VvIk9E5hdAas7pks+l1TGCcRIW0NJbj2p+1a1wLcZlVLHfC2c4z4UY+AtuL3Xue2s5lMMkbe38iya2Gid0V/FkZl7VniKgmrdyRxXZA9wft0PzFfgALTKWnoBoJpl6DprglMxZpkapvpb0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748996285; c=relaxed/simple; bh=vvzYz3uQ9MMaozEQnAeRM+GHHaJn/qRlXLRb/AZhEXU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=aWQ08MpBV0gRLHt4+KV+bReLc7Opst/dJyhte+Kg201tb/t5Z8vMAxd6tg7rO8Ntl9MIlFxrjJjIwjJqkrKC9H8Z0RK/Agy+QVyKPOCehNqL/jxoEKJgJEthxPjjOMx2uwXVfVdyprCRSQcr31xQwZuVS8alWFxQWg6Jm1imj04= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=nBH6JF5n; arc=none smtp.client-ip=198.175.65.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="nBH6JF5n" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1748996284; x=1780532284; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=vvzYz3uQ9MMaozEQnAeRM+GHHaJn/qRlXLRb/AZhEXU=; b=nBH6JF5nl13PWe/eFltzKrso1E0IHtq/G1BDdINmkM3NIuR1NTvn16fl zRbFuQpRX6iuHJ1pzG+lVhXGIRd6wHLW3MSsh/kpkqsUkwCwsY5ZtC7ob GD5DKe4yxeyMLxlR8hzXgwuqndCLA2zJw0KEPVl7u0iJFVTzppjidau9f ZsPEiovu3YlNrZ6EXBdPcgtSwUZDvJ0WQMj9V2bTk86xp5DmlBdiG0U4s bsb61FDqw9OaaFf5lHRbg91/JAYc2zaYqGk9zbVS4orFK/ZNaU8mpnfsj bVvbzBA54EJzquSJZ+ZJFvQsT8S2fYSfPEAxdZzvpdzAHxyTXOFUlqzgH Q==; X-CSE-ConnectionGUID: 9f/zIW0gQ0KQGd6oIOT98w== X-CSE-MsgGUID: 1R4tgbTfTJG/X1ieWWMXzQ== X-IronPort-AV: E=McAfee;i="6700,10204,11453"; a="62112941" X-IronPort-AV: E=Sophos;i="6.16,207,1744095600"; d="scan'208";a="62112941" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2025 17:18:01 -0700 X-CSE-ConnectionGUID: gFHP8ZaIQO2P1Wr1JTUmiQ== X-CSE-MsgGUID: 3zZuiT82S5+dHL688F5yXw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,207,1744095600"; d="scan'208";a="149904458" Received: from unknown (HELO [172.25.112.21]) ([172.25.112.21]) by fmviesa005.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2025 17:18:00 -0700 From: Ricardo Neri Date: Tue, 03 Jun 2025 17:15:15 -0700 Subject: [PATCH v4 03/10] dt-bindings: reserved-memory: Wakeup Mailbox for Intel processors Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250603-rneri-wakeup-mailbox-v4-3-d533272b7232@linux.intel.com> References: <20250603-rneri-wakeup-mailbox-v4-0-d533272b7232@linux.intel.com> In-Reply-To: <20250603-rneri-wakeup-mailbox-v4-0-d533272b7232@linux.intel.com> To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley , "Rafael J. Wysocki" Cc: Saurabh Sengar , Chris Oo , "Kirill A. Shutemov" , linux-hyperv@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, "Ravi V. Shankar" , Ricardo Neri , Yunhong Jiang , Ricardo Neri X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748996287; l=4376; i=ricardo.neri-calderon@linux.intel.com; s=20250602; h=from:subject:message-id; bh=vvzYz3uQ9MMaozEQnAeRM+GHHaJn/qRlXLRb/AZhEXU=; b=siYJEvDiKe+DCn4lcO2uPx6gRKyuWl+gMC+a9Alta4m8j0lQm1lqxadUmd+iFDNL+2Pi3JOgi PB/otJXRApoAc0Yp3dp/Gi29aWYTS+cdw7lqh56cjTOK7N9X7qBvGjl X-Developer-Key: i=ricardo.neri-calderon@linux.intel.com; a=ed25519; pk=NfZw5SyQ2lxVfmNMaMR6KUj3+0OhcwDPyRzFDH9gY2w= Add DeviceTree bindings to enumerate the wakeup mailbox used in platform firmware for Intel processors. x86 platforms commonly boot secondary CPUs using an INIT assert, de-assert followed by Start-Up IPI messages. The wakeup mailbox can be used when this mechanism is unavailable. The wakeup mailbox offers more control to the operating system to boot secondary CPUs than a spin-table. It allows the reuse of same wakeup vector for all CPUs while maintaining control over which CPUs to boot and when. While it is possible to achieve the same level of control using a spin- table, it would require to specify a separate `cpu-release-addr` for each secondary CPU. The operation and structure of the mailbox is described in the Multiprocessor Wakeup Structure defined in the ACPI specification. Note that this structure does not specify how to publish the mailbox to the operating system (ACPI-based platform firmware uses a separate table). No ACPI table is needed in DeviceTree-based firmware to enumerate the mailbox. Add a `compatible` property that the operating system can use to discover the mailbox. Nodes wanting to refer to the reserved memory usually define a `memory-region` property. /cpus/cpu* nodes would want to refer to the mailbox, but they do not have such property defined in the DeviceTree specification. Moreover, it would imply that there is a memory region per CPU. Co-developed-by: Yunhong Jiang Signed-off-by: Yunhong Jiang Signed-off-by: Ricardo Neri --- Changes since v3: - Removed redefinitions of the mailbox and instead referred to ACPI specification as per discussion on LKML. - Clarified that DeviceTree-based firmware do not require the use of ACPI tables to enumerate the mailbox. (Rob) - Described the need of using a `compatible` property. - Dropped the `alignment` property. (Krzysztof, Rafael) - Used a real address for the mailbox node. (Krzysztof) Changes since v2: - Implemented the mailbox as a reserved-memory node. Add to it a `compatible` property. (Krzysztof) - Explained the relationship between the mailbox and the `enable-mehod` property of the CPU nodes. - Expanded the documentation of the binding. Changes since v1: - Added more details to the description of the binding. - Added requirement a new requirement for cpu@N nodes to add an `enable-method`. --- .../reserved-memory/intel,wakeup-mailbox.yaml | 48 ++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/Documentation/devicetree/bindings/reserved-memory/intel,wakeup-mailbox.yaml b/Documentation/devicetree/bindings/reserved-memory/intel,wakeup-mailbox.yaml new file mode 100644 index 000000000000..f18643805866 --- /dev/null +++ b/Documentation/devicetree/bindings/reserved-memory/intel,wakeup-mailbox.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reserved-memory/intel,wakeup-mailbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Wakeup Mailbox for Intel processors + +description: | + The Wakeup Mailbox provides a mechanism for the operating system to wake up + secondary CPUs on Intel processors. It is an alternative to the INIT-!INIT- + SIPI sequence used on most x86 systems. + + The structure and operation of the mailbox is described in the Multiprocessor + Wakeup Structure of the ACPI specification. + + The implementation of the mailbox in platform firmware is described in the + Intel TDX Virtual Firmware Design Guide section 4.3.5. + + See https://www.intel.com/content/www/us/en/content-details/733585/intel-tdx-virtual-firmware-design-guide.html + +maintainers: + - Ricardo Neri + +allOf: + - $ref: reserved-memory.yaml + +properties: + compatible: + const: intel,wakeup-mailbox + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + reserved-memory { + #address-cells = <2>; + #size-cells = <1>; + + wakeup-mailbox@ffff0000 { + compatible = "intel,wakeup-mailbox"; + reg = <0x0 0xffff0000 0x1000>; + }; + }; From patchwork Wed Jun 4 00:15:16 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 895261 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 20108B676; Wed, 4 Jun 2025 00:18:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748996285; cv=none; b=WpO6QSEiHLo9t8BvqlsgcDu3cQz5aMQLrONinvq+AsUZR963ZCpGH0LqtuQR3orzi0sLQs1Vv6zm8eKTkymp7XcaJuLukpPXj9HIZTs17qqScct0pMnSYNXY2ztVAz63D9NUfrMcLWQf6SQ4/xkAInJNCKpLFST9KkKuNub4AP8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748996285; c=relaxed/simple; bh=inpJOnYjjazzTCmteT81ahYI4IV3tK4JVqafv/eEPZg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=TwxaiyA8cyLw5NJFH0lDMLbWOXWbkTc5PBfoZI66VWk99G/3nEonhOclVJ+KaUtHw5GE7Pn85b2f1MdkMlL0Psdwesri8+8zrow0xu7KXz0HWLzAxjdraFBXLkkK91mrMx7GXPZc4bHMXpaGg351803URLVCOt9V5j3+zY6JR54= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=hv4b45Kw; arc=none smtp.client-ip=198.175.65.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="hv4b45Kw" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1748996285; x=1780532285; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=inpJOnYjjazzTCmteT81ahYI4IV3tK4JVqafv/eEPZg=; b=hv4b45Kw480Nb86l7k1RRchY1ZUxxFgHK1eAerkmUjOqIaPQWwKietN+ jTaUHj/6S+hWI9HlzfOpgg5L1KbdbtZJEoZJeS4r+hMV/nlSb80wU1buH /FfJVjdNaZj8FQ3o6AYMvNoUfUhsBYi6683K//hUbb7i7pl+qWYb18/iA IeMxusMvwLywtYyOmJYMjNo7wjEi1whY/g9Tc/ZJKA+R1vTmQ1OvOPJk7 T8W80AigZ/fFhRJ/vldnorlLMVreJUUhOLK2yZ8B6qTo0Re3U9otRcXOz LaXtBNGc6QaxafuX7ae3Pb4vXaNC6lW8OrmJSJvVQa9xsLf4Ndh1gm1p6 A==; X-CSE-ConnectionGUID: sYc7+INDT16Lx03rtii/DQ== X-CSE-MsgGUID: 4zctpTudTxuRXgIAvNvVSg== X-IronPort-AV: E=McAfee;i="6700,10204,11453"; a="62112947" X-IronPort-AV: E=Sophos;i="6.16,207,1744095600"; d="scan'208";a="62112947" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2025 17:18:01 -0700 X-CSE-ConnectionGUID: M08Lh8dDTXC2X2LcgxjcIA== X-CSE-MsgGUID: Zqb5oS/SQyqvui0J7D6Avw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,207,1744095600"; d="scan'208";a="149904463" Received: from unknown (HELO [172.25.112.21]) ([172.25.112.21]) by fmviesa005.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2025 17:18:01 -0700 From: Ricardo Neri Date: Tue, 03 Jun 2025 17:15:16 -0700 Subject: [PATCH v4 04/10] x86/dt: Parse the Wakeup Mailbox for Intel processors Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250603-rneri-wakeup-mailbox-v4-4-d533272b7232@linux.intel.com> References: <20250603-rneri-wakeup-mailbox-v4-0-d533272b7232@linux.intel.com> In-Reply-To: <20250603-rneri-wakeup-mailbox-v4-0-d533272b7232@linux.intel.com> To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley , "Rafael J. Wysocki" Cc: Saurabh Sengar , Chris Oo , "Kirill A. Shutemov" , linux-hyperv@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, "Ravi V. Shankar" , Ricardo Neri , Yunhong Jiang , Ricardo Neri X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748996287; l=3986; i=ricardo.neri-calderon@linux.intel.com; s=20250602; h=from:subject:message-id; bh=inpJOnYjjazzTCmteT81ahYI4IV3tK4JVqafv/eEPZg=; b=ybjTFGxmYNWIJMl2LbblRhU6dFKhZ9DOVv/oPqO7nliMLIFFIt55lYdw6a6zWLEVPPbhtwlla lQPX+Z1pzUVCmOBgVV2kMWvkGIihd+hxqaXBEr6ozH66aR6sdWtrts2 X-Developer-Key: i=ricardo.neri-calderon@linux.intel.com; a=ed25519; pk=NfZw5SyQ2lxVfmNMaMR6KUj3+0OhcwDPyRzFDH9gY2w= The Wakeup Mailbox is a mechanism to boot secondary CPUs used on systems that do not want or cannot use the INIT + StartUp IPI messages. The platform firmware is expected to implement the mailbox as described in the Multiprocessor Wakeup Structure of the ACPI specification. It is also expected to publish the mailbox to the operating system as described in the corresponding DeviceTree schema that accompanies the documentation of the Linux kernel. Reuse the existing functionality to set the memory location of the mailbox and update the wakeup_secondary_cpu_64() APIC callback. do_boot_cpu() uses wakeup_secondary_cpu_64() when set. If a wakeup mailbox is found (enumerated via an ACPI table or a DeviceTree node) it will be used unconditionally. For cases in which this behavior is not desired, this APIC callback can be updated later during boot using platform-specific hooks. Co-developed-by: Yunhong Jiang Signed-off-by: Yunhong Jiang Signed-off-by: Ricardo Neri --- Changes since v3: - Look for the wakeup mailbox unconditionally, regardless of whether cpu@N nodes have an `enable-method` property. - Add a reference to the ACPI specification. (Rafael) Changes since v2: - Added extra sanity checks when parsing the mailbox node. - Probe the mailbox using its `compatible` property - Setup the Wakeup Mailbox if the `enable-method` is found in the CPU nodes. - Cleaned up unneeded ifdeffery. - Clarified the mechanisms used to override the wakeup_secondary_64() callback to not use the mailbox when not desired. (Michael) - Edited the commit message for clarity. Changes since v1: - Disabled CPU offlining. - Modified dtb_parse_mp_wake() to return the address of the mailbox. --- arch/x86/kernel/devicetree.c | 47 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c index dd8748c45529..494a560614a8 100644 --- a/arch/x86/kernel/devicetree.c +++ b/arch/x86/kernel/devicetree.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include @@ -125,6 +126,51 @@ static void __init dtb_setup_hpet(void) #endif } +#if defined(CONFIG_X86_64) && defined(CONFIG_SMP) + +#define WAKEUP_MAILBOX_SIZE 0x1000 +#define WAKEUP_MAILBOX_ALIGN 0x1000 + +/** dtb_wakeup_mailbox_setup() - Parse the wakeup mailbox from the device tree + * + * Look for the presence of a wakeup mailbox in the DeviceTree. The mailbox is + * expected to follow the structure and operation described in the Multiprocessor + * Wakeup Structure of the ACPI specification. + */ +static void __init dtb_wakeup_mailbox_setup(void) +{ + struct device_node *node; + struct resource res; + + node = of_find_compatible_node(NULL, NULL, "intel,wakeup-mailbox"); + if (!node) + return; + + if (of_address_to_resource(node, 0, &res)) + goto done; + + /* The mailbox is a 4KB-aligned region.*/ + if (res.start & (WAKEUP_MAILBOX_ALIGN - 1)) + goto done; + + /* The mailbox has a size of 4KB. */ + if (res.end - res.start + 1 != WAKEUP_MAILBOX_SIZE) + goto done; + + /* Not supported when the mailbox is used. */ + cpu_hotplug_disable_offlining(); + + acpi_setup_mp_wakeup_mailbox(res.start); +done: + of_node_put(node); +} +#else /* !CONFIG_X86_64 || !CONFIG_SMP */ +static inline int dtb_wakeup_mailbox_setup(void) +{ + return -EOPNOTSUPP; +} +#endif /* CONFIG_X86_64 && CONFIG_SMP */ + #ifdef CONFIG_X86_LOCAL_APIC static void __init dtb_cpu_setup(void) @@ -287,6 +333,7 @@ static void __init x86_dtb_parse_smp_config(void) dtb_setup_hpet(); dtb_apic_setup(); + dtb_wakeup_mailbox_setup(); } void __init x86_flattree_get_config(void) From patchwork Wed Jun 4 00:15:17 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 894024 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 78B341BC5C; Wed, 4 Jun 2025 00:18:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748996287; cv=none; b=kYljDw/LNa+l5h9nAs7+qqEG4C+J8ckStA37KYlOmw/6iO+epIZoNLD566qOsEKrdO5OniaN8/7fB+yFTrb9iiObcF5Wme5qV43nTxXeiIzMXNw1X+IIjow4NyoEoCAwVfzIMC185UtDF97LD9q0d9pO5huQLjNbvslD/vESN7E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748996287; c=relaxed/simple; bh=NWTFVdsTu15JID3vMZXamOvuYlBjkvLIfQE8cTt7NKg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=iW41UwodfQn+FcQTnzwFBHcQXhxsM5icu4xCCjgcf2E+PgZ0GxrdsQn9S/ppmyOIJASM/0lGdqphROvmF2yw95HWU2zajySwVs26p3xrZrKPNYzW16Ge4QTuquJG+TDWXmc6zEsGRzsn99T9rene8jQEi7kkF0UH/EnZF1S5fE0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=nBp4DTF8; arc=none smtp.client-ip=198.175.65.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="nBp4DTF8" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1748996286; x=1780532286; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=NWTFVdsTu15JID3vMZXamOvuYlBjkvLIfQE8cTt7NKg=; b=nBp4DTF8zvNwzJiP+1/a7ecP/O/bAxoMaF6VX3Z2VBuuAIaXWgaKgE1p wfEb3Fz97p+fmavB7asGrgbV59/WLWLNTu2849hAlWcqegIur9/b1Kjj2 WW2GOfc57FI3bAQsYbyC7EuEztgbxyZEKU6XTioFUGAzvyoRShHDPg+iD 7MSfDg2BQhuPANhgw4DiQY236nANwxF7F0m6pfShjqzKrsr6zOHkwyOOv GdFk9YzF/5raGsch19/NY2v88a/TlTyhYNZusnvZWVLCia0vy77i2rErB G5R4EpBlBiWvfaCifY6kJDIV0IW0ghRzv0049MH3vVbZa6haZszcJi5Dv g==; X-CSE-ConnectionGUID: XTn8HViyQ2uEtSFW6gZFHg== X-CSE-MsgGUID: i3wW5Ai0Q32zmb/7s3MXJw== X-IronPort-AV: E=McAfee;i="6700,10204,11453"; a="62112953" X-IronPort-AV: E=Sophos;i="6.16,207,1744095600"; d="scan'208";a="62112953" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2025 17:18:02 -0700 X-CSE-ConnectionGUID: FytyVrbJSn6EQTC47ZrZ3A== X-CSE-MsgGUID: 3aQpAMD1TWSq/JeozQXYyw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,207,1744095600"; d="scan'208";a="149904467" Received: from unknown (HELO [172.25.112.21]) ([172.25.112.21]) by fmviesa005.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2025 17:18:01 -0700 From: Ricardo Neri Date: Tue, 03 Jun 2025 17:15:17 -0700 Subject: [PATCH v4 05/10] x86/hyperv/vtl: Set real_mode_header in hv_vtl_init_platform() Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250603-rneri-wakeup-mailbox-v4-5-d533272b7232@linux.intel.com> References: <20250603-rneri-wakeup-mailbox-v4-0-d533272b7232@linux.intel.com> In-Reply-To: <20250603-rneri-wakeup-mailbox-v4-0-d533272b7232@linux.intel.com> To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley , "Rafael J. Wysocki" Cc: Saurabh Sengar , Chris Oo , "Kirill A. Shutemov" , linux-hyperv@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, "Ravi V. Shankar" , Ricardo Neri , Yunhong Jiang , Thomas Gleixner , Ricardo Neri X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748996287; l=1988; i=ricardo.neri-calderon@linux.intel.com; s=20250602; h=from:subject:message-id; bh=NksHFVn/eI0Fawofj7b00BEZiD32GqG4d/7RPbAEdi8=; b=MN+Qd6iKIzbJOTMiDJkH7medS+yCAXXXI1B2TzD3+vzND9xt24W4AWRTAtiLpb3eCFprENtUf 4lqo5BemmKJB3tL5Egmg24JdKGJDMEGcPaiHzQcQcuj3VN/cpby/Ab8 X-Developer-Key: i=ricardo.neri-calderon@linux.intel.com; a=ed25519; pk=NfZw5SyQ2lxVfmNMaMR6KUj3+0OhcwDPyRzFDH9gY2w= From: Yunhong Jiang Hyper-V VTL clears x86_platform.realmode_{init(), reserve()} in hv_vtl_platform_init() whereas it sets real_mode_header later in hv_vtl_early_init(). There is no need to deal with the real mode memory in two places: x86_platform.realmode_init() is invoked much later via an early_initcall. Set real_mode_header in hv_vtl_init_platform() to keep all code dealing with memory for the real mode trampoline in one place. Besides making the code more readable, it prepares it for a subsequent changeset in which the behavior needs to change to support Hyper-V VTL guests in TDX environment. Reviewed-by: Michael Kelley Suggested-by: Thomas Gleixner Signed-off-by: Yunhong Jiang Signed-off-by: Ricardo Neri --- Changes since v3: - Added Reviewed-by tag from Michael. Thanks! Changes since v2: - Edited the commit message for clarity. Changes since v1: - Introduced this patch. --- arch/x86/hyperv/hv_vtl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/hyperv/hv_vtl.c b/arch/x86/hyperv/hv_vtl.c index 4580936dcb03..6bd183ee484f 100644 --- a/arch/x86/hyperv/hv_vtl.c +++ b/arch/x86/hyperv/hv_vtl.c @@ -60,6 +60,7 @@ void __init hv_vtl_init_platform(void) x86_platform.realmode_reserve = x86_init_noop; x86_platform.realmode_init = x86_init_noop; + real_mode_header = &hv_vtl_real_mode_header; x86_init.irqs.pre_vector_init = x86_init_noop; x86_init.timers.timer_init = x86_init_noop; x86_init.resources.probe_roms = x86_init_noop; @@ -279,7 +280,6 @@ int __init hv_vtl_early_init(void) panic("XSAVE has to be disabled as it is not supported by this module.\n" "Please add 'noxsave' to the kernel command line.\n"); - real_mode_header = &hv_vtl_real_mode_header; apic_update_callback(wakeup_secondary_cpu_64, hv_vtl_wakeup_secondary_cpu); return 0; From patchwork Wed Jun 4 00:15:18 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 895260 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A4BB71F5F6; Wed, 4 Jun 2025 00:18:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748996287; cv=none; b=uRZ+8DvB8HxpoOVPsg0HVGIL8eXyr0mILPWtn96gz3yxYCMYLGandoBFY3fbitNVlxIFwIdGGACNzl8B7vLWbAtqdkQ4Rx4xwFDppQkOK93ilPwewFiH9dIx2nAmq6iV5VIR/Jk3glhuHmCDhdKfGmV4PW0x7+I2K2bh4anCmus= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748996287; c=relaxed/simple; bh=PUVIKq1UhmNARwP0ctBdFVOtRbG0LlOJlEurpP6Xx3E=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=PSx9iltcquB2KArONJXdTdMmAsnBXYibbG7K/DMcLxWsYohUhReFbGnk0ZbD91UqqdHbhqL0zFYtLQQ0CuEjzxv5IZpaLWNE312alGnBm8mdWy6CdsKhbtQg/ECN+DYQzaC71DH/a4yyRvg4hurGD69L0bOjhC1MNF7iS8Le0PA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=EBgQv1dU; arc=none smtp.client-ip=198.175.65.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="EBgQv1dU" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1748996286; x=1780532286; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=PUVIKq1UhmNARwP0ctBdFVOtRbG0LlOJlEurpP6Xx3E=; b=EBgQv1dUlHE2CZlhHxNg25hSEZKgiqCIcxfIET8r3fTOa6tXaVdFVD/p HhrPR6rFgd7qO8Ogqr1Xa2vNA88rVckdvXAQq6V1A8ppSkuQpEGgsdGFk yTlD2tYeSxjyzA54rAbTpz8sOIm6C2cHcqVxGc3lCm/SiH+nY8w7+e6Ww FINvemgpBnmMs0xMwgVCY4HIY79ar+EpetCWiEi8pZKoRXs+j127r9MVj P3dLeB2+mizSwSg58zQEjQQTWLCmfJQYUv2m8qvssqO7UTfiuyJ7+4qUM ZFMMA1X5b0AiGlaD/oEb7LCye0OTW92ma4axqKXojyST3m2UJDJIHpx+2 g==; X-CSE-ConnectionGUID: t5oLCuGHQvymGiRa0nXYrg== X-CSE-MsgGUID: cVe64yC8QiuSOW4LGKmEUA== X-IronPort-AV: E=McAfee;i="6700,10204,11453"; a="62112958" X-IronPort-AV: E=Sophos;i="6.16,207,1744095600"; d="scan'208";a="62112958" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2025 17:18:02 -0700 X-CSE-ConnectionGUID: /ko6f3r6TCCDd6JYel0ZPQ== X-CSE-MsgGUID: Ob0sN+IXQnGj7OFjfya1kw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,207,1744095600"; d="scan'208";a="149904471" Received: from unknown (HELO [172.25.112.21]) ([172.25.112.21]) by fmviesa005.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2025 17:18:01 -0700 From: Ricardo Neri Date: Tue, 03 Jun 2025 17:15:18 -0700 Subject: [PATCH v4 06/10] x86/realmode: Make the location of the trampoline configurable Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250603-rneri-wakeup-mailbox-v4-6-d533272b7232@linux.intel.com> References: <20250603-rneri-wakeup-mailbox-v4-0-d533272b7232@linux.intel.com> In-Reply-To: <20250603-rneri-wakeup-mailbox-v4-0-d533272b7232@linux.intel.com> To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley , "Rafael J. Wysocki" Cc: Saurabh Sengar , Chris Oo , "Kirill A. Shutemov" , linux-hyperv@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, "Ravi V. Shankar" , Ricardo Neri , Yunhong Jiang , Thomas Gleixner , Ricardo Neri X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748996287; l=3871; i=ricardo.neri-calderon@linux.intel.com; s=20250602; h=from:subject:message-id; bh=oG+sUwuixbImCg84nwDCAdPZ8WWhaG4+2hWqfX0US3g=; b=6eMJvAFiFCJGbc0qNGLUaFhNrRZ537Mn+HoUALex7amHrbkkOhLfHPAywBIjS6kzLkQYMT0jY XBqXoCRR2AnCVn3FCfciuLvuP43P7P9T+0SO2dXQMdq96vH/dBOBlwx X-Developer-Key: i=ricardo.neri-calderon@linux.intel.com; a=ed25519; pk=NfZw5SyQ2lxVfmNMaMR6KUj3+0OhcwDPyRzFDH9gY2w= From: Yunhong Jiang x86 CPUs boot in real mode. This mode uses 20-bit memory addresses (16-bit registers plus 4-bit segment selectors). This implies that the trampoline must reside under the 1MB memory boundary. There are platforms in which the firmware boots the secondary CPUs, switches them to long mode and transfers control to the kernel. An example of such mechanism is the ACPI Multiprocessor Wakeup Structure. In this scenario there is no restriction to locate the trampoline under 1MB memory. Moreover, certain platforms (for example, Hyper-V VTL guests) may not have memory available for allocation under 1MB. Add a new member to struct x86_init_resources to specify the upper bound for the location of the trampoline memory. Keep the default upper bound of 1MB to conserve the current behavior. Reviewed-by: Michael Kelley Originally-by: Thomas Gleixner Signed-off-by: Yunhong Jiang Signed-off-by: Ricardo Neri --- Changes since v3: - Added Reviewed-by tag from Michael. Thanks! Changes since v2: - Edited the commit message for clarity. - Minor tweaks to comments. - Removed the option to not reserve the first 1MB of memory as it is not needed. Changes since v1: - Added this patch using code that Thomas suggested: https://lore.kernel.org/lkml/87a5ho2q6x.ffs@tglx/ --- arch/x86/include/asm/x86_init.h | 3 +++ arch/x86/kernel/x86_init.c | 3 +++ arch/x86/realmode/init.c | 7 +++---- 3 files changed, 9 insertions(+), 4 deletions(-) diff --git a/arch/x86/include/asm/x86_init.h b/arch/x86/include/asm/x86_init.h index 36698cc9fb44..e770ce507a87 100644 --- a/arch/x86/include/asm/x86_init.h +++ b/arch/x86/include/asm/x86_init.h @@ -31,12 +31,15 @@ struct x86_init_mpparse { * platform * @memory_setup: platform specific memory setup * @dmi_setup: platform specific DMI setup + * @realmode_limit: platform specific address limit for the real mode trampoline + * (default 1M) */ struct x86_init_resources { void (*probe_roms)(void); void (*reserve_resources)(void); char *(*memory_setup)(void); void (*dmi_setup)(void); + unsigned long realmode_limit; }; /** diff --git a/arch/x86/kernel/x86_init.c b/arch/x86/kernel/x86_init.c index 0a2bbd674a6d..a25fd7282811 100644 --- a/arch/x86/kernel/x86_init.c +++ b/arch/x86/kernel/x86_init.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include @@ -69,6 +70,8 @@ struct x86_init_ops x86_init __initdata = { .reserve_resources = reserve_standard_io_resources, .memory_setup = e820__memory_setup_default, .dmi_setup = dmi_setup, + /* Has to be under 1M so we can execute real-mode AP code. */ + .realmode_limit = SZ_1M, }, .mpparse = { diff --git a/arch/x86/realmode/init.c b/arch/x86/realmode/init.c index ed5c63c0b4e5..01155f995b2b 100644 --- a/arch/x86/realmode/init.c +++ b/arch/x86/realmode/init.c @@ -46,7 +46,7 @@ void load_trampoline_pgtable(void) void __init reserve_real_mode(void) { - phys_addr_t mem; + phys_addr_t mem, limit = x86_init.resources.realmode_limit; size_t size = real_mode_size_needed(); if (!size) @@ -54,10 +54,9 @@ void __init reserve_real_mode(void) WARN_ON(slab_is_available()); - /* Has to be under 1M so we can execute real-mode AP code. */ - mem = memblock_phys_alloc_range(size, PAGE_SIZE, 0, 1<<20); + mem = memblock_phys_alloc_range(size, PAGE_SIZE, 0, limit); if (!mem) - pr_info("No sub-1M memory is available for the trampoline\n"); + pr_info("No memory below %pa for the real-mode trampoline\n", &limit); else set_real_mode_mem(mem); From patchwork Wed Jun 4 00:15:19 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 894023 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EA8963595A; Wed, 4 Jun 2025 00:18:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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a="62112963" X-IronPort-AV: E=Sophos;i="6.16,207,1744095600"; d="scan'208";a="62112963" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2025 17:18:02 -0700 X-CSE-ConnectionGUID: zTf4k3h6TjGu+vnS7EEd9Q== X-CSE-MsgGUID: /63SA10USl2JM0T6K3F+qg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,207,1744095600"; d="scan'208";a="149904476" Received: from unknown (HELO [172.25.112.21]) ([172.25.112.21]) by fmviesa005.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2025 17:18:01 -0700 From: Ricardo Neri Date: Tue, 03 Jun 2025 17:15:19 -0700 Subject: [PATCH v4 07/10] x86/hyperv/vtl: Setup the 64-bit trampoline for TDX guests Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250603-rneri-wakeup-mailbox-v4-7-d533272b7232@linux.intel.com> References: <20250603-rneri-wakeup-mailbox-v4-0-d533272b7232@linux.intel.com> In-Reply-To: <20250603-rneri-wakeup-mailbox-v4-0-d533272b7232@linux.intel.com> To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley , "Rafael J. Wysocki" Cc: Saurabh Sengar , Chris Oo , "Kirill A. Shutemov" , linux-hyperv@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, "Ravi V. Shankar" , Ricardo Neri , Yunhong Jiang , Ricardo Neri X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748996287; l=2512; i=ricardo.neri-calderon@linux.intel.com; s=20250602; h=from:subject:message-id; bh=cwjzbQJMuckUfYrMyGEivmvlDqF1G7Qp0Q7oqGDvum0=; b=iOiCh0sBp1vME5V7EgWP7K/SYZ9V0T2RvZgXULmi9oV7K8jmbntaWo8lLvDgOrtCv3sOa+yWr nsbZSp7iGfsBGOw+pVcZaxYYEU9YnmTOvTqfQptW1b2p2y4fLhUb57i X-Developer-Key: i=ricardo.neri-calderon@linux.intel.com; a=ed25519; pk=NfZw5SyQ2lxVfmNMaMR6KUj3+0OhcwDPyRzFDH9gY2w= From: Yunhong Jiang The hypervisor is an untrusted entity for TDX guests. It cannot be used to boot secondary CPUs - neither via hypercalls not the INIT assert, de-assert plus Start-Up IPI messages. Instead, the platform virtual firmware boots the secondary CPUs and puts them in a state to transfer control to the kernel. This mechanism uses the wakeup mailbox described in the Multiprocessor Wakeup Structure of the ACPI specification. The entry point to the kernel is trampoline_start64. Allocate and setup the trampoline using the default x86_platform callbacks. The platform firmware configures the secondary CPUs in long mode. It is no longer necessary to locate the trampoline under 1MB memory. After handoff from firmware, the trampoline code switches briefly to 32-bit addressing mode, which has an addressing limit of 4GB. Set the upper bound of the trampoline memory accordingly. Reviewed-by: Michael Kelley Signed-off-by: Yunhong Jiang Signed-off-by: Ricardo Neri --- Changes since v3: - Added Reviewed-by tag from Michael. Thanks! Changes since v2: - Added a note regarding there is no need to check for a present paravisor. - Edited commit message for clarity. Changes since v1: - Dropped the function hv_reserve_real_mode(). Instead, used the new members realmode_limit and reserve_bios members of x86_init to set the upper bound of the trampoline memory. (Thomas) --- arch/x86/hyperv/hv_vtl.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/x86/hyperv/hv_vtl.c b/arch/x86/hyperv/hv_vtl.c index 6bd183ee484f..8b497c8292d3 100644 --- a/arch/x86/hyperv/hv_vtl.c +++ b/arch/x86/hyperv/hv_vtl.c @@ -58,9 +58,14 @@ void __init hv_vtl_init_platform(void) { pr_info("Linux runs in Hyper-V Virtual Trust Level\n"); - x86_platform.realmode_reserve = x86_init_noop; - x86_platform.realmode_init = x86_init_noop; - real_mode_header = &hv_vtl_real_mode_header; + /* There is no paravisor present if we are here. */ + if (hv_isolation_type_tdx()) { + x86_init.resources.realmode_limit = SZ_4G; + } else { + x86_platform.realmode_reserve = x86_init_noop; + x86_platform.realmode_init = x86_init_noop; + real_mode_header = &hv_vtl_real_mode_header; + } x86_init.irqs.pre_vector_init = x86_init_noop; x86_init.timers.timer_init = x86_init_noop; x86_init.resources.probe_roms = x86_init_noop; From patchwork Wed Jun 4 00:15:20 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 895259 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4B20C7261C; Wed, 4 Jun 2025 00:18:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748996288; cv=none; b=OP3JzaLnaFF+U6vRO3yXWy4Zz6cuzAFQIxKi5jPPSOlPge9N0rLWEcWJWOEVeq2XpZbgt/Y5Eu47RuTk2/GCfZml7oa8oA5NhseEl2SSmSXOqK4jTpvQmbcPA8hWylRlPvPfX/h5jiuPosiLv7ZJbZoUXyLpGSbJyuk34LJIqXU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748996288; c=relaxed/simple; bh=V4sR4hWtPVMZ3ywoOFOkbkpBj99xQxKorVINhU2PHmw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=QeOpsDnQWLA9zUsUoPM66oJj2GfVpVAu+lCj8mRxytF+XuM/FjzDz/cckZUbIlB8ppFiCq+Mym1PyTxyQinI9ikpaVzmk7AJJ+FDSaKjUikEl+x8xDkwt/HUFMtUeDUsYUk+E/o2u43JjozdH9uFTFGyHjAEJMvgNd2x76BUzys= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=J93voas7; arc=none smtp.client-ip=198.175.65.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="J93voas7" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1748996288; x=1780532288; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=V4sR4hWtPVMZ3ywoOFOkbkpBj99xQxKorVINhU2PHmw=; b=J93voas7xz+e/dLn3+jO6thWXtyb+4jYMA108VDkpvnTzOlXHznZkM2g y1rOrFmtjgpiEv+VFoMQow/IUiFLrgtRuAUcWlnRE2Tx3peFALyuHezGR aMcPzXqxq6gI6IU/n+Z33DUIXeqcxm+B3DESIPgpuuE0jPy5nlH/cuP9s 98hALq12W5Hccvbge3erajDWAxTVM73veGUg4mrWC1KXKsmsqo3k8pfm8 M0Pm7CH8QBx2VmtHHm7fm0nr/Mnpphu+BZM2DrI6au+qlKK8cTmKKB2hW WZrmA2KNIsVW14qw4sRBFQ0vEHLRqL2Mgslloyz1FmQfzPAC5heQoplIR w==; X-CSE-ConnectionGUID: IdJP7aNFR+qa62rIc+Rscw== X-CSE-MsgGUID: x0bSJUzxQPK5PaeZ3Ww20Q== X-IronPort-AV: E=McAfee;i="6700,10204,11453"; a="62112969" X-IronPort-AV: E=Sophos;i="6.16,207,1744095600"; d="scan'208";a="62112969" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2025 17:18:02 -0700 X-CSE-ConnectionGUID: 6YWKi+xaQEibtUd3ry2T2Q== X-CSE-MsgGUID: va9ZTG5wTDKXle8JBnGjBA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,207,1744095600"; d="scan'208";a="149904480" Received: from unknown (HELO [172.25.112.21]) ([172.25.112.21]) by fmviesa005.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2025 17:18:01 -0700 From: Ricardo Neri Date: Tue, 03 Jun 2025 17:15:20 -0700 Subject: [PATCH v4 08/10] x86/smpwakeup: Add a helper get the address of the wakeup mailbox Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250603-rneri-wakeup-mailbox-v4-8-d533272b7232@linux.intel.com> References: <20250603-rneri-wakeup-mailbox-v4-0-d533272b7232@linux.intel.com> In-Reply-To: <20250603-rneri-wakeup-mailbox-v4-0-d533272b7232@linux.intel.com> To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley , "Rafael J. Wysocki" Cc: Saurabh Sengar , Chris Oo , "Kirill A. Shutemov" , linux-hyperv@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, "Ravi V. Shankar" , Ricardo Neri , Ricardo Neri X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748996287; l=1666; i=ricardo.neri-calderon@linux.intel.com; s=20250602; h=from:subject:message-id; bh=V4sR4hWtPVMZ3ywoOFOkbkpBj99xQxKorVINhU2PHmw=; b=YbzLXOrL8hy7jvbbqW4L3osjtuRhbSMmRT94LsT01Vh/TDKPLYC0KwlfS0L7vAp0K0UmNuoaX SlZyoAkkZbPA3rMXeVf/r6Oywxko8sgCM5ZUMkfv6Ziu8nhoyWeELmE X-Developer-Key: i=ricardo.neri-calderon@linux.intel.com; a=ed25519; pk=NfZw5SyQ2lxVfmNMaMR6KUj3+0OhcwDPyRzFDH9gY2w= A Hyper-V VTL level 2 guest on a TDX environment needs to map the physical page of the ACPI Multiprocessor Wakeup Structure as private (encrypted). It needs to know the physical address of this structure. Add a helper function. Reviewed-by: Michael Kelley Suggested-by: Michael Kelley Signed-off-by: Ricardo Neri --- Changes since v3: - Renamed function to acpi_get_mp_wakeup_mailbox_paddr(). - Added Reviewed-by tag from Michael. Thanks! Changes since v2: - Introduced this patch Changes since v1: - N/A --- arch/x86/include/asm/smp.h | 1 + arch/x86/kernel/smpwakeup.c | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/arch/x86/include/asm/smp.h b/arch/x86/include/asm/smp.h index 77dce560a70a..158e8979342e 100644 --- a/arch/x86/include/asm/smp.h +++ b/arch/x86/include/asm/smp.h @@ -148,6 +148,7 @@ static inline struct cpumask *cpu_l2c_shared_mask(int cpu) void acpi_setup_mp_wakeup_mailbox(u64 addr); struct acpi_madt_multiproc_wakeup_mailbox *acpi_get_mp_wakeup_mailbox(void); +u64 acpi_get_mp_wakeup_mailbox_paddr(void); #else /* !CONFIG_SMP */ #define wbinvd_on_cpu(cpu) wbinvd() diff --git a/arch/x86/kernel/smpwakeup.c b/arch/x86/kernel/smpwakeup.c index e34ffbfffaf5..1d24ca97bdf8 100644 --- a/arch/x86/kernel/smpwakeup.c +++ b/arch/x86/kernel/smpwakeup.c @@ -81,3 +81,8 @@ struct acpi_madt_multiproc_wakeup_mailbox *acpi_get_mp_wakeup_mailbox(void) { return acpi_mp_wake_mailbox; } + +u64 acpi_get_mp_wakeup_mailbox_paddr(void) +{ + return acpi_mp_wake_mailbox_paddr; +} From patchwork Wed Jun 4 00:15:21 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 894022 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8032D78F5E; Wed, 4 Jun 2025 00:18:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748996289; cv=none; b=TBYFuLNbLnUdkGNL/edLgfE4QRf4i41+T+vAy/3QLCuriKHub9FU4l3b87KsC8gRPCZs4GrrVCRtBr8frzk7/oMaLK3Tmm5TMGA9zE7W9dUu7bv8Hz+rdPe9CPz5T4dXqIupeIyOWXHoFb79GQK4Qxq2rQdQ4UJhXcPCT1VSCrI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748996289; c=relaxed/simple; bh=ahMl9gGZluKayAijS2KHGKWb3QX1PeyP1wqA7nZwVBg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=eHiEMGBqf3OHhQ7d2yg7mPqQpgTRj9CIP0u8rtgW5z4MKL33PFhKtOnN/GYNxAz8vYMBB6i9sexx5uUtSXl4ZJOYziynlxVQENVzrMIHZWGONtdkFlR2Acb6rBCPmG8+Raq86Zf0eJgTiVTBSXevh+kTqGhzaAZBlG4r+TSzGQc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=K99x7mJt; arc=none smtp.client-ip=198.175.65.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="K99x7mJt" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1748996288; x=1780532288; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=ahMl9gGZluKayAijS2KHGKWb3QX1PeyP1wqA7nZwVBg=; b=K99x7mJt8/2wUpgWOUP6SQTQSa15em2y9fMXS12F9+NZXvqRNjJ8OgUm z+Ovx8WY0qD+kY0iTMuqlHPvcJ/O8meZHStjjZ0//LcmnN8StAnSkoZ39 FPJq1pV05dHkm+qbSplBHcbwYNnFrOpwwLNfiOZlmY2dp+OXyUlp/+eWh eA9EZqtNyiDt3m1g4nB8/xSetHL1FiAnGLmwiXANyGKF/TbQaBXZJ7MFS 13NGegkZCqvrxow6z03x+OrvvxLrlL3zPJoZybaDvnNCScU4YlslbOwOy gGC7zrL3biD0/U8cWH+PxSWSqgDUdR5tjDVZkyHTrE36+T3xwDfnoHtso g==; X-CSE-ConnectionGUID: w41gQkwnRm+XiZxxYSm8xQ== X-CSE-MsgGUID: ssOr0ge8T1+I3a5zrviMEA== X-IronPort-AV: E=McAfee;i="6700,10204,11453"; a="62112972" X-IronPort-AV: E=Sophos;i="6.16,207,1744095600"; d="scan'208";a="62112972" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2025 17:18:02 -0700 X-CSE-ConnectionGUID: o7KteomWTiqC13zvEWT8Wg== X-CSE-MsgGUID: mvkNHSwNQEeigQfJHs5PAw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,207,1744095600"; d="scan'208";a="149904483" Received: from unknown (HELO [172.25.112.21]) ([172.25.112.21]) by fmviesa005.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2025 17:18:01 -0700 From: Ricardo Neri Date: Tue, 03 Jun 2025 17:15:21 -0700 Subject: [PATCH v4 09/10] x86/hyperv/vtl: Mark the wakeup mailbox page as private Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250603-rneri-wakeup-mailbox-v4-9-d533272b7232@linux.intel.com> References: <20250603-rneri-wakeup-mailbox-v4-0-d533272b7232@linux.intel.com> In-Reply-To: <20250603-rneri-wakeup-mailbox-v4-0-d533272b7232@linux.intel.com> To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley , "Rafael J. Wysocki" Cc: Saurabh Sengar , Chris Oo , "Kirill A. Shutemov" , linux-hyperv@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, "Ravi V. Shankar" , Ricardo Neri , Yunhong Jiang , Ricardo Neri X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748996287; l=2300; i=ricardo.neri-calderon@linux.intel.com; s=20250602; h=from:subject:message-id; bh=bKxLwQiFT1mEsXYGzQ6fKI1YFK6+0GKv4TRntu2AgMw=; b=1/Up4bCIx6mjNMhO3/oBdQNhSi1JTQh0eBL63IT62HJsLKEIAIhu05Pw+DbatnHJ9Z2zHctxn /Bu7utPgztACFr6NPwggXF+tRgD5FLgG6C4BhnOuuf8o2Z+maIsN9T0 X-Developer-Key: i=ricardo.neri-calderon@linux.intel.com; a=ed25519; pk=NfZw5SyQ2lxVfmNMaMR6KUj3+0OhcwDPyRzFDH9gY2w= From: Yunhong Jiang The current code maps MMIO devices as shared (decrypted) by default in a confidential computing VM. In a TDX environment, secondary CPUs are booted using the Multiprocessor Wakeup Structure defined in the ACPI specification. The virtual firmware and the operating system function in the guest context, without intervention from the VMM. Map the physical memory of the mailbox as private. Use the is_private_mmio() callback. Reviewed-by: Michael Kelley Signed-off-by: Yunhong Jiang Signed-off-by: Ricardo Neri --- Changes since v3: - Updated to use the renamed function acpi_get_mp_wakeup_mailbox_paddr(). - Added Reviewed-by tag from Michael. Thanks! Changes since v2: - Use the new helper function get_mp_wakeup_mailbox_paddr(). - Edited the commit message for clarity. Changes since v1: - Added the helper function within_page() to improve readability - Override the is_private_mmio() callback when detecting a TDX environment. The address of the mailbox is checked in hv_is_private_mmio_tdx(). --- arch/x86/hyperv/hv_vtl.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/x86/hyperv/hv_vtl.c b/arch/x86/hyperv/hv_vtl.c index 8b497c8292d3..995d1de7a9be 100644 --- a/arch/x86/hyperv/hv_vtl.c +++ b/arch/x86/hyperv/hv_vtl.c @@ -54,6 +54,18 @@ static void __noreturn hv_vtl_restart(char __maybe_unused *cmd) hv_vtl_emergency_restart(); } +static inline bool within_page(u64 addr, u64 start) +{ + return addr >= start && addr < (start + PAGE_SIZE); +} + +static bool hv_vtl_is_private_mmio_tdx(u64 addr) +{ + u64 mb_addr = acpi_get_mp_wakeup_mailbox_paddr(); + + return mb_addr && within_page(addr, mb_addr); +} + void __init hv_vtl_init_platform(void) { pr_info("Linux runs in Hyper-V Virtual Trust Level\n"); @@ -61,6 +73,8 @@ void __init hv_vtl_init_platform(void) /* There is no paravisor present if we are here. */ if (hv_isolation_type_tdx()) { x86_init.resources.realmode_limit = SZ_4G; + x86_platform.hyper.is_private_mmio = hv_vtl_is_private_mmio_tdx; + } else { x86_platform.realmode_reserve = x86_init_noop; x86_platform.realmode_init = x86_init_noop; From patchwork Wed Jun 4 00:15:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 895258 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B622286338; Wed, 4 Jun 2025 00:18:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748996289; cv=none; b=l5r7TdfU5KN8AIFK2CUIDmcaWseazSxnxl6WBzOLV1E7343aXRMqUp0mgFi22gy77CsrbAq7ozBZoQ+pHQUxwr/LZSohqYkDJWlRdqFXKXhh7qW9avkT4ww2FfOkoRcXD356U1dYSt8nExe6cCbbyBIwibJeNiHu+pWXCaI9y1E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748996289; c=relaxed/simple; bh=YMzG5+AadCckxPwzHaVnWjL9Y7atDKDPkNrr/M1BYpQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=U+STvnulgPklDf0F4mLzwBPpeD8iMsqPQP+c/FIY0wW2XKiAWQnUdGuuSoxZZ/IPPheAVr0xPvwDgx/c9/XzTKyGxnFEq2eD6nmNELGmyjo7jZL4+HcCiFi0lD+rGolqH2c1u3UPsstReLWvGVtZ2URV80/+W0eMvbXPeArdgy8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=S1tWAsgK; arc=none smtp.client-ip=198.175.65.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="S1tWAsgK" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1748996288; x=1780532288; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=YMzG5+AadCckxPwzHaVnWjL9Y7atDKDPkNrr/M1BYpQ=; b=S1tWAsgK04q3WWG6yx5I1kaI3yDrnO7/+YD7NrdtdtWKfwwnJLfHHG8V +kAwecBz3Cb3e05Eaz8Mau4q8culDiIFbVAsR4atsGvlglOopNiWdWOJo 6p+F1uieCj0TP926b1lSPEut5bQQlrLXne9EwG3ZziR5f9XChk4olDGng Vc06WV6drC5tQq0SMxY9LEeEQ1bIomL+4/ai9orK1JjGopRciVK3uSbJO mvA/JtI0L7Lm0HpmvGs/nas4KzVc36qb7i3JdlIxNZ3wnHj/wiwQHBSXl qKUhJfIWnxm/vpUTF9oSjgrnmrW9/O7TiJu+6YU/0hlqlJFbvBtVTNa6H g==; X-CSE-ConnectionGUID: tyX2Q5dWRwaaWZ0o+zE6kQ== X-CSE-MsgGUID: e8/VatTDSzyHRMJ24k8qEw== X-IronPort-AV: E=McAfee;i="6700,10204,11453"; a="62112974" X-IronPort-AV: E=Sophos;i="6.16,207,1744095600"; d="scan'208";a="62112974" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2025 17:18:02 -0700 X-CSE-ConnectionGUID: +0ZBoGqeTXaj2BQXnK6DtQ== X-CSE-MsgGUID: A4Uf1QcFSAm91jlrxnwHeA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,207,1744095600"; d="scan'208";a="149904486" Received: from unknown (HELO [172.25.112.21]) ([172.25.112.21]) by fmviesa005.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2025 17:18:01 -0700 From: Ricardo Neri Date: Tue, 03 Jun 2025 17:15:22 -0700 Subject: [PATCH v4 10/10] x86/hyperv/vtl: Use the wakeup mailbox to boot secondary CPUs Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250603-rneri-wakeup-mailbox-v4-10-d533272b7232@linux.intel.com> References: <20250603-rneri-wakeup-mailbox-v4-0-d533272b7232@linux.intel.com> In-Reply-To: <20250603-rneri-wakeup-mailbox-v4-0-d533272b7232@linux.intel.com> To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley , "Rafael J. Wysocki" Cc: Saurabh Sengar , Chris Oo , "Kirill A. Shutemov" , linux-hyperv@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, "Ravi V. Shankar" , Ricardo Neri , Ricardo Neri X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748996287; l=1828; i=ricardo.neri-calderon@linux.intel.com; s=20250602; h=from:subject:message-id; bh=YMzG5+AadCckxPwzHaVnWjL9Y7atDKDPkNrr/M1BYpQ=; b=AQX0mRFsZ9dxNlLT540Y7TjjN7bcbmpsiw30cxH6/zwuFQYEkgAnS0GiAk8Dh5iKMQ9me49xK sZKwsKJ+V7rDO57ChwsHvsuwtp/BntEe8NCaEPcH4LfK3UiIp3PYsuZ X-Developer-Key: i=ricardo.neri-calderon@linux.intel.com; a=ed25519; pk=NfZw5SyQ2lxVfmNMaMR6KUj3+0OhcwDPyRzFDH9gY2w= The hypervisor is an untrusted entity for TDX guests. It cannot be used to boot secondary CPUs. The function hv_vtl_wakeup_secondary_cpu() cannot be used. Instead, the virtual firmware boots the secondary CPUs and places them in a state to transfer control to the kernel using the wakeup mailbox. The kernel updates the APIC callback wakeup_secondary_cpu_64() to use the mailbox if detected early during boot (enumerated via either an ACPI table or a DeviceTree node). Reviewed-by: Michael Kelley Signed-off-by: Ricardo Neri --- Changes since v3: - Added Reviewed-by tag from Michael. Thanks! Changes since v2: - Unconditionally use the wakeup mailbox in a TDX confidential VM. (Michael). - Edited the commit message for clarity. Changes since v1: - None --- arch/x86/hyperv/hv_vtl.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/x86/hyperv/hv_vtl.c b/arch/x86/hyperv/hv_vtl.c index 995d1de7a9be..f3d4f06d1f17 100644 --- a/arch/x86/hyperv/hv_vtl.c +++ b/arch/x86/hyperv/hv_vtl.c @@ -299,7 +299,15 @@ int __init hv_vtl_early_init(void) panic("XSAVE has to be disabled as it is not supported by this module.\n" "Please add 'noxsave' to the kernel command line.\n"); - apic_update_callback(wakeup_secondary_cpu_64, hv_vtl_wakeup_secondary_cpu); + /* + * TDX confidential VMs do not trust the hypervisor and cannot use it to + * boot secondary CPUs. Instead, they will be booted using the wakeup + * mailbox if detected during boot. See setup_arch(). + * + * There is no paravisor present if we are here. + */ + if (!hv_isolation_type_tdx()) + apic_update_callback(wakeup_secondary_cpu_64, hv_vtl_wakeup_secondary_cpu); return 0; }