From patchwork Sun Jun 8 14:49:08 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Du, Bin" X-Patchwork-Id: 894861 Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2066.outbound.protection.outlook.com [40.107.236.66]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B67742505CE; Sun, 8 Jun 2025 14:49:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.236.66 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749394192; cv=fail; b=J7dMyhAO18UO1cYS1U79mjZCXZH2X2viO6OHWECVG6KP2xxA63cRIEW8QhGIfR+GwOUcHff+Vodu/yGs6h9bLWCAi2v+4jf/Rt+PBXadBzDP/KcpxKM42fAOf8pYHtB66ObLaD1ERbJPKU9dukgErj9DtG40OYd+LsNyf2davrs= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749394192; c=relaxed/simple; bh=+A8RBM/d/2xC2zgJ2DqZ9kw4pm4p6SbOz+3TNManqR4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=MlgsU6c76ARX3yMKDFVLkHQWe+VocWCR6pfvl3LMMP8u2z/WPhMyIejHulOHLOOg08iqNqvEWILf2EL4n9H7K0dW1y8C5VmCJf7Hij+T4y0ayObZGXkkmYxHvH3pfXCJrog8WTsn2xHxT0ChuRDTg4xmYc1tWtTLf3tJjPbwVxI= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com; spf=fail smtp.mailfrom=amd.com; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b=XjHynrLB; arc=fail smtp.client-ip=40.107.236.66 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=amd.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="XjHynrLB" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=wKrT/Ogo8XmddXOKPGcNChT6YJj+57syPoeSTyCC9EZzkgIhLuDEqUwEyFR7rhvyI61CoRXojjpvVS+zaTdNb6oPAu5mvrGG7T6kuunVPMPTY+IYg74+RtKSUWRp/0QXxsn2klo5fw1GV+yDDjKrZcctGmIsnTof4KmU+yi6+y+utOMlMexWgLFQHBuBWZqwBNCl+UXaxMiMuxvCFzpu8zm4+1AxyqOcZC0uOq37vKcmcmRYXvb2XLa0GHF5KhlYWgbec5YFsxH17XqoR4Wg3fqjl5gXc5mKIS6HSruZgqM01NkPeMtq1jvtFfWVay4/S2BBfCsq0KRxzBBGKMwyKw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=3e7UX37afj2KB2OrCYyMt5UsXmehvgk81bicExSVcOw=; b=NOdMPKRYBGmoHwCKA1lPtS+1RgKoq/81KjezUBBmYy5bBrlOT0lsZvi41ABR2vOC0cO3fTsSZCV+M0NGHmndP1kvI4RBZOBfmkQZjuRhbBTHHt2mwqu4DG0Fu30LOQEi4ccWduuqBAl2G69yxsLUYl+HW7l7QTGUvP8pB/Zp/ZrkO+8B3hwbGDISaHchElfgKeI45LyHquDNMwYL6uWCdAlPza5Ai/USCGKSAeMdd8QHSVRuIlcPYJHMt8yBalFAvd+g2VHp3KDym+zIXSUt/U32DDYiopbt2AvfETgj0Wdcfy/g+beqlzDng/g2oSEaarq8ODQl6zvq3VEIfbreaQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=3e7UX37afj2KB2OrCYyMt5UsXmehvgk81bicExSVcOw=; b=XjHynrLB+/vS95gtEnMFuZ/906C4SwlitTFSEOOfWweYmIEtdkXpCO5vmet0EwlnP21gphBIHzKxU5OY4lK5ceB16PcloDPJwsDG/S66FRaPGfCYG4cp9Qt9K1hNhNyTGB1u9/+GsWPdgDNbj6lnfZewfaoc7zpWXwJwNguKwD8= Received: from BY5PR17CA0046.namprd17.prod.outlook.com (2603:10b6:a03:167::23) by MW4PR12MB6923.namprd12.prod.outlook.com (2603:10b6:303:208::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8792.38; Sun, 8 Jun 2025 14:49:41 +0000 Received: from SJ5PEPF000001D3.namprd05.prod.outlook.com (2603:10b6:a03:167:cafe::4f) by BY5PR17CA0046.outlook.office365.com (2603:10b6:a03:167::23) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8746.30 via Frontend Transport; Sun, 8 Jun 2025 14:49:41 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SJ5PEPF000001D3.mail.protection.outlook.com (10.167.242.55) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8835.15 via Frontend Transport; Sun, 8 Jun 2025 14:49:41 +0000 Received: from 555e2b870847.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Sun, 8 Jun 2025 09:49:36 -0500 From: Bin Du To: , , , , , , , CC: , , , , , , , , "Bin Du" Subject: [PATCH v1 1/9] media: platform: amd: Introduce amd isp4 capture driver Date: Sun, 8 Jun 2025 22:49:08 +0800 Message-ID: <20250608144916.222835-2-Bin.Du@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250608144916.222835-1-Bin.Du@amd.com> References: <20250608144916.222835-1-Bin.Du@amd.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001D3:EE_|MW4PR12MB6923:EE_ X-MS-Office365-Filtering-Correlation-Id: e2912efc-be77-42b9-9f1c-08dda69bb35b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|36860700013|82310400026|376014; X-Microsoft-Antispam-Message-Info: HOa1NP74TARN9CqL/bVDfCNDHv7PMzeAZaxx5S7HYN/gRU1JX/5lzYjfhou1zvVmGUJWMbRAz4WMLSwRdInD+f63/PayCeLmpvGcAs6OD/IQ5tNBc9qzqvFi9/NwfQhlslYU+BfSQnQcLZc8GDO+dM5g9nalaT1xMzqxXg5XvnDG5uLrl3MmowHy+aU+x28XKXxfeKabOKEgO3hJdyjv9ptyyxjMMymt4bSJh8enkKiM0/dmZeK9Vk06kv9mpeiljXwgtWAOarwhzE2h0q78v41OJf3Q555Hmtvwrh5hZ4SIp599ldI2JAhPpNEVCV0yAnyiSKMFST3cfnXp5QPAN8rJvnL8aGBL1PpHgp+BIPg4Vs5MFDdF1Qldc6qkUD2kGCkBM3AMNZYVYn3ncexmXyWgoHvKzRSXpGfA7Z4INnZoB0bi3uBzqZJP9axllQRhhX/fvdkknFe1z9nNcRZW0tTa4rjZawFKxOV7Si7b+AkImNtfPEBIuGNIa0zNxn8olPge6MycSVGwSj85lFZmseOaXcw7NuG7iAWP9q2u8wk2tBT75oy+rnn1qH688PeFY1QVBM8u7LPbfgqfyI0X4MKWRAOpL+I67acNChlxOEU0es1dAMm+mAZIqIFmwmRHhLeiNLrGofvdOkn2Ag/OvWH68e3d9EKLThAbKZrTjoBDM3IowDlkAxNCzNkFARaU9w6DsSfrlRq0Xoji4qQbMvast8otmBtcefQNeOK2BMKB5MKndCcNW8nEfUeqXkxIuvotDzglNyAOzME+noRNISyrC4m5zQCkn9Mr7Y9FJL8f/H3uDTXPcb/Ns67z6y8rC9OPUk/1L/YHynHLUxykof1+53DvTBRzDrmS+b1AfHxo9CdLKuD8MHr49F5g6pdYmOa6H5vpbI9cyy4QnTnY6WR18ENJThsZDtFwzY+9rJL0lmmJZ2huUpCc5JYpfqaIojZ+5rfHx5I2Wpqo15qTQwiE3vtd3bz2NgbwEm6HGwe5My4RCk7qt4g9l3FgAgwt+jnlbXsYVThU7jwQXIwH5mT9AYnbljNphIzujrjyGEsLbD8Z8Tx/AYpUF270f5yn7UA3CRR90zo2MS1F4B8Ig8bagbHsVlneMyp+/nvW97PknfzlxKQtkPd0FVFQJ3+kCQr0QG3aanr5jTIOyqYep9M68ObsjlGS357WNfmMjXeodKouj5QB0/R2HREeTaSVFTFOfV5Qshpq2XtK6QLxSu1zV233uA+8NIx3ErwTuFtn0jJDtR/hLGRXcniU/esaETtrgWuXeja4VXMDLfoYlWeXKMs+hM7iAjkvdcNdeWWhgqceID/mKLKFkFa7ZH/E6UxPpORuSaF7ewpWUGIn3LlFvjc16s6JwWeGMB3P2Wl3rHmvZwFhcVbZ67ynHGU75Ql/+BYtzMgnUznk8KzZ8cEDDZ6Cfu2t3fnCxXFcUvOrJTL/TndPkZ3qe68IjYGTXsLrdfd9B/IpQAjuhIFxwBEkuf890i90boG0IcM8QJ2a8bwHTBDvj2DoIWZbv5db X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(1800799024)(36860700013)(82310400026)(376014); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jun 2025 14:49:41.4488 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e2912efc-be77-42b9-9f1c-08dda69bb35b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001D3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6923 Amd isp4 capture is a v4l2 media device which implements media controller interface. It has one sub-device (amd ISP4 sub-device) endpoint which can be connected to a remote CSI2 TX endpoint. It supports only one physical interface for now. Signed-off-by: Bin Du Signed-off-by: Svetoslav Stoilov Change-Id: I1a55f348db6a307797349203640132675aafbc0a --- drivers/media/platform/Kconfig | 1 + drivers/media/platform/Makefile | 1 + drivers/media/platform/amd/Kconfig | 15 +++ drivers/media/platform/amd/Makefile | 5 + drivers/media/platform/amd/isp4/Makefile | 16 +++ drivers/media/platform/amd/isp4/isp4.c | 139 +++++++++++++++++++++++ drivers/media/platform/amd/isp4/isp4.h | 35 ++++++ 7 files changed, 212 insertions(+) create mode 100644 drivers/media/platform/amd/Kconfig create mode 100644 drivers/media/platform/amd/Makefile create mode 100644 drivers/media/platform/amd/isp4/Makefile create mode 100644 drivers/media/platform/amd/isp4/isp4.c create mode 100644 drivers/media/platform/amd/isp4/isp4.h diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig index 85d2627776b6..d525c2262a7d 100644 --- a/drivers/media/platform/Kconfig +++ b/drivers/media/platform/Kconfig @@ -89,5 +89,6 @@ source "drivers/media/platform/ti/Kconfig" source "drivers/media/platform/verisilicon/Kconfig" source "drivers/media/platform/via/Kconfig" source "drivers/media/platform/xilinx/Kconfig" +source "drivers/media/platform/amd/Kconfig" endif # MEDIA_PLATFORM_DRIVERS diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile index ace4e34483dd..9f3d1693868d 100644 --- a/drivers/media/platform/Makefile +++ b/drivers/media/platform/Makefile @@ -32,6 +32,7 @@ obj-y += ti/ obj-y += verisilicon/ obj-y += via/ obj-y += xilinx/ +obj-y += amd/ # Please place here only ancillary drivers that aren't SoC-specific # Please keep it alphabetically sorted by Kconfig name diff --git a/drivers/media/platform/amd/Kconfig b/drivers/media/platform/amd/Kconfig new file mode 100644 index 000000000000..361b3d687529 --- /dev/null +++ b/drivers/media/platform/amd/Kconfig @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: MIT + +config AMD_ISP4 + tristate "AMD ISP4 and camera driver" + default y + depends on VIDEO_DEV && VIDEO_V4L2_SUBDEV_API + select VIDEOBUF2_CORE + select VIDEOBUF2_V4L2 + select VIDEOBUF2_MEMOPS + select VIDEOBUF2_VMALLOC + select VIDEOBUF2_DMA_CONTIG + select VIDEOBUF2_DMA_SG + help + This is support for AMD ISP4 and camera subsystem driver. + Say Y here to enable the ISP4 and camera device for video capture. diff --git a/drivers/media/platform/amd/Makefile b/drivers/media/platform/amd/Makefile new file mode 100644 index 000000000000..76146efcd2bf --- /dev/null +++ b/drivers/media/platform/amd/Makefile @@ -0,0 +1,5 @@ +# Copyright 2024 Advanced Micro Devices, Inc. +# add isp block +ifneq ($(CONFIG_AMD_ISP4),) +obj-y += isp4/ +endif diff --git a/drivers/media/platform/amd/isp4/Makefile b/drivers/media/platform/amd/isp4/Makefile new file mode 100644 index 000000000000..f2ac9b2a95f0 --- /dev/null +++ b/drivers/media/platform/amd/isp4/Makefile @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2025 Advanced Micro Devices, Inc. + +obj-$(CONFIG_AMD_ISP4) += amd_capture.o +amd_capture-objs := isp4.o + +ccflags-y += -I$(srctree)/drivers/media/platform/amd/isp4 +ccflags-y += -I$(srctree)/include + +ifneq ($(call cc-option, -mpreferred-stack-boundary=4),) + cc_stack_align := -mpreferred-stack-boundary=4 +endif + +ccflags-y += $(cc_stack_align) +ccflags-y += -DCONFIG_COMPAT diff --git a/drivers/media/platform/amd/isp4/isp4.c b/drivers/media/platform/amd/isp4/isp4.c new file mode 100644 index 000000000000..d0be90c5ec3b --- /dev/null +++ b/drivers/media/platform/amd/isp4/isp4.c @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2025 Advanced Micro Devices, Inc. + */ + +#include +#include +#include + +#include "isp4.h" + +#define VIDEO_BUF_NUM 5 + +#define ISP4_DRV_NAME "amd_isp_capture" + +/* interrupt num */ +static const u32 isp4_ringbuf_interrupt_num[] = { + 0, /* ISP_4_1__SRCID__ISP_RINGBUFFER_WPT9 */ + 1, /* ISP_4_1__SRCID__ISP_RINGBUFFER_WPT10 */ + 3, /* ISP_4_1__SRCID__ISP_RINGBUFFER_WPT11 */ + 4, /* ISP_4_1__SRCID__ISP_RINGBUFFER_WPT12 */ +}; + +#define to_isp4_device(dev) \ + ((struct isp4_device *)container_of(dev, struct isp4_device, v4l2_dev)) + +static irqreturn_t isp4_irq_handler(int irq, void *arg) +{ + struct isp4_device *isp_dev = dev_get_drvdata((struct device *)arg); + + if (!isp_dev) + goto error_drv_data; + +error_drv_data: + return IRQ_HANDLED; +} + +/* + * amd capture module + */ +static int isp4_capture_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct isp4_device *isp_dev; + + int i, irq, ret; + + isp_dev = devm_kzalloc(&pdev->dev, sizeof(*isp_dev), GFP_KERNEL); + if (!isp_dev) + return -ENOMEM; + + isp_dev->pdev = pdev; + dev->init_name = ISP4_DRV_NAME; + + for (i = 0; i < ARRAY_SIZE(isp4_ringbuf_interrupt_num); i++) { + irq = platform_get_irq(pdev, isp4_ringbuf_interrupt_num[i]); + if (irq < 0) + return dev_err_probe(dev, -ENODEV, + "fail to get irq %d\n", + isp4_ringbuf_interrupt_num[i]); + ret = devm_request_irq(&pdev->dev, irq, isp4_irq_handler, 0, + "ISP_IRQ", &pdev->dev); + if (ret) + return dev_err_probe(dev, ret, "fail to req irq %d\n", + irq); + } + + isp_dev->pltf_data = pdev->dev.platform_data; + + dev_dbg(dev, "isp irq registration successful\n"); + + /* Link the media device within the v4l2_device */ + isp_dev->v4l2_dev.mdev = &isp_dev->mdev; + + /* Initialize media device */ + strscpy(isp_dev->mdev.model, "amd_isp41_mdev", + sizeof(isp_dev->mdev.model)); + snprintf(isp_dev->mdev.bus_info, sizeof(isp_dev->mdev.bus_info), + "platform:%s", ISP4_DRV_NAME); + isp_dev->mdev.dev = &pdev->dev; + media_device_init(&isp_dev->mdev); + + /* register v4l2 device */ + snprintf(isp_dev->v4l2_dev.name, sizeof(isp_dev->v4l2_dev.name), + "AMD-V4L2-ROOT"); + ret = v4l2_device_register(&pdev->dev, &isp_dev->v4l2_dev); + if (ret) + return dev_err_probe(dev, ret, + "fail register v4l2 device\n"); + + dev_dbg(dev, "AMD ISP v4l2 device registered\n"); + + ret = media_device_register(&isp_dev->mdev); + if (ret) { + dev_err(dev, "fail to register media device %d\n", ret); + goto err_unreg_v4l2; + } + + platform_set_drvdata(pdev, isp_dev); + + pm_runtime_set_suspended(dev); + pm_runtime_enable(dev); + + return 0; + +err_unreg_v4l2: + v4l2_device_unregister(&isp_dev->v4l2_dev); + + return dev_err_probe(dev, ret, "isp probe fail\n"); +} + +static void isp4_capture_remove(struct platform_device *pdev) +{ + struct isp4_device *isp_dev = platform_get_drvdata(pdev); + struct device *dev = &pdev->dev; + + media_device_unregister(&isp_dev->mdev); + v4l2_device_unregister(&isp_dev->v4l2_dev); + dev_dbg(dev, "AMD ISP v4l2 device unregistered\n"); +} + +static struct platform_driver isp4_capture_drv = { + .probe = isp4_capture_probe, + .remove = isp4_capture_remove, + .driver = { + .name = ISP4_DRV_NAME, + .owner = THIS_MODULE, + } +}; + +module_platform_driver(isp4_capture_drv); + +MODULE_ALIAS("platform:" ISP4_DRV_NAME); +MODULE_IMPORT_NS("DMA_BUF"); + +MODULE_DESCRIPTION("AMD ISP4 Driver"); +MODULE_AUTHOR("Bin Du "); +MODULE_AUTHOR("Pratap Nirujogi "); +MODULE_LICENSE("GPL"); diff --git a/drivers/media/platform/amd/isp4/isp4.h b/drivers/media/platform/amd/isp4/isp4.h new file mode 100644 index 000000000000..27a7362ce6f9 --- /dev/null +++ b/drivers/media/platform/amd/isp4/isp4.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2025 Advanced Micro Devices, Inc. + */ + +#ifndef _ISP4_H_ +#define _ISP4_H_ + +#include +#include +#include +#include + +#define ISP4_GET_ISP_REG_BASE(isp4sd) (((isp4sd))->mmio) + +struct isp4_platform_data { + void *adev; + void *bo; + void *cpu_ptr; + u64 gpu_addr; + u32 size; + u32 asic_type; + resource_size_t base_rmmio_size; +}; + +struct isp4_device { + struct v4l2_device v4l2_dev; + struct media_device mdev; + + struct isp4_platform_data *pltf_data; + struct platform_device *pdev; + struct notifier_block i2c_nb; +}; + +#endif /* isp4.h */ From patchwork Sun Jun 8 14:49:09 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Du, Bin" X-Patchwork-Id: 895011 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2068.outbound.protection.outlook.com [40.107.220.68]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BDB042505D6; Sun, 8 Jun 2025 14:49:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.220.68 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749394192; cv=fail; b=Z78eXJjj9lAv3G9RKivOS5LT/sTDG1MRrPcuHwf/DpS/Teznv05d02ORLbjXonXvO5I5MMEOUQJDMqycAk05SCvV6t4uqHafborZ7NX4pIxk1Ymd3b4yYWDmYkUN+VozvHqdHiXeRr9Ep9Qqk941zxuKGEo7uPGn11lwR/dYIPM= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749394192; c=relaxed/simple; bh=mVRTlzqEUpuugglkzpjJadUFmzALq2pcv9PAufCBHsU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=B+Sa/7nVed0QKHH5UN8YL6v3vAVW4s8kjo9Ueb8wNKiLv351vRtXjntlZl/bnAMOgZgm0Fkcnw6n9dOF0c4wt9JPmkrUO6FVX8fqiMCoV3RLyck/n1uRL6Z1WXuK8ASgX2wI/27ad1Yo/wCeuESOfIumIZBfQh7dTKQtMRvDW/o= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com; spf=fail smtp.mailfrom=amd.com; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b=kEuokvlB; arc=fail smtp.client-ip=40.107.220.68 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=amd.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="kEuokvlB" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=cSHkqSmkAy5kAXEqbucuD+V8vvxpHMD3bLMDfzGqshnlDlcsjMPW0As9wHZHkgfVytHuPYoKcgRa+pTa6+DeYAbzXGdownMvew9LQCr03boXuvWXqPAlTZd9qM5SxsTgdhEVsul1pbr87OpdqsYHwrEPxDkwfr9ETnwHVBJu1PBSOWdf9PcUmKA7jLxLLLSb7CngYrXsCxhOwihAqOO6qL5DFs2XLvyqOm1Mw3aMNR0IezM9vR7iqRTh4GvyqR93nmVoNuAvw9L+nhOy+H/gD9zFHd/koo4KgtUnov+Uw4zHz5t+Ptd21qvLYZ2V3i+9nxZz9G2+Tel8iu5fCJ36rg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=jmy3fqO7OQkS3zvOlXrMcR5qIuQmokx9Te+0WsCmeKM=; b=BV/wlE5IDHTUZ1PskJ7qyaUYDpf4BVNHWOp+Z0h3xUfc0IA5qZ5dvDXd6JpLEeOnXFd8O4tGvEaVN2O/jSZOTli067/43aJddE+JWwxf5PSyEJJ9YmeRaWDRewsFqbw6GsGtD6xG8RF+yFkTAhzz+A5bNZLAEphS4uQ+7/rnW+qbvqfitS+wlsbiZmVzoRNdWBqfl5xSggDA/JfQxZbxozXD5mIlfHKbBNE8J92yVrUhm0dgYuNChNo/9v3lwaZFdK4itVc6iv5x+dwxIv1f6sgk2ngC6Es0Urbkbb+qzzt+fJOGVe9CiPqJcA6tm3SpkKCEXZNnx+0kVFMdzmZeZw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=jmy3fqO7OQkS3zvOlXrMcR5qIuQmokx9Te+0WsCmeKM=; b=kEuokvlB4g4iLk5mYu+z/MH1mq72jFLwyWVBBJjQNXRqnKc2pyDpeurx3FMHwo2wEB98d/vhykdKEMsk1gNyuAzOlpo4RUtmojggrm5FCy/CzaqVSoM+2lTk3N6oXjuM3QFrlnGqD0q5n9zwFbn2nvC1EQd62b6NzMKpINsW1TI= Received: from SJ0PR05CA0061.namprd05.prod.outlook.com (2603:10b6:a03:332::6) by LV5PR12MB9779.namprd12.prod.outlook.com (2603:10b6:408:301::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8792.35; Sun, 8 Jun 2025 14:49:46 +0000 Received: from SJ5PEPF000001D1.namprd05.prod.outlook.com (2603:10b6:a03:332:cafe::a5) by SJ0PR05CA0061.outlook.office365.com (2603:10b6:a03:332::6) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8835.9 via Frontend Transport; Sun, 8 Jun 2025 14:49:45 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SJ5PEPF000001D1.mail.protection.outlook.com (10.167.242.53) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8835.15 via Frontend Transport; Sun, 8 Jun 2025 14:49:45 +0000 Received: from 555e2b870847.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Sun, 8 Jun 2025 09:49:41 -0500 From: Bin Du To: , , , , , , , CC: , , , , , , , , "Bin Du" Subject: [PATCH v1 2/9] media: platform: amd: low level support for isp4 firmware Date: Sun, 8 Jun 2025 22:49:09 +0800 Message-ID: <20250608144916.222835-3-Bin.Du@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250608144916.222835-1-Bin.Du@amd.com> References: <20250608144916.222835-1-Bin.Du@amd.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001D1:EE_|LV5PR12MB9779:EE_ X-MS-Office365-Filtering-Correlation-Id: 07a8ab80-71e1-4e4f-64ab-08dda69bb5d2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700013|376014|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: +y9qMWBDcgEZ0AurDluY8qQeN1wdD32/Hg022efTJ9ec7P8RjN6nSihMRoRjOof/JMQwiZPzRQDeoWCV8Fi7pWk8UrXiMOLMAzM3Tw6KxBbcnaxU3Jz3za69LD3HsCm7V0mSev1mhlVdklRfRMRwOHH+q7w8XwT5coOXRBmmHV2gpGwPV1SzUj/9Xz5fUqYw/LTqVieqzIKCU+hw9OVLlB/XY4tAXVCFu7ETlUyO3xpvIS/jDKdDQPXvFrNDieI4/p9+0Wm5j/inDnAsszNaveySHjqBccE/aBvBsVHHSInq4QR/SGwNn0Pn7Nj1ZuRzHgLRaE5We9fUn7oBmw966PHftK6ac6EXn+eQ5lmdZEMK0gfveJxD6ViYG5gDoR2Z6EXTBmbagz3akTgIlDIdGaqbXUK6Y+Kzjd2aUeThzNtCeOSlPA7YV7lgH25+5ZD3Ggmz/Mj2NgEb0lBNT5ZYIIK0XhtCVvddy+m+y2Dy4V3suHAtVDSrUKKCCNKmvufjV4VHRBALlG+owEvhiTnoF2kEF2WnDQES/Uh35HJYVUIpaDQBWYWpUNKgzsjItWLw7YewcV7j/qXEKOB99OByDrHwhKrJOrllCCPNnL+JQQXhjxLsA5BRrzPTFKNoTaRZp0zfULcZOGM5rQgoJRYhItVF2fXphM7wRYl2EBf+dvjhfy29YLpoQRggmUzHfOySFi6qRU/JS3PF1gh3/jFz0G9Ngi6txs4PLk4BytK5uSrZDP87cUWDI+FvIFPiFCMxn4wRnkITvruTEY1z4eAEGM7v5iqwIx4g3lYbf46Vm3eu5vL7Bb8M3yiuo1DvR9hzOAeloySX9KQe8NuDPeZcxRaUZbY/8IUzJFF34VVM1J9kuB1/C0FnHSxTzKqBrxUSXQ/LdVnrTFsFOEnpuszLtkjXoxUrVI5ECtpvbO/rOgoG2c1LeSE0rmSiAtyyd26SiBvp2SdzLykhh91mKzq/2zsVQMxfkN3LctHXZAfkTY9E/08RJgCn+PEK7OeGPKbcsd81e95NFNinsTdI+HX3RZCPGcjYDnB6aviNMW1Ei8A7L1QG6OYIIs40ZHdPcxBd49uYkcTcQexr+HLeM6udyEFALcRsXE1nWdHA+4ArOd9Y49Hdz83QgbFY0Nitmal6v+bkO5+B/Mw3iVtTqQ+1R9wCYPQH8kozSAHKz4/GK4rcI7k2Y1pBtyc7dEqQfaTq3D0PXeAsFdfhgeOL7TJCo7WX3xIz9Pr3h1qRYMXM3Cm3GjOGLf2Mhj+qZhao2ZX6m+NfxF6TOcWL66SgNENU3XMrzf9N7pu5N34Eg76mgb5bAqa+sZz+scQiMPGj0id5M2jg9JSfQm4mr2APgVoYPqyeDEAbLACX9oASXrRSQptbIuwtGZjZ9a4HWqVqRC9xGPKidaZ3yugbUD4rucY7wTJA9ZYJ+wrnn4wHceBduf4CBYM9n2yd3UA9IkYaEj6za3ze1htVc/ZOFCgoQfg67d6e6EnzN7t8t6z9nLyFr+F3KB5doCjuHSGHw21kyiZ6 X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(36860700013)(376014)(82310400026)(1800799024); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jun 2025 14:49:45.5813 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 07a8ab80-71e1-4e4f-64ab-08dda69bb5d2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001D1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV5PR12MB9779 Low level functions for access the registers and mapping to their ranges. This change also includes register definitions for ring buffer used to communicate with ISP Firmware. Ring buffer is the communication interface between driver and ISP Firmware. Command and responses are exchanged through the ring buffer. Signed-off-by: Bin Du Signed-off-by: Svetoslav Stoilov Change-Id: Ic06d5387ade72c57f6efc6b699ceaa6aa91804ec --- drivers/media/platform/amd/isp4/Makefile | 3 +- drivers/media/platform/amd/isp4/isp4_hw.c | 46 +++++++ drivers/media/platform/amd/isp4/isp4_hw.h | 14 +++ drivers/media/platform/amd/isp4/isp4_hw_reg.h | 116 ++++++++++++++++++ 4 files changed, 178 insertions(+), 1 deletion(-) create mode 100644 drivers/media/platform/amd/isp4/isp4_hw.c create mode 100644 drivers/media/platform/amd/isp4/isp4_hw.h create mode 100644 drivers/media/platform/amd/isp4/isp4_hw_reg.h diff --git a/drivers/media/platform/amd/isp4/Makefile b/drivers/media/platform/amd/isp4/Makefile index f2ac9b2a95f0..4ef8be329d56 100644 --- a/drivers/media/platform/amd/isp4/Makefile +++ b/drivers/media/platform/amd/isp4/Makefile @@ -3,7 +3,8 @@ # Copyright (C) 2025 Advanced Micro Devices, Inc. obj-$(CONFIG_AMD_ISP4) += amd_capture.o -amd_capture-objs := isp4.o +amd_capture-objs := isp4.o \ + isp4_hw.o \ ccflags-y += -I$(srctree)/drivers/media/platform/amd/isp4 ccflags-y += -I$(srctree)/include diff --git a/drivers/media/platform/amd/isp4/isp4_hw.c b/drivers/media/platform/amd/isp4/isp4_hw.c new file mode 100644 index 000000000000..e5315330a514 --- /dev/null +++ b/drivers/media/platform/amd/isp4/isp4_hw.c @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2025 Advanced Micro Devices, Inc. + */ + +#include +#include + +#include "isp4_hw.h" +#include "isp4_hw_reg.h" + +#define RMMIO_SIZE 524288 + +u32 isp4hw_rreg(void __iomem *base, u32 reg) +{ + void __iomem *reg_addr; + + if (reg >= RMMIO_SIZE) + return RREG_FAILED_VAL; + + if (reg < ISP_MIPI_PHY0_REG0) + reg_addr = base + reg; + else if (reg <= ISP_MIPI_PHY0_REG0 + ISP_MIPI_PHY0_SIZE) + reg_addr = base + (reg - ISP_MIPI_PHY0_REG0); + else + return RREG_FAILED_VAL; + + return readl(reg_addr); +}; + +void isp4hw_wreg(void __iomem *base, u32 reg, u32 val) +{ + void __iomem *reg_addr; + + if (reg >= RMMIO_SIZE) + return; + + if (reg < ISP_MIPI_PHY0_REG0) + reg_addr = base + reg; + else if (reg <= ISP_MIPI_PHY0_REG0 + ISP_MIPI_PHY0_SIZE) + reg_addr = base + (reg - ISP_MIPI_PHY0_REG0); + else + return; + + writel(val, reg_addr); +}; diff --git a/drivers/media/platform/amd/isp4/isp4_hw.h b/drivers/media/platform/amd/isp4/isp4_hw.h new file mode 100644 index 000000000000..072d135b9e3a --- /dev/null +++ b/drivers/media/platform/amd/isp4/isp4_hw.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2025 Advanced Micro Devices, Inc. + */ + +#ifndef _ISP4_HW_H_ +#define _ISP4_HW_H_ + +#define RREG_FAILED_VAL 0xFFFFFFFF + +u32 isp4hw_rreg(void __iomem *base, u32 reg); +void isp4hw_wreg(void __iomem *base, u32 reg, u32 val); + +#endif diff --git a/drivers/media/platform/amd/isp4/isp4_hw_reg.h b/drivers/media/platform/amd/isp4/isp4_hw_reg.h new file mode 100644 index 000000000000..b11f12ba6c56 --- /dev/null +++ b/drivers/media/platform/amd/isp4/isp4_hw_reg.h @@ -0,0 +1,116 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2025 Advanced Micro Devices, Inc. + */ + +#ifndef _ISP4_HW_REG_H_ +#define _ISP4_HW_REG_H_ + +#define ISP_SOFT_RESET 0x62000 +#define ISP_SYS_INT0_EN 0x62010 +#define ISP_SYS_INT0_STATUS 0x62014 +#define ISP_SYS_INT0_ACK 0x62018 +#define ISP_CCPU_CNTL 0x62054 +#define ISP_STATUS 0x62058 +#define ISP_LOG_RB_BASE_LO0 0x62148 +#define ISP_LOG_RB_BASE_HI0 0x6214C +#define ISP_LOG_RB_SIZE0 0x62150 +#define ISP_LOG_RB_RPTR0 0x62154 +#define ISP_LOG_RB_WPTR0 0x62158 +#define ISP_RB_BASE_LO1 0x62170 +#define ISP_RB_BASE_HI1 0x62174 +#define ISP_RB_SIZE1 0x62178 +#define ISP_RB_RPTR1 0x6217C +#define ISP_RB_WPTR1 0x62180 +#define ISP_RB_BASE_LO2 0x62184 +#define ISP_RB_BASE_HI2 0x62188 +#define ISP_RB_SIZE2 0x6218C +#define ISP_RB_RPTR2 0x62190 +#define ISP_RB_WPTR2 0x62194 +#define ISP_RB_BASE_LO3 0x62198 +#define ISP_RB_BASE_HI3 0x6219C +#define ISP_RB_SIZE3 0x621A0 +#define ISP_RB_RPTR3 0x621A4 +#define ISP_RB_WPTR3 0x621A8 +#define ISP_RB_BASE_LO4 0x621AC +#define ISP_RB_BASE_HI4 0x621B0 +#define ISP_RB_SIZE4 0x621B4 +#define ISP_RB_RPTR4 0x621B8 +#define ISP_RB_WPTR4 0x621BC +#define ISP_RB_BASE_LO5 0x621C0 +#define ISP_RB_BASE_HI5 0x621C4 +#define ISP_RB_SIZE5 0x621C8 +#define ISP_RB_RPTR5 0x621CC +#define ISP_RB_WPTR5 0x621D0 +#define ISP_RB_BASE_LO6 0x621D4 +#define ISP_RB_BASE_HI6 0x621D8 +#define ISP_RB_SIZE6 0x621DC +#define ISP_RB_RPTR6 0x621E0 +#define ISP_RB_WPTR6 0x621E4 +#define ISP_RB_BASE_LO7 0x621E8 +#define ISP_RB_BASE_HI7 0x621EC +#define ISP_RB_SIZE7 0x621F0 +#define ISP_RB_RPTR7 0x621F4 +#define ISP_RB_WPTR7 0x621F8 +#define ISP_RB_BASE_LO8 0x621FC +#define ISP_RB_BASE_HI8 0x62200 +#define ISP_RB_SIZE8 0x62204 +#define ISP_RB_RPTR8 0x62208 +#define ISP_RB_WPTR8 0x6220C +#define ISP_RB_BASE_LO9 0x62210 +#define ISP_RB_BASE_HI9 0x62214 +#define ISP_RB_SIZE9 0x62218 +#define ISP_RB_RPTR9 0x6221C +#define ISP_RB_WPTR9 0x62220 +#define ISP_RB_BASE_LO10 0x62224 +#define ISP_RB_BASE_HI10 0x62228 +#define ISP_RB_SIZE10 0x6222C +#define ISP_RB_RPTR10 0x62230 +#define ISP_RB_WPTR10 0x62234 +#define ISP_RB_BASE_LO11 0x62238 +#define ISP_RB_BASE_HI11 0x6223C +#define ISP_RB_SIZE11 0x62240 +#define ISP_RB_RPTR11 0x62244 +#define ISP_RB_WPTR11 0x62248 +#define ISP_RB_BASE_LO12 0x6224C +#define ISP_RB_BASE_HI12 0x62250 +#define ISP_RB_SIZE12 0x62254 +#define ISP_RB_RPTR12 0x62258 +#define ISP_RB_WPTR12 0x6225C + +#define ISP_POWER_STATUS 0x60000 + +#define ISP_MIPI_PHY0_REG0 0x66700 +#define ISP_MIPI_PHY1_REG0 0x66780 +#define ISP_MIPI_PHY2_REG0 0x67400 + +#define ISP_MIPI_PHY0_SIZE 0xD30 + +/* ISP_SOFT_RESET */ +#define ISP_SOFT_RESET__CCPU_SOFT_RESET_MASK 0x00000001UL + +/* ISP_CCPU_CNTL */ +#define ISP_CCPU_CNTL__CCPU_HOST_SOFT_RST_MASK 0x00040000UL + +/* ISP_STATUS */ +#define ISP_STATUS__CCPU_REPORT_MASK 0x000000feUL + +/* ISP_SYS_INT0_STATUS */ +#define ISP_SYS_INT0_STATUS__SYS_INT_RINGBUFFER_WPT9_INT_MASK 0x00010000UL +#define ISP_SYS_INT0_STATUS__SYS_INT_RINGBUFFER_WPT10_INT_MASK 0x00040000UL +#define ISP_SYS_INT0_STATUS__SYS_INT_RINGBUFFER_WPT11_INT_MASK 0x00100000UL +#define ISP_SYS_INT0_STATUS__SYS_INT_RINGBUFFER_WPT12_INT_MASK 0x00400000UL + +/* ISP_SYS_INT0_EN */ +#define ISP_SYS_INT0_EN__SYS_INT_RINGBUFFER_WPT9_EN_MASK 0x00010000UL +#define ISP_SYS_INT0_EN__SYS_INT_RINGBUFFER_WPT10_EN_MASK 0x00040000UL +#define ISP_SYS_INT0_EN__SYS_INT_RINGBUFFER_WPT11_EN_MASK 0x00100000UL +#define ISP_SYS_INT0_EN__SYS_INT_RINGBUFFER_WPT12_EN_MASK 0x00400000UL + +/* ISP_SYS_INT0_ACK */ +#define ISP_SYS_INT0_ACK__SYS_INT_RINGBUFFER_WPT9_ACK_MASK 0x00010000UL +#define ISP_SYS_INT0_ACK__SYS_INT_RINGBUFFER_WPT10_ACK_MASK 0x00040000UL +#define ISP_SYS_INT0_ACK__SYS_INT_RINGBUFFER_WPT11_ACK_MASK 0x00100000UL +#define ISP_SYS_INT0_ACK__SYS_INT_RINGBUFFER_WPT12_ACK_MASK 0x00400000UL + +#endif From patchwork Sun Jun 8 14:49:10 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Du, Bin" X-Patchwork-Id: 895010 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2051.outbound.protection.outlook.com [40.107.243.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4C7E624E4DD; Sun, 8 Jun 2025 14:49:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.243.51 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749394198; cv=fail; b=XNl3HoF97RIDwuxMlhFHQYgqq4BmnuSw5jZfTRcIHrTPW1l4OAzXBe14d5eWIbD5OTUZPoBgIBG8EFpD7PlyY5l0Y761jQniogGd4jLezThGc8aazd0SQPJlpmasCeUVSiQB4RLCZQljo5gliKW/DXGPnTDNHy7JGbBkp+BMAfI= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749394198; c=relaxed/simple; bh=mfzX9me097Thinx6zRzKDi4hIMKBiHtef7enDYW38Ds=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=AH0urKWa0jHxORbJ7gf0n+aFGf3aHOK5dkYjqWFqSgrdW3UUU0bswW0IE/eKaGQ1AG6WLXaHXGDhqd2xOGc/W+2tgSa1bUC5C7Ga1a/qzDTbuzux1ktViyLPuzlLlDIo+RDt5cwuqf7jhERLemzKMrwaCSveJKWDoTUSNXEhLVk= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com; spf=fail smtp.mailfrom=amd.com; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b=oO4eanEE; arc=fail smtp.client-ip=40.107.243.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=amd.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="oO4eanEE" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=CtsUuJJKiwaOq80QVP7J4Uf+mv1ieNFHNNN2qseBtjhw1v/U6DBwGanOPcqmGmFfIhZQqDthaKdEizv71HbBGr2SmcYj051pa/ZAlAHpM3SzWqUAEBC3YJoshiAR8wIY9oiWFPerFNtj1Kj8swGeBHoXhiK29BkPIzpR7oaR+Y0vhQ2YSZDWntBr/D1R+2yY9SGAPQhrf+5/4sfFoBiWq//Mo9MqMDV7cFtAdV1jsyYgsuiuoQZFZrA2m1YY/mYNXJa7yiWXvANAFBlsXYJBC8mrSlV+CCGB+0ygD1rzXlhuDv4mdO+aLXldPFSuX5mKShjylf/H1+Vv+WDdzNRzNA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=t6JduJbEGc4iNdYiw2YQRYWJC2+L8pOjg+pRFqGZH78=; b=lZ7idkRhVtkwUlWrGoQqCIGXMAKFocABtELmU+9R6J6ESgJZjumxptvPzXIpWck+kFUJWWXaDxKiZ/Np00lfaK8RpKdBqnkKz8vQ5HA2MS2Ax8hbbBAdo9gSVZNd3BhBVoiqttHWeI4FE35hqXFeWkkX0WxW3pCjxamTJYw5GnK4thQ7nh9CKZMYxBl4v2HuUX14BFTAljAsJkasSLsdSame5qtQ+LenBktVPs+wn9vAy26AVKXG/SCEUoeHvAGK00g4rhzwNb4aXVWdoP6Cr88rIzGjaN99J04je/jbbFxB067V4jTYGRMMpk49PyIiKfPtFNGC9KR9KrFWDZSGSw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=t6JduJbEGc4iNdYiw2YQRYWJC2+L8pOjg+pRFqGZH78=; b=oO4eanEEtRlgd0DymGCbIHAugeXTEg37PM9yNWNrD3K/Mop9Y0WQVbGrY0UwKNTbNdZJg4a3ZT130W3/HkmJyVAKZYv40zTopTpLM/KpdpsLPcIyZSZDGC0Sioz7lBTjM4tMKA7W74qALLKjxUg3Cshmnzyymjg+8vio4aIuhIY= Received: from BY5PR03CA0006.namprd03.prod.outlook.com (2603:10b6:a03:1e0::16) by DS0PR12MB9323.namprd12.prod.outlook.com (2603:10b6:8:1b3::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8792.34; Sun, 8 Jun 2025 14:49:50 +0000 Received: from SJ5PEPF000001D4.namprd05.prod.outlook.com (2603:10b6:a03:1e0:cafe::5e) by BY5PR03CA0006.outlook.office365.com (2603:10b6:a03:1e0::16) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8769.18 via Frontend Transport; Sun, 8 Jun 2025 14:49:50 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SJ5PEPF000001D4.mail.protection.outlook.com (10.167.242.56) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8835.15 via Frontend Transport; Sun, 8 Jun 2025 14:49:50 +0000 Received: from 555e2b870847.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Sun, 8 Jun 2025 09:49:45 -0500 From: Bin Du To: , , , , , , , CC: , , , , , , , , "Bin Du" Subject: [PATCH v1 3/9] media: platform: amd: Add helpers to configure isp4 mipi phy Date: Sun, 8 Jun 2025 22:49:10 +0800 Message-ID: <20250608144916.222835-4-Bin.Du@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250608144916.222835-1-Bin.Du@amd.com> References: <20250608144916.222835-1-Bin.Du@amd.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001D4:EE_|DS0PR12MB9323:EE_ X-MS-Office365-Filtering-Correlation-Id: d50a78c5-0ba5-4c55-a437-08dda69bb886 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|376014|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: ZEKd9uwv2YF+gonBMMY4LED+VAGiwdfyO78R3YL4RCq6w5NtOw1ptKOTtHrEgHQyasIN874CaRu8vGURRXyx88XHHT1c6NgJfZOQogWY13G353QLM0uMvclks8ROOmiDI8A58mwbIeII05HEyfRBWHRVb/t75jVSXmEMN/rkLYpAsWH/NrHxMNH+NHwmwOSFFgIY/hT75rk+DsNxV/c9jsBx/sCDV44xCb+2GQHbe/oyaVfZ2gmHf8FqwmUn2XFrNAxgx8uyLBlnpfYy6c3NxYJzTXBn7as1lSdEXA4oJ5Hsmf3M3GY//OzbknS09Yn0Wc7LVDA/xX+XNqUYgwTMb2ymbauBksJD+moz25hA9fblVDTeLywvgpncIpXc6xtzE8jn4lUJ8Na/GqIGHXA4eqkoBSMxHMSJpixfXnAJgaP5nUlhA8Uf+Bc+8E8s1cc09OCRdh/p+hRlzu+sRtVMxyJyXDJFq1jEXNuEqoSjSuBM6csPKPEA2eWiTv8T670JtjIhdZttfcEXq3HpeivR9c6h2HTiGFBcnmXeT6n+EsBqdxeXz2/i2XkqGjjxvvDrV4VClsI8OKGI7i/mz+1SrXiUcLfMKz/aTrLfvwfXANDt+aQmkZTwUyLVSKF8mWPK4JV1sAww+/nGgbIk0dvdoyRfJuR4RGkUymM+i3xE8uJOI5Eqx8/WmhHMcTwSO1XB99Mz66dC44S3qjAcPj3H2BjUwMWbp0btf2UiytdEexArWzLYhl1hfvHvfYnhsnjYvJUyr5MOc6ps0iy7iTjSQcv6OB3YvS8wj0RIZ2RzO4mAbCt9QxN0y850StVh0kkFWLrKxqfoD0pavw6hNORMTzS3faOTiz71gXDB0IiRP1nCmdFK0leNJ4ciCKtoGz3KxgYjjGj3djR2SKk0C4xUst8DN+TKz17Sw24cJTvDc+KLUU50+bOwcxYl5wErHm/0qRcDfkpXkE75nEZRWWuJHeDIWUDOO+/kKDjFYB1imViqldv890ng+oGKCHlpaJio7CyEBRv+hJbZ3Dn6NBE7vvqOn1GCnZsG1TdhKZcGbwLn9mDcJoAs00/XObNtHp2Bq46hGt1yrzcq4Bpbv4bJKoCOWjPnTEfX3Jj8AsKpEXHWeJ430HDJbGzhBtwpH4iwPUxgD5fr995jXmi/HpuUppLrZXNDDKewp+1RMTjGfQEYJgXJK+fendEzGVygjXnZFqUuLu3Ct+JC/lJh/xhJSmAjn+0vyoMDXxLmfeZ0MVXaUakPa52OBm5/mLuaPTlJIT6INlWrKr2S3CgbB7KMTiohBZycCrOwXsxwvYJ+BTCmV3g4zwo68WNnuK4SCJC6E58EmZHYM5H9/VntrBaK4+j1O0lZT/Fjm+lDECwanhWa45eFAWkHYGmnyhSTzVxNOjP/K5ZihZYqz9Wfj03X9ib8GZdun4ueJym9FPJ/N8w5tcNJOxXYw7UAtFSmzFhwQ3P8YKNObHgvvNwLdBDi4ZVFuRyeAZdurkuPNTm4SU3b0mHzDop+jr4lnDbjXmKF X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(1800799024)(376014)(82310400026)(36860700013); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jun 2025 14:49:50.1178 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d50a78c5-0ba5-4c55-a437-08dda69bb886 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001D4.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB9323 The helper functions is for configuring, starting and stop the MIPI PHY. All configurations related to MIPI PHY configuration and calibration parameters are encapsulated in two helper functions: start and stop mipi phy. Signed-off-by: Bin Du Signed-off-by: Svetoslav Stoilov Change-Id: I5376794eb4e4116e1387e4f3607cdf6845f2cda4 --- drivers/media/platform/amd/isp4/Makefile | 1 + drivers/media/platform/amd/isp4/isp4_phy.c | 1507 ++++++++++++++++++++ drivers/media/platform/amd/isp4/isp4_phy.h | 14 + 3 files changed, 1522 insertions(+) create mode 100644 drivers/media/platform/amd/isp4/isp4_phy.c create mode 100644 drivers/media/platform/amd/isp4/isp4_phy.h diff --git a/drivers/media/platform/amd/isp4/Makefile b/drivers/media/platform/amd/isp4/Makefile index 4ef8be329d56..7cb496a56353 100644 --- a/drivers/media/platform/amd/isp4/Makefile +++ b/drivers/media/platform/amd/isp4/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_AMD_ISP4) += amd_capture.o amd_capture-objs := isp4.o \ + isp4_phy.o \ isp4_hw.o \ ccflags-y += -I$(srctree)/drivers/media/platform/amd/isp4 diff --git a/drivers/media/platform/amd/isp4/isp4_phy.c b/drivers/media/platform/amd/isp4/isp4_phy.c new file mode 100644 index 000000000000..1cf2eb58ea3b --- /dev/null +++ b/drivers/media/platform/amd/isp4/isp4_phy.c @@ -0,0 +1,1507 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2025 Advanced Micro Devices, Inc. + */ + +#include +#include + +#include "isp4_hw.h" +#include "isp4_hw_reg.h" +#include "isp4_phy.h" + +#define ISP_MIPI_DPHY 0 +#define T_DCO 5 /* nominal: 200MHz */ +#define TMIN_RX 4 +#define TIMEBASE 5 /* 5us */ + +#define MIN_T_HS_SETTLE_NS 95 +#define MAX_T_HS_SETTLE_NS 130 +#define MIN_T_HS_SETTLE_UI 4 +#define MAX_T_HS_SETTLE_UI 6 + +#define PPI_STARTUP_RW_COMMON_DPHY_2 0x0C02 +#define PPI_STARTUP_RW_COMMON_DPHY_6 0x0C06 +#define PPI_STARTUP_RW_COMMON_DPHY_7 0x0C07 +#define PPI_STARTUP_RW_COMMON_DPHY_8 0x0C08 +#define PPI_STARTUP_RW_COMMON_DPHY_10 0x0C10 +#define CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_2 0x1CF2 +#define CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_0 0x1CF0 +#define PPI_STARTUP_RW_COMMON_STARTUP_1_1 0x0C11 +#define PPI_CALIBCTRL_RW_COMMON_BG_0 0x0C26 +#define PPI_RW_LPDCOCAL_NREF 0x0E02 +#define PPI_RW_LPDCOCAL_NREF_RANGE 0x0E03 +#define PPI_RW_LPDCOCAL_TWAIT_CONFIG 0x0E05 +#define PPI_RW_LPDCOCAL_VT_CONFIG 0x0E06 +#define PPI_RW_LPDCOCAL_COARSE_CFG 0x0E08 +#define PPI_RW_COMMON_CFG 0x0E36 +#define PPI_RW_TERMCAL_CFG_0 0x0E40 +#define PPI_RW_OFFSETCAL_CFG_0 0x0E50 +#define PPI_RW_LPDCOCAL_TIMEBASE 0x0E01 +#define CORE_AFE_CTRL_2_0 0x1C20 +#define CORE_AFE_CTRL_2_1 0x1C21 +#define CORE_AFE_CTRL_2_3 0x1C23 +#define CORE_AFE_CTRL_2_5 0x1C25 +#define CORE_AFE_CTRL_2_6 0x1C26 +#define CORE_AFE_CTRL_2_7 0x1C27 +#define CORE_DIG_COMMON_RW_DESKEW_FINE_MEM 0x1FF0 +#define CORE_DIG_DLANE_CLK_RW_CFG_0 0x3800 +#define CORE_DIG_DLANE_0_RW_CFG_0 0x3000 +#define CORE_DIG_DLANE_1_RW_CFG_0 0x3200 +#define CORE_DIG_DLANE_2_RW_CFG_0 0x3400 +#define CORE_DIG_DLANE_3_RW_CFG_0 0x3600 +#define CORE_AFE_LANE0_CTRL_2_9 0x1029 +#define CORE_AFE_LANE1_CTRL_2_9 0x1229 +#define CORE_AFE_LANE2_CTRL_2_9 0x1429 +#define CORE_AFE_LANE3_CTRL_2_9 0x1629 +#define CORE_AFE_LANE4_CTRL_2_9 0x1829 +#define CORE_DIG_RW_COMMON_6 0x1C46 +#define CORE_DIG_RW_COMMON_7 0x1C47 +#define PPI_RW_DDLCAL_CFG_0 0x0E20 +#define PPI_RW_DDLCAL_CFG_1 0x0E21 +#define PPI_RW_DDLCAL_CFG_2 0x0E22 +#define PPI_RW_DDLCAL_CFG_3 0x0E23 +#define PPI_RW_DDLCAL_CFG_4 0x0E24 +#define PPI_RW_DDLCAL_CFG_5 0x0E25 +#define PPI_RW_DDLCAL_CFG_6 0x0E26 +#define PPI_RW_DDLCAL_CFG_7 0x0E27 +#define CORE_AFE_LANE0_CTRL_2_8 0x1028 +#define CORE_AFE_LANE1_CTRL_2_8 0x1228 +#define CORE_AFE_LANE2_CTRL_2_8 0x1428 +#define CORE_AFE_LANE3_CTRL_2_8 0x1628 +#define CORE_AFE_LANE4_CTRL_2_8 0x1828 +#define CORE_DIG_DLANE_0_RW_LP_0 0x3040 +#define CORE_DIG_DLANE_1_RW_LP_0 0x3240 +#define CORE_DIG_DLANE_2_RW_LP_0 0x3440 +#define CORE_DIG_DLANE_3_RW_LP_0 0x3640 +#define CORE_AFE_LANE0_CTRL_2_2 0x1022 +#define CORE_AFE_LANE1_CTRL_2_2 0x1222 +#define CORE_AFE_LANE2_CTRL_2_2 0x1422 +#define CORE_AFE_LANE3_CTRL_2_2 0x1622 +#define CORE_AFE_LANE4_CTRL_2_2 0x1822 +#define CORE_AFE_LANE0_CTRL_2_12 0x102C +#define CORE_AFE_LANE1_CTRL_2_12 0x122C +#define CORE_AFE_LANE2_CTRL_2_12 0x142C +#define CORE_AFE_LANE3_CTRL_2_12 0x162C +#define CORE_AFE_LANE4_CTRL_2_12 0x182C +#define CORE_AFE_LANE0_CTRL_2_13 0x102D +#define CORE_AFE_LANE1_CTRL_2_13 0x122D +#define CORE_AFE_LANE2_CTRL_2_13 0x142D +#define CORE_AFE_LANE3_CTRL_2_13 0x162D +#define CORE_AFE_LANE4_CTRL_2_13 0x182D +#define CORE_DIG_DLANE_CLK_RW_HS_RX_0 0x3880 +#define CORE_DIG_DLANE_CLK_RW_HS_RX_7 0x3887 +#define CORE_DIG_DLANE_0_RW_HS_RX_0 0x3080 +#define CORE_DIG_DLANE_1_RW_HS_RX_0 0x3280 +#define CORE_DIG_DLANE_2_RW_HS_RX_0 0x3480 +#define CORE_DIG_DLANE_3_RW_HS_RX_0 0x3680 +#define CORE_DIG_DLANE_0_RW_CFG_1 0x3001 +#define CORE_DIG_DLANE_1_RW_CFG_1 0x3201 +#define CORE_DIG_DLANE_2_RW_CFG_1 0x3401 +#define CORE_DIG_DLANE_3_RW_CFG_1 0x3601 +#define CORE_DIG_DLANE_0_RW_HS_RX_2 0x3082 +#define CORE_DIG_DLANE_1_RW_HS_RX_2 0x3282 +#define CORE_DIG_DLANE_2_RW_HS_RX_2 0x3482 +#define CORE_DIG_DLANE_3_RW_HS_RX_2 0x3682 +#define CORE_DIG_DLANE_0_RW_LP_2 0x3042 +#define CORE_DIG_DLANE_1_RW_LP_2 0x3242 +#define CORE_DIG_DLANE_2_RW_LP_2 0x3442 +#define CORE_DIG_DLANE_3_RW_LP_2 0x3642 +#define CORE_DIG_DLANE_CLK_RW_LP_0 0x3840 +#define CORE_DIG_DLANE_CLK_RW_LP_2 0x3842 +#define CORE_DIG_DLANE_0_RW_HS_RX_1 0x3081 +#define CORE_DIG_DLANE_1_RW_HS_RX_1 0x3281 +#define CORE_DIG_DLANE_2_RW_HS_RX_1 0x3481 +#define CORE_DIG_DLANE_3_RW_HS_RX_1 0x3681 +#define CORE_DIG_DLANE_0_RW_HS_RX_3 0x3083 +#define CORE_DIG_DLANE_1_RW_HS_RX_3 0x3283 +#define CORE_DIG_DLANE_2_RW_HS_RX_3 0x3483 +#define CORE_DIG_DLANE_3_RW_HS_RX_3 0x3683 +#define CORE_DIG_DLANE_0_RW_HS_RX_4 0x3084 +#define CORE_DIG_DLANE_1_RW_HS_RX_4 0x3284 +#define CORE_DIG_DLANE_2_RW_HS_RX_4 0x3484 +#define CORE_DIG_DLANE_3_RW_HS_RX_4 0x3684 +#define CORE_DIG_DLANE_0_RW_HS_RX_5 0x3085 +#define CORE_DIG_DLANE_1_RW_HS_RX_5 0x3285 +#define CORE_DIG_DLANE_2_RW_HS_RX_5 0x3485 +#define CORE_DIG_DLANE_3_RW_HS_RX_5 0x3685 +#define CORE_DIG_DLANE_0_RW_HS_RX_6 0x3086 +#define CORE_DIG_DLANE_1_RW_HS_RX_6 0x3286 +#define CORE_DIG_DLANE_2_RW_HS_RX_6 0x3486 +#define CORE_DIG_DLANE_3_RW_HS_RX_6 0x3686 +#define CORE_DIG_DLANE_0_RW_HS_RX_7 0x3087 +#define CORE_DIG_DLANE_1_RW_HS_RX_7 0x3287 +#define CORE_DIG_DLANE_2_RW_HS_RX_7 0x3487 +#define CORE_DIG_DLANE_3_RW_HS_RX_7 0x3687 +#define CORE_DIG_DLANE_0_RW_HS_RX_9 0x3089 +#define CORE_DIG_DLANE_1_RW_HS_RX_9 0x3289 +#define CORE_DIG_DLANE_2_RW_HS_RX_9 0x3489 +#define CORE_DIG_DLANE_3_RW_HS_RX_9 0x3689 +#define PPI_R_TERMCAL_DEBUG_0 0x0E41 + +#define PPI_STARTUP_RW_COMMON_DPHY_2_RCAL_ADDR_MASK 0x00FF +#define PPI_STARTUP_RW_COMMON_DPHY_10_PHY_READY_ADDR_MASK 0x00FF +#define CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_2_GLOBAL_ULPS_OVR_VAL_MASK 0x2000 +#define CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_2_GLOBAL_ULPS_OVR_EN_MASK 0x1000 +#define CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_0_CB_LP_DCO_EN_DLY_MASK 0x00FC +#define PPI_STARTUP_RW_COMMON_STARTUP_1_1_PHY_READY_DLY_MASK 0x0FFF +#define PPI_STARTUP_RW_COMMON_DPHY_6_LP_DCO_CAL_ADDR_MASK 0x00FF +#define PPI_CALIBCTRL_RW_COMMON_BG_0_BG_MAX_COUNTER_MASK 0x01FF +#define PPI_RW_LPDCOCAL_NREF_LPDCOCAL_NREF_MASK 0x07FF +#define PPI_RW_LPDCOCAL_NREF_RANGE_LPDCOCAL_NREF_RANGE_MASK 0x001F +#define PPI_RW_LPDCOCAL_TWAIT_CONFIG_LPDCOCAL_TWAIT_PON_MASK 0xFE00 +#define PPI_RW_LPDCOCAL_VT_CONFIG_LPDCOCAL_VT_TRACKING_EN_MASK 0x0001 +#define PPI_RW_LPDCOCAL_VT_CONFIG_LPDCOCAL_USE_IDEAL_NREF_MASK 0x0002 +#define PPI_RW_LPDCOCAL_VT_CONFIG_LPDCOCAL_VT_NREF_RANGE_MASK 0x007C +#define PPI_RW_LPDCOCAL_COARSE_CFG_NCOARSE_START_MASK 0x0003 +#define PPI_RW_COMMON_CFG_CFG_CLK_DIV_FACTOR_MASK 0x0003 +#define PPI_RW_TERMCAL_CFG_0_TERMCAL_TIMER_MASK 0x007F +#define PPI_RW_OFFSETCAL_CFG_0_OFFSETCAL_WAIT_THRESH_MASK 0x001F +#define PPI_RW_LPDCOCAL_TIMEBASE_LPDCOCAL_TIMEBASE_MASK 0x03FF +#define PPI_RW_LPDCOCAL_TWAIT_CONFIG_LPDCOCAL_TWAIT_COARSE_MASK 0x01FF +#define PPI_RW_LPDCOCAL_VT_CONFIG_LPDCOCAL_TWAIT_FINE_MASK 0xFF80 +#define CORE_AFE_CTRL_2_0_OA_CB_HSTX_VCOMM_REG_PON_OVR_VAL_MASK 0x0400 +#define CORE_AFE_CTRL_2_1_OA_CB_HSTX_VCOMM_REG_PON_OVR_EN_MASK 0x0400 +#define CORE_AFE_CTRL_2_1_OA_CB_HSTXLB_DCO_CLK0_EN_OVR_VAL_MASK 0x8000 +#define CORE_AFE_CTRL_2_3_OA_CB_HSTXLB_DCO_CLK0_EN_OVR_EN_MASK 0x0100 +#define CORE_AFE_CTRL_2_0_OA_CB_HSTXLB_DCO_CLK90_EN_OVR_VAL_MASK 0x8000 +#define CORE_AFE_CTRL_2_3_OA_CB_HSTXLB_DCO_CLK90_EN_OVR_EN_MASK 0x0200 +#define CORE_AFE_CTRL_2_6_OA_CB_HSTXLB_DCO_EN_OVR_EN_MASK 0x2000 +#define CORE_AFE_CTRL_2_7_OA_CB_HSTXLB_DCO_EN_OVR_VAL_MASK 0x0200 +#define CORE_AFE_CTRL_2_6_OA_CB_HSTXLB_DCO_PON_OVR_EN_MASK 0x1000 +#define CORE_AFE_CTRL_2_7_OA_CB_HSTXLB_DCO_PON_OVR_VAL_MASK 0x0100 +#define CORE_AFE_CTRL_2_6_OA_CB_HSTXLB_DCO_TUNE_CLKDIG_EN_OVR_EN_MASK 0x4000 +#define CORE_AFE_CTRL_2_7_OA_CB_HSTXLB_DCO_TUNE_CLKDIG_EN_OVR_VAL_MASK 0x0400 +#define CORE_AFE_CTRL_2_5_OA_CB_SEL_45OHM_50OHM_MASK 0x0100 +#define CORE_DIG_DLANE_CLK_RW_CFG_0_CFG_0_LP_PIN_SWAP_REG_MASK 0x0001 +#define CORE_DIG_DLANE_0_RW_CFG_0_CFG_0_LP_PIN_SWAP_REG_MASK 0x0001 +#define CORE_DIG_DLANE_1_RW_CFG_0_CFG_0_LP_PIN_SWAP_REG_MASK 0x0001 +#define CORE_DIG_DLANE_2_RW_CFG_0_CFG_0_LP_PIN_SWAP_REG_MASK 0x0001 +#define CORE_DIG_DLANE_3_RW_CFG_0_CFG_0_LP_PIN_SWAP_REG_MASK 0x0001 +#define CORE_DIG_DLANE_0_RW_CFG_0_CFG_0_HS_PIN_SWAP_REG_MASK 0x0002 +#define CORE_DIG_DLANE_1_RW_CFG_0_CFG_0_HS_PIN_SWAP_REG_MASK 0x0002 +#define CORE_DIG_DLANE_2_RW_CFG_0_CFG_0_HS_PIN_SWAP_REG_MASK 0x0002 +#define CORE_DIG_DLANE_3_RW_CFG_0_CFG_0_HS_PIN_SWAP_REG_MASK 0x0002 +#define CORE_AFE_LANE0_CTRL_2_9_OA_LANE0_HSRX_SEL_GATED_POLARITY_MASK 0x0100 +#define CORE_AFE_LANE1_CTRL_2_9_OA_LANE1_HSRX_SEL_GATED_POLARITY_MASK 0x0100 +#define CORE_AFE_LANE2_CTRL_2_9_OA_LANE2_HSRX_SEL_GATED_POLARITY_MASK 0x0100 +#define CORE_AFE_LANE3_CTRL_2_9_OA_LANE3_HSRX_SEL_GATED_POLARITY_MASK 0x0100 +#define CORE_AFE_LANE4_CTRL_2_9_OA_LANE4_HSRX_SEL_GATED_POLARITY_MASK 0x0100 +#define CORE_DIG_RW_COMMON_7_LANE0_HSRX_WORD_CLK_SEL_GATING_REG_MASK 0x0003 +#define CORE_DIG_RW_COMMON_7_LANE1_HSRX_WORD_CLK_SEL_GATING_REG_MASK 0x000C +#define CORE_DIG_RW_COMMON_7_LANE2_HSRX_WORD_CLK_SEL_GATING_REG_MASK 0x0030 +#define CORE_DIG_RW_COMMON_7_LANE3_HSRX_WORD_CLK_SEL_GATING_REG_MASK 0x00C0 +#define CORE_DIG_RW_COMMON_7_LANE4_HSRX_WORD_CLK_SEL_GATING_REG_MASK 0x0300 +#define PPI_STARTUP_RW_COMMON_DPHY_8_CPHY_DDL_CAL_ADDR_MASK 0x00FF +#define PPI_STARTUP_RW_COMMON_DPHY_7_DPHY_DDL_CAL_ADDR_MASK 0x00FF +#define PPI_RW_DDLCAL_CFG_0_DDLCAL_TIMEBASE_TARGET_MASK 0x03FF +#define PPI_RW_DDLCAL_CFG_7_DDLCAL_DECR_WAIT_MASK 0x1F80 +#define PPI_RW_DDLCAL_CFG_1_DDLCAL_DISABLE_TIME_MASK 0xFF00 +#define PPI_RW_DDLCAL_CFG_2_DDLCAL_WAIT_MASK 0xF000 +#define PPI_RW_DDLCAL_CFG_2_DDLCAL_TUNE_MODE_MASK 0x0C00 +#define PPI_RW_DDLCAL_CFG_2_DDLCAL_DDL_DLL_MASK 0x0100 +#define PPI_RW_DDLCAL_CFG_2_DDLCAL_ENABLE_WAIT_MASK 0x00FF +#define PPI_RW_DDLCAL_CFG_2_DDLCAL_UPDATE_SETTINGS_MASK 0x0200 +#define PPI_RW_DDLCAL_CFG_4_DDLCAL_STUCK_THRESH_MASK 0x03FF +#define PPI_RW_DDLCAL_CFG_6_DDLCAL_MAX_DIFF_MASK 0x03FF +#define PPI_RW_DDLCAL_CFG_7_DDLCAL_START_DELAY_MASK 0x007F +#define PPI_RW_DDLCAL_CFG_3_DDLCAL_COUNTER_REF_MASK 0x03FF +#define PPI_RW_DDLCAL_CFG_1_DDLCAL_MAX_PHASE_MASK 0x00FF +#define PPI_RW_DDLCAL_CFG_5_DDLCAL_DLL_FBK_MASK 0x03F0 +#define PPI_RW_DDLCAL_CFG_5_DDLCAL_DDL_COARSE_BANK_MASK 0x000F +#define CORE_AFE_LANE0_CTRL_2_8_OA_LANE0_HSRX_CDPHY_SEL_FAST_MASK 0x1000 +#define CORE_AFE_LANE1_CTRL_2_8_OA_LANE1_HSRX_CDPHY_SEL_FAST_MASK 0x1000 +#define CORE_AFE_LANE2_CTRL_2_8_OA_LANE2_HSRX_CDPHY_SEL_FAST_MASK 0x1000 +#define CORE_AFE_LANE3_CTRL_2_8_OA_LANE3_HSRX_CDPHY_SEL_FAST_MASK 0x1000 +#define CORE_AFE_LANE4_CTRL_2_8_OA_LANE4_HSRX_CDPHY_SEL_FAST_MASK 0x1000 +#define CORE_DIG_DLANE_0_RW_LP_0_LP_0_TTAGO_REG_MASK 0x0F00 +#define CORE_DIG_DLANE_1_RW_LP_0_LP_0_TTAGO_REG_MASK 0x0F00 +#define CORE_DIG_DLANE_2_RW_LP_0_LP_0_TTAGO_REG_MASK 0x0F00 +#define CORE_DIG_DLANE_3_RW_LP_0_LP_0_TTAGO_REG_MASK 0x0F00 +#define CORE_AFE_LANE0_CTRL_2_2_OA_LANE0_SEL_LANE_CFG_MASK 0x0001 +#define CORE_AFE_LANE1_CTRL_2_2_OA_LANE1_SEL_LANE_CFG_MASK 0x0001 +#define CORE_AFE_LANE2_CTRL_2_2_OA_LANE2_SEL_LANE_CFG_MASK 0x0001 +#define CORE_AFE_LANE3_CTRL_2_2_OA_LANE3_SEL_LANE_CFG_MASK 0x0001 +#define CORE_AFE_LANE4_CTRL_2_2_OA_LANE4_SEL_LANE_CFG_MASK 0x0001 +#define CORE_DIG_RW_COMMON_6_DESERIALIZER_EN_DEASS_COUNT_THRESH_D_MASK 0x0038 +#define CORE_DIG_RW_COMMON_6_DESERIALIZER_DIV_EN_DELAY_THRESH_D_MASK 0x0007 +#define CORE_AFE_LANE0_CTRL_2_12_OA_LANE0_HSRX_DPHY_DDL_BYPASS_EN_OVR_VAL_MASK 0x0002 +#define CORE_AFE_LANE1_CTRL_2_12_OA_LANE1_HSRX_DPHY_DDL_BYPASS_EN_OVR_VAL_MASK 0x0002 +#define CORE_AFE_LANE2_CTRL_2_12_OA_LANE2_HSRX_DPHY_DDL_BYPASS_EN_OVR_VAL_MASK 0x0002 +#define CORE_AFE_LANE3_CTRL_2_12_OA_LANE3_HSRX_DPHY_DDL_BYPASS_EN_OVR_VAL_MASK 0x0002 +#define CORE_AFE_LANE4_CTRL_2_12_OA_LANE4_HSRX_DPHY_DDL_BYPASS_EN_OVR_VAL_MASK 0x0002 +#define CORE_AFE_LANE0_CTRL_2_13_OA_LANE0_HSRX_DPHY_DDL_BYPASS_EN_OVR_EN_MASK 0x0002 +#define CORE_AFE_LANE1_CTRL_2_13_OA_LANE1_HSRX_DPHY_DDL_BYPASS_EN_OVR_EN_MASK 0x0002 +#define CORE_AFE_LANE2_CTRL_2_13_OA_LANE2_HSRX_DPHY_DDL_BYPASS_EN_OVR_EN_MASK 0x0002 +#define CORE_AFE_LANE3_CTRL_2_13_OA_LANE3_HSRX_DPHY_DDL_BYPASS_EN_OVR_EN_MASK 0x0002 +#define CORE_AFE_LANE4_CTRL_2_13_OA_LANE4_HSRX_DPHY_DDL_BYPASS_EN_OVR_EN_MASK 0x0002 +#define CORE_AFE_LANE0_CTRL_2_12_OA_LANE0_HSRX_DPHY_DLL_EN_OVR_VAL_MASK 0x0008 +#define CORE_AFE_LANE1_CTRL_2_12_OA_LANE1_HSRX_DPHY_DLL_EN_OVR_VAL_MASK 0x0008 +#define CORE_AFE_LANE2_CTRL_2_12_OA_LANE2_HSRX_DPHY_DLL_EN_OVR_VAL_MASK 0x0008 +#define CORE_AFE_LANE3_CTRL_2_12_OA_LANE3_HSRX_DPHY_DLL_EN_OVR_VAL_MASK 0x0008 +#define CORE_AFE_LANE4_CTRL_2_12_OA_LANE4_HSRX_DPHY_DLL_EN_OVR_VAL_MASK 0x0008 +#define CORE_AFE_LANE0_CTRL_2_13_OA_LANE0_HSRX_DPHY_DLL_EN_OVR_EN_MASK 0x0008 +#define CORE_AFE_LANE1_CTRL_2_13_OA_LANE1_HSRX_DPHY_DLL_EN_OVR_EN_MASK 0x0008 +#define CORE_AFE_LANE2_CTRL_2_13_OA_LANE2_HSRX_DPHY_DLL_EN_OVR_EN_MASK 0x0008 +#define CORE_AFE_LANE3_CTRL_2_13_OA_LANE3_HSRX_DPHY_DLL_EN_OVR_EN_MASK 0x0008 +#define CORE_AFE_LANE4_CTRL_2_13_OA_LANE4_HSRX_DPHY_DLL_EN_OVR_EN_MASK 0x0008 +#define CORE_AFE_LANE2_CTRL_2_9_OA_LANE2_HSRX_HS_CLK_DIV_MASK 0x00E0 +#define CORE_AFE_LANE1_CTRL_2_9_OA_LANE1_HSRX_HS_CLK_DIV_MASK 0x00E0 +#define CORE_DIG_DLANE_CLK_RW_HS_RX_0_HS_RX_0_TCLKSETTLE_REG_MASK 0x00FF +#define CORE_DIG_DLANE_CLK_RW_HS_RX_7_HS_RX_7_TCLKMISS_REG_MASK 0x00FF +#define CORE_DIG_DLANE_0_RW_HS_RX_0_HS_RX_0_THSSETTLE_REG_MASK 0xFF00 +#define CORE_DIG_DLANE_1_RW_HS_RX_0_HS_RX_0_THSSETTLE_REG_MASK 0xFF00 +#define CORE_DIG_DLANE_2_RW_HS_RX_0_HS_RX_0_THSSETTLE_REG_MASK 0xFF00 +#define CORE_DIG_DLANE_3_RW_HS_RX_0_HS_RX_0_THSSETTLE_REG_MASK 0xFF00 +#define CORE_DIG_DLANE_0_RW_CFG_1_CFG_1_DESKEW_SUPPORTED_REG_MASK 0x0004 +#define CORE_DIG_DLANE_1_RW_CFG_1_CFG_1_DESKEW_SUPPORTED_REG_MASK 0x0004 +#define CORE_DIG_DLANE_2_RW_CFG_1_CFG_1_DESKEW_SUPPORTED_REG_MASK 0x0004 +#define CORE_DIG_DLANE_3_RW_CFG_1_CFG_1_DESKEW_SUPPORTED_REG_MASK 0x0004 +#define CORE_DIG_DLANE_0_RW_CFG_1_CFG_1_SOT_DETECTION_REG_MASK 0x0008 +#define CORE_DIG_DLANE_1_RW_CFG_1_CFG_1_SOT_DETECTION_REG_MASK 0x0008 +#define CORE_DIG_DLANE_2_RW_CFG_1_CFG_1_SOT_DETECTION_REG_MASK 0x0008 +#define CORE_DIG_DLANE_3_RW_CFG_1_CFG_1_SOT_DETECTION_REG_MASK 0x0008 +#define CORE_DIG_DLANE_0_RW_HS_RX_2_HS_RX_2_IGNORE_ALTERNCAL_REG_MASK 0x8000 +#define CORE_DIG_DLANE_1_RW_HS_RX_2_HS_RX_2_IGNORE_ALTERNCAL_REG_MASK 0x8000 +#define CORE_DIG_DLANE_2_RW_HS_RX_2_HS_RX_2_IGNORE_ALTERNCAL_REG_MASK 0x8000 +#define CORE_DIG_DLANE_3_RW_HS_RX_2_HS_RX_2_IGNORE_ALTERNCAL_REG_MASK 0x8000 +#define CORE_DIG_DLANE_0_RW_LP_0_LP_0_ITMINRX_REG_MASK 0xF000 +#define CORE_DIG_DLANE_1_RW_LP_0_LP_0_ITMINRX_REG_MASK 0xF000 +#define CORE_DIG_DLANE_2_RW_LP_0_LP_0_ITMINRX_REG_MASK 0xF000 +#define CORE_DIG_DLANE_3_RW_LP_0_LP_0_ITMINRX_REG_MASK 0xF000 +#define CORE_DIG_DLANE_0_RW_LP_2_LP_2_FILTER_INPUT_SAMPLING_REG_MASK 0x0001 +#define CORE_DIG_DLANE_1_RW_LP_2_LP_2_FILTER_INPUT_SAMPLING_REG_MASK 0x0001 +#define CORE_DIG_DLANE_2_RW_LP_2_LP_2_FILTER_INPUT_SAMPLING_REG_MASK 0x0001 +#define CORE_DIG_DLANE_3_RW_LP_2_LP_2_FILTER_INPUT_SAMPLING_REG_MASK 0x0001 +#define CORE_DIG_DLANE_CLK_RW_LP_0_LP_0_ITMINRX_REG_MASK 0xF000 +#define CORE_DIG_DLANE_CLK_RW_LP_2_LP_2_FILTER_INPUT_SAMPLING_REG_MASK 0x0001 +#define CORE_DIG_DLANE_0_RW_HS_RX_2_HS_RX_2_UPDATE_SETTINGS_DESKEW_REG_MASK 0x2000 +#define CORE_DIG_DLANE_1_RW_HS_RX_2_HS_RX_2_UPDATE_SETTINGS_DESKEW_REG_MASK 0x2000 +#define CORE_DIG_DLANE_2_RW_HS_RX_2_HS_RX_2_UPDATE_SETTINGS_DESKEW_REG_MASK 0x2000 +#define CORE_DIG_DLANE_3_RW_HS_RX_2_HS_RX_2_UPDATE_SETTINGS_DESKEW_REG_MASK 0x2000 +#define CORE_DIG_DLANE_0_RW_HS_RX_1_HS_RX_1_FILTER_SIZE_DESKEW_REG_MASK 0x00FF +#define CORE_DIG_DLANE_1_RW_HS_RX_1_HS_RX_1_FILTER_SIZE_DESKEW_REG_MASK 0x00FF +#define CORE_DIG_DLANE_2_RW_HS_RX_1_HS_RX_1_FILTER_SIZE_DESKEW_REG_MASK 0x00FF +#define CORE_DIG_DLANE_3_RW_HS_RX_1_HS_RX_1_FILTER_SIZE_DESKEW_REG_MASK 0x00FF +#define CORE_DIG_DLANE_0_RW_HS_RX_2_HS_RX_2_WINDOW_SIZE_DESKEW_REG_MASK 0x1E00 +#define CORE_DIG_DLANE_1_RW_HS_RX_2_HS_RX_2_WINDOW_SIZE_DESKEW_REG_MASK 0x1E00 +#define CORE_DIG_DLANE_2_RW_HS_RX_2_HS_RX_2_WINDOW_SIZE_DESKEW_REG_MASK 0x1E00 +#define CORE_DIG_DLANE_3_RW_HS_RX_2_HS_RX_2_WINDOW_SIZE_DESKEW_REG_MASK 0x1E00 +#define CORE_DIG_DLANE_0_RW_HS_RX_3_HS_RX_3_STEP_SIZE_DESKEW_REG_MASK 0x0007 +#define CORE_DIG_DLANE_1_RW_HS_RX_3_HS_RX_3_STEP_SIZE_DESKEW_REG_MASK 0x0007 +#define CORE_DIG_DLANE_2_RW_HS_RX_3_HS_RX_3_STEP_SIZE_DESKEW_REG_MASK 0x0007 +#define CORE_DIG_DLANE_3_RW_HS_RX_3_HS_RX_3_STEP_SIZE_DESKEW_REG_MASK 0x0007 +#define CORE_DIG_DLANE_0_RW_HS_RX_4_HS_RX_4_MAX_ITERATIONS_DESKEW_REG_MASK 0xFFFF +#define CORE_DIG_DLANE_1_RW_HS_RX_4_HS_RX_4_MAX_ITERATIONS_DESKEW_REG_MASK 0xFFFF +#define CORE_DIG_DLANE_2_RW_HS_RX_4_HS_RX_4_MAX_ITERATIONS_DESKEW_REG_MASK 0xFFFF +#define CORE_DIG_DLANE_3_RW_HS_RX_4_HS_RX_4_MAX_ITERATIONS_DESKEW_REG_MASK 0xFFFF +#define CORE_DIG_DLANE_0_RW_HS_RX_5_HS_RX_5_DDL_LEFT_INIT_REG_MASK 0x00FF +#define CORE_DIG_DLANE_1_RW_HS_RX_5_HS_RX_5_DDL_LEFT_INIT_REG_MASK 0x00FF +#define CORE_DIG_DLANE_2_RW_HS_RX_5_HS_RX_5_DDL_LEFT_INIT_REG_MASK 0x00FF +#define CORE_DIG_DLANE_3_RW_HS_RX_5_HS_RX_5_DDL_LEFT_INIT_REG_MASK 0x00FF +#define CORE_DIG_DLANE_0_RW_HS_RX_5_HS_RX_5_DDL_MID_INIT_REG_MASK 0xFF00 +#define CORE_DIG_DLANE_1_RW_HS_RX_5_HS_RX_5_DDL_MID_INIT_REG_MASK 0xFF00 +#define CORE_DIG_DLANE_2_RW_HS_RX_5_HS_RX_5_DDL_MID_INIT_REG_MASK 0xFF00 +#define CORE_DIG_DLANE_3_RW_HS_RX_5_HS_RX_5_DDL_MID_INIT_REG_MASK 0xFF00 +#define CORE_DIG_DLANE_0_RW_HS_RX_6_HS_RX_6_DDL_RIGHT_INIT_REG_MASK 0x00FF +#define CORE_DIG_DLANE_1_RW_HS_RX_6_HS_RX_6_DDL_RIGHT_INIT_REG_MASK 0x00FF +#define CORE_DIG_DLANE_2_RW_HS_RX_6_HS_RX_6_DDL_RIGHT_INIT_REG_MASK 0x00FF +#define CORE_DIG_DLANE_3_RW_HS_RX_6_HS_RX_6_DDL_RIGHT_INIT_REG_MASK 0x00FF +#define CORE_DIG_DLANE_0_RW_HS_RX_7_HS_RX_7_DESKEW_AUTO_ALGO_SEL_REG_MASK 0x2000 +#define CORE_DIG_DLANE_1_RW_HS_RX_7_HS_RX_7_DESKEW_AUTO_ALGO_SEL_REG_MASK 0x2000 +#define CORE_DIG_DLANE_2_RW_HS_RX_7_HS_RX_7_DESKEW_AUTO_ALGO_SEL_REG_MASK 0x2000 +#define CORE_DIG_DLANE_3_RW_HS_RX_7_HS_RX_7_DESKEW_AUTO_ALGO_SEL_REG_MASK 0x2000 +#define CORE_DIG_DLANE_0_RW_HS_RX_7_HS_RX_7_SELECT_ALTERNATE_ALGO_REG_MASK 0x8000 +#define CORE_DIG_DLANE_1_RW_HS_RX_7_HS_RX_7_SELECT_ALTERNATE_ALGO_REG_MASK 0x8000 +#define CORE_DIG_DLANE_2_RW_HS_RX_7_HS_RX_7_SELECT_ALTERNATE_ALGO_REG_MASK 0x8000 +#define CORE_DIG_DLANE_3_RW_HS_RX_7_HS_RX_7_SELECT_ALTERNATE_ALGO_REG_MASK 0x8000 +#define CORE_DIG_DLANE_0_RW_HS_RX_3_HS_RX_3_FJUMP_DESKEW_REG_MASK 0x01F8 +#define CORE_DIG_DLANE_1_RW_HS_RX_3_HS_RX_3_FJUMP_DESKEW_REG_MASK 0x01F8 +#define CORE_DIG_DLANE_2_RW_HS_RX_3_HS_RX_3_FJUMP_DESKEW_REG_MASK 0x01F8 +#define CORE_DIG_DLANE_3_RW_HS_RX_3_HS_RX_3_FJUMP_DESKEW_REG_MASK 0x01F8 +#define CORE_DIG_DLANE_0_RW_HS_RX_9_HS_RX_9_PHASE_BOUND_REG_MASK 0x00FF +#define CORE_DIG_DLANE_1_RW_HS_RX_9_HS_RX_9_PHASE_BOUND_REG_MASK 0x00FF +#define CORE_DIG_DLANE_2_RW_HS_RX_9_HS_RX_9_PHASE_BOUND_REG_MASK 0x00FF +#define CORE_DIG_DLANE_3_RW_HS_RX_9_HS_RX_9_PHASE_BOUND_REG_MASK 0x00FF +#define CORE_DIG_DLANE_0_RW_HS_RX_6_HS_RX_6_MIN_EYE_OPENING_DESKEW_REG_MASK 0xFF00 +#define CORE_DIG_DLANE_1_RW_HS_RX_6_HS_RX_6_MIN_EYE_OPENING_DESKEW_REG_MASK 0xFF00 +#define CORE_DIG_DLANE_2_RW_HS_RX_6_HS_RX_6_MIN_EYE_OPENING_DESKEW_REG_MASK 0xFF00 +#define CORE_DIG_DLANE_3_RW_HS_RX_6_HS_RX_6_MIN_EYE_OPENING_DESKEW_REG_MASK 0xFF00 +#define CORE_DIG_DLANE_CLK_RW_CFG_0_CFG_0_HS_PIN_SWAP_REG_MASK 0x0002 + +struct isp4phy_mipi_reg_seq { + u16 addr; + u16 mask; + u16 data; +}; + +union isp4phy_mipi_0 { + struct { + u32 shutdownz : 1; + u32 rstz : 1; + } bit; + u32 value; +}; + +union isp4phy_mipi_1 { + struct { + u32 mode : 1; + } bit; + u32 value; +}; + +union isp4phy_mipi_2 { + struct { + u32 rxdatawidthhs_0 : 2; + u32 rxdatawidthhs_1 : 2; + u32 rxdatawidthhs_2 : 2; + u32 rxdatawidthhs_3 : 2; + } bit; + u32 value; +}; + +struct isp4phy_mipi_3 { + u32 reserved; +}; + +union isp4phy_mipi_4 { + struct { + u32 enableclk : 1; + u32 enable_0 : 1; + u32 enable_1 : 1; + u32 enable_2 : 1; + u32 enable_3 : 1; + } bit; + u32 value; +}; + +union isp4phy_mipi_5 { + struct { + u32 forcerxmode_0 : 1; + u32 forcerxmode_1 : 1; + u32 forcerxmode_2 : 1; + u32 forcerxmode_3 : 1; + u32 forcerxmode_clk : 1; + } bit; + u32 value; +}; + +union isp4phy_mipi_6 { + struct { + u32 turndisable_0 : 1; + u32 turndisable_1 : 1; + u32 turndisable_2 : 1; + u32 turndisable_3 : 1; + } bit; + u32 value; +}; + +union isp4phy_mipi_7 { + struct { + u32 ready : 1; + } bit; + u32 value; +}; + +union isp4phy_mipi_ind_idx { + struct { + u32 addr : 16; + } bit; + u32 value; +}; + +union isp4phy_mipi_ind_data { + struct { + u32 data : 16; + } bit; + u32 value; +}; + +union isp4phy_mipi_ind_wack { + struct { + u32 ack : 1; + u32 pslverr : 1; + } bit; + u32 value; +}; + +struct isp4phy_mipi_reg { + union isp4phy_mipi_0 isp_mipi_phy0; + union isp4phy_mipi_1 isp_mipi_phy1; + union isp4phy_mipi_2 isp_mipi_phy2; + struct isp4phy_mipi_3 isp_mipi_phy3; + union isp4phy_mipi_4 isp_mipi_phy4; + union isp4phy_mipi_5 isp_mipi_phy5; + union isp4phy_mipi_6 isp_mipi_phy6; + union isp4phy_mipi_7 isp_mipi_phy7; + u32 reserve; + union isp4phy_mipi_ind_idx isp_mipi_phy_ind_idx; + union isp4phy_mipi_ind_data isp_mipi_phy_ind_data; + union isp4phy_mipi_ind_wack isp_mipi_phy_inc_wack; +}; + +struct isp4phy_mipi_config { + u16 afe_lanex_ctrl_2_8oa_cdphy_sel_fast_reg; + u16 max_phase; + u16 ddlcal_cfg_5ddlcal_dll_fbk_reg; + u16 ddlcal_cfg_5ddlcal_ddl_coarse_bank_reg; + u16 afe_lanex_ctrl_2_12oa_dphy_ddl_bypass_en_ovr_val_reg; + u16 afe_lanex_ctrl_2_13oa_dphy_ddl_bypass_en_ovr_en_reg; + u16 afe_lanex_ctrl_2_12oa_dphy_dll_en_ovr_val_reg; + u16 afe_lanex_ctrl_2_13oa_dphy_dll_en_ovr_en_reg; + u16 cfg_1cfg_1_sot_detection_reg; + u16 hs_rx_2hs_rx_2_ignore_alterncal_reg; + u16 cfg_1cfg_1_deskew_supported_reg; + u16 afe_lanex_ctrl_2_9oa_hs_clk_div_reg; + u16 hs_rx_0hs_rx_0_thssettle_reg; + u16 hs_rx_3hs_rx_3_fjump_deskew_reg; + u16 hs_rx_6hs_rx_6_min_eye_opening_deskew_reg; +}; + +enum isp4phy_mipi_id { + ISP_MIPI_PHY_ID_0 = 0, + ISP_MIPI_PHY_ID_1 = 1, + ISP_MIPI_PHY_ID_2 = 2, + ISP_MIPI_PHY_ID_MAX +}; + +static const struct isp4phy_mipi_reg *isp_mipi_phy_reg[ISP_MIPI_PHY_ID_MAX] = { + (struct isp4phy_mipi_reg *)ISP_MIPI_PHY0_REG0, + (struct isp4phy_mipi_reg *)ISP_MIPI_PHY1_REG0, + (struct isp4phy_mipi_reg *)ISP_MIPI_PHY2_REG0, +}; + +static const struct isp4phy_mipi_reg_seq startup_seq_general_common_config[] = { + { PPI_STARTUP_RW_COMMON_DPHY_10, PPI_STARTUP_RW_COMMON_DPHY_10_PHY_READY_ADDR_MASK, 0x30 }, + { CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_2, CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_2_GLOBAL_ULPS_OVR_VAL_MASK, 0x0 }, + { CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_2, CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_2_GLOBAL_ULPS_OVR_EN_MASK, 0x1 }, + { CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_0, CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_0_CB_LP_DCO_EN_DLY_MASK, 0x3F }, + { PPI_STARTUP_RW_COMMON_STARTUP_1_1, PPI_STARTUP_RW_COMMON_STARTUP_1_1_PHY_READY_DLY_MASK, 0x233 }, + { PPI_STARTUP_RW_COMMON_DPHY_6, PPI_STARTUP_RW_COMMON_DPHY_6_LP_DCO_CAL_ADDR_MASK, 0x27 }, + { PPI_CALIBCTRL_RW_COMMON_BG_0, PPI_CALIBCTRL_RW_COMMON_BG_0_BG_MAX_COUNTER_MASK, 0x1F4 }, + { PPI_RW_LPDCOCAL_NREF, PPI_RW_LPDCOCAL_NREF_LPDCOCAL_NREF_MASK, 0x320 }, + { PPI_RW_LPDCOCAL_NREF_RANGE, PPI_RW_LPDCOCAL_NREF_RANGE_LPDCOCAL_NREF_RANGE_MASK, 0x1B }, + { PPI_RW_LPDCOCAL_TWAIT_CONFIG, PPI_RW_LPDCOCAL_TWAIT_CONFIG_LPDCOCAL_TWAIT_PON_MASK, 0x7F }, + { PPI_RW_LPDCOCAL_VT_CONFIG, PPI_RW_LPDCOCAL_VT_CONFIG_LPDCOCAL_VT_NREF_RANGE_MASK, 0x1B }, + { PPI_RW_LPDCOCAL_VT_CONFIG, PPI_RW_LPDCOCAL_VT_CONFIG_LPDCOCAL_USE_IDEAL_NREF_MASK, 0x1 }, + { PPI_RW_LPDCOCAL_VT_CONFIG, PPI_RW_LPDCOCAL_VT_CONFIG_LPDCOCAL_VT_TRACKING_EN_MASK, 0x0 }, + { PPI_RW_LPDCOCAL_COARSE_CFG, PPI_RW_LPDCOCAL_COARSE_CFG_NCOARSE_START_MASK, 0x1 }, + { PPI_RW_COMMON_CFG, PPI_RW_COMMON_CFG_CFG_CLK_DIV_FACTOR_MASK, 0x3 }, +}; + +static const struct isp4phy_mipi_reg_seq startup_seq_common[] = { + { PPI_STARTUP_RW_COMMON_DPHY_2, PPI_STARTUP_RW_COMMON_DPHY_2_RCAL_ADDR_MASK, 0x5 }, + { PPI_RW_TERMCAL_CFG_0, PPI_RW_TERMCAL_CFG_0_TERMCAL_TIMER_MASK, 0x17 }, + { PPI_RW_OFFSETCAL_CFG_0, PPI_RW_OFFSETCAL_CFG_0_OFFSETCAL_WAIT_THRESH_MASK, 0x4 }, + { PPI_RW_LPDCOCAL_TIMEBASE, PPI_RW_LPDCOCAL_TIMEBASE_LPDCOCAL_TIMEBASE_MASK, 0x5F }, + { PPI_RW_LPDCOCAL_TWAIT_CONFIG, PPI_RW_LPDCOCAL_TWAIT_CONFIG_LPDCOCAL_TWAIT_COARSE_MASK, 0x1D }, + { PPI_RW_LPDCOCAL_VT_CONFIG, PPI_RW_LPDCOCAL_VT_CONFIG_LPDCOCAL_TWAIT_FINE_MASK, 0x1D }, + { CORE_AFE_CTRL_2_0, CORE_AFE_CTRL_2_0_OA_CB_HSTX_VCOMM_REG_PON_OVR_VAL_MASK, 0x0 }, + { CORE_AFE_CTRL_2_1, CORE_AFE_CTRL_2_1_OA_CB_HSTX_VCOMM_REG_PON_OVR_EN_MASK, 0x1 }, + { CORE_AFE_CTRL_2_1, CORE_AFE_CTRL_2_1_OA_CB_HSTXLB_DCO_CLK0_EN_OVR_VAL_MASK, 0x0 }, + { CORE_AFE_CTRL_2_3, CORE_AFE_CTRL_2_3_OA_CB_HSTXLB_DCO_CLK0_EN_OVR_EN_MASK, 0x1 }, + { CORE_AFE_CTRL_2_0, CORE_AFE_CTRL_2_0_OA_CB_HSTXLB_DCO_CLK90_EN_OVR_VAL_MASK, 0x0 }, + { CORE_AFE_CTRL_2_3, CORE_AFE_CTRL_2_3_OA_CB_HSTXLB_DCO_CLK90_EN_OVR_EN_MASK, 0x1 }, + { CORE_AFE_CTRL_2_6, CORE_AFE_CTRL_2_6_OA_CB_HSTXLB_DCO_EN_OVR_EN_MASK, 0x1 }, + { CORE_AFE_CTRL_2_7, CORE_AFE_CTRL_2_7_OA_CB_HSTXLB_DCO_EN_OVR_VAL_MASK, 0x0 }, + { CORE_AFE_CTRL_2_6, CORE_AFE_CTRL_2_6_OA_CB_HSTXLB_DCO_PON_OVR_EN_MASK, 0x1 }, + { CORE_AFE_CTRL_2_7, CORE_AFE_CTRL_2_7_OA_CB_HSTXLB_DCO_PON_OVR_VAL_MASK, 0x0 }, + { CORE_AFE_CTRL_2_6, CORE_AFE_CTRL_2_6_OA_CB_HSTXLB_DCO_TUNE_CLKDIG_EN_OVR_EN_MASK, 0x1 }, + { CORE_AFE_CTRL_2_7, CORE_AFE_CTRL_2_7_OA_CB_HSTXLB_DCO_TUNE_CLKDIG_EN_OVR_VAL_MASK, 0x0 }, + { CORE_AFE_CTRL_2_5, CORE_AFE_CTRL_2_5_OA_CB_SEL_45OHM_50OHM_MASK, 0x0 }, +}; + +static const struct isp4phy_mipi_reg_seq + startup_seq_dphy_periodic_deskew_program[] = { + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x404 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x40C }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x414 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x41C }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x423 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x429 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x430 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x43A }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x445 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x44A }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x450 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x45A }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x465 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x469 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x472 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x47A }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x485 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x489 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x490 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x49A }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x4A4 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x4AC }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x4B4 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x4BC }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x4C4 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x4CC }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x4D4 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x4DC }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x4E4 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x4EC }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x4F4 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x4FC }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x504 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x50C }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x514 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x51C }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x523 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x529 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x530 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x53A }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x545 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x54A }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x550 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x55A }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x565 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x569 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x572 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x57A }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x585 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x589 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x590 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x59A }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x5A4 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x5AC }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x5B4 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x5BC }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x5C4 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x5CC }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x5D4 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x5DC }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x5E4 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x5EC }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x5F4 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x5FC }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x604 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x60C }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x614 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x61C }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x623 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x629 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x632 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x63A }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x645 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x64A }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x650 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x65A }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x665 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x669 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x672 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x67A }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x685 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x689 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x690 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x69A }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x6A4 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x6AC }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x6B4 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x6BC }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x6C4 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x6CC }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x6D4 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x6DC }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x6E4 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x6EC }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x6F4 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x6FC }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x704 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x70C }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x714 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x71C }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x723 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x72A }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x730 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x73A }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x745 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x74A }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x750 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x75A }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x765 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x769 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x772 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x77A }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x785 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x789 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x790 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x79A }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x7A4 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x7AC }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x7B4 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x7BC }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x7C4 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x7CC }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x7D4 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x7DC }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x7E4 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x7EC }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x7F4 }, + { CORE_DIG_COMMON_RW_DESKEW_FINE_MEM, 0, 0x7FC }, +}; + +inline u16 isp4phy_rreg(void __iomem *base, u32 phy_id, u16 addr) +{ + const struct isp4phy_mipi_reg *reg = isp_mipi_phy_reg[phy_id]; + + isp4hw_wreg(base, (uintptr_t)(®->isp_mipi_phy_ind_idx), addr); + return (u16)isp4hw_rreg(base, (uintptr_t)(®->isp_mipi_phy_ind_data)); +} + +inline void isp4phy_wreg(void __iomem *base, u32 phy_id, u16 addr, u16 data) +{ + const struct isp4phy_mipi_reg *reg = isp_mipi_phy_reg[phy_id]; + + isp4hw_wreg(base, (uintptr_t)(®->isp_mipi_phy_ind_idx), addr); + isp4hw_wreg(base, (uintptr_t)(®->isp_mipi_phy_ind_data), data); +} + +static void isp4phy_mask_wreg(void __iomem *base, u32 phy_id, u16 addr, + u16 mask, u16 regval) +{ + unsigned long _mask = mask; + u16 shift = 0; + u16 data; + + data = isp4phy_rreg(base, phy_id, addr); + if (mask) + shift = find_first_bit(&_mask, 16); + data = (data & ~mask) | ((regval << shift) & mask); + + isp4phy_wreg(base, phy_id, addr, data); +} + +static void isp4phy_optional_features_dphy(void __iomem *base, u32 phy_id) +{ + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_CLK_RW_CFG_0, + CORE_DIG_DLANE_CLK_RW_CFG_0_CFG_0_LP_PIN_SWAP_REG_MASK, 0x0); + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_CLK_RW_CFG_0, + CORE_DIG_DLANE_CLK_RW_CFG_0_CFG_0_HS_PIN_SWAP_REG_MASK, 0x0); + + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_0_RW_CFG_0, + CORE_DIG_DLANE_0_RW_CFG_0_CFG_0_LP_PIN_SWAP_REG_MASK, 0x0); + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_1_RW_CFG_0, + CORE_DIG_DLANE_1_RW_CFG_0_CFG_0_LP_PIN_SWAP_REG_MASK, 0x0); + if (phy_id <= ISP_MIPI_PHY_ID_1) { + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_2_RW_CFG_0, + CORE_DIG_DLANE_2_RW_CFG_0_CFG_0_LP_PIN_SWAP_REG_MASK, 0x0); + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_3_RW_CFG_0, + CORE_DIG_DLANE_3_RW_CFG_0_CFG_0_LP_PIN_SWAP_REG_MASK, 0x0); + } + + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_0_RW_CFG_0, + CORE_DIG_DLANE_0_RW_CFG_0_CFG_0_HS_PIN_SWAP_REG_MASK, 0x0); + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_1_RW_CFG_0, + CORE_DIG_DLANE_1_RW_CFG_0_CFG_0_HS_PIN_SWAP_REG_MASK, 0x0); + if (phy_id <= ISP_MIPI_PHY_ID_1) { + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_2_RW_CFG_0, + CORE_DIG_DLANE_2_RW_CFG_0_CFG_0_HS_PIN_SWAP_REG_MASK, 0x0); + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_3_RW_CFG_0, + CORE_DIG_DLANE_3_RW_CFG_0_CFG_0_HS_PIN_SWAP_REG_MASK, 0x0); + } + + isp4phy_mask_wreg(base, phy_id, CORE_AFE_LANE0_CTRL_2_9, + CORE_AFE_LANE0_CTRL_2_9_OA_LANE0_HSRX_SEL_GATED_POLARITY_MASK, 0x0); + isp4phy_mask_wreg(base, phy_id, CORE_AFE_LANE1_CTRL_2_9, + CORE_AFE_LANE1_CTRL_2_9_OA_LANE1_HSRX_SEL_GATED_POLARITY_MASK, 0x0); + isp4phy_mask_wreg(base, phy_id, CORE_AFE_LANE2_CTRL_2_9, + CORE_AFE_LANE2_CTRL_2_9_OA_LANE2_HSRX_SEL_GATED_POLARITY_MASK, 0x0); + if (phy_id <= ISP_MIPI_PHY_ID_1) { + isp4phy_mask_wreg(base, phy_id, CORE_AFE_LANE3_CTRL_2_9, + CORE_AFE_LANE3_CTRL_2_9_OA_LANE3_HSRX_SEL_GATED_POLARITY_MASK, 0x0); + isp4phy_mask_wreg(base, phy_id, CORE_AFE_LANE4_CTRL_2_9, + CORE_AFE_LANE4_CTRL_2_9_OA_LANE4_HSRX_SEL_GATED_POLARITY_MASK, 0x0); + } +} + +static void isp4phy_dphy_periodic_deskew_program(void __iomem *base, + u32 phy_id) +{ + for (int ctr = 0; + ctr < ARRAY_SIZE(startup_seq_dphy_periodic_deskew_program); + ctr++) + isp4phy_wreg(base, phy_id, + startup_seq_dphy_periodic_deskew_program[ctr].addr, + startup_seq_dphy_periodic_deskew_program[ctr].data); +} + +static void isp4phy_dphy_specific(void __iomem *base, u32 phy_id, + u64 data_rate, + struct isp4phy_mipi_config *phycfg) +{ + u64 half_rate = data_rate >> 1; + u16 ddl_cal; + + ddl_cal = TIMEBASE * half_rate; + ddl_cal = (ddl_cal + 31) >> 5; + + isp4phy_mask_wreg(base, phy_id, CORE_DIG_RW_COMMON_7, + CORE_DIG_RW_COMMON_7_LANE0_HSRX_WORD_CLK_SEL_GATING_REG_MASK, 0x0); + isp4phy_mask_wreg(base, phy_id, CORE_DIG_RW_COMMON_7, + CORE_DIG_RW_COMMON_7_LANE1_HSRX_WORD_CLK_SEL_GATING_REG_MASK, 0x0); + isp4phy_mask_wreg(base, phy_id, CORE_DIG_RW_COMMON_7, + CORE_DIG_RW_COMMON_7_LANE2_HSRX_WORD_CLK_SEL_GATING_REG_MASK, 0x0); + if (phy_id <= ISP_MIPI_PHY_ID_1) { + isp4phy_mask_wreg(base, phy_id, CORE_DIG_RW_COMMON_7, + CORE_DIG_RW_COMMON_7_LANE3_HSRX_WORD_CLK_SEL_GATING_REG_MASK, 0x0); + isp4phy_mask_wreg(base, phy_id, CORE_DIG_RW_COMMON_7, + CORE_DIG_RW_COMMON_7_LANE4_HSRX_WORD_CLK_SEL_GATING_REG_MASK, 0x0); + } + + isp4phy_mask_wreg(base, phy_id, PPI_STARTUP_RW_COMMON_DPHY_8, + PPI_STARTUP_RW_COMMON_DPHY_8_CPHY_DDL_CAL_ADDR_MASK, 0x50); + + if (data_rate < 1500) { + isp4phy_mask_wreg(base, phy_id, PPI_STARTUP_RW_COMMON_DPHY_7, + PPI_STARTUP_RW_COMMON_DPHY_7_DPHY_DDL_CAL_ADDR_MASK, 0x68); + } else { + /* Digital Delay Line (DDL) tuning calibration */ + isp4phy_mask_wreg(base, phy_id, PPI_STARTUP_RW_COMMON_DPHY_7, + PPI_STARTUP_RW_COMMON_DPHY_7_DPHY_DDL_CAL_ADDR_MASK, 0x28); + isp4phy_mask_wreg(base, phy_id, PPI_RW_DDLCAL_CFG_0, + PPI_RW_DDLCAL_CFG_0_DDLCAL_TIMEBASE_TARGET_MASK, 0x77); /* LUT->24MHz case */ + isp4phy_mask_wreg(base, phy_id, PPI_RW_DDLCAL_CFG_7, + PPI_RW_DDLCAL_CFG_7_DDLCAL_DECR_WAIT_MASK, 0x22); + isp4phy_mask_wreg(base, phy_id, PPI_RW_DDLCAL_CFG_1, + PPI_RW_DDLCAL_CFG_1_DDLCAL_DISABLE_TIME_MASK, 0x17); /* LUT->24MHz case */ + isp4phy_mask_wreg(base, phy_id, PPI_RW_DDLCAL_CFG_2, + PPI_RW_DDLCAL_CFG_2_DDLCAL_WAIT_MASK, 0x4); + isp4phy_mask_wreg(base, phy_id, PPI_RW_DDLCAL_CFG_2, + PPI_RW_DDLCAL_CFG_2_DDLCAL_TUNE_MODE_MASK, 0x2); + isp4phy_mask_wreg(base, phy_id, PPI_RW_DDLCAL_CFG_2, + PPI_RW_DDLCAL_CFG_2_DDLCAL_DDL_DLL_MASK, 0x1); + isp4phy_mask_wreg(base, phy_id, PPI_RW_DDLCAL_CFG_2, + PPI_RW_DDLCAL_CFG_2_DDLCAL_ENABLE_WAIT_MASK, 0x17); /* LUT->24MHz case */ + isp4phy_mask_wreg(base, phy_id, PPI_RW_DDLCAL_CFG_2, + PPI_RW_DDLCAL_CFG_2_DDLCAL_UPDATE_SETTINGS_MASK, 0x1); + isp4phy_mask_wreg(base, phy_id, PPI_RW_DDLCAL_CFG_4, + PPI_RW_DDLCAL_CFG_4_DDLCAL_STUCK_THRESH_MASK, 0xA); + isp4phy_mask_wreg(base, phy_id, PPI_RW_DDLCAL_CFG_6, + PPI_RW_DDLCAL_CFG_6_DDLCAL_MAX_DIFF_MASK, 0xA); + isp4phy_mask_wreg(base, phy_id, PPI_RW_DDLCAL_CFG_7, + PPI_RW_DDLCAL_CFG_7_DDLCAL_START_DELAY_MASK, 0xB); /* LUT->24MHz case */ + isp4phy_mask_wreg(base, phy_id, PPI_RW_DDLCAL_CFG_3, + PPI_RW_DDLCAL_CFG_3_DDLCAL_COUNTER_REF_MASK, ddl_cal); + isp4phy_mask_wreg(base, phy_id, PPI_RW_DDLCAL_CFG_1, + PPI_RW_DDLCAL_CFG_1_DDLCAL_MAX_PHASE_MASK, phycfg->max_phase); + isp4phy_mask_wreg(base, phy_id, PPI_RW_DDLCAL_CFG_5, + PPI_RW_DDLCAL_CFG_5_DDLCAL_DLL_FBK_MASK, + phycfg->ddlcal_cfg_5ddlcal_dll_fbk_reg); + isp4phy_mask_wreg(base, phy_id, PPI_RW_DDLCAL_CFG_5, + PPI_RW_DDLCAL_CFG_5_DDLCAL_DDL_COARSE_BANK_MASK, + phycfg->ddlcal_cfg_5ddlcal_ddl_coarse_bank_reg); + isp4phy_mask_wreg(base, phy_id, CORE_AFE_LANE0_CTRL_2_8, + CORE_AFE_LANE0_CTRL_2_8_OA_LANE0_HSRX_CDPHY_SEL_FAST_MASK, + phycfg->afe_lanex_ctrl_2_8oa_cdphy_sel_fast_reg); + isp4phy_mask_wreg(base, phy_id, CORE_AFE_LANE1_CTRL_2_8, + CORE_AFE_LANE1_CTRL_2_8_OA_LANE1_HSRX_CDPHY_SEL_FAST_MASK, + phycfg->afe_lanex_ctrl_2_8oa_cdphy_sel_fast_reg); + isp4phy_mask_wreg(base, phy_id, CORE_AFE_LANE2_CTRL_2_8, + CORE_AFE_LANE2_CTRL_2_8_OA_LANE2_HSRX_CDPHY_SEL_FAST_MASK, + phycfg->afe_lanex_ctrl_2_8oa_cdphy_sel_fast_reg); + if (phy_id <= ISP_MIPI_PHY_ID_1) { + isp4phy_mask_wreg(base, phy_id, CORE_AFE_LANE3_CTRL_2_8, + CORE_AFE_LANE3_CTRL_2_8_OA_LANE3_HSRX_CDPHY_SEL_FAST_MASK, + phycfg->afe_lanex_ctrl_2_8oa_cdphy_sel_fast_reg); + isp4phy_mask_wreg(base, phy_id, CORE_AFE_LANE4_CTRL_2_8, + CORE_AFE_LANE4_CTRL_2_8_OA_LANE4_HSRX_CDPHY_SEL_FAST_MASK, + phycfg->afe_lanex_ctrl_2_8oa_cdphy_sel_fast_reg); + } + } + + /* Write 6 if Tlpx (far end / near end) ratio < 1 + * Write 7 if Tlpx (far end / near end) ratio >= 1 + */ + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_0_RW_LP_0, + CORE_DIG_DLANE_0_RW_LP_0_LP_0_TTAGO_REG_MASK, 0x7); + /* Write 6 if Tlpx (far end / near end) ratio < 1 + * Write 7 if Tlpx (far end / near end) ratio >= 1 + */ + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_1_RW_LP_0, + CORE_DIG_DLANE_1_RW_LP_0_LP_0_TTAGO_REG_MASK, 0x7); + if (phy_id <= ISP_MIPI_PHY_ID_1) { + /* Write 6 if Tlpx (far end / near end) ratio < 1 + * Write 7 if Tlpx (far end / near end) ratio >= 1 + */ + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_2_RW_LP_0, + CORE_DIG_DLANE_2_RW_LP_0_LP_0_TTAGO_REG_MASK, 0x7); + /* Write 6 if Tlpx (far end / near end) ratio < 1 + * Write 7 if Tlpx (far end / near end) ratio >= 1 + */ + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_3_RW_LP_0, + CORE_DIG_DLANE_3_RW_LP_0_LP_0_TTAGO_REG_MASK, 0x7); + } + + isp4phy_mask_wreg(base, phy_id, CORE_AFE_LANE0_CTRL_2_2, + CORE_AFE_LANE0_CTRL_2_2_OA_LANE0_SEL_LANE_CFG_MASK, 0x0); + + if (phy_id <= ISP_MIPI_PHY_ID_1) { + isp4phy_mask_wreg(base, phy_id, CORE_AFE_LANE1_CTRL_2_2, + CORE_AFE_LANE1_CTRL_2_2_OA_LANE1_SEL_LANE_CFG_MASK, 0x0); + isp4phy_mask_wreg(base, phy_id, CORE_AFE_LANE2_CTRL_2_2, + CORE_AFE_LANE2_CTRL_2_2_OA_LANE2_SEL_LANE_CFG_MASK, 0x1); + isp4phy_mask_wreg(base, phy_id, CORE_AFE_LANE3_CTRL_2_2, + CORE_AFE_LANE3_CTRL_2_2_OA_LANE3_SEL_LANE_CFG_MASK, 0x0); + isp4phy_mask_wreg(base, phy_id, CORE_AFE_LANE4_CTRL_2_2, + CORE_AFE_LANE4_CTRL_2_2_OA_LANE4_SEL_LANE_CFG_MASK, 0x0); + } else { + isp4phy_mask_wreg(base, phy_id, CORE_AFE_LANE1_CTRL_2_2, + CORE_AFE_LANE1_CTRL_2_2_OA_LANE1_SEL_LANE_CFG_MASK, 0x1); + isp4phy_mask_wreg(base, phy_id, CORE_AFE_LANE2_CTRL_2_2, + CORE_AFE_LANE2_CTRL_2_2_OA_LANE2_SEL_LANE_CFG_MASK, 0x0); + } + + isp4phy_mask_wreg(base, phy_id, CORE_DIG_RW_COMMON_6, + CORE_DIG_RW_COMMON_6_DESERIALIZER_EN_DEASS_COUNT_THRESH_D_MASK, 0x1); + isp4phy_mask_wreg(base, phy_id, CORE_DIG_RW_COMMON_6, + CORE_DIG_RW_COMMON_6_DESERIALIZER_DIV_EN_DELAY_THRESH_D_MASK, 0x1); + + isp4phy_mask_wreg(base, phy_id, CORE_AFE_LANE0_CTRL_2_12, + CORE_AFE_LANE0_CTRL_2_12_OA_LANE0_HSRX_DPHY_DDL_BYPASS_EN_OVR_VAL_MASK, + phycfg->afe_lanex_ctrl_2_12oa_dphy_ddl_bypass_en_ovr_val_reg); + isp4phy_mask_wreg(base, phy_id, CORE_AFE_LANE1_CTRL_2_12, + CORE_AFE_LANE1_CTRL_2_12_OA_LANE1_HSRX_DPHY_DDL_BYPASS_EN_OVR_VAL_MASK, + phycfg->afe_lanex_ctrl_2_12oa_dphy_ddl_bypass_en_ovr_val_reg); + isp4phy_mask_wreg(base, phy_id, CORE_AFE_LANE2_CTRL_2_12, + CORE_AFE_LANE2_CTRL_2_12_OA_LANE2_HSRX_DPHY_DDL_BYPASS_EN_OVR_VAL_MASK, + phycfg->afe_lanex_ctrl_2_12oa_dphy_ddl_bypass_en_ovr_val_reg); + if (phy_id <= ISP_MIPI_PHY_ID_1) { + isp4phy_mask_wreg(base, phy_id, CORE_AFE_LANE3_CTRL_2_12, + CORE_AFE_LANE3_CTRL_2_12_OA_LANE3_HSRX_DPHY_DDL_BYPASS_EN_OVR_VAL_MASK, + phycfg->afe_lanex_ctrl_2_12oa_dphy_ddl_bypass_en_ovr_val_reg); + isp4phy_mask_wreg(base, phy_id, CORE_AFE_LANE4_CTRL_2_12, + CORE_AFE_LANE4_CTRL_2_12_OA_LANE4_HSRX_DPHY_DDL_BYPASS_EN_OVR_VAL_MASK, + phycfg->afe_lanex_ctrl_2_12oa_dphy_ddl_bypass_en_ovr_val_reg); + } + + isp4phy_mask_wreg(base, phy_id, CORE_AFE_LANE0_CTRL_2_13, + CORE_AFE_LANE0_CTRL_2_13_OA_LANE0_HSRX_DPHY_DDL_BYPASS_EN_OVR_EN_MASK, + phycfg->afe_lanex_ctrl_2_13oa_dphy_ddl_bypass_en_ovr_en_reg); + isp4phy_mask_wreg(base, phy_id, CORE_AFE_LANE1_CTRL_2_13, + CORE_AFE_LANE1_CTRL_2_13_OA_LANE1_HSRX_DPHY_DDL_BYPASS_EN_OVR_EN_MASK, + phycfg->afe_lanex_ctrl_2_13oa_dphy_ddl_bypass_en_ovr_en_reg); + isp4phy_mask_wreg(base, phy_id, CORE_AFE_LANE2_CTRL_2_13, + CORE_AFE_LANE2_CTRL_2_13_OA_LANE2_HSRX_DPHY_DDL_BYPASS_EN_OVR_EN_MASK, + phycfg->afe_lanex_ctrl_2_13oa_dphy_ddl_bypass_en_ovr_en_reg); + if (phy_id <= ISP_MIPI_PHY_ID_1) { + isp4phy_mask_wreg(base, phy_id, CORE_AFE_LANE3_CTRL_2_13, + CORE_AFE_LANE3_CTRL_2_13_OA_LANE3_HSRX_DPHY_DDL_BYPASS_EN_OVR_EN_MASK, + phycfg->afe_lanex_ctrl_2_13oa_dphy_ddl_bypass_en_ovr_en_reg); + isp4phy_mask_wreg(base, phy_id, CORE_AFE_LANE4_CTRL_2_13, + CORE_AFE_LANE4_CTRL_2_13_OA_LANE4_HSRX_DPHY_DDL_BYPASS_EN_OVR_EN_MASK, + phycfg->afe_lanex_ctrl_2_13oa_dphy_ddl_bypass_en_ovr_en_reg); + } + + isp4phy_mask_wreg(base, phy_id, CORE_AFE_LANE0_CTRL_2_12, + CORE_AFE_LANE0_CTRL_2_12_OA_LANE0_HSRX_DPHY_DLL_EN_OVR_VAL_MASK, + phycfg->afe_lanex_ctrl_2_12oa_dphy_dll_en_ovr_val_reg); + isp4phy_mask_wreg(base, phy_id, CORE_AFE_LANE1_CTRL_2_12, + CORE_AFE_LANE1_CTRL_2_12_OA_LANE1_HSRX_DPHY_DLL_EN_OVR_VAL_MASK, + phycfg->afe_lanex_ctrl_2_12oa_dphy_dll_en_ovr_val_reg); + isp4phy_mask_wreg(base, phy_id, CORE_AFE_LANE2_CTRL_2_12, + CORE_AFE_LANE2_CTRL_2_12_OA_LANE2_HSRX_DPHY_DLL_EN_OVR_VAL_MASK, + phycfg->afe_lanex_ctrl_2_12oa_dphy_dll_en_ovr_val_reg); + if (phy_id <= ISP_MIPI_PHY_ID_1) { + isp4phy_mask_wreg(base, phy_id, CORE_AFE_LANE3_CTRL_2_12, + CORE_AFE_LANE3_CTRL_2_12_OA_LANE3_HSRX_DPHY_DLL_EN_OVR_VAL_MASK, + phycfg->afe_lanex_ctrl_2_12oa_dphy_dll_en_ovr_val_reg); + isp4phy_mask_wreg(base, phy_id, CORE_AFE_LANE4_CTRL_2_12, + CORE_AFE_LANE4_CTRL_2_12_OA_LANE4_HSRX_DPHY_DLL_EN_OVR_VAL_MASK, + phycfg->afe_lanex_ctrl_2_12oa_dphy_dll_en_ovr_val_reg); + } + + isp4phy_mask_wreg(base, phy_id, CORE_AFE_LANE0_CTRL_2_13, + CORE_AFE_LANE0_CTRL_2_13_OA_LANE0_HSRX_DPHY_DLL_EN_OVR_EN_MASK, + phycfg->afe_lanex_ctrl_2_13oa_dphy_dll_en_ovr_en_reg); + isp4phy_mask_wreg(base, phy_id, CORE_AFE_LANE1_CTRL_2_13, + CORE_AFE_LANE1_CTRL_2_13_OA_LANE1_HSRX_DPHY_DLL_EN_OVR_EN_MASK, + phycfg->afe_lanex_ctrl_2_13oa_dphy_dll_en_ovr_en_reg); + isp4phy_mask_wreg(base, phy_id, CORE_AFE_LANE2_CTRL_2_13, + CORE_AFE_LANE2_CTRL_2_13_OA_LANE2_HSRX_DPHY_DLL_EN_OVR_EN_MASK, + phycfg->afe_lanex_ctrl_2_13oa_dphy_dll_en_ovr_en_reg); + if (phy_id <= ISP_MIPI_PHY_ID_1) { + isp4phy_mask_wreg(base, phy_id, CORE_AFE_LANE3_CTRL_2_13, + CORE_AFE_LANE3_CTRL_2_13_OA_LANE3_HSRX_DPHY_DLL_EN_OVR_EN_MASK, + phycfg->afe_lanex_ctrl_2_13oa_dphy_dll_en_ovr_en_reg); + isp4phy_mask_wreg(base, phy_id, CORE_AFE_LANE4_CTRL_2_13, + CORE_AFE_LANE4_CTRL_2_13_OA_LANE4_HSRX_DPHY_DLL_EN_OVR_EN_MASK, + phycfg->afe_lanex_ctrl_2_13oa_dphy_dll_en_ovr_en_reg); + isp4phy_mask_wreg(base, phy_id, CORE_AFE_LANE2_CTRL_2_9, + CORE_AFE_LANE2_CTRL_2_9_OA_LANE2_HSRX_HS_CLK_DIV_MASK, + phycfg->afe_lanex_ctrl_2_9oa_hs_clk_div_reg); + } else { + isp4phy_mask_wreg(base, phy_id, CORE_AFE_LANE1_CTRL_2_9, + CORE_AFE_LANE1_CTRL_2_9_OA_LANE1_HSRX_HS_CLK_DIV_MASK, + phycfg->afe_lanex_ctrl_2_9oa_hs_clk_div_reg); + } + + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_CLK_RW_HS_RX_0, + CORE_DIG_DLANE_CLK_RW_HS_RX_0_HS_RX_0_TCLKSETTLE_REG_MASK, 0x1C); + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_CLK_RW_HS_RX_7, + CORE_DIG_DLANE_CLK_RW_HS_RX_7_HS_RX_7_TCLKMISS_REG_MASK, 0x6); + + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_0_RW_HS_RX_0, + CORE_DIG_DLANE_0_RW_HS_RX_0_HS_RX_0_THSSETTLE_REG_MASK, + phycfg->hs_rx_0hs_rx_0_thssettle_reg); + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_1_RW_HS_RX_0, + CORE_DIG_DLANE_1_RW_HS_RX_0_HS_RX_0_THSSETTLE_REG_MASK, + phycfg->hs_rx_0hs_rx_0_thssettle_reg); + if (phy_id <= ISP_MIPI_PHY_ID_1) { + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_2_RW_HS_RX_0, + CORE_DIG_DLANE_2_RW_HS_RX_0_HS_RX_0_THSSETTLE_REG_MASK, + phycfg->hs_rx_0hs_rx_0_thssettle_reg); + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_3_RW_HS_RX_0, + CORE_DIG_DLANE_3_RW_HS_RX_0_HS_RX_0_THSSETTLE_REG_MASK, + phycfg->hs_rx_0hs_rx_0_thssettle_reg); + } + + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_0_RW_CFG_1, + CORE_DIG_DLANE_0_RW_CFG_1_CFG_1_DESKEW_SUPPORTED_REG_MASK, + phycfg->cfg_1cfg_1_deskew_supported_reg); + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_1_RW_CFG_1, + CORE_DIG_DLANE_1_RW_CFG_1_CFG_1_DESKEW_SUPPORTED_REG_MASK, + phycfg->cfg_1cfg_1_deskew_supported_reg); + if (phy_id <= ISP_MIPI_PHY_ID_1) { + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_2_RW_CFG_1, + CORE_DIG_DLANE_2_RW_CFG_1_CFG_1_DESKEW_SUPPORTED_REG_MASK, + phycfg->cfg_1cfg_1_deskew_supported_reg); + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_3_RW_CFG_1, + CORE_DIG_DLANE_3_RW_CFG_1_CFG_1_DESKEW_SUPPORTED_REG_MASK, + phycfg->cfg_1cfg_1_deskew_supported_reg); + } + + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_0_RW_CFG_1, + CORE_DIG_DLANE_0_RW_CFG_1_CFG_1_SOT_DETECTION_REG_MASK, + phycfg->cfg_1cfg_1_sot_detection_reg); + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_1_RW_CFG_1, + CORE_DIG_DLANE_1_RW_CFG_1_CFG_1_SOT_DETECTION_REG_MASK, + phycfg->cfg_1cfg_1_sot_detection_reg); + if (phy_id <= ISP_MIPI_PHY_ID_1) { + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_2_RW_CFG_1, + CORE_DIG_DLANE_2_RW_CFG_1_CFG_1_SOT_DETECTION_REG_MASK, + phycfg->cfg_1cfg_1_sot_detection_reg); + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_3_RW_CFG_1, + CORE_DIG_DLANE_3_RW_CFG_1_CFG_1_SOT_DETECTION_REG_MASK, + phycfg->cfg_1cfg_1_sot_detection_reg); + } + + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_0_RW_HS_RX_2, + CORE_DIG_DLANE_0_RW_HS_RX_2_HS_RX_2_IGNORE_ALTERNCAL_REG_MASK, + phycfg->hs_rx_2hs_rx_2_ignore_alterncal_reg); + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_1_RW_HS_RX_2, + CORE_DIG_DLANE_1_RW_HS_RX_2_HS_RX_2_IGNORE_ALTERNCAL_REG_MASK, + phycfg->hs_rx_2hs_rx_2_ignore_alterncal_reg); + if (phy_id <= ISP_MIPI_PHY_ID_1) { + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_2_RW_HS_RX_2, + CORE_DIG_DLANE_2_RW_HS_RX_2_HS_RX_2_IGNORE_ALTERNCAL_REG_MASK, + phycfg->hs_rx_2hs_rx_2_ignore_alterncal_reg); + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_3_RW_HS_RX_2, + CORE_DIG_DLANE_3_RW_HS_RX_2_HS_RX_2_IGNORE_ALTERNCAL_REG_MASK, + phycfg->hs_rx_2hs_rx_2_ignore_alterncal_reg); + } + + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_0_RW_LP_0, + CORE_DIG_DLANE_0_RW_LP_0_LP_0_ITMINRX_REG_MASK, 0x1); + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_1_RW_LP_0, + CORE_DIG_DLANE_1_RW_LP_0_LP_0_ITMINRX_REG_MASK, 0x1); + if (phy_id <= ISP_MIPI_PHY_ID_1) { + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_2_RW_LP_0, + CORE_DIG_DLANE_2_RW_LP_0_LP_0_ITMINRX_REG_MASK, 0x1); + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_3_RW_LP_0, + CORE_DIG_DLANE_3_RW_LP_0_LP_0_ITMINRX_REG_MASK, 0x1); + } + + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_0_RW_LP_2, + CORE_DIG_DLANE_0_RW_LP_2_LP_2_FILTER_INPUT_SAMPLING_REG_MASK, 0x0); + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_1_RW_LP_2, + CORE_DIG_DLANE_1_RW_LP_2_LP_2_FILTER_INPUT_SAMPLING_REG_MASK, 0x0); + if (phy_id <= ISP_MIPI_PHY_ID_1) { + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_2_RW_LP_2, + CORE_DIG_DLANE_2_RW_LP_2_LP_2_FILTER_INPUT_SAMPLING_REG_MASK, 0x0); + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_3_RW_LP_2, + CORE_DIG_DLANE_3_RW_LP_2_LP_2_FILTER_INPUT_SAMPLING_REG_MASK, 0x0); + } + + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_CLK_RW_LP_0, + CORE_DIG_DLANE_CLK_RW_LP_0_LP_0_ITMINRX_REG_MASK, 0x1); + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_CLK_RW_LP_2, + CORE_DIG_DLANE_CLK_RW_LP_2_LP_2_FILTER_INPUT_SAMPLING_REG_MASK, 0x0); + + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_0_RW_HS_RX_2, + CORE_DIG_DLANE_0_RW_HS_RX_2_HS_RX_2_UPDATE_SETTINGS_DESKEW_REG_MASK, 0x1); + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_1_RW_HS_RX_2, + CORE_DIG_DLANE_1_RW_HS_RX_2_HS_RX_2_UPDATE_SETTINGS_DESKEW_REG_MASK, 0x1); + if (phy_id <= ISP_MIPI_PHY_ID_1) { + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_2_RW_HS_RX_2, + CORE_DIG_DLANE_2_RW_HS_RX_2_HS_RX_2_UPDATE_SETTINGS_DESKEW_REG_MASK, 0x1); + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_3_RW_HS_RX_2, + CORE_DIG_DLANE_3_RW_HS_RX_2_HS_RX_2_UPDATE_SETTINGS_DESKEW_REG_MASK, 0x1); + } + + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_0_RW_HS_RX_1, + CORE_DIG_DLANE_0_RW_HS_RX_1_HS_RX_1_FILTER_SIZE_DESKEW_REG_MASK, 0x10); + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_1_RW_HS_RX_1, + CORE_DIG_DLANE_1_RW_HS_RX_1_HS_RX_1_FILTER_SIZE_DESKEW_REG_MASK, 0x10); + if (phy_id <= ISP_MIPI_PHY_ID_1) { + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_2_RW_HS_RX_1, + CORE_DIG_DLANE_2_RW_HS_RX_1_HS_RX_1_FILTER_SIZE_DESKEW_REG_MASK, 0x10); + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_3_RW_HS_RX_1, + CORE_DIG_DLANE_3_RW_HS_RX_1_HS_RX_1_FILTER_SIZE_DESKEW_REG_MASK, 0x10); + } + + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_0_RW_HS_RX_2, + CORE_DIG_DLANE_0_RW_HS_RX_2_HS_RX_2_WINDOW_SIZE_DESKEW_REG_MASK, 0x3); + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_1_RW_HS_RX_2, + CORE_DIG_DLANE_1_RW_HS_RX_2_HS_RX_2_WINDOW_SIZE_DESKEW_REG_MASK, 0x3); + if (phy_id <= ISP_MIPI_PHY_ID_1) { + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_2_RW_HS_RX_2, + CORE_DIG_DLANE_2_RW_HS_RX_2_HS_RX_2_WINDOW_SIZE_DESKEW_REG_MASK, 0x3); + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_3_RW_HS_RX_2, + CORE_DIG_DLANE_3_RW_HS_RX_2_HS_RX_2_WINDOW_SIZE_DESKEW_REG_MASK, 0x3); + } + + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_0_RW_HS_RX_3, + CORE_DIG_DLANE_0_RW_HS_RX_3_HS_RX_3_STEP_SIZE_DESKEW_REG_MASK, 0x1); + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_1_RW_HS_RX_3, + CORE_DIG_DLANE_1_RW_HS_RX_3_HS_RX_3_STEP_SIZE_DESKEW_REG_MASK, 0x1); + if (phy_id <= ISP_MIPI_PHY_ID_1) { + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_2_RW_HS_RX_3, + CORE_DIG_DLANE_2_RW_HS_RX_3_HS_RX_3_STEP_SIZE_DESKEW_REG_MASK, 0x1); + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_3_RW_HS_RX_3, + CORE_DIG_DLANE_3_RW_HS_RX_3_HS_RX_3_STEP_SIZE_DESKEW_REG_MASK, 0x1); + } + + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_0_RW_HS_RX_4, + CORE_DIG_DLANE_0_RW_HS_RX_4_HS_RX_4_MAX_ITERATIONS_DESKEW_REG_MASK, 0x96); + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_1_RW_HS_RX_4, + CORE_DIG_DLANE_1_RW_HS_RX_4_HS_RX_4_MAX_ITERATIONS_DESKEW_REG_MASK, 0x96); + if (phy_id <= ISP_MIPI_PHY_ID_1) { + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_2_RW_HS_RX_4, + CORE_DIG_DLANE_2_RW_HS_RX_4_HS_RX_4_MAX_ITERATIONS_DESKEW_REG_MASK, 0x96); + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_3_RW_HS_RX_4, + CORE_DIG_DLANE_3_RW_HS_RX_4_HS_RX_4_MAX_ITERATIONS_DESKEW_REG_MASK, 0x96); + } + + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_0_RW_HS_RX_5, + CORE_DIG_DLANE_0_RW_HS_RX_5_HS_RX_5_DDL_LEFT_INIT_REG_MASK, 0x0); + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_1_RW_HS_RX_5, + CORE_DIG_DLANE_1_RW_HS_RX_5_HS_RX_5_DDL_LEFT_INIT_REG_MASK, 0x0); + if (phy_id <= ISP_MIPI_PHY_ID_1) { + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_2_RW_HS_RX_5, + CORE_DIG_DLANE_2_RW_HS_RX_5_HS_RX_5_DDL_LEFT_INIT_REG_MASK, 0x0); + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_3_RW_HS_RX_5, + CORE_DIG_DLANE_3_RW_HS_RX_5_HS_RX_5_DDL_LEFT_INIT_REG_MASK, 0x0); + } + + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_0_RW_HS_RX_5, + CORE_DIG_DLANE_0_RW_HS_RX_5_HS_RX_5_DDL_MID_INIT_REG_MASK, 0x1); + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_1_RW_HS_RX_5, + CORE_DIG_DLANE_1_RW_HS_RX_5_HS_RX_5_DDL_MID_INIT_REG_MASK, 0x1); + if (phy_id <= ISP_MIPI_PHY_ID_1) { + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_2_RW_HS_RX_5, + CORE_DIG_DLANE_2_RW_HS_RX_5_HS_RX_5_DDL_MID_INIT_REG_MASK, 0x1); + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_3_RW_HS_RX_5, + CORE_DIG_DLANE_3_RW_HS_RX_5_HS_RX_5_DDL_MID_INIT_REG_MASK, 0x1); + } + + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_0_RW_HS_RX_6, + CORE_DIG_DLANE_0_RW_HS_RX_6_HS_RX_6_DDL_RIGHT_INIT_REG_MASK, 0x2); + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_1_RW_HS_RX_6, + CORE_DIG_DLANE_1_RW_HS_RX_6_HS_RX_6_DDL_RIGHT_INIT_REG_MASK, 0x2); + if (phy_id <= ISP_MIPI_PHY_ID_1) { + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_2_RW_HS_RX_6, + CORE_DIG_DLANE_2_RW_HS_RX_6_HS_RX_6_DDL_RIGHT_INIT_REG_MASK, 0x2); + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_3_RW_HS_RX_6, + CORE_DIG_DLANE_3_RW_HS_RX_6_HS_RX_6_DDL_RIGHT_INIT_REG_MASK, 0x2); + } + + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_0_RW_HS_RX_7, + CORE_DIG_DLANE_0_RW_HS_RX_7_HS_RX_7_DESKEW_AUTO_ALGO_SEL_REG_MASK, 0x0); + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_1_RW_HS_RX_7, + CORE_DIG_DLANE_1_RW_HS_RX_7_HS_RX_7_DESKEW_AUTO_ALGO_SEL_REG_MASK, 0x0); + if (phy_id <= ISP_MIPI_PHY_ID_1) { + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_2_RW_HS_RX_7, + CORE_DIG_DLANE_2_RW_HS_RX_7_HS_RX_7_DESKEW_AUTO_ALGO_SEL_REG_MASK, 0x0); + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_3_RW_HS_RX_7, + CORE_DIG_DLANE_3_RW_HS_RX_7_HS_RX_7_DESKEW_AUTO_ALGO_SEL_REG_MASK, 0x0); + } + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_0_RW_HS_RX_7, + CORE_DIG_DLANE_0_RW_HS_RX_7_HS_RX_7_SELECT_ALTERNATE_ALGO_REG_MASK, 0x0); + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_1_RW_HS_RX_7, + CORE_DIG_DLANE_1_RW_HS_RX_7_HS_RX_7_SELECT_ALTERNATE_ALGO_REG_MASK, 0x0); + if (phy_id <= ISP_MIPI_PHY_ID_1) { + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_2_RW_HS_RX_7, + CORE_DIG_DLANE_2_RW_HS_RX_7_HS_RX_7_SELECT_ALTERNATE_ALGO_REG_MASK, 0x0); + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_3_RW_HS_RX_7, + CORE_DIG_DLANE_3_RW_HS_RX_7_HS_RX_7_SELECT_ALTERNATE_ALGO_REG_MASK, 0x0); + } + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_0_RW_HS_RX_3, + CORE_DIG_DLANE_0_RW_HS_RX_3_HS_RX_3_FJUMP_DESKEW_REG_MASK, + phycfg->hs_rx_3hs_rx_3_fjump_deskew_reg); + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_1_RW_HS_RX_3, + CORE_DIG_DLANE_1_RW_HS_RX_3_HS_RX_3_FJUMP_DESKEW_REG_MASK, + phycfg->hs_rx_3hs_rx_3_fjump_deskew_reg); + if (phy_id <= ISP_MIPI_PHY_ID_1) { + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_2_RW_HS_RX_3, + CORE_DIG_DLANE_2_RW_HS_RX_3_HS_RX_3_FJUMP_DESKEW_REG_MASK, + phycfg->hs_rx_3hs_rx_3_fjump_deskew_reg); + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_3_RW_HS_RX_3, + CORE_DIG_DLANE_3_RW_HS_RX_3_HS_RX_3_FJUMP_DESKEW_REG_MASK, + phycfg->hs_rx_3hs_rx_3_fjump_deskew_reg); + } + + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_0_RW_HS_RX_9, + CORE_DIG_DLANE_0_RW_HS_RX_9_HS_RX_9_PHASE_BOUND_REG_MASK, + phycfg->max_phase); + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_1_RW_HS_RX_9, + CORE_DIG_DLANE_1_RW_HS_RX_9_HS_RX_9_PHASE_BOUND_REG_MASK, + phycfg->max_phase); + if (phy_id <= ISP_MIPI_PHY_ID_1) { + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_2_RW_HS_RX_9, + CORE_DIG_DLANE_2_RW_HS_RX_9_HS_RX_9_PHASE_BOUND_REG_MASK, + phycfg->max_phase); + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_3_RW_HS_RX_9, + CORE_DIG_DLANE_3_RW_HS_RX_9_HS_RX_9_PHASE_BOUND_REG_MASK, + phycfg->max_phase); + } + + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_0_RW_HS_RX_6, + CORE_DIG_DLANE_0_RW_HS_RX_6_HS_RX_6_MIN_EYE_OPENING_DESKEW_REG_MASK, + phycfg->hs_rx_6hs_rx_6_min_eye_opening_deskew_reg); + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_1_RW_HS_RX_6, + CORE_DIG_DLANE_1_RW_HS_RX_6_HS_RX_6_MIN_EYE_OPENING_DESKEW_REG_MASK, + phycfg->hs_rx_6hs_rx_6_min_eye_opening_deskew_reg); + if (phy_id <= ISP_MIPI_PHY_ID_1) { + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_2_RW_HS_RX_6, + CORE_DIG_DLANE_2_RW_HS_RX_6_HS_RX_6_MIN_EYE_OPENING_DESKEW_REG_MASK, + phycfg->hs_rx_6hs_rx_6_min_eye_opening_deskew_reg); + isp4phy_mask_wreg(base, phy_id, CORE_DIG_DLANE_3_RW_HS_RX_6, + CORE_DIG_DLANE_3_RW_HS_RX_6_HS_RX_6_MIN_EYE_OPENING_DESKEW_REG_MASK, + phycfg->hs_rx_6hs_rx_6_min_eye_opening_deskew_reg); + } +} + +static void isp4phy_common(void __iomem *base, u32 phy_id) +{ + for (int ctr = 0; ctr < ARRAY_SIZE(startup_seq_common); ctr++) + isp4phy_mask_wreg(base, phy_id, startup_seq_common[ctr].addr, + startup_seq_common[ctr].mask, + startup_seq_common[ctr].data); +} + +static void isp4phy_general_common_config(void __iomem *base, u32 phy_id) +{ + for (int ctr = 0; ctr < ARRAY_SIZE(startup_seq_general_common_config); ctr++) + isp4phy_mask_wreg(base, phy_id, + startup_seq_general_common_config[ctr].addr, + startup_seq_general_common_config[ctr].mask, + startup_seq_general_common_config[ctr].data); +} + +static void +isp4phy_calculate_datarate_cfgs_rx(u32 phy_id, u64 data_rate, + u32 lane, + struct isp4phy_mipi_config *phycfg) +{ + u64 half_rate = data_rate >> 1; + u64 hs_clk_freq; + + hs_clk_freq = half_rate * 1000; + + if (data_rate <= 2500) + phycfg->hs_rx_2hs_rx_2_ignore_alterncal_reg = 1; + else if (data_rate <= 4500) + phycfg->hs_rx_2hs_rx_2_ignore_alterncal_reg = 0; + + if (data_rate < 1500) { + /* do nothing */ + } else if (data_rate < 1588) { + phycfg->afe_lanex_ctrl_2_8oa_cdphy_sel_fast_reg = 0; + phycfg->max_phase = 143; + phycfg->ddlcal_cfg_5ddlcal_dll_fbk_reg = 17; + phycfg->ddlcal_cfg_5ddlcal_ddl_coarse_bank_reg = 3; + } else if (data_rate < 1688) { + phycfg->afe_lanex_ctrl_2_8oa_cdphy_sel_fast_reg = 0; + phycfg->max_phase = 135; + phycfg->ddlcal_cfg_5ddlcal_dll_fbk_reg = 16; + phycfg->ddlcal_cfg_5ddlcal_ddl_coarse_bank_reg = 2; + } else if (data_rate < 1800) { + phycfg->afe_lanex_ctrl_2_8oa_cdphy_sel_fast_reg = 0; + phycfg->max_phase = 127; + phycfg->ddlcal_cfg_5ddlcal_dll_fbk_reg = 15; + phycfg->ddlcal_cfg_5ddlcal_ddl_coarse_bank_reg = 2; + } else if (data_rate < 1929) { + phycfg->afe_lanex_ctrl_2_8oa_cdphy_sel_fast_reg = 0; + phycfg->max_phase = 119; + phycfg->ddlcal_cfg_5ddlcal_dll_fbk_reg = 14; + phycfg->ddlcal_cfg_5ddlcal_ddl_coarse_bank_reg = 2; + } else if (data_rate < 2077) { + phycfg->afe_lanex_ctrl_2_8oa_cdphy_sel_fast_reg = 0; + phycfg->max_phase = 111; + phycfg->ddlcal_cfg_5ddlcal_dll_fbk_reg = 13; + phycfg->ddlcal_cfg_5ddlcal_ddl_coarse_bank_reg = 2; + } else if (data_rate < 2250) { + phycfg->afe_lanex_ctrl_2_8oa_cdphy_sel_fast_reg = 0; + phycfg->max_phase = 103; + phycfg->ddlcal_cfg_5ddlcal_dll_fbk_reg = 12; + phycfg->ddlcal_cfg_5ddlcal_ddl_coarse_bank_reg = 1; + } else if (data_rate < 2455) { + phycfg->afe_lanex_ctrl_2_8oa_cdphy_sel_fast_reg = 0; + phycfg->max_phase = 95; + phycfg->ddlcal_cfg_5ddlcal_dll_fbk_reg = 11; + phycfg->ddlcal_cfg_5ddlcal_ddl_coarse_bank_reg = 1; + } else if (data_rate < 2700) { + phycfg->afe_lanex_ctrl_2_8oa_cdphy_sel_fast_reg = 0; + phycfg->max_phase = 87; + phycfg->ddlcal_cfg_5ddlcal_dll_fbk_reg = 10; + phycfg->ddlcal_cfg_5ddlcal_ddl_coarse_bank_reg = 1; + } else if (data_rate < 3000) { + phycfg->afe_lanex_ctrl_2_8oa_cdphy_sel_fast_reg = 0; + phycfg->max_phase = 79; + phycfg->ddlcal_cfg_5ddlcal_dll_fbk_reg = 9; + phycfg->ddlcal_cfg_5ddlcal_ddl_coarse_bank_reg = 1; + } else if (data_rate < 3230) { + phycfg->afe_lanex_ctrl_2_8oa_cdphy_sel_fast_reg = 0; + phycfg->max_phase = 71; + phycfg->ddlcal_cfg_5ddlcal_dll_fbk_reg = 8; + phycfg->ddlcal_cfg_5ddlcal_ddl_coarse_bank_reg = 0; + } else if (data_rate < 3600) { + phycfg->afe_lanex_ctrl_2_8oa_cdphy_sel_fast_reg = 1; + phycfg->max_phase = 87; + phycfg->ddlcal_cfg_5ddlcal_dll_fbk_reg = 10; + phycfg->ddlcal_cfg_5ddlcal_ddl_coarse_bank_reg = 1; + } else if (data_rate < 4000) { + phycfg->afe_lanex_ctrl_2_8oa_cdphy_sel_fast_reg = 1; + phycfg->max_phase = 79; + phycfg->ddlcal_cfg_5ddlcal_dll_fbk_reg = 9; + phycfg->ddlcal_cfg_5ddlcal_ddl_coarse_bank_reg = 1; + } else if (data_rate < 4500) { + phycfg->afe_lanex_ctrl_2_8oa_cdphy_sel_fast_reg = 1; + phycfg->max_phase = 71; + phycfg->ddlcal_cfg_5ddlcal_dll_fbk_reg = 8; + phycfg->ddlcal_cfg_5ddlcal_ddl_coarse_bank_reg = 1; + } else { + phycfg->afe_lanex_ctrl_2_8oa_cdphy_sel_fast_reg = 1; + phycfg->max_phase = 63; + phycfg->ddlcal_cfg_5ddlcal_dll_fbk_reg = 7; + phycfg->ddlcal_cfg_5ddlcal_ddl_coarse_bank_reg = 0; + } + + if (data_rate <= 1500) { + phycfg->afe_lanex_ctrl_2_12oa_dphy_ddl_bypass_en_ovr_val_reg = 1; + phycfg->afe_lanex_ctrl_2_13oa_dphy_ddl_bypass_en_ovr_en_reg = 1; + phycfg->afe_lanex_ctrl_2_12oa_dphy_dll_en_ovr_val_reg = 0; + phycfg->afe_lanex_ctrl_2_13oa_dphy_dll_en_ovr_en_reg = 1; + phycfg->cfg_1cfg_1_deskew_supported_reg = 0; + phycfg->cfg_1cfg_1_sot_detection_reg = 1; + } else if (data_rate <= 4500) { + phycfg->afe_lanex_ctrl_2_12oa_dphy_ddl_bypass_en_ovr_val_reg = 0; + phycfg->afe_lanex_ctrl_2_13oa_dphy_ddl_bypass_en_ovr_en_reg = 0; + phycfg->afe_lanex_ctrl_2_12oa_dphy_dll_en_ovr_val_reg = 0; + phycfg->afe_lanex_ctrl_2_13oa_dphy_dll_en_ovr_en_reg = 0; + phycfg->cfg_1cfg_1_deskew_supported_reg = 1; + phycfg->cfg_1cfg_1_sot_detection_reg = 0; + } + + if (data_rate < 160) + phycfg->afe_lanex_ctrl_2_9oa_hs_clk_div_reg = 0b001; + else if (data_rate < 320) + phycfg->afe_lanex_ctrl_2_9oa_hs_clk_div_reg = 0b010; + else if (data_rate < 640) + phycfg->afe_lanex_ctrl_2_9oa_hs_clk_div_reg = 0b011; + else if (data_rate < 1280) + phycfg->afe_lanex_ctrl_2_9oa_hs_clk_div_reg = 0b100; + else if (data_rate < 2560) + phycfg->afe_lanex_ctrl_2_9oa_hs_clk_div_reg = 0b101; + else + phycfg->afe_lanex_ctrl_2_9oa_hs_clk_div_reg = 0b110; + + u32 t_hs_settle_ns = MIN_T_HS_SETTLE_NS + MAX_T_HS_SETTLE_NS; + + t_hs_settle_ns = t_hs_settle_ns >> 1; + u32 t_hs_settle_ui = MIN_T_HS_SETTLE_UI + MAX_T_HS_SETTLE_UI; + + t_hs_settle_ui = t_hs_settle_ui >> 1; + + t_hs_settle_ui = t_hs_settle_ui * 1000000; + t_hs_settle_ui = t_hs_settle_ui >> 1; + do_div(t_hs_settle_ui, hs_clk_freq); + u32 ths_settle_target = t_hs_settle_ns + t_hs_settle_ui; + + do_div(ths_settle_target, T_DCO); + phycfg->hs_rx_0hs_rx_0_thssettle_reg = ths_settle_target - TMIN_RX - 7; + + u16 jump_deskew_reg = phycfg->max_phase + 39; + + do_div(jump_deskew_reg, 40); + phycfg->hs_rx_3hs_rx_3_fjump_deskew_reg = jump_deskew_reg; + + u16 eye_opening_deskew_reg = phycfg->max_phase + 4; + + do_div(eye_opening_deskew_reg, 5); + phycfg->hs_rx_6hs_rx_6_min_eye_opening_deskew_reg = eye_opening_deskew_reg; +} + +static void isp4phy_startup_seq_dphy_rx(void __iomem *base, u32 phy_id, + u64 data_rate, u32 lane) +{ + struct isp4phy_mipi_config phycfg; + + memset(&phycfg, 0, sizeof(phycfg)); + + isp4phy_calculate_datarate_cfgs_rx(phy_id, data_rate, lane, &phycfg); + isp4phy_general_common_config(base, phy_id); + isp4phy_common(base, phy_id); + isp4phy_dphy_specific(base, phy_id, data_rate, &phycfg); + isp4phy_dphy_periodic_deskew_program(base, phy_id); + isp4phy_optional_features_dphy(base, phy_id); +} + +static int isp4phy_startup_seq_cdphy_rx(struct device *dev, + void __iomem *base, u32 phy_id, + u64 data_rate, u32 lane) +{ + struct isp4phy_mipi_reg phy_reg = {0}; + + /* readback the mipi phy reg */ + phy_reg.isp_mipi_phy0.value = + isp4hw_rreg(base, (uintptr_t)&isp_mipi_phy_reg[phy_id]->isp_mipi_phy0); + phy_reg.isp_mipi_phy1.value = + isp4hw_rreg(base, (uintptr_t)&isp_mipi_phy_reg[phy_id]->isp_mipi_phy1); + phy_reg.isp_mipi_phy2.value = + isp4hw_rreg(base, (uintptr_t)&isp_mipi_phy_reg[phy_id]->isp_mipi_phy2); + phy_reg.isp_mipi_phy4.value = + isp4hw_rreg(base, (uintptr_t)&isp_mipi_phy_reg[phy_id]->isp_mipi_phy4); + phy_reg.isp_mipi_phy5.value = + isp4hw_rreg(base, (uintptr_t)&isp_mipi_phy_reg[phy_id]->isp_mipi_phy5); + phy_reg.isp_mipi_phy6.value = + isp4hw_rreg(base, (uintptr_t)&isp_mipi_phy_reg[phy_id]->isp_mipi_phy6); + phy_reg.isp_mipi_phy7.value = + isp4hw_rreg(base, (uintptr_t)&isp_mipi_phy_reg[phy_id]->isp_mipi_phy7); + + phy_reg.isp_mipi_phy0.bit.shutdownz = 0; + phy_reg.isp_mipi_phy0.bit.rstz = 0; + isp4hw_wreg(base, (uintptr_t)(&isp_mipi_phy_reg[phy_id]->isp_mipi_phy0), + phy_reg.isp_mipi_phy0.value); + + /*PHY register access test */ + isp4phy_wreg(base, phy_id, CORE_DIG_DLANE_0_RW_LP_0, 0x473C); + usleep_range(10, 20); + if (isp4phy_rreg(base, phy_id, CORE_DIG_DLANE_0_RW_LP_0) == 0x473C) { + dev_dbg(dev, "PHY register access test suc\n"); + } else { + dev_err(dev, "PHY register access test fail\n"); + return -EFAULT; + } + + /** T1: top level static inputs must be set to the desired + * configuration (for example, phyMode. These *inputs can be + * identified with Startup and Active Mode state: Static label + * in Chapter 4, ¡°Signal Descriptions¡±). + */ + phy_reg.isp_mipi_phy5.value = (1 << lane) - 1; + phy_reg.isp_mipi_phy5.bit.forcerxmode_clk = 1; + isp4hw_wreg(base, (uintptr_t)&isp_mipi_phy_reg[phy_id]->isp_mipi_phy5, + phy_reg.isp_mipi_phy5.value); + + phy_reg.isp_mipi_phy4.value = (0x2 << lane) - 1; + isp4hw_wreg(base, (uintptr_t)&isp_mipi_phy_reg[phy_id]->isp_mipi_phy4, + phy_reg.isp_mipi_phy4.value); + + phy_reg.isp_mipi_phy1.bit.mode = ISP_MIPI_DPHY; + isp4hw_wreg(base, (uintptr_t)(&isp_mipi_phy_reg[phy_id]->isp_mipi_phy1), + phy_reg.isp_mipi_phy1.value); + + /** T2: APB slave is active and can be accessed (presetN = 1b1)*/ + /** T3: static register fields are programmed/read through the APB, + * with PHY in reset (these register + * fields can be found in Chapter 11.2, Static Register Access). + */ + /* DPHY mode setup */ + isp4phy_startup_seq_dphy_rx(base, phy_id, data_rate, lane); + + /** T4: initial programming phase is over and PHY is ready + * to leave Shutdown Mode (shutdownN = 1¡¯b1 + * and rstN = 1¡¯b1). + */ + phy_reg.isp_mipi_phy0.bit.shutdownz = 1; + phy_reg.isp_mipi_phy0.bit.rstz = 1; + isp4hw_wreg(base, (uintptr_t)&isp_mipi_phy_reg[phy_id]->isp_mipi_phy0, + phy_reg.isp_mipi_phy0.value); + + dev_dbg(dev, "Termination calibration observability: 0x%x\n", + isp4phy_rreg(base, phy_id, PPI_R_TERMCAL_DEBUG_0)); + + /** T5: internal calibrations ongoing. No configurations are accepted + * during power-on-reset (POR). + * phyReady asserts to signal that POR is complete. + */ + do { + usleep_range(1000, 2000); + phy_reg.isp_mipi_phy7.value = + isp4hw_rreg(base, (uintptr_t)&isp_mipi_phy_reg[phy_id]->isp_mipi_phy7); + dev_dbg(dev, "Wait for phyReady: 0x%x\n", + phy_reg.isp_mipi_phy7.value); + } while (phy_reg.isp_mipi_phy7.bit.ready != 1); + + /** T6: dynamic register fields can be programmed/read through APB + * (these register fields can be found in Chapter 11.3, Dynamic Register Access). + * Check Chapter 9.3.4, D-PHY and C-PHY HS Receivers for analog settings that must be + * programmed in T3. + */ + + /** T7: de-assert forcerxmode_N.*/ + phy_reg.isp_mipi_phy5.bit.forcerxmode_0 = 0; + phy_reg.isp_mipi_phy5.bit.forcerxmode_1 = 0; + phy_reg.isp_mipi_phy5.bit.forcerxmode_2 = 0; + phy_reg.isp_mipi_phy5.bit.forcerxmode_3 = 0; + phy_reg.isp_mipi_phy5.bit.forcerxmode_clk = 0; + isp4hw_wreg(base, (uintptr_t)(&isp_mipi_phy_reg[phy_id]->isp_mipi_phy5), + phy_reg.isp_mipi_phy5.value); + return 0; +} + +int isp4phy_start(struct device *dev, + void __iomem *base, u32 phy_id, u64 bit_rate, + u32 lane_num) +{ + if (phy_id >= ISP_MIPI_PHY_ID_MAX) + return -EINVAL; + + if (phy_id == 2 && lane_num > 2) { + dev_err(dev, "MIPI PHY 2 just has 2 lane\n"); + return -EINVAL; + } + + if (phy_id == 0 && lane_num > 4) { + dev_err(dev, "fail invalid lane number %u for phy0\n", + lane_num); + return -EINVAL; + } + + return isp4phy_startup_seq_cdphy_rx(dev, base, phy_id, bit_rate, lane_num); +} + +int isp4phy_stop(void __iomem *base, u32 phy_id) +{ + struct isp4phy_mipi_reg phy_reg = {0}; + + if (phy_id >= ISP_MIPI_PHY_ID_MAX) + return -EINVAL; + + phy_reg.isp_mipi_phy0.value = + isp4hw_rreg(base, (uintptr_t) + (&isp_mipi_phy_reg[phy_id]->isp_mipi_phy0)); + + /* shutdown phy */ + phy_reg.isp_mipi_phy0.bit.shutdownz = 0; + phy_reg.isp_mipi_phy0.bit.rstz = 0; + isp4hw_wreg(base, + (uintptr_t)(&isp_mipi_phy_reg[phy_id]->isp_mipi_phy0), + phy_reg.isp_mipi_phy0.value); + + return 0; +} diff --git a/drivers/media/platform/amd/isp4/isp4_phy.h b/drivers/media/platform/amd/isp4/isp4_phy.h new file mode 100644 index 000000000000..2909892dbd00 --- /dev/null +++ b/drivers/media/platform/amd/isp4/isp4_phy.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2025 Advanced Micro Devices, Inc. + */ + +#ifndef _ISP4_PHY_H_ +#define _ISP4_PHY_H_ + +int isp4phy_start(struct device *dev, + void __iomem *base, u32 phy_id, u64 bit_rate, + u32 lane_num); +int isp4phy_stop(void __iomem *base, u32 phy_id); + +#endif From patchwork Sun Jun 8 14:49:11 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Du, Bin" X-Patchwork-Id: 894860 Received: from NAM02-SN1-obe.outbound.protection.outlook.com (mail-sn1nam02on2083.outbound.protection.outlook.com [40.107.96.83]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A4A5B22A7EC; Sun, 8 Jun 2025 14:50:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.96.83 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749394204; cv=fail; b=OjMibDliXab72bMjFUXy7ASYTIrk6c2AQlkdJkO6ZSqv75P2g/h+uEjdt62RHqngisUqLC9cPkosmu28LUGwd/nwWg/tZieGtZ3jFEORktqlx4p9Kyp+0pRfvPhyOQdLZARu08zopUy51YEB5ydRrU7GO58Q5bepdBe9NmPJeuw= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749394204; c=relaxed/simple; bh=ZraS2G6Z0ayRdd6roYGpd1iO7lPO7RHq7UZfd2JKQ5Y=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=I94yRXpSyiy+s5dNccsqjMPAKHeINSmYBh491405lqfB3GunpuLMjintsseVV7YBQbDY6kkJC1/sBgZbDp2hsH8jzMHTkdPLgUAHejxgp2VPduwh9b9XtLmuQsCW/U+dqpCkKiiImAPKRmiIal42WzgF9Hf/rXYRHsTjB1vjRYc= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com; spf=fail smtp.mailfrom=amd.com; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b=uDAj6hIo; arc=fail smtp.client-ip=40.107.96.83 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=amd.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="uDAj6hIo" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=ZamEFXGAoT7lLzgpW1PzCrU7jlgjoFE468FoOrCFIxYzv6RCTUQcJA21xnRTkaXTw/M0Fz5Lh660q/ttN7RQKi2qOgJ+H89obw5MBEMn2jsaLBm14cLy/k7m6Bhomdsat637YW7bJY+MWvnq3RfbWPC8Nbq4xI9fmm5njyMhcvyjqV0bz9pTL9BfpmVvsa+mHgGog8WN+GERcaR+N0b2/mDfN1D+Wl5i3gvKMZLKhP1NKDP1WjVjSS88DPuJbktmKZtJlYfP7Dmb/JEEexRTJm6H2+8wbj4al1rCWSEMW63lwyxRxkrO+NaJ+CLNN+WB9YNt8jMZS7HjQ5nrTntS7g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=o7OQWvnef0sc5wRky3R37nIsw1QLY8MriPcN6FAPSrU=; b=oydIAdLVOeGervmEh+4Uk/fx1WKL59B4kmOEGYaEB4afhxgNCmo3GWD1zntsswG7FD1qh+pZTQTNUrGopPGVFbUTVoSeKM7xEyUru9GMXFeFYUf36gXFJ/tM0G89di1saX84qSvAQZt2wpjwqoTDQoSds3gZ7i5Z45SISZkuI7tmXR8WP8IMl3J9lpLbZ/v94c5k8Orjp2gCwW+sPjHhXbNqXDx2UheHNEsH1HLhiPIsyvNRs9T0bDR95U7gvo1Onm9BBaskcTls2PsMc0ij98d4rj1AUJ0pfnjOdLdbjyQTYqZCnKArU5LXLDafIO4/eHzsbO+Wx6HCBRIw9/AIyg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=o7OQWvnef0sc5wRky3R37nIsw1QLY8MriPcN6FAPSrU=; b=uDAj6hIoUzisx9UQ8m1bRViZ3RfR0zliKI9Rj/7jTJxfsdxz6Jn7VnZf+tAUhFi0j2QjJYH4N2lCT+5Jdrd2Wb30J/hcQbkQmf1JaMY+7NpA9QPDmujqc0Frn7G9ERUNLoyKzo8Xw4gGs2Ukh7JxCYilAnaQ5OK9JoUhsAx0q8g= Received: from SJ0PR05CA0124.namprd05.prod.outlook.com (2603:10b6:a03:33d::9) by IA1PR12MB8286.namprd12.prod.outlook.com (2603:10b6:208:3f8::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8792.34; Sun, 8 Jun 2025 14:49:55 +0000 Received: from SJ5PEPF000001D0.namprd05.prod.outlook.com (2603:10b6:a03:33d:cafe::25) by SJ0PR05CA0124.outlook.office365.com (2603:10b6:a03:33d::9) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8835.14 via Frontend Transport; Sun, 8 Jun 2025 14:49:54 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SJ5PEPF000001D0.mail.protection.outlook.com (10.167.242.52) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8835.15 via Frontend Transport; Sun, 8 Jun 2025 14:49:54 +0000 Received: from 555e2b870847.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Sun, 8 Jun 2025 09:49:49 -0500 From: Bin Du To: , , , , , , , CC: , , , , , , , , "Bin Du" Subject: [PATCH v1 4/9] media: platform: amd: Add isp4 fw and hw interface Date: Sun, 8 Jun 2025 22:49:11 +0800 Message-ID: <20250608144916.222835-5-Bin.Du@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250608144916.222835-1-Bin.Du@amd.com> References: <20250608144916.222835-1-Bin.Du@amd.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001D0:EE_|IA1PR12MB8286:EE_ X-MS-Office365-Filtering-Correlation-Id: bbd3359f-e4c7-4d39-3546-08dda69bbb0f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: u0WOqgqX/y7y+zoZvK99ryAYCiPAALAPNrdOHdlLuOSGOAYPmd0XoU1iNDbx3viOEX2/4g24SQy9bxoAqFAJV1Ok9pUVlrsCjHt+d8e6gn0+wEWHAAKFPdyQKlRSq0TF6POAMdpJa6pVSzC3HZ9rqAZog0ZPk9St4EvrjRhm5ze1zv8o94o648MYR90J/D/BYeP623LAL9oc9bqUvWjCalaNJiwNldbEoG3gMZgQQTc9kc5pR0kbF7R2XhIwvjZEjSJpQgpFGhMZkIDCL16OljqSkqEa2KSmgkj9+ZJRs4GXYhki+rdIVVis+UW3VbhWZ+NQjjl3hjBqikdX/cFZQY2Ueer9zurnZFSE39YObobC8FI23CPJ90eqJMCp0/5+5hpvPJqGvNVDJhtNuArwfnmwWR/zjI6vxBK4D0sd6xVDJiInHOeYoMspGBS9O8DA09irRPAjz6tu1Ubkl6AkukykGDN3uuNnPfC9hFA18+T3vdsGWtXnuVlJZjuejbdvvMKZtHi+Ha5tiSsQPQf6moPr0BJUqV1PEspH37vQe+rtzfVjpv/n2ZARweCo0/fsSBplodAWEdJlNC2gL9c6olKnrDF5SHoy+D2p1nIo+hwWN+Gn/38aJVwbz6gW2e1mfuX8b53n2ZkkLxo2auwKhPZ612GLEr+YQlO7rbTgLcAY0XN7U6e5K1gWBSZXV21uDqwXvp1j2S5qX8Z0ripcVxtHDCi/QOU69wuuCZROXLfbxq7FDQeZlZ6w2am2tpLnQqdRJ8bEIh/XIGKxX4rYgmesYMmspYCtrV/RrFF34B0QyJ9adHmQWbAtoG9T/NvQHl+O1X/8TwLxZE2RvquIVNtaMvj1ftpICKSv+rtvgBiocgHWzYCpQAE7F7uTl2fEuL/H/sArO4VH456FKKaSUNsrLwa+7bZGJyT01R6pnVx2SWvuTJDYNx2m6/4HO6oGGom/ps0hVqJcXIvbLuYyKxtp1/MJGnGaoufZcKxQNknoL8tA32CqC+3a86QnSjGPlrXx5GAOND/6KiTwE5xvUQj3h6xnII/JXAHvsVE4QKdn0yhSQ9b5HAUW97bS0aLbocQE3HdQ2Dr0y2RYGsPMw+l6K4pfmUCu6lfmT62lGeNlAzbqhZ0s9gGWxjxc7borm6z90fSX6Lggptgcc1UTKJszCuSyIVmlV8/K4nSZllSDSN1/aTof/AlLMmL3eo69jTf7KwvZUuz4MS98sJL3KM44AQyL4DXehmtvv/j2VTJrn2d/NnkpNyDm7JSl1RpbSdi73ksWPbDF8Fgz6v28gQUEW5JpP06BV/j4a95NPnem74pkCyk4rAGsDBMBoYia4vQoWCDQXQIOMpMJbPzxbnCpDCNNxVosk9ckWZPFXdTW24CzOgTRMoZoUNMQ2VMjc7CQWZPI5/aXfqMTqtVpeAHV0ZtnwKGGJRNhJAdRwbm52BKjiSBQtoBUDh4DlfybTB62HfncOz7BAfIvgpPPTshfWZQV1tioNtmsq1q38gNrAQeL0w/GZ6QHz/IoT38m X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jun 2025 14:49:54.3683 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bbd3359f-e4c7-4d39-3546-08dda69bbb0f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001D0.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8286 ISP firmware controls ISP HW pipeline using dedicated embedded processor called ccpu. The communication between ISP FW and driver is using commands and response messages sent through the ring buffer. Command buffers support either global setting that is not specific to the steam and support stream specific parameters. Response buffers contains ISP FW notification information such as frame buffer done and command done. IRQ is used for receiving response buffer from ISP firmware, which is handled in the main isp4 media device. ISP ccpu is booted up through the firmware loading helper function prior to stream start. Memory used for command buffer and response buffer needs to be allocated from amdgpu buffer manager because isp4 is a child device of amdgpu. Signed-off-by: Bin Du Signed-off-by: Svetoslav Stoilov Change-Id: Ib15ed5b21fba7686d174a1326e3a66573e93b0ea --- drivers/media/platform/amd/isp4/Makefile | 15 + .../platform/amd/isp4/isp4_fw_cmd_resp.h | 318 +++++ .../media/platform/amd/isp4/isp4_interface.c | 1058 +++++++++++++++++ .../media/platform/amd/isp4/isp4_interface.h | 164 +++ 4 files changed, 1555 insertions(+) create mode 100644 drivers/media/platform/amd/isp4/isp4_fw_cmd_resp.h create mode 100644 drivers/media/platform/amd/isp4/isp4_interface.c create mode 100644 drivers/media/platform/amd/isp4/isp4_interface.h diff --git a/drivers/media/platform/amd/isp4/Makefile b/drivers/media/platform/amd/isp4/Makefile index 7cb496a56353..c76b8a327be6 100644 --- a/drivers/media/platform/amd/isp4/Makefile +++ b/drivers/media/platform/amd/isp4/Makefile @@ -5,10 +5,25 @@ obj-$(CONFIG_AMD_ISP4) += amd_capture.o amd_capture-objs := isp4.o \ isp4_phy.o \ + isp4_interface.o \ isp4_hw.o \ ccflags-y += -I$(srctree)/drivers/media/platform/amd/isp4 +ccflags-y += -I$(srctree)/drivers/gpu/drm/amd/include +ccflags-y += -I$(srctree)/drivers/gpu/drm/amd/amdgpu +ccflags-y += -I$(srctree)/drivers/gpu/drm/amd/pm/inc +ccflags-y += -I$(srctree)/include/drm ccflags-y += -I$(srctree)/include +ccflags-y += -I$(srctree)/include/uapi/drm +ccflags-y += -I$(srctree)/drivers/gpu/drm/amd/scheduler +ccflags-y += -I$(srctree)/drivers/gpu/drm/amd/powerplay/inc +ccflags-y += -I$(srctree)/drivers/gpu/drm/amd/acp/include +ccflags-y += -I$(srctree)/drivers/gpu/drm/amd/display +ccflags-y += -I$(srctree)/drivers/gpu/drm/amd/display/include +ccflags-y += -I$(srctree)/drivers/gpu/drm/amd/display/modules/inc +ccflags-y += -I$(srctree)/drivers/gpu/drm/amd/display/dc +ccflags-y += -I$(srctree)/drivers/gpu/drm/amd/display/amdgpu_dm +ccflags-y += -I$(srctree)/../external/libdrm/amdgpu ifneq ($(call cc-option, -mpreferred-stack-boundary=4),) cc_stack_align := -mpreferred-stack-boundary=4 diff --git a/drivers/media/platform/amd/isp4/isp4_fw_cmd_resp.h b/drivers/media/platform/amd/isp4/isp4_fw_cmd_resp.h new file mode 100644 index 000000000000..437d89469af2 --- /dev/null +++ b/drivers/media/platform/amd/isp4/isp4_fw_cmd_resp.h @@ -0,0 +1,318 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2025 Advanced Micro Devices, Inc. + */ + +#ifndef _ISP4_CMD_RESP_H_ +#define _ISP4_CMD_RESP_H_ + +/* + * @brief Host and Firmware command & response channel. + * Two types of command/response channel. + * Type Global Command has one command/response channel. + * Type Stream Command has one command/response channel. + *----------- ------------ + *| | --------------------------- | | + *| | ---->| Global Command |----> | | + *| | --------------------------- | | + *| | | | + *| | | | + *| | --------------------------- | | + *| | ---->| Stream Command |----> | | + *| | --------------------------- | | + *| | | | + *| | | | + *| | | | + *| HOST | | Firmware | + *| | | | + *| | | | + *| | -------------------------- | | + *| | <----| Global Response |<---- | | + *| | -------------------------- | | + *| | | | + *| | | | + *| | -------------------------- | | + *| | <----| Stream Response |<---- | | + *| | -------------------------- | | + *| | | | + *| | | | + *----------- ------------ + */ + +/* + * @brief command ID format + * cmd_id is in the format of following type: + * type: indicate command type, global/stream commands. + * group: indicate the command group. + * id: A unique command identification in one type and group. + * |<-Bit31 ~ Bit24->|<-Bit23 ~ Bit16->|<-Bit15 ~ Bit0->| + * | type | group | id | + */ + +#define CMD_TYPE_SHIFT (24) +#define CMD_GROUP_SHIFT (16) +#define CMD_TYPE_STREAM_CTRL ((u32)0x2 << CMD_TYPE_SHIFT) + +#define CMD_GROUP_STREAM_CTRL ((u32)0x1 << CMD_GROUP_SHIFT) +#define CMD_GROUP_STREAM_BUFFER ((u32)0x4 << CMD_GROUP_SHIFT) + +/* Stream Command */ +#define CMD_ID_SET_STREAM_CONFIG \ + (CMD_TYPE_STREAM_CTRL | CMD_GROUP_STREAM_CTRL | 0x1) +#define CMD_ID_SET_OUT_CHAN_PROP \ + (CMD_TYPE_STREAM_CTRL | CMD_GROUP_STREAM_CTRL | 0x3) +#define CMD_ID_ENABLE_OUT_CHAN \ + (CMD_TYPE_STREAM_CTRL | CMD_GROUP_STREAM_CTRL | 0x5) +#define CMD_ID_START_STREAM \ + (CMD_TYPE_STREAM_CTRL | CMD_GROUP_STREAM_CTRL | 0x7) +#define CMD_ID_STOP_STREAM \ + (CMD_TYPE_STREAM_CTRL | CMD_GROUP_STREAM_CTRL | 0x8) + +/* Stream Buffer Command */ +#define CMD_ID_SEND_BUFFER \ + (CMD_TYPE_STREAM_CTRL | CMD_GROUP_STREAM_BUFFER | 0x1) + +/* + * @brief response ID format + * resp_id is in the format of following type: + * type: indicate command type, global/stream commands. + * group: indicate the command group. + * id: A unique command identification in one type and group. + * |<-Bit31 ~ Bit24->|<-Bit23 ~ Bit16->|<-Bit15 ~ Bit0->| + * | type | group | id | + */ + +#define RESP_GROUP_SHIFT (16) +#define RESP_GROUP_MASK (0xff << RESP_GROUP_SHIFT) + +#define GET_RESP_GROUP_VALUE(resp_id) \ + (((resp_id) & RESP_GROUP_MASK) >> \ + RESP_GROUP_SHIFT) +#define GET_RESP_ID_VALUE(resp_id) ((resp_id) & 0xffff) + +#define RESP_GROUP_GENERAL (0x1 << RESP_GROUP_SHIFT) +#define RESP_GROUP_NOTIFICATION (0x3 << RESP_GROUP_SHIFT) + +/* General Response */ +#define RESP_ID_CMD_DONE (RESP_GROUP_GENERAL | 0x1) + +/* Notification */ +#define RESP_ID_NOTI_FRAME_DONE (RESP_GROUP_NOTIFICATION | 0x1) + +#define CMD_STATUS_SUCCESS (0) +#define CMD_STATUS_FAIL (1) +#define CMD_STATUS_SKIPPED (2) + +#define ADDR_SPACE_TYPE_GPU_VA 4 + +#define FW_MEMORY_POOL_SIZE (200 * 1024 * 1024) + +/* + * standard ISP mipicsi=>isp + */ +#define MIPI0_ISP_PIPELINE_ID 0x5f91 + +enum isp4fw_sensor_id { + SENSOR_ID_ON_MIPI0 = 0, /* Sensor id for ISP input from MIPI port 0 */ +}; + +enum isp4fw_stream_id { + STREAM_ID_INVALID = -1, /* STREAM_ID_INVALID. */ + STREAM_ID_1 = 0, /* STREAM_ID_1. */ + STREAM_ID_2 = 1, /* STREAM_ID_2. */ + STREAM_ID_3 = 2, /* STREAM_ID_3. */ + STREAM_ID_MAXIMUM /* STREAM_ID_MAXIMUM. */ +}; + +enum isp4fw_image_format { + IMAGE_FORMAT_NV12 = 1, /* 4:2:0,semi-planar, 8-bit */ + IMAGE_FORMAT_YUV422INTERLEAVED = 7, /* interleave, 4:2:2, 8-bit */ +}; + +enum isp4fw_pipe_out_ch { + ISP_PIPE_OUT_CH_PREVIEW = 0, +}; + +enum isp4fw_yuv_range { + ISP_YUV_RANGE_FULL = 0, /* YUV value range in 0~255 */ + ISP_YUV_RANGE_NARROW = 1, /* YUV value range in 16~235 */ + ISP_YUV_RANGE_MAX +}; + +enum isp4fw_buffer_type { + BUFFER_TYPE_PREVIEW = 8, + BUFFER_TYPE_META_INFO = 10, + BUFFER_TYPE_MEM_POOL = 15, +}; + +enum isp4fw_buffer_status { + BUFFER_STATUS_INVALID, /* The buffer is INVALID */ + BUFFER_STATUS_SKIPPED, /* The buffer is not filled with image data */ + BUFFER_STATUS_EXIST, /* The buffer is exist and waiting for filled */ + BUFFER_STATUS_DONE, /* The buffer is filled with image data */ + BUFFER_STATUS_LACK, /* The buffer is unavailable */ + BUFFER_STATUS_DIRTY, /* The buffer is dirty, probably caused by + * LMI leakage + */ + BUFFER_STATUS_MAX /* The buffer STATUS_MAX */ +}; + +enum isp4fw_buffer_source { + /* The buffer is from the stream buffer queue */ + BUFFER_SOURCE_STREAM, +}; + +struct isp4fw_error_code { + u32 code1; + u32 code2; + u32 code3; + u32 code4; + u32 code5; +}; + +/* + * Command Structure for FW + */ + +struct isp4fw_cmd { + u32 cmd_seq_num; + u32 cmd_id; + u32 cmd_param[12]; + u16 cmd_stream_id; + u8 cmd_silent_resp; + u8 reserved; + u32 cmd_check_sum; +}; + +struct isp4fw_resp_cmd_done { + /* The host2fw command seqNum. + * To indicate which command this response refer to. + */ + u32 cmd_seq_num; + /* The host2fw command id for host double check. */ + u32 cmd_id; + /* Indicate the command process status. + * 0 means success. 1 means fail. 2 means skipped + */ + u16 cmd_status; + /* If the cmd_status is 1, that means the command is processed fail, */ + /* host can check the isp4fw_error_code to get the detail + * error information + */ + u16 isp4fw_error_code; + /* The response payload will be in different struct type */ + /* according to different cmd done response. */ + u8 payload[36]; +}; + +struct isp4fw_resp_param_package { + u32 package_addr_lo; /* The low 32 bit addr of the pkg address. */ + u32 package_addr_hi; /* The high 32 bit addr of the pkg address. */ + u32 package_size; /* The total pkg size in bytes. */ + u32 package_check_sum; /* The byte sum of the pkg. */ +}; + +struct isp4fw_resp { + u32 resp_seq_num; + u32 resp_id; + union { + struct isp4fw_resp_cmd_done cmd_done; + struct isp4fw_resp_param_package frame_done; + u32 resp_param[12]; + } param; + u8 reserved[4]; + u32 resp_check_sum; +}; + +struct isp4fw_mipi_pipe_path_cfg { + u32 b_enable; + enum isp4fw_sensor_id isp4fw_sensor_id; +}; + +struct isp4fw_isp_pipe_path_cfg { + u32 isp_pipe_id; /* pipe ids for pipeline construction */ +}; + +struct isp4fw_isp_stream_cfg { + /* Isp mipi path */ + struct isp4fw_mipi_pipe_path_cfg mipi_pipe_path_cfg; + /* Isp pipe path */ + struct isp4fw_isp_pipe_path_cfg isp_pipe_path_cfg; + /* enable TNR */ + u32 b_enable_tnr; + /* number of frame rta per-processing, + * set to 0 to use fw default value + */ + u32 rta_frames_per_proc; +}; + +struct isp4fw_image_prop { + enum isp4fw_image_format image_format; /* Image format */ + u32 width; /* Width */ + u32 height; /* Height */ + u32 luma_pitch; /* Luma pitch */ + u32 chroma_pitch; /* Chrom pitch */ + enum isp4fw_yuv_range yuv_range; /* YUV value range */ +}; + +struct isp4fw_buffer { + /* A check num for debug usage, host need to */ + /* set the buf_tags to different number */ + u32 buf_tags; + union { + u32 value; + struct { + u32 space : 16; + u32 vmid : 16; + } bit; + } vmid_space; + u32 buf_base_a_lo; /* Low address of buffer A */ + u32 buf_base_a_hi; /* High address of buffer A */ + u32 buf_size_a; /* Buffer size of buffer A */ + + u32 buf_base_b_lo; /* Low address of buffer B */ + u32 buf_base_b_hi; /* High address of buffer B */ + u32 buf_size_b; /* Buffer size of buffer B */ + + u32 buf_base_c_lo; /* Low address of buffer C */ + u32 buf_base_c_hi; /* High address of buffer C */ + u32 buf_size_c; /* Buffer size of buffer C */ +}; + +struct isp4fw_buffer_meta_info { + u32 enabled; /* enabled flag */ + enum isp4fw_buffer_status status; /* BufferStatus */ + struct isp4fw_error_code err; /* err code */ + enum isp4fw_buffer_source source; /* BufferSource */ + struct isp4fw_image_prop image_prop; /* image_prop */ + struct isp4fw_buffer buffer; /* buffer */ +}; + +struct isp4fw_meta_info { + u32 poc; /* frame id */ + u32 fc_id; /* frame ctl id */ + u32 time_stamp_lo; /* time_stamp_lo */ + u32 time_stamp_hi; /* time_stamp_hi */ + struct isp4fw_buffer_meta_info preview; /* preview BufferMetaInfo */ +}; + +struct isp4fw_cmd_send_buffer { + enum isp4fw_buffer_type buffer_type; /* buffer Type */ + struct isp4fw_buffer buffer; /* buffer info */ +}; + +struct isp4fw_cmd_set_out_ch_prop { + enum isp4fw_pipe_out_ch ch; /* ISP pipe out channel */ + struct isp4fw_image_prop image_prop; /* image property */ +}; + +struct isp4fw_cmd_enable_out_ch { + enum isp4fw_pipe_out_ch ch; /* ISP pipe out channel */ + u32 is_enable; /* If enable channel or not */ +}; + +struct isp4fw_cmd_set_stream_cfg { + struct isp4fw_isp_stream_cfg stream_cfg; /* stream path config */ +}; + +#endif diff --git a/drivers/media/platform/amd/isp4/isp4_interface.c b/drivers/media/platform/amd/isp4/isp4_interface.c new file mode 100644 index 000000000000..d46d7487a994 --- /dev/null +++ b/drivers/media/platform/amd/isp4/isp4_interface.c @@ -0,0 +1,1058 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2025 Advanced Micro Devices, Inc. + */ + +#include + +#include "amdgpu_object.h" + +#include "isp4_fw_cmd_resp.h" +#include "isp4_hw.h" +#include "isp4_hw_reg.h" +#include "isp4_interface.h" + +#define ISP4IF_FW_RESP_RB_IRQ_EN_MASK \ + (ISP_SYS_INT0_EN__SYS_INT_RINGBUFFER_WPT9_EN_MASK | \ + ISP_SYS_INT0_EN__SYS_INT_RINGBUFFER_WPT10_EN_MASK | \ + ISP_SYS_INT0_EN__SYS_INT_RINGBUFFER_WPT11_EN_MASK | \ + ISP_SYS_INT0_EN__SYS_INT_RINGBUFFER_WPT12_EN_MASK) + +struct isp4if_rb_config { + const char *name; + u32 index; + u32 reg_rptr; + u32 reg_wptr; + u32 reg_base_lo; + u32 reg_base_hi; + u32 reg_size; + u32 val_size; + u64 base_mc_addr; + void *base_sys_addr; +}; + +/* FW cmd ring buffer configuration */ +static struct isp4if_rb_config + isp4if_cmd_rb_config[ISP4IF_STREAM_ID_MAX] = { + { + .name = "CMD_RB_GBL0", + .index = 3, + .reg_rptr = ISP_RB_RPTR4, + .reg_wptr = ISP_RB_WPTR4, + .reg_base_lo = ISP_RB_BASE_LO4, + .reg_base_hi = ISP_RB_BASE_HI4, + .reg_size = ISP_RB_SIZE4, + }, + { + .name = "CMD_RB_STR1", + .index = 0, + .reg_rptr = ISP_RB_RPTR1, + .reg_wptr = ISP_RB_WPTR1, + .reg_base_lo = ISP_RB_BASE_LO1, + .reg_base_hi = ISP_RB_BASE_HI1, + .reg_size = ISP_RB_SIZE1, + }, + { + .name = "CMD_RB_STR2", + .index = 1, + .reg_rptr = ISP_RB_RPTR2, + .reg_wptr = ISP_RB_WPTR2, + .reg_base_lo = ISP_RB_BASE_LO2, + .reg_base_hi = ISP_RB_BASE_HI2, + .reg_size = ISP_RB_SIZE2, + }, + { + .name = "CMD_RB_STR3", + .index = 2, + .reg_rptr = ISP_RB_RPTR3, + .reg_wptr = ISP_RB_WPTR3, + .reg_base_lo = ISP_RB_BASE_LO3, + .reg_base_hi = ISP_RB_BASE_HI3, + .reg_size = ISP_RB_SIZE3, + }, +}; + +/* FW resp ring buffer configuration */ +static struct isp4if_rb_config + isp4if_resp_rb_config[ISP4IF_STREAM_ID_MAX] = { + { + .name = "RES_RB_GBL0", + .index = 3, + .reg_rptr = ISP_RB_RPTR12, + .reg_wptr = ISP_RB_WPTR12, + .reg_base_lo = ISP_RB_BASE_LO12, + .reg_base_hi = ISP_RB_BASE_HI12, + .reg_size = ISP_RB_SIZE12, + }, + { + .name = "RES_RB_STR1", + .index = 0, + .reg_rptr = ISP_RB_RPTR9, + .reg_wptr = ISP_RB_WPTR9, + .reg_base_lo = ISP_RB_BASE_LO9, + .reg_base_hi = ISP_RB_BASE_HI9, + .reg_size = ISP_RB_SIZE9, + }, + { + .name = "RES_RB_STR2", + .index = 1, + .reg_rptr = ISP_RB_RPTR10, + .reg_wptr = ISP_RB_WPTR10, + .reg_base_lo = ISP_RB_BASE_LO10, + .reg_base_hi = ISP_RB_BASE_HI10, + .reg_size = ISP_RB_SIZE10, + }, + { + .name = "RES_RB_STR3", + .index = 2, + .reg_rptr = ISP_RB_RPTR11, + .reg_wptr = ISP_RB_WPTR11, + .reg_base_lo = ISP_RB_BASE_LO11, + .reg_base_hi = ISP_RB_BASE_HI11, + .reg_size = ISP_RB_SIZE11, + }, +}; + +/* FW log ring buffer configuration */ +static struct isp4if_rb_config isp4if_log_rb_config = { + .name = "LOG_RB", + .index = 0, + .reg_rptr = ISP_LOG_RB_RPTR0, + .reg_wptr = ISP_LOG_RB_WPTR0, + .reg_base_lo = ISP_LOG_RB_BASE_LO0, + .reg_base_hi = ISP_LOG_RB_BASE_HI0, + .reg_size = ISP_LOG_RB_SIZE0, +}; + +static struct isp4if_gpu_mem_info *isp4if_gpu_mem_alloc(struct isp4_interface + *ispif, + u32 mem_size) +{ + struct isp4if_gpu_mem_info *mem_info; + struct amdgpu_bo *bo = NULL; + struct amdgpu_device *adev; + struct device *dev; + + void *cpu_ptr; + u64 gpu_addr; + u32 ret; + + dev = ispif->dev; + + if (!mem_size) + return NULL; + + mem_info = kzalloc(sizeof(*mem_info), GFP_KERNEL); + if (!mem_info) + return NULL; + + adev = (struct amdgpu_device *)ispif->adev; + mem_info->mem_size = mem_size; + mem_info->mem_align = ISP4IF_ISP_MC_ADDR_ALIGN; + mem_info->mem_domain = AMDGPU_GEM_DOMAIN_GTT; + + ret = amdgpu_bo_create_kernel(adev, + mem_info->mem_size, + mem_info->mem_align, + mem_info->mem_domain, + &bo, + &gpu_addr, + &cpu_ptr); + + if (!cpu_ptr || ret) { + dev_err(dev, "gpuvm buffer alloc fail, size %u\n", mem_size); + kfree(mem_info); + return NULL; + } + + mem_info->sys_addr = cpu_ptr; + mem_info->gpu_mc_addr = gpu_addr; + mem_info->mem_handle = (void *)bo; + + return mem_info; +} + +static int isp4if_gpu_mem_free(struct isp4_interface *ispif, + struct isp4if_gpu_mem_info *mem_info) +{ + struct device *dev = ispif->dev; + struct amdgpu_bo *bo; + + if (!mem_info) { + dev_err(dev, "invalid mem_info\n"); + return -EINVAL; + } + + bo = (struct amdgpu_bo *)mem_info->mem_handle; + + amdgpu_bo_free_kernel(&bo, &mem_info->gpu_mc_addr, &mem_info->sys_addr); + + kfree(mem_info); + + return 0; +} + +static int isp4if_dealloc_fw_gpumem(struct isp4_interface *ispif) +{ + int i; + + if (ispif->fw_mem_pool) { + isp4if_gpu_mem_free(ispif, ispif->fw_mem_pool); + ispif->fw_mem_pool = NULL; + } + + if (ispif->fw_cmd_resp_buf) { + isp4if_gpu_mem_free(ispif, ispif->fw_cmd_resp_buf); + ispif->fw_cmd_resp_buf = NULL; + } + + if (ispif->fw_log_buf) { + isp4if_gpu_mem_free(ispif, ispif->fw_log_buf); + ispif->fw_log_buf = NULL; + } + + for (i = 0; i < ISP4IF_MAX_STREAM_META_BUF_COUNT; i++) { + if (ispif->metainfo_buf_pool[i]) { + isp4if_gpu_mem_free(ispif, ispif->metainfo_buf_pool[i]); + ispif->metainfo_buf_pool[i] = NULL; + } + } + + return 0; +} + +static int isp4if_alloc_fw_gpumem(struct isp4_interface *ispif) +{ + struct device *dev = ispif->dev; + int i; + + ispif->fw_mem_pool = isp4if_gpu_mem_alloc(ispif, FW_MEMORY_POOL_SIZE); + if (!ispif->fw_mem_pool) + goto error_no_memory; + + ispif->fw_cmd_resp_buf = + isp4if_gpu_mem_alloc(ispif, ISP4IF_RB_PMBMAP_MEM_SIZE); + if (!ispif->fw_cmd_resp_buf) + goto error_no_memory; + + ispif->fw_log_buf = + isp4if_gpu_mem_alloc(ispif, ISP4IF_FW_LOG_RINGBUF_SIZE); + if (!ispif->fw_log_buf) + goto error_no_memory; + + for (i = 0; i < ISP4IF_MAX_STREAM_META_BUF_COUNT; i++) { + ispif->metainfo_buf_pool[i] = + isp4if_gpu_mem_alloc(ispif, + ISP4IF_META_INFO_BUF_SIZE); + if (!ispif->metainfo_buf_pool[i]) + goto error_no_memory; + } + + return 0; + +error_no_memory: + dev_err(dev, "failed to allocate gpu memory"); + return -ENOMEM; +} + +static u32 isp4if_compute_check_sum(u8 *buf, u32 buf_size) +{ + u32 checksum = 0; + u8 *surplus_ptr; + u32 *buffer; + u32 i; + + buffer = (u32 *)buf; + for (i = 0; i < buf_size / sizeof(u32); i++) + checksum += buffer[i]; + + surplus_ptr = (u8 *)&buffer[i]; + /* add surplus data crc checksum */ + for (i = 0; i < buf_size % sizeof(u32); i++) + checksum += surplus_ptr[i]; + + return checksum; +} + +void isp4if_clear_cmdq(struct isp4_interface *ispif) +{ + struct isp4if_cmd_element *buf_node = NULL; + struct isp4if_cmd_element *tmp_node = NULL; + + guard(mutex)(&ispif->cmdq_mutex); + + list_for_each_entry_safe(buf_node, tmp_node, &ispif->cmdq, list) { + list_del(&buf_node->list); + kfree(buf_node); + } +} + +static bool isp4if_is_cmdq_rb_full(struct isp4_interface *ispif, + enum isp4if_stream_id cmd_buf_idx) +{ + struct isp4if_rb_config *rb_config; + u32 rd_ptr, wr_ptr; + u32 new_wr_ptr; + u32 rreg; + u32 wreg; + u32 len; + + rb_config = &isp4if_cmd_rb_config[cmd_buf_idx]; + rreg = rb_config->reg_rptr; + wreg = rb_config->reg_wptr; + len = rb_config->val_size; + + rd_ptr = isp4hw_rreg(ispif->mmio, rreg); + wr_ptr = isp4hw_rreg(ispif->mmio, wreg); + + new_wr_ptr = wr_ptr + sizeof(struct isp4fw_cmd); + + if (wr_ptr >= rd_ptr) { + if (new_wr_ptr < len) { + return false; + } else if (new_wr_ptr == len) { + if (rd_ptr == 0) + return true; + + return false; + } + + new_wr_ptr -= len; + if (new_wr_ptr < rd_ptr) + return false; + + return true; + } + + if (new_wr_ptr < rd_ptr) + return false; + + return true; +} + +static struct isp4if_cmd_element * +isp4if_append_cmd_2_cmdq(struct isp4_interface *ispif, + struct isp4if_cmd_element *cmd_ele) +{ + struct isp4if_cmd_element *copy_command = NULL; + + copy_command = kmalloc(sizeof(*copy_command), GFP_KERNEL); + if (!copy_command) + return NULL; + + memcpy(copy_command, cmd_ele, sizeof(*copy_command)); + + guard(mutex)(&ispif->cmdq_mutex); + + list_add_tail(©_command->list, &ispif->cmdq); + + return copy_command; +} + +struct isp4if_cmd_element * +isp4if_rm_cmd_from_cmdq(struct isp4_interface *ispif, + u32 seq_num, + u32 cmd_id) +{ + struct isp4if_cmd_element *buf_node = NULL; + struct isp4if_cmd_element *tmp_node = NULL; + + guard(mutex)(&ispif->cmdq_mutex); + + list_for_each_entry_safe(buf_node, tmp_node, &ispif->cmdq, list) { + if (buf_node->seq_num == seq_num && + buf_node->cmd_id == cmd_id) { + list_del(&buf_node->list); + return buf_node; + } + } + + return NULL; +} + +static int isp4if_insert_isp_fw_cmd(struct isp4_interface *ispif, + enum isp4if_stream_id stream, + struct isp4fw_cmd *cmd) +{ + struct isp4if_rb_config *rb_config; + struct device *dev = ispif->dev; + u64 mem_addr; + u64 mem_sys; + u32 wr_ptr; + u32 rd_ptr; + u32 rreg; + u32 wreg; + u32 len; + + rb_config = &isp4if_cmd_rb_config[stream]; + rreg = rb_config->reg_rptr; + wreg = rb_config->reg_wptr; + mem_sys = (u64)rb_config->base_sys_addr; + mem_addr = rb_config->base_mc_addr; + len = rb_config->val_size; + + if (isp4if_is_cmdq_rb_full(ispif, stream)) { + dev_err(dev, "fail no cmdslot (%d)\n", stream); + return -EINVAL; + } + + wr_ptr = isp4hw_rreg(ispif->mmio, wreg); + rd_ptr = isp4hw_rreg(ispif->mmio, rreg); + + if (rd_ptr > len) { + dev_err(dev, "fail (%u),rd_ptr %u(should<=%u),wr_ptr %u\n", + stream, rd_ptr, len, wr_ptr); + return -EINVAL; + } + + if (wr_ptr > len) { + dev_err(dev, "fail (%u),wr_ptr %u(should<=%u), rd_ptr %u\n", + stream, wr_ptr, len, rd_ptr); + return -EINVAL; + } + + if (wr_ptr < rd_ptr) { + mem_addr += wr_ptr; + + memcpy((u8 *)(mem_sys + wr_ptr), + (u8 *)cmd, sizeof(struct isp4fw_cmd)); + } else { + if ((len - wr_ptr) >= (sizeof(struct isp4fw_cmd))) { + mem_addr += wr_ptr; + + memcpy((u8 *)(mem_sys + wr_ptr), + (u8 *)cmd, sizeof(struct isp4fw_cmd)); + } else { + u32 size; + u8 *src; + + src = (u8 *)cmd; + size = len - wr_ptr; + + memcpy((u8 *)(mem_sys + wr_ptr), src, size); + + src += size; + size = sizeof(struct isp4fw_cmd) - size; + memcpy((u8 *)(mem_sys), src, size); + } + } + + wr_ptr += sizeof(struct isp4fw_cmd); + if (wr_ptr >= len) + wr_ptr -= len; + + isp4hw_wreg(ispif->mmio, wreg, wr_ptr); + + return 0; +} + +static inline enum isp4if_stream_id isp4if_get_fw_stream(u32 cmd_id) +{ + return ISP4IF_STREAM_ID_1; +} + +static int isp4if_send_fw_cmd(struct isp4_interface *ispif, + u32 cmd_id, + void *package, + u32 package_size, + wait_queue_head_t *wq, + u32 *wq_cond, + u32 *seq) +{ + enum isp4if_stream_id stream = isp4if_get_fw_stream(cmd_id); + struct isp4if_cmd_element command_element = { 0 }; + struct isp4if_gpu_mem_info *gpu_mem = NULL; + struct isp4if_cmd_element *cmd_ele = NULL; + struct isp4if_rb_config *rb_config; + struct device *dev = ispif->dev; + struct isp4fw_cmd cmd = {0}; + u64 package_base = 0; + u32 sleep_count; + u32 seq_num; + u32 rreg; + u32 wreg; + u32 len; + int ret; + + if (package_size > sizeof(cmd.cmd_param)) { + dev_err(dev, "fail pkgsize(%u)>%lu cmd:0x%x,stream %d\n", + package_size, sizeof(cmd.cmd_param), cmd_id, stream); + return -EINVAL; + } + + sleep_count = 0; + + rb_config = &isp4if_resp_rb_config[stream]; + rreg = rb_config->reg_rptr; + wreg = rb_config->reg_wptr; + len = rb_config->val_size; + + guard(mutex)(&ispif->isp4if_mutex); + + while (1) { + if (isp4if_is_cmdq_rb_full(ispif, stream)) { + u32 rd_ptr, wr_ptr; + + if (sleep_count < ISP4IF_MAX_SLEEP_COUNT) { + msleep(ISP4IF_MAX_SLEEP_TIME); + sleep_count++; + continue; + } + rd_ptr = isp4hw_rreg(ispif->mmio, rreg); + wr_ptr = isp4hw_rreg(ispif->mmio, wreg); + dev_err(dev, + "failed to get free cmdq slot, stream (%d)\n", + stream); + return -ETIMEDOUT; + } + break; + } + + cmd.cmd_id = cmd_id; + switch (stream) { + case ISP4IF_STREAM_ID_GLOBAL: + cmd.cmd_stream_id = (u16)STREAM_ID_INVALID; + break; + case ISP4IF_STREAM_ID_1: + cmd.cmd_stream_id = STREAM_ID_1; + break; + default: + dev_err(dev, "fail bad stream id %d\n", stream); + return -EINVAL; + } + + if (package && package_size) + memcpy(cmd.cmd_param, package, package_size); + + seq_num = ispif->host2fw_seq_num++; + cmd.cmd_seq_num = seq_num; + cmd.cmd_check_sum = + isp4if_compute_check_sum((u8 *)&cmd, sizeof(cmd) - 4); + + if (seq) + *seq = seq_num; + command_element.seq_num = seq_num; + command_element.cmd_id = cmd_id; + command_element.mc_addr = package_base; + command_element.wq = wq; + command_element.wq_cond = wq_cond; + command_element.gpu_pkg = gpu_mem; + command_element.stream = stream; + /* only append the fw cmd to queue when its response needs to be + * waited for, currently there are only two such commands, + * disable channel and stop stream which are only sent after close + * camera + */ + if (wq && wq_cond) { + cmd_ele = isp4if_append_cmd_2_cmdq(ispif, &command_element); + if (!cmd_ele) { + dev_err(dev, "fail for isp_append_cmd_2_cmdq\n"); + return -ENOMEM; + } + } + + ret = isp4if_insert_isp_fw_cmd(ispif, stream, &cmd); + if (ret) { + dev_err(dev, "fail for insert_isp_fw_cmd camId (0x%08x)\n", + cmd_id); + if (cmd_ele) { + isp4if_rm_cmd_from_cmdq(ispif, cmd_ele->seq_num, + cmd_ele->cmd_id); + kfree(cmd_ele); + } + } + + return ret; +} + +static int isp4if_send_buffer(struct isp4_interface *ispif, + struct isp4if_img_buf_info *buf_info) +{ + struct isp4fw_cmd_send_buffer cmd; + + memset(&cmd, 0, sizeof(cmd)); + cmd.buffer_type = BUFFER_TYPE_PREVIEW; + cmd.buffer.vmid_space.bit.vmid = 0; + cmd.buffer.vmid_space.bit.space = ADDR_SPACE_TYPE_GPU_VA; + isp4if_split_addr64(buf_info->planes[0].mc_addr, + &cmd.buffer.buf_base_a_lo, + &cmd.buffer.buf_base_a_hi); + cmd.buffer.buf_size_a = buf_info->planes[0].len; + + isp4if_split_addr64(buf_info->planes[1].mc_addr, + &cmd.buffer.buf_base_b_lo, + &cmd.buffer.buf_base_b_hi); + cmd.buffer.buf_size_b = buf_info->planes[1].len; + + isp4if_split_addr64(buf_info->planes[2].mc_addr, + &cmd.buffer.buf_base_c_lo, + &cmd.buffer.buf_base_c_hi); + cmd.buffer.buf_size_c = buf_info->planes[2].len; + + return isp4if_send_fw_cmd(ispif, CMD_ID_SEND_BUFFER, &cmd, + sizeof(cmd), NULL, NULL, NULL); +} + +static void isp4if_init_rb_config(struct isp4_interface *ispif, + struct isp4if_rb_config *rb_config) +{ + u32 lo; + u32 hi; + + isp4if_split_addr64(rb_config->base_mc_addr, &lo, &hi); + + isp4hw_wreg(GET_ISP4IF_REG_BASE(ispif), + rb_config->reg_rptr, 0x0); + isp4hw_wreg(GET_ISP4IF_REG_BASE(ispif), + rb_config->reg_wptr, 0x0); + isp4hw_wreg(GET_ISP4IF_REG_BASE(ispif), + rb_config->reg_base_lo, lo); + isp4hw_wreg(GET_ISP4IF_REG_BASE(ispif), + rb_config->reg_base_hi, hi); + isp4hw_wreg(GET_ISP4IF_REG_BASE(ispif), + rb_config->reg_size, rb_config->val_size); +} + +static int isp4if_fw_init(struct isp4_interface *ispif) +{ + struct isp4if_rb_config *rb_config; + u32 offset; + int i; + + /* initialize CMD_RB streams */ + for (i = 0; i < ISP4IF_STREAM_ID_MAX; i++) { + rb_config = (isp4if_cmd_rb_config + i); + offset = ispif->aligned_rb_chunk_size * + (rb_config->index + ispif->cmd_rb_base_index); + + rb_config->val_size = ISP4IF_FW_CMD_BUF_SIZE; + rb_config->base_sys_addr = + (u8 *)ispif->fw_cmd_resp_buf->sys_addr + offset; + rb_config->base_mc_addr = + ispif->fw_cmd_resp_buf->gpu_mc_addr + offset; + + isp4if_init_rb_config(ispif, rb_config); + } + + /* initialize RESP_RB streams */ + for (i = 0; i < ISP4IF_STREAM_ID_MAX; i++) { + rb_config = (isp4if_resp_rb_config + i); + offset = ispif->aligned_rb_chunk_size * + (rb_config->index + ispif->resp_rb_base_index); + + rb_config->val_size = ISP4IF_FW_CMD_BUF_SIZE; + rb_config->base_sys_addr = + (u8 *)ispif->fw_cmd_resp_buf->sys_addr + offset; + rb_config->base_mc_addr = + ispif->fw_cmd_resp_buf->gpu_mc_addr + offset; + + isp4if_init_rb_config(ispif, rb_config); + } + + /* initialize LOG_RB stream */ + rb_config = &isp4if_log_rb_config; + rb_config->val_size = ISP4IF_FW_LOG_RINGBUF_SIZE; + rb_config->base_mc_addr = ispif->fw_log_buf->gpu_mc_addr; + rb_config->base_sys_addr = ispif->fw_log_buf->sys_addr; + + isp4if_init_rb_config(ispif, rb_config); + + return 0; +} + +static int isp4if_wait_fw_ready(struct isp4_interface *ispif, + u32 isp_status_addr) +{ + struct device *dev = ispif->dev; + u32 fw_ready_timeout; + u32 timeout_ms = 100; + u32 interval_ms = 1; + u32 timeout = 0; + u32 reg_val; + + fw_ready_timeout = timeout_ms / interval_ms; + + /* wait for FW initialize done! */ + while (timeout < fw_ready_timeout) { + reg_val = isp4hw_rreg(GET_ISP4IF_REG_BASE(ispif), + isp_status_addr); + if (reg_val & ISP_STATUS__CCPU_REPORT_MASK) + return 0; + + msleep(interval_ms); + timeout++; + } + + dev_err(dev, "ISP CCPU FW boot failed\n"); + + return -ETIME; +} + +static void isp4if_enable_ccpu(struct isp4_interface *ispif) +{ + u32 reg_val; + + reg_val = isp4hw_rreg(GET_ISP4IF_REG_BASE(ispif), ISP_SOFT_RESET); + reg_val &= (~ISP_SOFT_RESET__CCPU_SOFT_RESET_MASK); + isp4hw_wreg(GET_ISP4IF_REG_BASE(ispif), ISP_SOFT_RESET, reg_val); + + usleep_range(100, 150); + + reg_val = isp4hw_rreg(GET_ISP4IF_REG_BASE(ispif), ISP_CCPU_CNTL); + reg_val &= (~ISP_CCPU_CNTL__CCPU_HOST_SOFT_RST_MASK); + isp4hw_wreg(GET_ISP4IF_REG_BASE(ispif), ISP_CCPU_CNTL, reg_val); +} + +static void isp4if_disable_ccpu(struct isp4_interface *ispif) +{ + u32 reg_val; + + reg_val = isp4hw_rreg(GET_ISP4IF_REG_BASE(ispif), ISP_CCPU_CNTL); + reg_val |= ISP_CCPU_CNTL__CCPU_HOST_SOFT_RST_MASK; + isp4hw_wreg(GET_ISP4IF_REG_BASE(ispif), ISP_CCPU_CNTL, reg_val); + + usleep_range(100, 150); + + reg_val = isp4hw_rreg(GET_ISP4IF_REG_BASE(ispif), ISP_SOFT_RESET); + reg_val |= ISP_SOFT_RESET__CCPU_SOFT_RESET_MASK; + isp4hw_wreg(GET_ISP4IF_REG_BASE(ispif), ISP_SOFT_RESET, reg_val); +} + +static int isp4if_fw_boot(struct isp4_interface *ispif) +{ + struct device *dev = ispif->dev; + + if (ispif->status != ISP4IF_STATUS_PWR_ON) { + dev_err(dev, "invalid isp power status %d\n", ispif->status); + return -EINVAL; + } + + isp4if_disable_ccpu(ispif); + + isp4if_fw_init(ispif); + + /* clear ccpu status */ + isp4hw_wreg(GET_ISP4IF_REG_BASE(ispif), ISP_STATUS, 0x0); + + isp4if_enable_ccpu(ispif); + + if (isp4if_wait_fw_ready(ispif, ISP_STATUS)) { + isp4if_disable_ccpu(ispif); + return -EINVAL; + } + + /* enable interrupts */ + isp4hw_wreg(GET_ISP4IF_REG_BASE(ispif), ISP_SYS_INT0_EN, + ISP4IF_FW_RESP_RB_IRQ_EN_MASK); + + ispif->status = ISP4IF_STATUS_FW_RUNNING; + + dev_dbg(dev, "ISP CCPU FW boot success\n"); + + return 0; +} + +int isp4if_f2h_resp(struct isp4_interface *ispif, + enum isp4if_stream_id stream, + void *resp) +{ + struct isp4fw_resp *response = resp; + struct isp4if_rb_config *rb_config; + struct device *dev = ispif->dev; + u32 rd_ptr_dbg; + u32 wr_ptr_dbg; + void *mem_sys; + u64 mem_addr; + u32 checksum; + u32 rd_ptr; + u32 wr_ptr; + u32 rreg; + u32 wreg; + u32 len; + + rb_config = &isp4if_resp_rb_config[stream]; + rreg = rb_config->reg_rptr; + wreg = rb_config->reg_wptr; + mem_sys = rb_config->base_sys_addr; + mem_addr = rb_config->base_mc_addr; + len = rb_config->val_size; + + rd_ptr = isp4hw_rreg(GET_ISP4IF_REG_BASE(ispif), rreg); + wr_ptr = isp4hw_rreg(GET_ISP4IF_REG_BASE(ispif), wreg); + rd_ptr_dbg = rd_ptr; + wr_ptr_dbg = wr_ptr; + + if (rd_ptr > len) { + dev_err(dev, "fail (%u),rd_ptr %u(should<=%u),wr_ptr %u\n", + stream, rd_ptr, len, wr_ptr); + return -EINVAL; + } + + if (wr_ptr > len) { + dev_err(dev, "fail (%u),wr_ptr %u(should<=%u), rd_ptr %u\n", + stream, wr_ptr, len, rd_ptr); + return -EINVAL; + } + + if (rd_ptr < wr_ptr) { + if ((wr_ptr - rd_ptr) >= (sizeof(struct isp4fw_resp))) { + memcpy((u8 *)response, (u8 *)mem_sys + rd_ptr, + sizeof(struct isp4fw_resp)); + + rd_ptr += sizeof(struct isp4fw_resp); + if (rd_ptr < len) { + isp4hw_wreg(GET_ISP4IF_REG_BASE(ispif), + rreg, rd_ptr); + } else { + dev_err(dev, "(%u),rd %u(should<=%u),wr %u\n", + stream, rd_ptr, len, wr_ptr); + return -EINVAL; + } + + } else { + dev_err(dev, "sth wrong with wptr and rptr\n"); + return -EINVAL; + } + } else if (rd_ptr > wr_ptr) { + u64 src_addr; + u32 size; + u8 *dst; + + dst = (u8 *)response; + + src_addr = mem_addr + rd_ptr; + size = len - rd_ptr; + if (size > sizeof(struct isp4fw_resp)) { + mem_addr += rd_ptr; + memcpy((u8 *)response, + (u8 *)(mem_sys) + rd_ptr, + sizeof(struct isp4fw_resp)); + rd_ptr += sizeof(struct isp4fw_resp); + if (rd_ptr < len) { + isp4hw_wreg(GET_ISP4IF_REG_BASE(ispif), + rreg, rd_ptr); + } else { + dev_err(dev, "(%u),rd %u(should<=%u),wr %u\n", + stream, rd_ptr, len, wr_ptr); + return -EINVAL; + } + + } else { + if ((size + wr_ptr) < (sizeof(struct isp4fw_resp))) { + dev_err(dev, "sth wrong with wptr and rptr1\n"); + return -EINVAL; + } + + memcpy(dst, (u8 *)(mem_sys) + rd_ptr, size); + + dst += size; + src_addr = mem_addr; + size = sizeof(struct isp4fw_resp) - size; + if (size) + memcpy(dst, (u8 *)(mem_sys), size); + rd_ptr = size; + if (rd_ptr < len) { + isp4hw_wreg(GET_ISP4IF_REG_BASE(ispif), + rreg, rd_ptr); + } else { + dev_err(dev, "(%u),rd %u(should<=%u),wr %u\n", + stream, rd_ptr, len, wr_ptr); + return -EINVAL; + } + } + } else { + return -ETIME; + } + + checksum = isp4if_compute_check_sum((u8 *)response, + (sizeof(struct isp4fw_resp) - 4)); + + if (checksum != response->resp_check_sum) { + dev_err(dev, "resp checksum 0x%x,should 0x%x,rptr %u,wptr %u\n", + checksum, response->resp_check_sum, + rd_ptr_dbg, wr_ptr_dbg); + + dev_err(dev, "(%u), seqNo %u, resp_id (0x%x)\n", + stream, + response->resp_seq_num, + response->resp_id); + + return -EINVAL; + } + + return 0; +} + +int isp4if_send_command(struct isp4_interface *ispif, + u32 cmd_id, + void *package, + u32 package_size) +{ + return isp4if_send_fw_cmd(ispif, + cmd_id, package, + package_size, NULL, NULL, NULL); +} + +int isp4if_send_command_sync(struct isp4_interface *ispif, + u32 cmd_id, + void *package, + u32 package_size, + u32 timeout) +{ + struct device *dev = ispif->dev; + DECLARE_WAIT_QUEUE_HEAD(cmd_wq); + u32 wq_cond = 0; + int ret; + u32 seq; + + ret = isp4if_send_fw_cmd(ispif, + cmd_id, package, + package_size, &cmd_wq, &wq_cond, &seq); + + if (ret) { + dev_err(dev, "send fw cmd fail %d\n", ret); + return ret; + } + + ret = wait_event_timeout(cmd_wq, wq_cond != 0, + msecs_to_jiffies(timeout)); + + /* timeout occurred */ + if (ret == 0) { + struct isp4if_cmd_element *ele; + + ele = isp4if_rm_cmd_from_cmdq(ispif, seq, cmd_id); + kfree(ele); + return -ETIMEDOUT; + } + + return 0; +} + +void isp4if_clear_bufq(struct isp4_interface *ispif) +{ + struct isp4if_img_buf_node *buf_node = NULL; + struct isp4if_img_buf_node *tmp_node = NULL; + + guard(mutex)(&ispif->bufq_mutex); + + list_for_each_entry_safe(buf_node, tmp_node, &ispif->bufq, + node) { + list_del(&buf_node->node); + kfree(buf_node); + } +} + +void isp4if_dealloc_buffer_node(struct isp4if_img_buf_node *buf_node) +{ + kfree(buf_node); +} + +struct isp4if_img_buf_node * +isp4if_alloc_buffer_node(struct isp4if_img_buf_info *buf_info) +{ + struct isp4if_img_buf_node *node = NULL; + + node = kmalloc(sizeof(*node), GFP_KERNEL); + if (node) + node->buf_info = *buf_info; + + return node; +}; + +struct isp4if_img_buf_node * +isp4if_dequeue_buffer(struct isp4_interface *ispif) +{ + struct isp4if_img_buf_node *buf_node = NULL; + + guard(mutex)(&ispif->bufq_mutex); + + buf_node = list_first_entry_or_null(&ispif->bufq, + typeof(*buf_node), + node); + if (buf_node) + list_del(&buf_node->node); + + return buf_node; +} + +int isp4if_queue_buffer(struct isp4_interface *ispif, + struct isp4if_img_buf_node *buf_node) +{ + int ret; + + ret = isp4if_send_buffer(ispif, &buf_node->buf_info); + if (ret) + return ret; + + guard(mutex)(&ispif->bufq_mutex); + + list_add_tail(&buf_node->node, &ispif->bufq); + + return 0; +} + +int isp4if_stop(struct isp4_interface *ispif) +{ + isp4if_disable_ccpu(ispif); + + isp4if_dealloc_fw_gpumem(ispif); + + return 0; +} + +int isp4if_start(struct isp4_interface *ispif) +{ + int ret; + + ret = isp4if_alloc_fw_gpumem(ispif); + if (ret) + goto failed_gpumem_alloc; + + ret = isp4if_fw_boot(ispif); + if (ret) + goto failed_fw_boot; + + return 0; + +failed_gpumem_alloc: + return -ENOMEM; + +failed_fw_boot: + isp4if_dealloc_fw_gpumem(ispif); + return ret; +} + +int isp4if_deinit(struct isp4_interface *ispif) +{ + isp4if_clear_cmdq(ispif); + + isp4if_clear_bufq(ispif); + + mutex_destroy(&ispif->cmdq_mutex); + mutex_destroy(&ispif->bufq_mutex); + mutex_destroy(&ispif->isp4if_mutex); + + return 0; +} + +int isp4if_init(struct isp4_interface *ispif, struct device *dev, + void *amdgpu_dev, void __iomem *isp_mmip) +{ + ispif->dev = dev; + ispif->adev = amdgpu_dev; + ispif->mmio = isp_mmip; + + ispif->cmd_rb_base_index = 0; + ispif->resp_rb_base_index = ISP4IF_RESP_CHAN_TO_RB_OFFSET - 1; + ispif->aligned_rb_chunk_size = ISP4IF_RB_PMBMAP_MEM_CHUNK & 0xffffffc0; + + mutex_init(&ispif->cmdq_mutex); /* used for cmdq access */ + mutex_init(&ispif->bufq_mutex); /* used for bufq access */ + mutex_init(&ispif->isp4if_mutex); /* used for commands sent to ispfw */ + + INIT_LIST_HEAD(&ispif->cmdq); + INIT_LIST_HEAD(&ispif->bufq); + + return 0; +} diff --git a/drivers/media/platform/amd/isp4/isp4_interface.h b/drivers/media/platform/amd/isp4/isp4_interface.h new file mode 100644 index 000000000000..b2ca147b78b6 --- /dev/null +++ b/drivers/media/platform/amd/isp4/isp4_interface.h @@ -0,0 +1,164 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2025 Advanced Micro Devices, Inc. + */ + +#ifndef _ISP4_INTERFACE_ +#define _ISP4_INTERFACE_ + +#define ISP4IF_RB_MAX (25) +#define ISP4IF_RESP_CHAN_TO_RB_OFFSET (9) +#define ISP4IF_RB_PMBMAP_MEM_SIZE (16 * 1024 * 1024 - 1) +#define ISP4IF_RB_PMBMAP_MEM_CHUNK (ISP4IF_RB_PMBMAP_MEM_SIZE \ + / (ISP4IF_RB_MAX - 1)) +#define ISP4IF_ISP_MC_ADDR_ALIGN (1024 * 32) +#define ISP4IF_HOST2FW_COMMAND_SIZE (sizeof(struct isp4fw_cmd)) +#define ISP4IF_FW_CMD_BUF_COUNT 4 +#define ISP4IF_FW_RESP_BUF_COUNT 4 +#define ISP4IF_MAX_NUM_HOST2FW_COMMAND (40) +#define ISP4IF_FW_CMD_BUF_SIZE (ISP4IF_MAX_NUM_HOST2FW_COMMAND \ + * ISP4IF_HOST2FW_COMMAND_SIZE) +#define ISP4IF_MAX_SLEEP_COUNT (10) +#define ISP4IF_MAX_SLEEP_TIME (33) + +#define ISP4IF_META_INFO_BUF_SIZE ALIGN(sizeof(struct isp4fw_meta_info), 0x8000) +#define ISP4IF_MAX_STREAM_META_BUF_COUNT 6 + +#define ISP4IF_FW_LOG_RINGBUF_SIZE (2 * 1024 * 1024) + +#define ISP4IF_MAX_CMD_RESPONSE_BUF_SIZE (4 * 1024) + +#define GET_ISP4IF_REG_BASE(ispif) (((ispif))->mmio) + +enum isp4if_stream_id { + ISP4IF_STREAM_ID_GLOBAL = 0, + ISP4IF_STREAM_ID_1 = 1, + ISP4IF_STREAM_ID_MAX = 4 +}; + +enum isp4if_status { + ISP4IF_STATUS_PWR_OFF, + ISP4IF_STATUS_PWR_ON, + ISP4IF_STATUS_FW_RUNNING, + ISP4IF_FSM_STATUS_MAX +}; + +struct isp4if_gpu_mem_info { + u32 mem_domain; + u64 mem_size; + u32 mem_align; + u64 gpu_mc_addr; + void *sys_addr; + void *mem_handle; +}; + +struct isp4if_img_buf_info { + struct { + void *sys_addr; + u64 mc_addr; + u32 len; + } planes[3]; +}; + +struct isp4if_img_buf_node { + struct list_head node; + struct isp4if_img_buf_info buf_info; +}; + +struct isp4if_cmd_element { + struct list_head list; + u32 seq_num; + u32 cmd_id; + enum isp4if_stream_id stream; + u64 mc_addr; + wait_queue_head_t *wq; + u32 *wq_cond; + struct isp4if_gpu_mem_info *gpu_pkg; +}; + +struct isp4_interface { + struct amdgpu_device *adev; + + struct device *dev; + void __iomem *mmio; + + struct mutex cmdq_mutex; /* used for cmdq access */ + struct mutex bufq_mutex; /* used for bufq access */ + struct mutex isp4if_mutex; /* used to send fw cmd and read fw log */ + + struct list_head cmdq; /* commands sent to fw */ + struct list_head bufq; /* buffers sent to fw */ + + enum isp4if_status status; + u32 host2fw_seq_num; + + /* FW ring buffer configs */ + u32 cmd_rb_base_index; + u32 resp_rb_base_index; + u32 aligned_rb_chunk_size; + + /* ISP fw buffers */ + struct isp4if_gpu_mem_info *fw_log_buf; + struct isp4if_gpu_mem_info *fw_cmd_resp_buf; + struct isp4if_gpu_mem_info *fw_mem_pool; + struct isp4if_gpu_mem_info * + metainfo_buf_pool[ISP4IF_MAX_STREAM_META_BUF_COUNT]; +}; + +static inline void isp4if_split_addr64(u64 addr, u32 *lo, u32 *hi) +{ + if (lo) + *lo = (u32)(addr & 0xffffffff); + if (hi) + *hi = (u32)(addr >> 32); +} + +static inline u64 isp4if_join_addr64(u32 lo, u32 hi) +{ + return (((u64)hi) << 32) | (u64)lo; +} + +int isp4if_f2h_resp(struct isp4_interface *ispif, + enum isp4if_stream_id stream, + void *response); + +int isp4if_send_command(struct isp4_interface *ispif, + u32 cmd_id, + void *package, + u32 package_size); + +int isp4if_send_command_sync(struct isp4_interface *ispif, + u32 cmd_id, + void *package, + u32 package_size, + u32 timeout); + +struct isp4if_cmd_element * +isp4if_rm_cmd_from_cmdq(struct isp4_interface *ispif, + u32 seq_num, + u32 cmd_id); + +void isp4if_clear_cmdq(struct isp4_interface *ispif); + +void isp4if_clear_bufq(struct isp4_interface *ispif); + +void isp4if_dealloc_buffer_node(struct isp4if_img_buf_node *buf_node); + +struct isp4if_img_buf_node * +isp4if_alloc_buffer_node(struct isp4if_img_buf_info *buf_info); + +struct isp4if_img_buf_node *isp4if_dequeue_buffer(struct isp4_interface *ispif); + +int isp4if_queue_buffer(struct isp4_interface *ispif, + struct isp4if_img_buf_node *buf_node); + +int isp4if_stop(struct isp4_interface *ispif); + +int isp4if_start(struct isp4_interface *ispif); + +int isp4if_deinit(struct isp4_interface *ispif); + +int isp4if_init(struct isp4_interface *ispif, struct device *dev, + void *amdgpu_dev, void __iomem *isp_mmip); + +#endif From patchwork Sun Jun 8 14:49:12 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Du, Bin" X-Patchwork-Id: 895009 Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2081.outbound.protection.outlook.com [40.107.236.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 738FA2522B4; Sun, 8 Jun 2025 14:50:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.236.81 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749394209; cv=fail; b=j3BGiQdHPaSKa2aN4UXDIG7cD0OhSEWHnQ7MUFqtcecVB45R3UlQsR+J9rMjX19dg8YOSqi4kp57iKBi5bGIZa+/+2m8j+8VC3no4DjKZ7mQIHS211gYSPw/QTq27y+ou89YGZ9qoMi28XtbWEibISfJgaLf4LC6oyGGuk3892g= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749394209; c=relaxed/simple; bh=RpRIbFB/RHVa2ppe9OkwpqFUbEHrxYTfQkhOjVq4n2s=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=nsR9gfS01WelnkvSq7FcZwqiirUrbL/oUDl/i4ojJbYsWZso6sk4RkDf6cWMmzrQ6YWNbNy9TWA8fjT7UOojq2ig2qLBC4ICuur1VuEbq6Fr723WCSn3IKymG5ItHQ/TCBypq+WILH6AHZyUPa3bvwYngy+pTuqw5S0V6A160Zc= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com; spf=fail smtp.mailfrom=amd.com; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b=bgrMzoZq; arc=fail smtp.client-ip=40.107.236.81 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=amd.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="bgrMzoZq" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=jSbCz8X441G9wX5vi2NB0MGvlSa+zFMQ1KO3RuGwYpz5Q6degXYTZsz8odUkldqk9jZqv9I3qi19c9kH5QeQPnQIQtI6pcbzllORfyX/R9lTZX3PQOJu11RpMMxMeVKYOIp0uBRgffSsFqbTYF7rS5wtJh/ph4nzNCBbz6bkDp8CydluATHtW4uCLyVarmSh7nauWZLBJbI0uyZeGZWUicspNopBj1i8NkMacjgbPNZucWXxdOJjxP69yz423nCRJzLTrT4JLHfnWn1yMceH4ZYNBfBwott8MwFE56EJlvz5V8RDVGUJrD+RwO5Jhoy956IkDbqV5MJUt1UhjTvaxg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=iT6LMExGnUJIKR4qqh6ZYV7xzCDVPlFbUOn60pd2bGg=; b=lcp/rIhVdy4ime/8qw86oSm5G0aeUEv62zaPqlymzMd9Wrx4wKbdCRNgVMYPzJExCRgCR5FFTGWQcsOvbI352K2lwi5uzhFwUDcVeIan0xr44Y6w5bRyVDTkBQwpOIxmGu0zS40Ej136QeaCWknpXKPiFCQ58LuJW6D8x3ZoQOdnSA1qEkZKc6/kMvY3u1zYhDcbEpyG0iOahJQldM35tCTO2IJNVdBUqgE1l6MHKnr3M9ZevKyd9VIQN+md7m1jd2KnmVASmeenhmrw8ExeRLcC8/TyW5wvHtBm1KaD383b1v0qbMW0fjD7nLHQ13FVPR3IgkYPNc/1KKoPglGcoA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=iT6LMExGnUJIKR4qqh6ZYV7xzCDVPlFbUOn60pd2bGg=; b=bgrMzoZqkHW0Sdb4LcoGHhpQf7SaqTYgqupttv1X4uE8jqFfOyi7K1CV6ShTRx+3XWE4K7vnsyWbgPnjmQe8mrWYp4klv2dpQnGBPrOdSOaKBZx9pu+O1ll0mbEIkSYpyokjobiF7ifioQn9RR63sjZe04owyRcVsXs+3it9cHM= Received: from SJ0PR13CA0209.namprd13.prod.outlook.com (2603:10b6:a03:2c3::34) by SA1PR12MB8841.namprd12.prod.outlook.com (2603:10b6:806:376::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8792.34; Sun, 8 Jun 2025 14:50:00 +0000 Received: from SJ5PEPF000001D5.namprd05.prod.outlook.com (2603:10b6:a03:2c3:cafe::f3) by SJ0PR13CA0209.outlook.office365.com (2603:10b6:a03:2c3::34) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8835.10 via Frontend Transport; Sun, 8 Jun 2025 14:49:59 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SJ5PEPF000001D5.mail.protection.outlook.com (10.167.242.57) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8835.15 via Frontend Transport; Sun, 8 Jun 2025 14:49:59 +0000 Received: from 555e2b870847.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Sun, 8 Jun 2025 09:49:53 -0500 From: Bin Du To: , , , , , , , CC: , , , , , , , , "Bin Du" Subject: [PATCH v1 5/9] media: platform: amd: isp4 subdev and firmware loading handling added Date: Sun, 8 Jun 2025 22:49:12 +0800 Message-ID: <20250608144916.222835-6-Bin.Du@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250608144916.222835-1-Bin.Du@amd.com> References: <20250608144916.222835-1-Bin.Du@amd.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001D5:EE_|SA1PR12MB8841:EE_ X-MS-Office365-Filtering-Correlation-Id: bf637e47-1c44-4cc4-db60-08dda69bbe13 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|36860700013|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: J2UE+p3mPy5KOpOLCI9D7NFW1JRP4smZyREVuIPXOwPHY7KglR0DhaXC3G7xzxzg9n3Hk9mh6mxhWbQwz7gtHgaKtDdcCTl36HiL9kF3rqxiBm4PsJve0gOuZZFdaBd9Zcwl3xCYzzV+0+qie5SZNst/P7AdD9nQuozFRA5DhidAohTxN9MEvLViZ/ipAVWBczNWcdW9bRJeeyM/+BVZzcYLfp4WrV7dC9qM8Qn5sKvZoh5R/ThVFfyuiIyPSSDe0KZSimcahr95jx/yQyPSlD/qbNOChgi5LzPrLseMm3zc+4GmFgy1ENwIpqOBAbRlExRgWiUjVumwlXFEFUjOotnMPyg4wKwZg34NoT/nN5CzbM3UT5T4eGNUi4pync8PcZDvLhysbkRZkVnurCv5IDIISk9spqkKQ92GTJkcNnLcQvv0Oyr5SWYatJT6Dco5Gf7XwA7SvpzjeymbRGXDw0hs/TroULO4r9q3jwz2cSYcSFOIadRJ2AaPLbxuWcte5XGj+SWUk5fn44XsBVWLcRUPZe+w1+Rt/MCQkkiFOmcZimvJg2znqQQKeM8Fizbs94Xr1Usl1mwvGGUsQPjlgmsB7GDAZBC4dlV1F2jnanoiuuoMXlsP0IhVik4pfTUJO4IdQu56A80HwjFcR1VCKxjpF95qmPfXNWz1Od4rkwc81786C2M+jm4vY8iQNUMcbEan0JS2Cnz4c3q7XpOOxKPaStrE2mota4iQBtaTM+j6TPmLIUtxjsTSC796xBpt0GzzWkPksbMstEUBZbJkEngDos1rNerKdtm58NrEwbgYEtiomTqdsWNp7zl/Vgz3kRQN7AKh1b4+w7jMhg+Ve8A4aKo2owoZoY+l/1+nZhw+uvrvfLvCOlJ8VD3keOwMbWBr2N86Djzmt+t5x45y41tYkrfhhYjQNMK2IECk0iWvZzAZhMTSFvS0xrr+YotLHYSrjc6Q0c9LLMH/Wcp2BhsjsCejcdToEzmyQ4dGQg6tR8dDV8UlqVli43DMTMjpdR7BAtARF8NnQ3nIB1X6JsutEp4F+N8Ifjxu4zB0nizikZLMrNJQrbsT/HwqN0nbGzAqNMCi+ZjENzvXygZedpEWGZUYToiL6mxXcncOgEdybLlM4q5hKIv8DyYin7B09YHri8ls5h3yRXUMSuA4hyF5YmSrgSbQ4WnDbsCbx4bxVGiMOOJ77VY8o6xes7eajDh0pIjNA7EomdQe7MneVRgvCxt0uEzG2J7L3wz1NAQCzQvvb61XtZBRENs12kWSJyTaS9m5aQ+yksdF9yGD08StEdmzajNknAIS5aZCV8n4zk5aVjGVbk3TZp/ix2BlkFm76noQsSEB7tvz2wy63MbPijF+snWRi1+SR0nTSdMGrdW/Qv9VwgHpS2r8ocRHD8RIGw/oALHrBU1Y+3Qiae/M66arADMl1lmWC3yXO0XB0uDLG+qDrJ5Mt59ixkzCLkzBXWmafnPVI+TRlgy/hmfS7tinRbuBXvfPKwnE1R9+KEmIHUKRK5pKJ63iFrm8 X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(376014)(36860700013)(1800799024)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jun 2025 14:49:59.4331 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bf637e47-1c44-4cc4-db60-08dda69bbe13 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001D5.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB8841 Isp4 sub-device is implementing v4l2 sub-device interface. It has one capture video node, and supports only preview stream. It manages firmware states, stream configuration and mipi phy configuration. This change also adds interrupt handling and notification for isp firmware to isp-subdevice. Signed-off-by: Bin Du Signed-off-by: Svetoslav Stoilov Change-Id: I87d5877226c37a3c4271552ee3bb7316e13de0be --- drivers/media/platform/amd/isp4/Makefile | 3 +- drivers/media/platform/amd/isp4/isp4.c | 240 +++- drivers/media/platform/amd/isp4/isp4.h | 4 +- drivers/media/platform/amd/isp4/isp4_subdev.c | 1213 +++++++++++++++++ drivers/media/platform/amd/isp4/isp4_subdev.h | 145 ++ 5 files changed, 1595 insertions(+), 10 deletions(-) create mode 100644 drivers/media/platform/amd/isp4/isp4_subdev.c create mode 100644 drivers/media/platform/amd/isp4/isp4_subdev.h diff --git a/drivers/media/platform/amd/isp4/Makefile b/drivers/media/platform/amd/isp4/Makefile index c76b8a327be6..d2f1523ad07a 100644 --- a/drivers/media/platform/amd/isp4/Makefile +++ b/drivers/media/platform/amd/isp4/Makefile @@ -3,9 +3,10 @@ # Copyright (C) 2025 Advanced Micro Devices, Inc. obj-$(CONFIG_AMD_ISP4) += amd_capture.o -amd_capture-objs := isp4.o \ +amd_capture-objs := isp4_subdev.o \ isp4_phy.o \ isp4_interface.o \ + isp4.o \ isp4_hw.o \ ccflags-y += -I$(srctree)/drivers/media/platform/amd/isp4 diff --git a/drivers/media/platform/amd/isp4/isp4.c b/drivers/media/platform/amd/isp4/isp4.c index d0be90c5ec3b..2dc7ea3b02e8 100644 --- a/drivers/media/platform/amd/isp4/isp4.c +++ b/drivers/media/platform/amd/isp4/isp4.c @@ -7,11 +7,17 @@ #include #include -#include "isp4.h" +#include "amdgpu_object.h" -#define VIDEO_BUF_NUM 5 +#include "isp4.h" +#include "isp4_hw.h" #define ISP4_DRV_NAME "amd_isp_capture" +#define ISP4_FW_RESP_RB_IRQ_STATUS_MASK \ + (ISP_SYS_INT0_STATUS__SYS_INT_RINGBUFFER_WPT9_INT_MASK | \ + ISP_SYS_INT0_STATUS__SYS_INT_RINGBUFFER_WPT10_INT_MASK | \ + ISP_SYS_INT0_STATUS__SYS_INT_RINGBUFFER_WPT11_INT_MASK | \ + ISP_SYS_INT0_STATUS__SYS_INT_RINGBUFFER_WPT12_INT_MASK) /* interrupt num */ static const u32 isp4_ringbuf_interrupt_num[] = { @@ -24,23 +30,207 @@ static const u32 isp4_ringbuf_interrupt_num[] = { #define to_isp4_device(dev) \ ((struct isp4_device *)container_of(dev, struct isp4_device, v4l2_dev)) +static int isp4_create_links(struct isp4_device *isp4_dev, + struct v4l2_subdev *sensor_sdev) +{ + struct v4l2_subdev *isp4_sdev = &isp4_dev->isp_sdev.sdev; + struct device *dev = &isp4_dev->pdev->dev; + int ret; + + ret = media_create_pad_link(&sensor_sdev->entity, + 0, &isp4_sdev->entity, 0, + MEDIA_LNK_FL_ENABLED | + MEDIA_LNK_FL_IMMUTABLE); + if (ret) + dev_err(dev, "create sensor to isp link fail:%d\n", ret); + + return ret; +} + +static int isp4_register_subdev_and_create_links(struct isp4_device *isp_dev, + struct v4l2_subdev *sdev) +{ + struct device *dev = &isp_dev->pdev->dev; + int ret; + + ret = isp4_create_links(isp_dev, sdev); + if (ret) + dev_err(dev, "fail create isp link:%d\n", ret); + + ret = v4l2_device_register_subdev_nodes(&isp_dev->v4l2_dev); + if (ret != 0) { + dev_warn(dev, "register subdev as nodes fail:%d\n", ret); + ret = 0; + } + + return ret; +} + +static int isp4_camera_sensor_bound(struct v4l2_async_notifier *notifier, + struct v4l2_subdev *sensor_sdev, + struct v4l2_async_connection *asd) +{ + struct isp4_device *isp_dev = to_isp4_device(notifier->v4l2_dev); + struct device *dev = &isp_dev->pdev->dev; + int ret; + + ret = isp4_register_subdev_and_create_links(isp_dev, sensor_sdev); + if (ret) + dev_err(dev, "register sensor subdev fail:%d\n", + ret); + else + dev_dbg(dev, "register sensor subdev suc\n"); + return ret; +} + +static void isp4_camera_sensor_unbind(struct v4l2_async_notifier *notifier, + struct v4l2_subdev *sensor_sdev, + struct v4l2_async_connection *asd) +{ +} + +static const struct v4l2_async_notifier_operations isp4_camera_sensor_ops = { + .bound = isp4_camera_sensor_bound, + .unbind = isp4_camera_sensor_unbind, +}; + +static void isp4_wake_up_resp_thread(struct isp4_subdev *isp, u32 index) +{ + if (isp && index < ISP4SD_MAX_FW_RESP_STREAM_NUM) { + struct isp4sd_thread_handler *thread_ctx = + &isp->fw_resp_thread[index]; + + thread_ctx->wq_cond = 1; + wake_up_interruptible(&thread_ctx->waitq); + } +} + +static void isp4_resp_interrupt_notify(struct isp4_subdev *isp, u32 intr_status) +{ + bool wake = (isp->ispif.status == ISP4IF_STATUS_FW_RUNNING); + + u32 intr_ack = 0; + + /* global response */ + if (intr_status & + ISP_SYS_INT0_STATUS__SYS_INT_RINGBUFFER_WPT12_INT_MASK) { + if (wake) + isp4_wake_up_resp_thread(isp, 0); + + intr_ack |= ISP_SYS_INT0_ACK__SYS_INT_RINGBUFFER_WPT12_ACK_MASK; + } + + /* stream 1 response */ + if (intr_status & + ISP_SYS_INT0_STATUS__SYS_INT_RINGBUFFER_WPT9_INT_MASK) { + if (wake) + isp4_wake_up_resp_thread(isp, 1); + + intr_ack |= ISP_SYS_INT0_ACK__SYS_INT_RINGBUFFER_WPT9_ACK_MASK; + } + + /* stream 2 response */ + if (intr_status & + ISP_SYS_INT0_STATUS__SYS_INT_RINGBUFFER_WPT10_INT_MASK) { + if (wake) + isp4_wake_up_resp_thread(isp, 2); + + intr_ack |= ISP_SYS_INT0_ACK__SYS_INT_RINGBUFFER_WPT10_ACK_MASK; + } + + /* stream 3 response */ + if (intr_status & + ISP_SYS_INT0_STATUS__SYS_INT_RINGBUFFER_WPT11_INT_MASK) { + if (wake) + isp4_wake_up_resp_thread(isp, 3); + + intr_ack |= ISP_SYS_INT0_ACK__SYS_INT_RINGBUFFER_WPT11_ACK_MASK; + } + + /* clear ISP_SYS interrupts */ + isp4hw_wreg(ISP4_GET_ISP_REG_BASE(isp), ISP_SYS_INT0_ACK, intr_ack); +} + static irqreturn_t isp4_irq_handler(int irq, void *arg) { - struct isp4_device *isp_dev = dev_get_drvdata((struct device *)arg); + struct isp4_device *isp_dev = dev_get_drvdata(arg); + struct isp4_subdev *isp = NULL; + u32 isp_sys_irq_status = 0x0; + u32 r1; if (!isp_dev) - goto error_drv_data; + return IRQ_HANDLED; + + isp = &isp_dev->isp_sdev; + /* check ISP_SYS interrupts status */ + r1 = isp4hw_rreg(ISP4_GET_ISP_REG_BASE(isp), ISP_SYS_INT0_STATUS); + + isp_sys_irq_status = r1 & ISP4_FW_RESP_RB_IRQ_STATUS_MASK; + + isp4_resp_interrupt_notify(isp, isp_sys_irq_status); -error_drv_data: return IRQ_HANDLED; } +static int isp4_parse_fwnode_init_async_nf(struct isp4_device *isp_dev) +{ + struct isp4_subdev *isp_sdev = &isp_dev->isp_sdev; + struct device *dev = &isp_dev->pdev->dev; + struct v4l2_async_connection *asd; + struct fwnode_handle *fwnode; + struct fwnode_handle *ep; + int ret; + + fwnode = dev_fwnode(dev); + + ep = fwnode_graph_get_next_endpoint(fwnode, NULL); + if (!ep) + return -ENXIO; + + ret = fwnode_property_read_u32(ep, "phy-id", &isp_sdev->phy_id); + if (ret) + return ret; + + ret = fwnode_property_read_u64(ep, "phy-bit-rate", + &isp_sdev->phy_bit_rate); + if (ret) + return ret; + + isp_sdev->phy_num_data_lanes = + fwnode_property_count_u32(ep, "data-lanes"); + + fwnode_handle_put(ep); + + v4l2_async_nf_init(&isp_dev->notifier, &isp_dev->v4l2_dev); + + asd = v4l2_async_nf_add_fwnode(&isp_dev->notifier, ep, + struct v4l2_async_connection); + if (IS_ERR(asd)) { + ret = PTR_ERR(asd); + goto err_async_nf_cleanup; + } + + isp_dev->notifier.ops = &isp4_camera_sensor_ops; + ret = v4l2_async_nf_register(&isp_dev->notifier); + if (ret) { + dev_err(dev, "v4l2_async_nf_register fail:%d", ret); + goto err_async_nf_cleanup; + } + + return 0; + +err_async_nf_cleanup: + v4l2_async_nf_cleanup(&isp_dev->notifier); + return ret; +} + /* * amd capture module */ static int isp4_capture_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; + struct isp4_subdev *isp_sdev; struct isp4_device *isp_dev; int i, irq, ret; @@ -52,6 +242,17 @@ static int isp4_capture_probe(struct platform_device *pdev) isp_dev->pdev = pdev; dev->init_name = ISP4_DRV_NAME; + isp_sdev = &isp_dev->isp_sdev; + isp_sdev->mmio = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(isp_sdev->mmio)) + return dev_err_probe(dev, PTR_ERR(isp_sdev->mmio), + "isp ioremap fail\n"); + + isp_sdev->isp_phy_mmio = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(isp_sdev->isp_phy_mmio)) + return dev_err_probe(dev, PTR_ERR(isp_sdev->isp_phy_mmio), + "isp phy mmio ioremap fail\n"); + for (i = 0; i < ARRAY_SIZE(isp4_ringbuf_interrupt_num); i++) { irq = platform_get_irq(pdev, isp4_ringbuf_interrupt_num[i]); if (irq < 0) @@ -90,10 +291,23 @@ static int isp4_capture_probe(struct platform_device *pdev) dev_dbg(dev, "AMD ISP v4l2 device registered\n"); + ret = isp4sd_init(&isp_dev->isp_sdev, &isp_dev->v4l2_dev, + isp_dev->pltf_data->adev); + if (ret) { + dev_err(dev, "fail init isp4 sub dev %d\n", ret); + goto err_unreg_v4l2; + } + + ret = isp4_parse_fwnode_init_async_nf(isp_dev); + if (ret) { + dev_err(dev, "fail to parse fwnode %d\n", ret); + goto err_unreg_v4l2; + } + ret = media_device_register(&isp_dev->mdev); if (ret) { dev_err(dev, "fail to register media device %d\n", ret); - goto err_unreg_v4l2; + goto err_isp4_deinit; } platform_set_drvdata(pdev, isp_dev); @@ -103,6 +317,10 @@ static int isp4_capture_probe(struct platform_device *pdev) return 0; +err_isp4_deinit: + v4l2_async_nf_unregister(&isp_dev->notifier); + v4l2_async_nf_cleanup(&isp_dev->notifier); + isp4sd_deinit(&isp_dev->isp_sdev); err_unreg_v4l2: v4l2_device_unregister(&isp_dev->v4l2_dev); @@ -112,11 +330,17 @@ static int isp4_capture_probe(struct platform_device *pdev) static void isp4_capture_remove(struct platform_device *pdev) { struct isp4_device *isp_dev = platform_get_drvdata(pdev); - struct device *dev = &pdev->dev; + + v4l2_async_nf_unregister(&isp_dev->notifier); + v4l2_async_nf_cleanup(&isp_dev->notifier); + v4l2_device_unregister_subdev(&isp_dev->isp_sdev.sdev); media_device_unregister(&isp_dev->mdev); + media_entity_cleanup(&isp_dev->isp_sdev.sdev.entity); v4l2_device_unregister(&isp_dev->v4l2_dev); - dev_dbg(dev, "AMD ISP v4l2 device unregistered\n"); + dev_dbg(&pdev->dev, "AMD ISP v4l2 device unregistered\n"); + + isp4sd_deinit(&isp_dev->isp_sdev); } static struct platform_driver isp4_capture_drv = { diff --git a/drivers/media/platform/amd/isp4/isp4.h b/drivers/media/platform/amd/isp4/isp4.h index 27a7362ce6f9..596431b4a5c2 100644 --- a/drivers/media/platform/amd/isp4/isp4.h +++ b/drivers/media/platform/amd/isp4/isp4.h @@ -7,9 +7,9 @@ #define _ISP4_H_ #include -#include #include #include +#include "isp4_subdev.h" #define ISP4_GET_ISP_REG_BASE(isp4sd) (((isp4sd))->mmio) @@ -25,11 +25,13 @@ struct isp4_platform_data { struct isp4_device { struct v4l2_device v4l2_dev; + struct isp4_subdev isp_sdev; struct media_device mdev; struct isp4_platform_data *pltf_data; struct platform_device *pdev; struct notifier_block i2c_nb; + struct v4l2_async_notifier notifier; }; #endif /* isp4.h */ diff --git a/drivers/media/platform/amd/isp4/isp4_subdev.c b/drivers/media/platform/amd/isp4/isp4_subdev.c new file mode 100644 index 000000000000..4b28fbd6867b --- /dev/null +++ b/drivers/media/platform/amd/isp4/isp4_subdev.c @@ -0,0 +1,1213 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2025 Advanced Micro Devices, Inc. + */ + +#include +#include +#include + +#include "isp4_fw_cmd_resp.h" +#include "isp4_hw.h" +#include "isp4_interface.h" +#include "isp4_phy.h" +#include "isp4_subdev.h" + +#define ISP4SD_MAX_CMD_RESP_BUF_SIZE (4 * 1024) +#define ISP4SD_MIN_BUF_CNT_BEF_START_STREAM 4 + +#define ISP4SD_PERFORMANCE_STATE_LOW 0 +#define ISP4SD_PERFORMANCE_STATE_HIGH 1 + +#define ISP4SD_FW_CMD_TIMEOUT_IN_MS 500 +#define ISP4SD_WAIT_RESP_IRQ_TIMEOUT 5 /* ms */ +/* align 32KB */ +#define ISP4SD_META_BUF_SIZE ALIGN(sizeof(struct isp4fw_meta_info), 0x8000) + +#define to_isp4_subdev(v4l2_sdev) \ + container_of(v4l2_sdev, struct isp4_subdev, sdev) + +#define to_isp4_vdev(isp4_vid) \ + container_of(isp4_vid, struct isp4_subdev, isp_vdev) + +static const char *isp4sd_entity_name = "amd isp4"; + +struct isp4sd_mbus_image_format_remap { + u32 mbus_code; + enum isp4fw_image_format image_format; +}; + +static const struct isp4sd_mbus_image_format_remap + isp4sd_image_formats[] = { + { + .mbus_code = MEDIA_BUS_FMT_YUYV8_1_5X8, + .image_format = IMAGE_FORMAT_NV12, + }, + { + .mbus_code = MEDIA_BUS_FMT_YUYV8_1X16, + .image_format = IMAGE_FORMAT_YUV422INTERLEAVED, + }, +}; + +static void isp4sd_module_enable(struct isp4_subdev *isp_subdev, bool enable) +{ + if (isp_subdev->enable_gpio) { + gpiod_set_value(isp_subdev->enable_gpio, enable ? 1 : 0); + dev_dbg(isp_subdev->dev, "%s isp_subdev module\n", + enable ? "enable" : "disable"); + } +} + +static int isp4sd_setup_fw_mem_pool(struct isp4_subdev *isp_subdev) +{ + struct isp4_interface *ispif = &isp_subdev->ispif; + struct isp4fw_cmd_send_buffer buf_type; + struct device *dev = isp_subdev->dev; + int ret; + + if (!ispif->fw_mem_pool) { + dev_err(dev, "fail to alloc mem pool\n"); + return -ENOMEM; + } + + memset(&buf_type, 0, sizeof(buf_type)); + buf_type.buffer_type = BUFFER_TYPE_MEM_POOL; + buf_type.buffer.buf_tags = 0; + buf_type.buffer.vmid_space.bit.vmid = 0; + buf_type.buffer.vmid_space.bit.space = ADDR_SPACE_TYPE_GPU_VA; + isp4if_split_addr64(ispif->fw_mem_pool->gpu_mc_addr, + &buf_type.buffer.buf_base_a_lo, + &buf_type.buffer.buf_base_a_hi); + buf_type.buffer.buf_size_a = (u32)ispif->fw_mem_pool->mem_size; + + ret = isp4if_send_command(ispif, CMD_ID_SEND_BUFFER, + &buf_type, sizeof(buf_type)); + if (ret) { + dev_err(dev, "send fw mem pool 0x%llx(%u) fail %d\n", + ispif->fw_mem_pool->gpu_mc_addr, + buf_type.buffer.buf_size_a, + ret); + return ret; + } + + dev_dbg(dev, "send fw mem pool 0x%llx(%u) suc\n", + ispif->fw_mem_pool->gpu_mc_addr, + buf_type.buffer.buf_size_a); + + return 0; +}; + +static int isp4sd_set_stream_path(struct isp4_subdev *isp_subdev) +{ + struct isp4_interface *ispif = &isp_subdev->ispif; + struct isp4fw_cmd_set_stream_cfg cmd = {0}; + struct device *dev = isp_subdev->dev; + + cmd.stream_cfg.mipi_pipe_path_cfg.isp4fw_sensor_id = SENSOR_ID_ON_MIPI0; + cmd.stream_cfg.mipi_pipe_path_cfg.b_enable = true; + cmd.stream_cfg.isp_pipe_path_cfg.isp_pipe_id = MIPI0_ISP_PIPELINE_ID; + + cmd.stream_cfg.b_enable_tnr = true; + dev_dbg(dev, "isp4fw_sensor_id %d, pipeId 0x%x EnableTnr %u\n", + cmd.stream_cfg.mipi_pipe_path_cfg.isp4fw_sensor_id, + cmd.stream_cfg.isp_pipe_path_cfg.isp_pipe_id, + cmd.stream_cfg.b_enable_tnr); + + return isp4if_send_command(ispif, CMD_ID_SET_STREAM_CONFIG, + &cmd, sizeof(cmd)); +} + +static int isp4sd_send_meta_buf(struct isp4_subdev *isp_subdev) +{ + struct isp4_interface *ispif = &isp_subdev->ispif; + struct isp4fw_cmd_send_buffer buf_type = { 0 }; + struct isp4sd_sensor_info *sensor_info; + struct device *dev = isp_subdev->dev; + u32 i; + + sensor_info = &isp_subdev->sensor_info; + for (i = 0; i < ISP4IF_MAX_STREAM_META_BUF_COUNT; i++) { + int ret; + + if (!sensor_info->meta_info_buf[i]) { + dev_err(dev, "fail for no meta info buf(%u)\n", i); + return -ENOMEM; + } + buf_type.buffer_type = BUFFER_TYPE_META_INFO; + buf_type.buffer.buf_tags = 0; + buf_type.buffer.vmid_space.bit.vmid = 0; + buf_type.buffer.vmid_space.bit.space = ADDR_SPACE_TYPE_GPU_VA; + isp4if_split_addr64(sensor_info->meta_info_buf[i]->gpu_mc_addr, + &buf_type.buffer.buf_base_a_lo, + &buf_type.buffer.buf_base_a_hi); + buf_type.buffer.buf_size_a = + (u32)sensor_info->meta_info_buf[i]->mem_size; + ret = isp4if_send_command(ispif, CMD_ID_SEND_BUFFER, + &buf_type, + sizeof(buf_type)); + if (ret) { + dev_err(dev, "send meta info(%u) fail\n", i); + return ret; + } + } + + dev_dbg(dev, "send meta info suc\n"); + return 0; +} + +static int isp4sd_enum_mbus_code(struct v4l2_subdev *isp_subdev, + struct v4l2_subdev_state *state, + struct v4l2_subdev_mbus_code_enum *code_enum) +{ + if (code_enum->index >= ARRAY_SIZE(isp4sd_image_formats)) + return -EINVAL; + + code_enum->code = isp4sd_image_formats[code_enum->index].mbus_code; + + return 0; +} + +static bool isp4sd_get_str_out_prop(struct isp4_subdev *isp_subdev, + struct isp4fw_image_prop *out_prop, + struct v4l2_subdev_state *state, u32 pad) +{ + struct v4l2_mbus_framefmt *format = NULL; + struct device *dev = isp_subdev->dev; + bool ret; + + format = v4l2_subdev_state_get_format(state, pad, 0); + if (!format) { + dev_err(dev, "fail get subdev state format\n"); + return false; + } + + switch (format->code) { + case MEDIA_BUS_FMT_YUYV8_1_5X8: + out_prop->image_format = IMAGE_FORMAT_NV12; + out_prop->width = format->width; + out_prop->height = format->height; + out_prop->luma_pitch = format->width; + out_prop->chroma_pitch = out_prop->width; + ret = true; + break; + case MEDIA_BUS_FMT_YUYV8_1X16: + out_prop->image_format = IMAGE_FORMAT_YUV422INTERLEAVED; + out_prop->width = format->width; + out_prop->height = format->height; + out_prop->luma_pitch = format->width * 2; + out_prop->chroma_pitch = 0; + ret = true; + break; + default: + dev_err(dev, "fail for bad image format:0x%x\n", + format->code); + ret = false; + break; + } + + if (!out_prop->width || !out_prop->height) + ret = false; + return ret; +} + +static int isp4sd_kickoff_stream(struct isp4_subdev *isp_subdev, u32 w, u32 h) +{ + struct isp4sd_sensor_info *sensor_info = &isp_subdev->sensor_info; + struct isp4_interface *ispif = &isp_subdev->ispif; + struct device *dev = isp_subdev->dev; + + if (sensor_info->status == ISP4SD_START_STATUS_STARTED) { + return 0; + } else if (sensor_info->status == ISP4SD_START_STATUS_START_FAIL) { + dev_err(dev, "fail for previous start fail\n"); + return -EINVAL; + } + + dev_dbg(dev, "w:%u,h:%u\n", w, h); + + sensor_info->status = ISP4SD_START_STATUS_START_FAIL; + + if (isp4sd_send_meta_buf(isp_subdev)) { + dev_err(dev, "fail to send meta buf\n"); + return -EINVAL; + }; + + sensor_info->status = ISP4SD_START_STATUS_NOT_START; + + if (!sensor_info->start_stream_cmd_sent && + sensor_info->buf_sent_cnt >= + ISP4SD_MIN_BUF_CNT_BEF_START_STREAM) { + int ret = isp4if_send_command(ispif, CMD_ID_START_STREAM, + NULL, 0); + if (ret) { + dev_err(dev, "fail to start stream\n"); + return ret; + } + + sensor_info->start_stream_cmd_sent = true; + } else { + dev_dbg(dev, + "no send START_STREAM, start_sent %u, buf_sent %u\n", + sensor_info->start_stream_cmd_sent, + sensor_info->buf_sent_cnt); + } + + return 0; +} + +static int isp4sd_setup_output(struct isp4_subdev *isp_subdev, + struct v4l2_subdev_state *state, u32 pad) +{ + struct isp4sd_sensor_info *sensor_info = &isp_subdev->sensor_info; + struct isp4sd_output_info *output_info = + &isp_subdev->sensor_info.output_info; + struct isp4fw_cmd_set_out_ch_prop cmd_ch_prop = {0}; + struct isp4_interface *ispif = &isp_subdev->ispif; + struct isp4fw_cmd_enable_out_ch cmd_ch_en = {0}; + struct isp4fw_image_prop *out_prop; + struct device *dev = isp_subdev->dev; + int ret; + + if (output_info->start_status == ISP4SD_START_STATUS_STARTED) + return 0; + + if (output_info->start_status == ISP4SD_START_STATUS_START_FAIL) { + dev_err(dev, "fail for previous start fail\n"); + return -EINVAL; + } + + out_prop = &cmd_ch_prop.image_prop; + cmd_ch_prop.ch = ISP_PIPE_OUT_CH_PREVIEW; + cmd_ch_en.ch = ISP_PIPE_OUT_CH_PREVIEW; + cmd_ch_en.is_enable = true; + + if (!isp4sd_get_str_out_prop(isp_subdev, out_prop, state, pad)) { + dev_err(dev, "fail to get out prop\n"); + return -EINVAL; + } + + dev_dbg(dev, "channel: w:h=%u:%u,lp:%u,cp%u\n", + cmd_ch_prop.image_prop.width, cmd_ch_prop.image_prop.height, + cmd_ch_prop.image_prop.luma_pitch, + cmd_ch_prop.image_prop.chroma_pitch); + + ret = isp4if_send_command(ispif, CMD_ID_SET_OUT_CHAN_PROP, + &cmd_ch_prop, + sizeof(cmd_ch_prop)); + if (ret) { + output_info->start_status = ISP4SD_START_STATUS_START_FAIL; + dev_err(dev, "fail to set out prop\n"); + return ret; + }; + + ret = isp4if_send_command(ispif, CMD_ID_ENABLE_OUT_CHAN, + &cmd_ch_en, sizeof(cmd_ch_en)); + + if (ret) { + output_info->start_status = ISP4SD_START_STATUS_START_FAIL; + dev_err(dev, "fail to enable channel\n"); + return ret; + } + + if (!sensor_info->start_stream_cmd_sent) { + ret = isp4sd_kickoff_stream(isp_subdev, out_prop->width, + out_prop->height); + if (ret) { + dev_err(dev, "kickoff stream fail %d\n", ret); + return ret; + } + /* sensor_info->start_stream_cmd_sent will be set to true + * 1. in isp4sd_kickoff_stream, if app first send buffer then + * start stream + * 2. in isp_set_stream_buf, if app first start stream, then + * send buffer + * because ISP FW has the requirement, host needs to send buffer + * before send start stream cmd + */ + if (sensor_info->start_stream_cmd_sent) { + sensor_info->status = ISP4SD_START_STATUS_STARTED; + output_info->start_status = ISP4SD_START_STATUS_STARTED; + dev_dbg(dev, "kickoff stream suc,start cmd sent\n"); + } else { + dev_dbg(dev, "kickoff stream suc,start cmd not sent\n"); + } + } else { + dev_dbg(dev, "stream running, no need kickoff\n"); + output_info->start_status = ISP4SD_START_STATUS_STARTED; + } + + dev_dbg(dev, "setup output suc\n"); + return 0; +} + +static int isp4sd_alloc_meta_buf(struct isp4_subdev *isp_subdev) +{ + struct isp4sd_sensor_info *sensor_info = &isp_subdev->sensor_info; + struct isp4_interface *ispif = &isp_subdev->ispif; + struct device *dev = isp_subdev->dev; + u32 i; + + /* TODO: check alloc method */ + for (i = 0; i < ISP4IF_MAX_STREAM_META_BUF_COUNT; i++) { + if (!sensor_info->meta_info_buf[i]) { + sensor_info->meta_info_buf[i] = + ispif->metainfo_buf_pool[i]; + if (sensor_info->meta_info_buf[i]) { + dev_dbg(dev, "valid %u meta_info_buf ok\n", i); + } else { + dev_err(dev, + "invalid %u meta_info_buf fail\n", i); + return -ENOMEM; + } + } + } + + return 0; +} + +static int isp4sd_init_stream(struct isp4_subdev *isp_subdev) +{ + struct device *dev = isp_subdev->dev; + int ret; + + ret = isp4sd_setup_fw_mem_pool(isp_subdev); + if (ret) { + dev_err(dev, "fail to setup fw mem pool\n"); + return ret; + } + + ret = isp4sd_alloc_meta_buf(isp_subdev); + if (ret) { + dev_err(dev, "fail to alloc fw driver shared buf\n"); + return ret; + } + + ret = isp4sd_set_stream_path(isp_subdev); + if (ret) { + dev_err(dev, "fail to setup stream path\n"); + return ret; + } + + return 0; +} + +static void isp4sd_reset_stream_info(struct isp4_subdev *isp_subdev, + struct v4l2_subdev_state *state, u32 pad) +{ + struct isp4sd_sensor_info *sensor_info = &isp_subdev->sensor_info; + struct v4l2_mbus_framefmt *format = NULL; + struct isp4sd_output_info *str_info; + int i; + + format = v4l2_subdev_state_get_format(state, + pad, + 0); + + if (!format) { + pr_err("fail reset stream info for not get format\n"); + + } else { + memset(format, 0, sizeof(*format)); + format->code = MEDIA_BUS_FMT_YUYV8_1_5X8; + } + + for (i = 0; i < ISP4IF_MAX_STREAM_META_BUF_COUNT; i++) + sensor_info->meta_info_buf[i] = NULL; + + str_info = &sensor_info->output_info; + str_info->start_status = ISP4SD_START_STATUS_NOT_START; +} + +static bool isp4sd_is_stream_running(struct isp4_subdev *isp_subdev) +{ + struct isp4sd_sensor_info *sif; + enum isp4sd_start_status stat; + + sif = &isp_subdev->sensor_info; + stat = sif->output_info.start_status; + if (stat == ISP4SD_START_STATUS_STARTED) + return true; + + return false; +} + +static void isp4sd_reset_camera_info(struct isp4_subdev *isp_subdev, + struct v4l2_subdev_state *state, u32 pad) +{ + struct isp4sd_sensor_info *info = &isp_subdev->sensor_info; + + info->status = ISP4SD_START_STATUS_NOT_START; + isp4sd_reset_stream_info(isp_subdev, state, pad); + + info->start_stream_cmd_sent = false; +} + +static int isp4sd_uninit_stream(struct isp4_subdev *isp_subdev, + struct v4l2_subdev_state *state, u32 pad) +{ + struct isp4_interface *ispif = &isp_subdev->ispif; + struct device *dev = isp_subdev->dev; + bool running; + + running = isp4sd_is_stream_running(isp_subdev); + + if (running) { + dev_dbg(dev, "fail for stream is still running\n"); + return -EINVAL; + } + + isp4sd_reset_camera_info(isp_subdev, state, pad); + + isp4if_clear_cmdq(ispif); + return 0; +} + +static void isp4sd_fw_resp_cmd_done(struct isp4_subdev *isp_subdev, + enum isp4if_stream_id stream_id, + struct isp4fw_resp_cmd_done *para) +{ + struct isp4_interface *ispif = &isp_subdev->ispif; + struct isp4if_cmd_element *ele = + isp4if_rm_cmd_from_cmdq(ispif, para->cmd_seq_num, para->cmd_id); + struct device *dev = isp_subdev->dev; + + dev_dbg(dev, "stream %d,cmd (0x%08x)(%d),seq %u, ele %p\n", + stream_id, + para->cmd_id, para->cmd_status, para->cmd_seq_num, + ele); + + if (!ele) + return; + + if (ele->wq) { + dev_dbg(dev, "signal event %p\n", ele->wq); + if (ele->wq_cond) + *ele->wq_cond = 1; + wake_up(ele->wq); + } + + kfree(ele); +} + +static struct isp4fw_meta_info * +isp4sd_get_meta_by_mc(struct isp4_subdev *isp_subdev, + u64 mc) +{ + u32 i; + + for (i = 0; i < ISP4IF_MAX_STREAM_META_BUF_COUNT; i++) { + struct isp4if_gpu_mem_info *meta_info_buf = + isp_subdev->sensor_info.meta_info_buf[i]; + + if (meta_info_buf) { + if (mc == meta_info_buf->gpu_mc_addr) + return meta_info_buf->sys_addr; + } + } + return NULL; +}; + +static struct isp4if_img_buf_node * +isp4sd_preview_done(struct isp4_subdev *isp_subdev, + struct isp4fw_meta_info *meta) +{ + struct isp4_interface *ispif = &isp_subdev->ispif; + struct isp4if_img_buf_node *prev = NULL; + struct device *dev = isp_subdev->dev; + + if (!meta) { + dev_err(dev, "fail bad param for preview done\n"); + return prev; + } + + if (meta->preview.enabled && + (meta->preview.status == BUFFER_STATUS_SKIPPED || + meta->preview.status == BUFFER_STATUS_DONE || + meta->preview.status == BUFFER_STATUS_DIRTY)) { + struct isp4sd_output_info *str_info; + + str_info = &isp_subdev->sensor_info.output_info; + prev = isp4if_dequeue_buffer(ispif); + + if (!prev) + dev_err(dev, "fail null prev buf\n"); + + } else if (meta->preview.enabled) { + dev_err(dev, "fail bad preview status %u\n", + meta->preview.status); + } + + return prev; +} + +static void isp4sd_send_meta_info(struct isp4_subdev *isp_subdev, + u64 meta_info_mc) +{ + struct isp4_interface *ispif = &isp_subdev->ispif; + struct isp4fw_cmd_send_buffer buf_type; + struct device *dev = isp_subdev->dev; + + if (isp_subdev->sensor_info.status != ISP4SD_START_STATUS_STARTED) { + dev_warn(dev, "not working status %i, meta_info 0x%llx\n", + isp_subdev->sensor_info.status, meta_info_mc); + return; + } + + if (meta_info_mc) { + memset(&buf_type, 0, sizeof(buf_type)); + buf_type.buffer_type = BUFFER_TYPE_META_INFO; + buf_type.buffer.buf_tags = 0; + buf_type.buffer.vmid_space.bit.vmid = 0; + buf_type.buffer.vmid_space.bit.space = ADDR_SPACE_TYPE_GPU_VA; + isp4if_split_addr64(meta_info_mc, + &buf_type.buffer.buf_base_a_lo, + &buf_type.buffer.buf_base_a_hi); + + buf_type.buffer.buf_size_a = ISP4SD_META_BUF_SIZE; + if (isp4if_send_command(ispif, CMD_ID_SEND_BUFFER, + &buf_type, sizeof(buf_type))) { + dev_err(dev, "fail send meta_info 0x%llx\n", + meta_info_mc); + } else { + dev_dbg(dev, "resend meta_info 0x%llx\n", meta_info_mc); + } + } +} + +static void isp4sd_fw_resp_frame_done(struct isp4_subdev *isp_subdev, + enum isp4if_stream_id stream_id, + struct isp4fw_resp_param_package *para) +{ + struct isp4if_img_buf_node *prev = NULL; + struct device *dev = isp_subdev->dev; + struct isp4fw_meta_info *meta; + u64 mc = 0; + + mc = isp4if_join_addr64(para->package_addr_lo, para->package_addr_hi); + meta = isp4sd_get_meta_by_mc(isp_subdev, mc); + if (mc == 0 || !meta) { + dev_err(dev, "fail to get meta from mc %llx\n", mc); + return; + } + + dev_dbg(dev, "ts:%llu,streamId:%d,poc:%u,preview_en:%u,(%i)\n", + ktime_get_ns(), stream_id, meta->poc, + meta->preview.enabled, + meta->preview.status); + + prev = isp4sd_preview_done(isp_subdev, meta); + + isp4if_dealloc_buffer_node(prev); + + if (isp_subdev->sensor_info.status == ISP4SD_START_STATUS_STARTED) + isp4sd_send_meta_info(isp_subdev, mc); + + dev_dbg(dev, "stream_id:%d, status:%d\n", stream_id, + isp_subdev->sensor_info.status); +} + +static void isp4sd_fw_resp_func(struct isp4_subdev *isp_subdev, + enum isp4if_stream_id stream_id) +{ + struct isp4_interface *ispif = &isp_subdev->ispif; + struct device *dev = isp_subdev->dev; + struct isp4fw_resp resp; + + if (ispif->status < ISP4IF_STATUS_FW_RUNNING) + return; + + while (true) { + s32 ret; + + ret = isp4if_f2h_resp(ispif, stream_id, &resp); + if (ret) + break; + + switch (resp.resp_id) { + case RESP_ID_CMD_DONE: + isp4sd_fw_resp_cmd_done(isp_subdev, stream_id, + &resp.param.cmd_done); + break; + case RESP_ID_NOTI_FRAME_DONE: + isp4sd_fw_resp_frame_done(isp_subdev, stream_id, + &resp.param.frame_done); + break; + default: + dev_err(dev, "-><- fail respid (0x%x)\n", + resp.resp_id); + break; + } + } +} + +static s32 isp4sd_fw_resp_thread_wrapper(void *context) +{ + struct isp4_subdev_thread_param *para = context; + struct isp4sd_thread_handler *thread_ctx; + enum isp4if_stream_id stream_id; + + struct isp4_subdev *isp_subdev; + struct device *dev; + u64 timeout; + + if (!para) { + dev_err(dev, "fail null context for resp thread\n"); + return -EINVAL; + } + + isp_subdev = para->isp_subdev; + dev = isp_subdev->dev; + + switch (para->idx) { + case 0: + stream_id = ISP4IF_STREAM_ID_GLOBAL; + break; + case 1: + stream_id = ISP4IF_STREAM_ID_1; + break; + default: + dev_err(dev, "fail invalid %d\n", para->idx); + return -EINVAL; + } + + thread_ctx = &isp_subdev->fw_resp_thread[para->idx]; + + thread_ctx->wq_cond = 0; + mutex_init(&thread_ctx->mutex); + init_waitqueue_head(&thread_ctx->waitq); + timeout = msecs_to_jiffies(ISP4SD_WAIT_RESP_IRQ_TIMEOUT); + + dev_dbg(dev, "[%u] started\n", para->idx); + + while (true) { + wait_event_interruptible_timeout(thread_ctx->waitq, + thread_ctx->wq_cond != 0, + timeout); + thread_ctx->wq_cond = 0; + + if (kthread_should_stop()) { + dev_dbg(dev, "[%u] quit\n", para->idx); + break; + } + + mutex_lock(&thread_ctx->mutex); + isp4sd_fw_resp_func(isp_subdev, stream_id); + mutex_unlock(&thread_ctx->mutex); + } + + mutex_destroy(&thread_ctx->mutex); + + return 0; +} + +static int isp4sd_start_resp_proc_threads(struct isp4_subdev *isp_subdev) +{ + struct device *dev = isp_subdev->dev; + int i; + + for (i = 0; i < ISP4SD_MAX_FW_RESP_STREAM_NUM; i++) { + struct isp4sd_thread_handler *thread_ctx = + &isp_subdev->fw_resp_thread[i]; + + isp_subdev->isp_resp_para[i].idx = i; + isp_subdev->isp_resp_para[i].isp_subdev = isp_subdev; + + thread_ctx->thread = kthread_run(isp4sd_fw_resp_thread_wrapper, + &isp_subdev->isp_resp_para[i], + "amd_isp4_thread"); + if (IS_ERR(thread_ctx->thread)) { + dev_err(dev, "create thread [%d] fail\n", i); + return -EINVAL; + } + } + + return 0; +} + +static int isp4sd_stop_resp_proc_threads(struct isp4_subdev *isp_subdev) +{ + int i; + + for (i = 0; i < ISP4SD_MAX_FW_RESP_STREAM_NUM; i++) { + struct isp4sd_thread_handler *thread_ctx = + &isp_subdev->fw_resp_thread[i]; + + if (thread_ctx->thread) { + kthread_stop(thread_ctx->thread); + thread_ctx->thread = NULL; + } + } + + return 0; +} + +static u32 isp4sd_get_started_stream_count(struct isp4_subdev *isp_subdev) +{ + u32 cnt = 0; + + if (isp_subdev->sensor_info.status == ISP4SD_START_STATUS_STARTED) + cnt++; + return cnt; +} + +static int isp4sd_pwroff_and_deinit(struct isp4_subdev *isp_subdev) +{ + struct isp4sd_sensor_info *sensor_info = &isp_subdev->sensor_info; + unsigned int perf_state = ISP4SD_PERFORMANCE_STATE_LOW; + struct isp4_interface *ispif = &isp_subdev->ispif; + + struct device *dev = isp_subdev->dev; + u32 cnt; + int ret; + + mutex_lock(&isp_subdev->ops_mutex); + + if (sensor_info->status == ISP4SD_START_STATUS_STARTED) { + dev_err(dev, "fail for stream still running\n"); + mutex_unlock(&isp_subdev->ops_mutex); + return -EINVAL; + } + + sensor_info->status = ISP4SD_START_STATUS_NOT_START; + cnt = isp4sd_get_started_stream_count(isp_subdev); + if (cnt > 0) { + dev_dbg(dev, "no need power off isp_subdev\n"); + mutex_unlock(&isp_subdev->ops_mutex); + return 0; + } + + isp4if_stop(ispif); + + ret = dev_pm_genpd_set_performance_state(dev, perf_state); + if (ret) + dev_err(dev, + "fail to set isp_subdev performance state %u,ret %d\n", + perf_state, ret); + isp4sd_stop_resp_proc_threads(isp_subdev); + dev_dbg(dev, "isp_subdev stop resp proc streads suc"); + /* hold ccpu reset */ + isp4hw_wreg(isp_subdev->mmio, ISP_SOFT_RESET, 0x0); + isp4hw_wreg(isp_subdev->mmio, ISP_POWER_STATUS, 0); + ret = pm_runtime_put_sync(dev); + if (ret) + dev_err(dev, "power off isp_subdev fail %d\n", ret); + else + dev_dbg(dev, "power off isp_subdev suc\n"); + + ispif->status = ISP4IF_STATUS_PWR_OFF; + isp4if_clear_cmdq(ispif); + isp4sd_module_enable(isp_subdev, false); + + msleep(20); + + mutex_unlock(&isp_subdev->ops_mutex); + + return 0; +} + +static int isp4sd_pwron_and_init(struct isp4_subdev *isp_subdev) +{ + struct isp4_interface *ispif = &isp_subdev->ispif; + struct device *dev = isp_subdev->dev; + int ret; + + if (ispif->status == ISP4IF_STATUS_FW_RUNNING) { + dev_dbg(dev, "camera already opened, do nothing\n"); + return 0; + } + + mutex_lock(&isp_subdev->ops_mutex); + + isp4sd_module_enable(isp_subdev, true); + + isp_subdev->sensor_info.start_stream_cmd_sent = false; + isp_subdev->sensor_info.buf_sent_cnt = 0; + + if (ispif->status < ISP4IF_STATUS_PWR_ON) { + unsigned int perf_state = ISP4SD_PERFORMANCE_STATE_HIGH; + + ret = pm_runtime_get_sync(dev); + if (ret) { + dev_err(dev, "fail to power on isp_subdev ret %d\n", + ret); + goto err_unlock_and_close; + } + + /* ISPPG ISP Power Status */ + isp4hw_wreg(isp_subdev->mmio, ISP_POWER_STATUS, 0x7FF); + ret = dev_pm_genpd_set_performance_state(dev, perf_state); + if (ret) { + dev_err(dev, + "fail to set performance state %u, ret %d\n", + perf_state, ret); + goto err_unlock_and_close; + } + + ispif->status = ISP4IF_STATUS_PWR_ON; + + if (isp4sd_start_resp_proc_threads(isp_subdev)) { + dev_err(dev, "isp_start_resp_proc_threads fail"); + goto err_unlock_and_close; + } else { + dev_dbg(dev, "create resp threads ok"); + } + } + + isp_subdev->sensor_info.start_stream_cmd_sent = false; + isp_subdev->sensor_info.buf_sent_cnt = 0; + + ret = isp4if_start(ispif); + if (ret) { + dev_err(dev, "fail to start isp_subdev interface\n"); + goto err_unlock_and_close; + } + + mutex_unlock(&isp_subdev->ops_mutex); + return 0; +err_unlock_and_close: + mutex_unlock(&isp_subdev->ops_mutex); + isp4sd_pwroff_and_deinit(isp_subdev); + return -EINVAL; +} + +static int isp4sd_stop_stream(struct isp4_subdev *isp_subdev, + struct v4l2_subdev_state *state, u32 pad) +{ + struct isp4sd_output_info *output_info = + &isp_subdev->sensor_info.output_info; + struct isp4_interface *ispif = &isp_subdev->ispif; + struct device *dev = isp_subdev->dev; + int ret = 0; + + dev_dbg(dev, "status %i\n", output_info->start_status); + mutex_lock(&isp_subdev->ops_mutex); + + if (output_info->start_status == ISP4SD_START_STATUS_STARTED) { + struct isp4fw_cmd_enable_out_ch cmd_ch_disable; + + cmd_ch_disable.ch = ISP_PIPE_OUT_CH_PREVIEW; + cmd_ch_disable.is_enable = false; + ret = isp4if_send_command_sync(ispif, + CMD_ID_ENABLE_OUT_CHAN, + &cmd_ch_disable, + sizeof(cmd_ch_disable), + ISP4SD_FW_CMD_TIMEOUT_IN_MS); + if (ret) + dev_err(dev, "fail to disable stream\n"); + else + dev_dbg(dev, "wait disable stream suc\n"); + + ret = isp4if_send_command_sync(ispif, CMD_ID_STOP_STREAM, + NULL, + 0, + ISP4SD_FW_CMD_TIMEOUT_IN_MS); + if (ret) + dev_err(dev, "fail to stop steam\n"); + else + dev_dbg(dev, "wait stop stream suc\n"); + } + + isp4if_clear_bufq(ispif); + + output_info->start_status = ISP4SD_START_STATUS_NOT_START; + isp4sd_reset_stream_info(isp_subdev, state, pad); + + mutex_unlock(&isp_subdev->ops_mutex); + + isp4sd_uninit_stream(isp_subdev, state, pad); + + return ret; +} + +static int isp4sd_start_stream(struct isp4_subdev *isp_subdev, + struct v4l2_subdev_state *state, u32 pad) +{ + struct isp4sd_output_info *output_info = + &isp_subdev->sensor_info.output_info; + struct isp4_interface *ispif = &isp_subdev->ispif; + struct device *dev = isp_subdev->dev; + int ret; + + mutex_lock(&isp_subdev->ops_mutex); + + if (ispif->status != ISP4IF_STATUS_FW_RUNNING) { + mutex_unlock(&isp_subdev->ops_mutex); + dev_err(dev, "fail, bad fsm %d", ispif->status); + return -EINVAL; + } + + ret = isp4sd_init_stream(isp_subdev); + + if (ret) { + dev_err(dev, "fail to init isp_subdev stream\n"); + ret = -EINVAL; + goto unlock_and_check_ret; + } + + if (output_info->start_status == ISP4SD_START_STATUS_STARTED) { + ret = 0; + dev_dbg(dev, "stream started, do nothing\n"); + goto unlock_and_check_ret; + } else if (output_info->start_status == + ISP4SD_START_STATUS_START_FAIL) { + ret = -EINVAL; + dev_err(dev, "stream fail to start before\n"); + goto unlock_and_check_ret; + } + + if (isp4sd_setup_output(isp_subdev, state, pad)) { + dev_err(dev, "fail to setup output\n"); + ret = -EINVAL; + } else { + ret = 0; + dev_dbg(dev, "suc to setup out\n"); + } +unlock_and_check_ret: + mutex_unlock(&isp_subdev->ops_mutex); + if (ret) { + isp4sd_stop_stream(isp_subdev, state, pad); + dev_err(dev, "start stream fail\n"); + } else { + dev_dbg(dev, "start stream suc\n"); + } + + return ret; +} + +static int isp4sd_subdev_pre_streamon(struct v4l2_subdev *sd, u32 flags) +{ + struct isp4_subdev *isp_subdev = to_isp4_subdev(sd); + int ret; + + u32 num_data_lanes = isp_subdev->phy_num_data_lanes; + u64 phy_bit_rate = isp_subdev->phy_bit_rate; + u32 phy_id = isp_subdev->phy_id; + + ret = isp4phy_start(isp_subdev->dev, + isp_subdev->isp_phy_mmio, phy_id, + phy_bit_rate, num_data_lanes); + if (ret) { + dev_err(isp_subdev->dev, + "fail start phy,lane %d id %u bitrate %llu, %d\n", + num_data_lanes, phy_id, phy_bit_rate, ret); + return ret; + } + + dev_dbg(isp_subdev->dev, "start phy suc,lane %d id %u bit_rate %llu\n", + num_data_lanes, phy_id, phy_bit_rate); + + return ret; +} + +static int isp4sd_subdev_post_streamoff(struct v4l2_subdev *sd) +{ + struct isp4_subdev *isp_subdev = to_isp4_subdev(sd); + int ret; + + dev_dbg(isp_subdev->dev, "stopping phy %u\n", isp_subdev->phy_id); + ret = isp4phy_stop(isp_subdev->isp_phy_mmio, + isp_subdev->phy_id); + if (ret) + dev_err(isp_subdev->dev, "fail to stop the Phy:%d", ret); + + return ret; +} + +static int isp4sd_subdev_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) +{ + return 0; +} + +static int isp4sd_set_power(struct v4l2_subdev *sd, int on) +{ + struct isp4_subdev *ispsd = to_isp4_subdev(sd); + + if (on) + return isp4sd_pwron_and_init(ispsd); + else + return isp4sd_pwroff_and_deinit(ispsd); +}; + +static const struct v4l2_subdev_core_ops isp4sd_core_ops = { + .s_power = isp4sd_set_power, +}; + +static const struct v4l2_subdev_video_ops isp4sd_video_ops = { + .s_stream = v4l2_subdev_s_stream_helper, + .pre_streamon = isp4sd_subdev_pre_streamon, + .post_streamoff = isp4sd_subdev_post_streamoff, +}; + +static int isp4sd_set_pad_format(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *fmt) +{ + struct isp4sd_output_info *steam_info = + &(to_isp4_subdev(sd)->sensor_info.output_info); + struct v4l2_mbus_framefmt *format; + + format = v4l2_subdev_state_get_format(sd_state, fmt->pad); + + if (!format) { + dev_err(sd->dev, "fail to get state format\n"); + return -EINVAL; + } + + *format = fmt->format; + switch (format->code) { + case MEDIA_BUS_FMT_YUYV8_1_5X8: + steam_info->image_size = format->width * format->height * 3 / 2; + break; + case MEDIA_BUS_FMT_YUYV8_1X16: + steam_info->image_size = format->width * format->height * 2; + break; + default: + steam_info->image_size = 0; + break; + } + if (!steam_info->image_size) { + dev_err(sd->dev, + "fail set pad format,code 0x%x,width %u, height %u\n", + format->code, format->width, format->height); + return -EINVAL; + } + dev_dbg(sd->dev, + "set pad format suc, code:%x w:%u h:%u size:%u\n", format->code, + format->width, format->height, steam_info->image_size); + + return 0; +} + +static int isp4sd_enable_streams(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state, u32 pad, + u64 streams_mask) +{ + struct isp4_subdev *ispsd = to_isp4_subdev(sd); + + return isp4sd_start_stream(ispsd, state, pad); +} + +static int isp4sd_disable_streams(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state, u32 pad, + u64 streams_mask) +{ + struct isp4_subdev *ispsd = to_isp4_subdev(sd); + + return isp4sd_stop_stream(ispsd, state, pad); +} + +static const struct v4l2_subdev_pad_ops isp4sd_pad_ops = { + .enum_mbus_code = isp4sd_enum_mbus_code, + .get_fmt = v4l2_subdev_get_fmt, + .set_fmt = isp4sd_set_pad_format, + .enable_streams = isp4sd_enable_streams, + .disable_streams = isp4sd_disable_streams, +}; + +static const struct v4l2_subdev_ops isp4sd_subdev_ops = { + .core = &isp4sd_core_ops, + .video = &isp4sd_video_ops, + .pad = &isp4sd_pad_ops, +}; + +static const struct v4l2_subdev_internal_ops isp4sd_subdev_internal_ops = { + .open = isp4sd_subdev_open, +}; + +static int isp4sd_sdev_link_validate(struct media_link *link) +{ + return 0; +} + +static const struct media_entity_operations isp4sd_sdev_ent_ops = { + .link_validate = isp4sd_sdev_link_validate, +}; + +int isp4sd_init(struct isp4_subdev *isp_subdev, + struct v4l2_device *v4l2_dev, + void *amdgpu_dev) +{ + struct isp4_interface *ispif = &isp_subdev->ispif; + struct isp4sd_sensor_info *sensor_info; + struct isp4sd_output_info *output_info; + struct device *dev = v4l2_dev->dev; + int ret; + + isp_subdev->dev = dev; + isp_subdev->amdgpu_dev = amdgpu_dev; + v4l2_subdev_init(&isp_subdev->sdev, &isp4sd_subdev_ops); + isp_subdev->sdev.owner = THIS_MODULE; + isp_subdev->sdev.dev = dev; + snprintf(isp_subdev->sdev.name, sizeof(isp_subdev->sdev.name), "%s", + dev_name(dev)); + + isp_subdev->sdev.flags = V4L2_SUBDEV_FL_HAS_DEVNODE; + isp_subdev->sdev.entity.name = isp4sd_entity_name; + isp_subdev->sdev.entity.function = MEDIA_ENT_F_PROC_VIDEO_ISP; + isp_subdev->sdev.entity.ops = &isp4sd_sdev_ent_ops; + isp_subdev->sdev_pad[0].flags = MEDIA_PAD_FL_SINK; + isp_subdev->sdev_pad[1].flags = MEDIA_PAD_FL_SOURCE; + ret = media_entity_pads_init(&isp_subdev->sdev.entity, 2, + isp_subdev->sdev_pad); + if (ret) { + dev_err(dev, "fail to init isp4 subdev entity pad %d\n", ret); + return ret; + } + ret = v4l2_subdev_init_finalize(&isp_subdev->sdev); + if (ret < 0) { + dev_err(dev, "fail to init finalize isp4 subdev %d\n", + ret); + return ret; + } + ret = v4l2_device_register_subdev(v4l2_dev, &isp_subdev->sdev); + if (ret) { + dev_err(dev, "fail to register isp4 subdev to V4L2 device %d\n", + ret); + goto err_media_clean_up; + } + + output_info = &isp_subdev->sensor_info.output_info; + sensor_info = &isp_subdev->sensor_info; + + isp4if_init(ispif, dev, amdgpu_dev, isp_subdev->mmio); + + mutex_init(&isp_subdev->ops_mutex); + sensor_info->start_stream_cmd_sent = false; + sensor_info->status = ISP4SD_START_STATUS_NOT_START; + + /* create ISP enable gpio control */ + isp_subdev->enable_gpio = devm_gpiod_get(isp_subdev->dev, + "enable_isp", + GPIOD_OUT_LOW); + if (IS_ERR(isp_subdev->enable_gpio)) { + dev_err(dev, "fail to get gpiod %d\n", ret); + media_entity_cleanup(&isp_subdev->sdev.entity); + return PTR_ERR(isp_subdev->enable_gpio); + } + + isp_subdev->host2fw_seq_num = 1; + ispif->status = ISP4IF_STATUS_PWR_OFF; + + if (ret) + goto err_media_clean_up; + return ret; + +err_media_clean_up: + media_entity_cleanup(&isp_subdev->sdev.entity); + return ret; +} + +void isp4sd_deinit(struct isp4_subdev *isp_subdev) +{ + struct isp4_interface *ispif = &isp_subdev->ispif; + struct isp4sd_output_info *output_info; + + output_info = &isp_subdev->sensor_info.output_info; + media_entity_cleanup(&isp_subdev->sdev.entity); + + isp4if_deinit(ispif); + + isp4sd_module_enable(isp_subdev, false); + + ispif->status = ISP4IF_STATUS_PWR_OFF; +} diff --git a/drivers/media/platform/amd/isp4/isp4_subdev.h b/drivers/media/platform/amd/isp4/isp4_subdev.h new file mode 100644 index 000000000000..99ec914a95ce --- /dev/null +++ b/drivers/media/platform/amd/isp4/isp4_subdev.h @@ -0,0 +1,145 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2025 Advanced Micro Devices, Inc. + */ + +#ifndef _ISP4_CONTEXT_H_ +#define _ISP4_CONTEXT_H_ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "isp4_fw_cmd_resp.h" +#include "isp4_hw_reg.h" +#include "isp4_interface.h" + +/* + * one is for none sesnor specefic response which is not used now + * another is for sensor specific response + */ +#define ISP4SD_MAX_FW_RESP_STREAM_NUM 2 + +/* + * cmd used to register frame done callback, parameter is + * struct isp4sd_register_framedone_cb_param * + * when a image buffer is filled by ISP, ISP will call the registered callback. + * callback func prototype is isp4sd_framedone_cb, cb_ctx can be anything + * provided by caller which will be provided back as the first parameter of the + * callback function. + * both cb_func and cb_ctx are provide by caller, set cb_func to NULL to + * unregister the callback + */ + +/* used to indicate the ISP status*/ +enum isp4sd_status { + ISP4SD_STATUS_PWR_OFF, + ISP4SD_STATUS_PWR_ON, + ISP4SD_STATUS_FW_RUNNING, + ISP4SD_STATUS_MAX +}; + +/*used to indicate the status of sensor, output stream */ +enum isp4sd_start_status { + ISP4SD_START_STATUS_NOT_START, + ISP4SD_START_STATUS_STARTED, + ISP4SD_START_STATUS_START_FAIL, +}; + +struct isp4sd_img_buf_node { + struct list_head node; + struct isp4if_img_buf_info buf_info; +}; + +/* this is isp output after processing bayer raw input from sensor */ +struct isp4sd_output_info { + enum isp4sd_start_status start_status; + u32 image_size; +}; + +/* This struct represents the sensor info which is input or source of ISP, + * meta_info_buf is the buffer store the fw to driver metainfo response + * status is the sensor status + * output_info is the isp output info after ISP processing the sensor input, + * start_stream_cmd_sent mean if CMD_ID_START_STREAM has sent to fw. + * buf_sent_cnt is buffer count app has sent to receive the images + */ +struct isp4sd_sensor_info { + struct isp4if_gpu_mem_info * + meta_info_buf[ISP4IF_MAX_STREAM_META_BUF_COUNT]; + struct isp4sd_output_info output_info; + enum isp4sd_start_status status; + bool start_stream_cmd_sent; + u32 buf_sent_cnt; +}; + +/* + * Thread created by driver to receive fw response + * thread will be wakeup by fw to driver response interrupt + */ +struct isp4sd_thread_handler { + struct task_struct *thread; + struct mutex mutex; /* mutex */ + wait_queue_head_t waitq; + int wq_cond; +}; + +struct isp4_subdev_thread_param { + u32 idx; + struct isp4_subdev *isp_subdev; +}; + +struct isp4_subdev { + struct v4l2_subdev sdev; + struct isp4_interface ispif; + + /* + * sdev_pad[0] is sink pad connected to sensor + * sdev_pad[0] is sink pad connected to sensor + * sdev_pad[1] is sourc pad connected v4l2 video device + */ + struct media_pad sdev_pad[2]; + + enum isp4sd_status isp_status; + struct mutex ops_mutex; /* ops_mutex */ + + /* Used to store fw cmds sent to FW whose response driver needs + * to wait for + */ + struct isp4sd_thread_handler + fw_resp_thread[ISP4SD_MAX_FW_RESP_STREAM_NUM]; + + u32 host2fw_seq_num; + + struct isp4sd_sensor_info sensor_info; + + /* gpio descriptor */ + struct gpio_desc *enable_gpio; + struct device *dev; + void *amdgpu_dev; + void __iomem *mmio; + struct isp4_subdev_thread_param + isp_resp_para[ISP4SD_MAX_FW_RESP_STREAM_NUM]; +#ifdef CONFIG_DEBUG_FS + struct dentry *debugfs_dir; + bool enable_fw_log; + char *fw_log_output; +#endif + u32 phy_num_data_lanes; + u32 phy_id; + u64 phy_bit_rate; + + void __iomem *isp_phy_mmio; +}; + +int isp4sd_init(struct isp4_subdev *isp_subdev, + struct v4l2_device *v4l2_dev, + void *amdgpu_dev); +void isp4sd_deinit(struct isp4_subdev *isp_subdev); + +#endif From patchwork Sun Jun 8 14:49:13 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Du, Bin" X-Patchwork-Id: 894859 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2069.outbound.protection.outlook.com [40.107.243.69]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 34300253346; Sun, 8 Jun 2025 14:50:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.243.69 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749394214; cv=fail; b=EyWGlpZ3kkf15QdDUNXnk8MuGNWf30Q00BHAzZV+KgrR14UXbOd3BD0Pf1i2A+/s2Z5Ue20cKAzi/GyoVAcyDuEDunh2oiskKLrFEu2fDnEE/WWXz35ZuvQSsuVv/ZL+hU+T/0HIa6JjOHzNAIyQwNjc8Hs2EvPN0DkdJfcOQg8= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749394214; c=relaxed/simple; bh=W4wsFsOqy3u280H+qSYb0rug4hVC7JqCdjmR8Z4xRDM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=tzAJEVdNuXsWWlvv/cC0TmNAsysuae18urcHwoU1NQqqC7kACqbfaoh5HYhbISSxhX1qH5gqTX8TehIWfTf1G6fM4lDpLN3HM4cJZWLyq0HCd2Iq5zBMmaMYBMjP0NaLwLLCY8yIdnVJ49sMvnLKNEgqEkbzKI+dUn9o/zj8rwo= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com; spf=fail smtp.mailfrom=amd.com; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b=Xl8tC4EV; arc=fail smtp.client-ip=40.107.243.69 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=amd.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="Xl8tC4EV" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=v61zaKxQzAZtV3Yt6KmCX0EsOUSqcezdzYJgpKBEl8dWUoT32XAGefZcVS7aq7wJ0K0X/GwD3tpDbrUKfewnDRFzeSTc173MR6RNEf1dh10xtNB4B3bzT+R7NC4hpkyIZIazi/eVsrbVHeyt+8Sef8nTVYi96Nfz0mkSLCHqk4dothkvEmx6NNihBHeJg1TIXcStvZbr/pbRFtWTny/6bDc3WSHLUWvmL9aBynMlNUkel31RDhXeDCcSLIu91OdZ4LWnLXGnROvHM7qUsgTW+yTGy/ActCUkyS19DRjsEojH6Q1vC6wgKeLT9FaP5pkXULYFTOb8F8+8nSd5eo3IwA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Jj8neAIhr/I6GR5Mv8vYpC+xdi8nYjXErV3Gbokybhk=; b=RbpQ8d9/wNQZc3dZtBz9welkwtCqevOWDCJzeEHWBsIG/Nae1OdGm8bBIHnMGTH/TbwdrsEl6qou4bZFYxQnvJZkKpCY4StRYQenVwhVCHu4Gpf8GoZPC/SHj8RYTbikhqLOlVdwpC+inwG/UJU0NeYz0ZjdLpCURO3d1jOewXrOaZ0lpCj5vPP1KMpmOnY5LCjk+ylgpNT8Hi+3C7oyOZEfj+wVD1Q/qlUuWsqRlTeUtzJsr+Rf6hD6hJTNsLH/j3/mCElc6bL1BBN7AzCpR4HwvdhBLqn74gBZmFEcSviRFKpMf3zrB/ktOOLMUr116DKQxAn4EZrIINkF7kuIlA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Jj8neAIhr/I6GR5Mv8vYpC+xdi8nYjXErV3Gbokybhk=; b=Xl8tC4EVvtzUxwBhixFZruQ0cQZX45sq5lQWg1UvJveK/30IueBF5FXCTgV3gDe3G8dEWi1XSjI2fZdWkTQP6WPIDjzitseOZJf457JazvMFfcZmxbWMINGPSp/zLAMwpFAVBxXmuaa8yP57gL6OKAhOxsHqNTZw8T5E1yAyFjM= Received: from MW4PR03CA0063.namprd03.prod.outlook.com (2603:10b6:303:b6::8) by BL3PR12MB6620.namprd12.prod.outlook.com (2603:10b6:208:38f::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8792.35; Sun, 8 Jun 2025 14:50:04 +0000 Received: from SJ5PEPF000001D7.namprd05.prod.outlook.com (2603:10b6:303:b6:cafe::c3) by MW4PR03CA0063.outlook.office365.com (2603:10b6:303:b6::8) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8769.19 via Frontend Transport; Sun, 8 Jun 2025 14:50:02 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SJ5PEPF000001D7.mail.protection.outlook.com (10.167.242.59) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8835.15 via Frontend Transport; Sun, 8 Jun 2025 14:50:02 +0000 Received: from 555e2b870847.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Sun, 8 Jun 2025 09:49:58 -0500 From: Bin Du To: , , , , , , , CC: , , , , , , , , "Bin Du" Subject: [PATCH v1 6/9] media: platform: amd: isp4 video node and buffers handling added Date: Sun, 8 Jun 2025 22:49:13 +0800 Message-ID: <20250608144916.222835-7-Bin.Du@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250608144916.222835-1-Bin.Du@amd.com> References: <20250608144916.222835-1-Bin.Du@amd.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001D7:EE_|BL3PR12MB6620:EE_ X-MS-Office365-Filtering-Correlation-Id: e9e57a16-9337-4dde-b615-08dda69bbffc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|36860700013|82310400026|376014; X-Microsoft-Antispam-Message-Info: bqo08ir18XBhjf7XuD96VReCuoIr9kZYHx13pNqVTyPCCOEaZ8vU6tLtmhzXUYP6pzFZ0ti3jzBt6sF/Og0A6DMh3R1JNaDpS07RNkTCC9eQd0vSo5QgbWzoGQeEKSUUYz/WpY+gpexzKaUFjoV/kmChMKkw9fkgSqiip8QkIs4FzRgDKH+rWy+DVtYUePcSTRQT6H+J5ZGXbnUmB9q+taGLY8ABAvLrEPfZVha0UNE7sUHTQrXIppvnSYLCI7ttIFSaqD2EObqSDCNAdB66nthe43GduEqrz8hjxdS3g0IctWX8pQ753ErVVz6c28psA8It75fA0xVoJP4YxuevOhbm5SCAWhn0QQZbChW4TyE3R/5K/9O/XEJULshNLDa5cgMeWLy/lgM4DELoyWm8vGqXkJ9Je8hYc9MNg81fr1oErOVF53Ye+gEVLaIh++mRgemXa+OWRfW4LwyH4cmWb00EJqbX3tb87EhbQgnA5dksXaXrUi7uzIF6GZDTcvTmAMCBWoo7sHghuhSkgkupRBM28FZoCObU8lDKjdWeYDiTKDOMMI15XtJ7W3Wh1+NzZlvWFhKMtuXO38ytTIoQwERq+d3dtmEgrdcGrKSiRHt7Zd4SAWRkEE5ZJZVuFyMW0LAudrUzevobWqYpr1IjOxM0TFEcr/NxqP5D5TpEvcnGcn+kROFrXpHSS8AVWs5AjI7tWKfjKHBesJhJEcn2MZye3kHo08tf43k4r5XhEBNIFox06kYfo8OkDhf51u1neK9xmNCtu/bXxgSNex8YtRsIb350ldE777OcoeTnSMMcf/AXNj8ffklfdzpJOsQ0AWW9OlXPawsb/skKklq/p/Ne8C0JQ+QtM/DSHKlcWVXUB5VxYNcHhXyV4Vc6/hik9MvMh74ulfk9KLk1/LOofWy5URtgWBRZ6YUjUH+aIdMltXoGrlZxWdhs4MPXcgbJIQaYr2dF8b3vZ8yTl40G2jIdDUlw/6hXeF3K+l7e1iHMhIXEbe5NZWnsvM2EYAntaQ4KKpi7+SNjaAXmdP3xOduLF8MLl+IzjSvx9D5ynU/jhPQjqwvsjO9jDzIw2Vp+w6CZEU6cQkBq+VyayHfgoa9mGRx43YaKc2XvOwiPb6kOn0XCeNush4G5v9rofa9m35Y76BjVYmQBL4RlzrTZ8lTd4uqaTwYmhBVcv+eohvdS9gkY5XXf4w4gRiXuyK9xRaZGbRyaaWjJQobRdm2UEyqsPyZpkJOioXOPkBPTujV0EIqzash7/jmRb/LELJtREGsvSGIJapiMM4hFnsFiHii2JchuRDUm4/kdLio/PXzg3Ly18+Mmr/+j3yKFOVNGpoNGTyFAzGNJQcmrMTyRpQ9wN/FWnEPfTunWXDUtA4prD7rZDU3QyJ4FTXA27rNVUvegnL1YNFxutuvfg+VzZB6nU01kAYTLdS0ZMtNFC4UE4SRqfg0z0BhKoQxraJG9IzytvkAASi/oKeu+LQcxAJazyE3G44Jv+UTKNDgn/ZFwlgcDyjivFXUND2sfkHgU X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(1800799024)(36860700013)(82310400026)(376014); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jun 2025 14:50:02.6377 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e9e57a16-9337-4dde-b615-08dda69bbffc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001D7.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6620 Isp video implements v4l2 video interface and supports NV12 and YUYV. It manages buffers, pipeline power and state. Signed-off-by: Bin Du Signed-off-by: Svetoslav Stoilov Change-Id: I42178ebe877dd1901bd801a23d8f825827282e56 --- drivers/media/platform/amd/isp4/Makefile | 1 + drivers/media/platform/amd/isp4/isp4.c | 13 +- drivers/media/platform/amd/isp4/isp4_subdev.c | 128 +- drivers/media/platform/amd/isp4/isp4_subdev.h | 2 + drivers/media/platform/amd/isp4/isp4_video.c | 1457 +++++++++++++++++ drivers/media/platform/amd/isp4/isp4_video.h | 93 ++ 6 files changed, 1684 insertions(+), 10 deletions(-) create mode 100644 drivers/media/platform/amd/isp4/isp4_video.c create mode 100644 drivers/media/platform/amd/isp4/isp4_video.h diff --git a/drivers/media/platform/amd/isp4/Makefile b/drivers/media/platform/amd/isp4/Makefile index d2f1523ad07a..a68f18fe79b4 100644 --- a/drivers/media/platform/amd/isp4/Makefile +++ b/drivers/media/platform/amd/isp4/Makefile @@ -7,6 +7,7 @@ amd_capture-objs := isp4_subdev.o \ isp4_phy.o \ isp4_interface.o \ isp4.o \ + isp4_video.o \ isp4_hw.o \ ccflags-y += -I$(srctree)/drivers/media/platform/amd/isp4 diff --git a/drivers/media/platform/amd/isp4/isp4.c b/drivers/media/platform/amd/isp4/isp4.c index 2dc7ea3b02e8..3beb35293504 100644 --- a/drivers/media/platform/amd/isp4/isp4.c +++ b/drivers/media/platform/amd/isp4/isp4.c @@ -310,6 +310,16 @@ static int isp4_capture_probe(struct platform_device *pdev) goto err_isp4_deinit; } + ret = media_create_pad_link(&isp_dev->isp_sdev.sdev.entity, + 1, &isp_dev->isp_sdev.isp_vdev.vdev.entity, + 0, + MEDIA_LNK_FL_ENABLED | + MEDIA_LNK_FL_IMMUTABLE); + if (ret) { + dev_err(dev, "fail to create pad link %d\n", ret); + goto err_unreg_video_dev_notifier; + } + platform_set_drvdata(pdev, isp_dev); pm_runtime_set_suspended(dev); @@ -317,9 +327,10 @@ static int isp4_capture_probe(struct platform_device *pdev) return 0; -err_isp4_deinit: +err_unreg_video_dev_notifier: v4l2_async_nf_unregister(&isp_dev->notifier); v4l2_async_nf_cleanup(&isp_dev->notifier); +err_isp4_deinit: isp4sd_deinit(&isp_dev->isp_sdev); err_unreg_v4l2: v4l2_device_unregister(&isp_dev->v4l2_dev); diff --git a/drivers/media/platform/amd/isp4/isp4_subdev.c b/drivers/media/platform/amd/isp4/isp4_subdev.c index 4b28fbd6867b..816fa3a127f5 100644 --- a/drivers/media/platform/amd/isp4/isp4_subdev.c +++ b/drivers/media/platform/amd/isp4/isp4_subdev.c @@ -167,6 +167,24 @@ static int isp4sd_enum_mbus_code(struct v4l2_subdev *isp_subdev, return 0; } +static int isp4sd_enum_frame_size(struct v4l2_subdev *isp_subdev, + struct v4l2_subdev_state *state, + struct v4l2_subdev_frame_size_enum *fse) +{ + struct v4l2_frmsize_discrete min, max; + + if (fse->index >= ARRAY_SIZE(isp4sd_image_formats)) + return -EINVAL; + + isp4vid_frmsize_range(&min, &max); + fse->min_width = min.width; + fse->max_width = max.width; + fse->min_height = min.height; + fse->max_height = max.height; + + return 0; +} + static bool isp4sd_get_str_out_prop(struct isp4_subdev *isp_subdev, struct isp4fw_image_prop *out_prop, struct v4l2_subdev_state *state, u32 pad) @@ -509,17 +527,14 @@ isp4sd_get_meta_by_mc(struct isp4_subdev *isp_subdev, static struct isp4if_img_buf_node * isp4sd_preview_done(struct isp4_subdev *isp_subdev, - struct isp4fw_meta_info *meta) + struct isp4fw_meta_info *meta, + struct isp4vid_framedone_param *pcb) { struct isp4_interface *ispif = &isp_subdev->ispif; struct isp4if_img_buf_node *prev = NULL; struct device *dev = isp_subdev->dev; - if (!meta) { - dev_err(dev, "fail bad param for preview done\n"); - return prev; - } - + pcb->preview.status = ISP4VID_BUF_DONE_STATUS_ABSENT; if (meta->preview.enabled && (meta->preview.status == BUFFER_STATUS_SKIPPED || meta->preview.status == BUFFER_STATUS_DONE || @@ -529,9 +544,12 @@ isp4sd_preview_done(struct isp4_subdev *isp_subdev, str_info = &isp_subdev->sensor_info.output_info; prev = isp4if_dequeue_buffer(ispif); - if (!prev) + if (!prev) { dev_err(dev, "fail null prev buf\n"); - + } else { + pcb->preview.buf = prev->buf_info; + pcb->preview.status = ISP4VID_BUF_DONE_STATUS_SUCCESS; + } } else if (meta->preview.enabled) { dev_err(dev, "fail bad preview status %u\n", meta->preview.status); @@ -578,6 +596,7 @@ static void isp4sd_fw_resp_frame_done(struct isp4_subdev *isp_subdev, enum isp4if_stream_id stream_id, struct isp4fw_resp_param_package *para) { + struct isp4vid_framedone_param pcb = {0}; struct isp4if_img_buf_node *prev = NULL; struct device *dev = isp_subdev->dev; struct isp4fw_meta_info *meta; @@ -590,12 +609,17 @@ static void isp4sd_fw_resp_frame_done(struct isp4_subdev *isp_subdev, return; } + pcb.poc = meta->poc; + pcb.cam_id = 0; + dev_dbg(dev, "ts:%llu,streamId:%d,poc:%u,preview_en:%u,(%i)\n", ktime_get_ns(), stream_id, meta->poc, meta->preview.enabled, meta->preview.status); - prev = isp4sd_preview_done(isp_subdev, meta); + prev = isp4sd_preview_done(isp_subdev, meta, &pcb); + if (pcb.preview.status != ISP4VID_BUF_DONE_STATUS_ABSENT) + isp4vid_notify(&isp_subdev->isp_vdev, &pcb); isp4if_dealloc_buffer_node(prev); @@ -974,6 +998,84 @@ static int isp4sd_start_stream(struct isp4_subdev *isp_subdev, return ret; } +static int ispsd4_subdev_link_validate(struct media_link *link) +{ + return 0; +} + +static const struct media_entity_operations isp4sd_subdev_ent_ops = { + .link_validate = ispsd4_subdev_link_validate, +}; + +static int isp4sd_ioc_send_img_buf(struct isp4vid_dev *sd, + struct isp4if_img_buf_info *buf_info) +{ + struct isp4_subdev *isp_subdev = to_isp4_vdev(sd); + struct isp4_interface *ispif = &isp_subdev->ispif; + struct isp4if_img_buf_node *buf_node = NULL; + struct device *dev = isp_subdev->dev; + int ret = -EINVAL; + + mutex_lock(&isp_subdev->ops_mutex); + /* TODO: remove isp_status */ + if (ispif->status != ISP4IF_STATUS_FW_RUNNING) { + dev_err(dev, "fail send img buf for bad fsm %d\n", + ispif->status); + mutex_unlock(&isp_subdev->ops_mutex); + return -EINVAL; + } + + buf_node = isp4if_alloc_buffer_node(buf_info); + if (!buf_node) { + dev_err(dev, "fail alloc sys img buf info node\n"); + ret = -ENOMEM; + goto unlock_and_return; + } + + ret = isp4if_queue_buffer(ispif, buf_node); + if (ret) { + dev_err(dev, "fail to queue image buf, %d\n", ret); + goto error_release_buf_node; + } + + if (!isp_subdev->sensor_info.start_stream_cmd_sent) { + isp_subdev->sensor_info.buf_sent_cnt++; + + if (isp_subdev->sensor_info.buf_sent_cnt >= + ISP4SD_MIN_BUF_CNT_BEF_START_STREAM) { + ret = isp4if_send_command(ispif, CMD_ID_START_STREAM, + NULL, 0); + + if (ret) { + dev_err(dev, "fail to START_STREAM"); + goto error_release_buf_node; + } + isp_subdev->sensor_info.start_stream_cmd_sent = true; + isp_subdev->sensor_info.output_info.start_status = + ISP4SD_START_STATUS_STARTED; + isp_subdev->sensor_info.status = + ISP4SD_START_STATUS_STARTED; + } else { + dev_dbg(dev, + "no send start,required %u,buf sent %u\n", + ISP4SD_MIN_BUF_CNT_BEF_START_STREAM, + isp_subdev->sensor_info.buf_sent_cnt); + } + } + + mutex_unlock(&isp_subdev->ops_mutex); + + return 0; + +error_release_buf_node: + isp4if_dealloc_buffer_node(buf_node); + +unlock_and_return: + mutex_unlock(&isp_subdev->ops_mutex); + + return ret; +} + static int isp4sd_subdev_pre_streamon(struct v4l2_subdev *sd, u32 flags) { struct isp4_subdev *isp_subdev = to_isp4_subdev(sd); @@ -1098,6 +1200,7 @@ static int isp4sd_disable_streams(struct v4l2_subdev *sd, static const struct v4l2_subdev_pad_ops isp4sd_pad_ops = { .enum_mbus_code = isp4sd_enum_mbus_code, + .enum_frame_size = isp4sd_enum_frame_size, .get_fmt = v4l2_subdev_get_fmt, .set_fmt = isp4sd_set_pad_format, .enable_streams = isp4sd_enable_streams, @@ -1123,6 +1226,10 @@ static const struct media_entity_operations isp4sd_sdev_ent_ops = { .link_validate = isp4sd_sdev_link_validate, }; +static const struct isp4vid_ops isp4sd_isp4vid_ops = { + .send_buffer = isp4sd_ioc_send_img_buf, +}; + int isp4sd_init(struct isp4_subdev *isp_subdev, struct v4l2_device *v4l2_dev, void *amdgpu_dev) @@ -1188,6 +1295,8 @@ int isp4sd_init(struct isp4_subdev *isp_subdev, isp_subdev->host2fw_seq_num = 1; ispif->status = ISP4IF_STATUS_PWR_OFF; + ret = isp4vid_dev_init(&isp_subdev->isp_vdev, &isp_subdev->sdev, + &isp4sd_isp4vid_ops, amdgpu_dev); if (ret) goto err_media_clean_up; return ret; @@ -1203,6 +1312,7 @@ void isp4sd_deinit(struct isp4_subdev *isp_subdev) struct isp4sd_output_info *output_info; output_info = &isp_subdev->sensor_info.output_info; + isp4vid_dev_deinit(&isp_subdev->isp_vdev); media_entity_cleanup(&isp_subdev->sdev.entity); isp4if_deinit(ispif); diff --git a/drivers/media/platform/amd/isp4/isp4_subdev.h b/drivers/media/platform/amd/isp4/isp4_subdev.h index 99ec914a95ce..e04811dd2591 100644 --- a/drivers/media/platform/amd/isp4/isp4_subdev.h +++ b/drivers/media/platform/amd/isp4/isp4_subdev.h @@ -18,6 +18,7 @@ #include "isp4_fw_cmd_resp.h" #include "isp4_hw_reg.h" #include "isp4_interface.h" +#include "isp4_video.h" /* * one is for none sesnor specefic response which is not used now @@ -97,6 +98,7 @@ struct isp4_subdev_thread_param { struct isp4_subdev { struct v4l2_subdev sdev; struct isp4_interface ispif; + struct isp4vid_dev isp_vdev; /* * sdev_pad[0] is sink pad connected to sensor diff --git a/drivers/media/platform/amd/isp4/isp4_video.c b/drivers/media/platform/amd/isp4/isp4_video.c new file mode 100644 index 000000000000..39f0b6e49713 --- /dev/null +++ b/drivers/media/platform/amd/isp4/isp4_video.c @@ -0,0 +1,1457 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2025 Advanced Micro Devices, Inc. + */ + +#include +#include +#include +#include + +#include "amdgpu_object.h" +#include "isp4_interface.h" +#include "isp4_subdev.h" +#include "isp4_video.h" + +#define ISP4VID_ISP_DRV_NAME "amd_isp_capture" +#define ISP4VID_VIDEO_BUF_NUM 5 +#define ISP4VID_MAX_PREVIEW_FPS 30 +#define ISP4VID_DEFAULT_FMT isp4vid_formats[0] + +#define ISP4VID_PAD_VIDEO_OUTPUT 1 + +/* timeperframe default */ +#define ISP4VID_ISP_TPF_DEFAULT isp4vid_tpfs[0] + +/* amdisp buffer for vb2 operations */ +struct isp4vid_vb2_buf { + struct device *dev; + void *vaddr; + struct frame_vector *vec; + enum dma_data_direction dma_dir; + unsigned long size; + refcount_t refcount; + struct dma_buf *dbuf; + void *bo; + u64 gpu_addr; + struct vb2_vmarea_handler handler; + bool is_expbuf; +}; + +static int isp4vid_vb2_mmap(void *buf_priv, struct vm_area_struct *vma); + +static void isp4vid_vb2_put(void *buf_priv); + +static const char *isp4vid_video_dev_name = "Preview"; + +/* Sizes must be in increasing order */ +static const struct v4l2_frmsize_discrete isp4vid_frmsize[] = { + {640, 360}, + {640, 480}, + {1280, 720}, + {1280, 960}, + {1920, 1080}, + {1920, 1440}, + {2560, 1440}, + {2880, 1620}, + {2880, 1624}, + {2888, 1808}, +}; + +static const u32 isp4vid_formats[] = { + V4L2_PIX_FMT_NV12, + V4L2_PIX_FMT_YUYV +}; + +/* timeperframe list */ +static const struct v4l2_fract isp4vid_tpfs[] = { + {.numerator = 1, .denominator = ISP4VID_MAX_PREVIEW_FPS} +}; + +static void +isp4vid_handle_frame_done(struct isp4vid_dev *isp_vdev, + const struct isp4if_img_buf_info *img_buf, + bool done_suc) +{ + struct isp4vid_capture_buffer *isp4vid_buf; + enum vb2_buffer_state state; + void *vbuf; + + mutex_lock(&isp_vdev->buf_list_lock); + + /* Get the first entry of the list */ + isp4vid_buf = list_first_entry_or_null(&isp_vdev->buf_list, + typeof(*isp4vid_buf), list); + if (!isp4vid_buf) { + mutex_unlock(&isp_vdev->buf_list_lock); + return; + } + + vbuf = vb2_plane_vaddr(&isp4vid_buf->vb2.vb2_buf, 0); + + if (vbuf != img_buf->planes[0].sys_addr) { + dev_err(isp_vdev->dev, "Invalid vbuf"); + mutex_unlock(&isp_vdev->buf_list_lock); + return; + } + + /* Remove this entry from the list */ + list_del(&isp4vid_buf->list); + + mutex_unlock(&isp_vdev->buf_list_lock); + + /* Fill the buffer */ + isp4vid_buf->vb2.vb2_buf.timestamp = ktime_get_ns(); + isp4vid_buf->vb2.sequence = isp_vdev->sequence++; + isp4vid_buf->vb2.field = V4L2_FIELD_ANY; + + /* at most 2 planes */ + vb2_set_plane_payload(&isp4vid_buf->vb2.vb2_buf, + 0, isp_vdev->format.sizeimage); + + state = done_suc ? VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR; + vb2_buffer_done(&isp4vid_buf->vb2.vb2_buf, state); + + dev_dbg(isp_vdev->dev, "call vb2_buffer_done(size=%u)\n", + isp_vdev->format.sizeimage); +} + +s32 isp4vid_notify(void *cb_ctx, struct isp4vid_framedone_param *evt_param) +{ + struct isp4vid_dev *isp4vid_vdev = cb_ctx; + + if (evt_param->preview.status != ISP4VID_BUF_DONE_STATUS_ABSENT) { + bool suc; + + suc = (evt_param->preview.status == + ISP4VID_BUF_DONE_STATUS_SUCCESS); + isp4vid_handle_frame_done(isp4vid_vdev, + &evt_param->preview.buf, + suc); + } + + return 0; +} + +void isp4vid_frmsize_range(struct v4l2_frmsize_discrete *min, + struct v4l2_frmsize_discrete *max) +{ + if (!min || !max) { + pr_err("fail, null param\n"); + return; + } + + min->width = isp4vid_frmsize[0].width; + min->height = isp4vid_frmsize[0].height; + max->width = isp4vid_frmsize[ARRAY_SIZE(isp4vid_frmsize) - 1].width; + max->height = isp4vid_frmsize[ARRAY_SIZE(isp4vid_frmsize) - 1].height; +} + +static unsigned int isp4vid_vb2_num_users(void *buf_priv) +{ + struct isp4vid_vb2_buf *buf = buf_priv; + + if (!buf) { + pr_err("fail null buf handle\n"); + return 0; + } + return refcount_read(&buf->refcount); +} + +static int isp4vid_vb2_mmap(void *buf_priv, struct vm_area_struct *vma) +{ + struct isp4vid_vb2_buf *buf = buf_priv; + int ret; + + if (!buf) { + pr_err("fail no memory to map\n"); + return -EINVAL; + } + + ret = remap_vmalloc_range(vma, buf->vaddr, 0); + if (ret) { + dev_err(buf->dev, "fail remap vmalloc mem, %d\n", ret); + return ret; + } + + /* + * Make sure that vm_areas for 2 buffers won't be merged together + */ + vm_flags_set(vma, VM_DONTEXPAND); + + dev_dbg(buf->dev, "mmap isp user bo 0x%llx size %ld refcount %d\n", + buf->gpu_addr, buf->size, buf->refcount.refs.counter); + + return 0; +} + +static void *isp4vid_vb2_vaddr(struct vb2_buffer *vb, void *buf_priv) +{ + struct isp4vid_vb2_buf *buf = buf_priv; + + if (!buf) { + pr_err("fail for empty buf\n"); + return NULL; + } + + if (!buf->vaddr) { + dev_err(buf->dev, + "fail for buf vaddr is null\n"); + return NULL; + } + return buf->vaddr; +} + +static void isp4vid_vb2_detach_dmabuf(void *mem_priv) +{ + struct isp4vid_vb2_buf *buf = mem_priv; + + if (!buf) { + pr_err("fail invalid buf handle\n"); + return; + } + + struct iosys_map map = IOSYS_MAP_INIT_VADDR(buf->vaddr); + + dev_dbg(buf->dev, "detach dmabuf of isp user bo 0x%llx size %ld", + buf->gpu_addr, buf->size); + + if (buf->vaddr) + dma_buf_vunmap_unlocked(buf->dbuf, &map); + + // put dmabuf for exported ones + dma_buf_put(buf->dbuf); + + kfree(buf); +} + +static void *isp4vid_vb2_attach_dmabuf(struct vb2_buffer *vb, + struct device *dev, + struct dma_buf *dbuf, + unsigned long size) +{ + struct isp4vid_vb2_buf *buf; + + if (dbuf->size < size) { + dev_err(dev, "Invalid dmabuf size %ld %ld", dbuf->size, size); + return ERR_PTR(-EFAULT); + } + + buf = kzalloc(sizeof(*buf), GFP_KERNEL); + if (!buf) + return ERR_PTR(-ENOMEM); + + struct isp4vid_vb2_buf *dbg_buf = (struct isp4vid_vb2_buf *)dbuf->priv; + + buf->dev = dev; + buf->dbuf = dbuf; + buf->dma_dir = vb->vb2_queue->dma_dir; + buf->size = size; + + dev_dbg(dev, "attach dmabuf of isp user bo 0x%llx size %ld", + dbg_buf->gpu_addr, dbg_buf->size); + + return buf; +} + +static void isp4vid_vb2_unmap_dmabuf(void *mem_priv) +{ + struct isp4vid_vb2_buf *buf = mem_priv; + + if (!buf) { + pr_err("fail invalid buf handle\n"); + return; + } + + struct iosys_map map = IOSYS_MAP_INIT_VADDR(buf->vaddr); + + dev_dbg(buf->dev, "unmap dmabuf of isp user bo 0x%llx size %ld", + buf->gpu_addr, buf->size); + + dma_buf_vunmap_unlocked(buf->dbuf, &map); + buf->vaddr = NULL; +} + +static int isp4vid_vb2_map_dmabuf(void *mem_priv) +{ + struct isp4vid_vb2_buf *mmap_buf = NULL; + struct isp4vid_vb2_buf *buf = mem_priv; + struct iosys_map map; + int ret; + + memset(&map, 0x0, sizeof(map)); + + if (!buf) { + pr_err("fail invalid buf handle\n"); + return -EINVAL; + } + + ret = dma_buf_vmap_unlocked(buf->dbuf, &map); + if (ret) { + dev_err(buf->dev, "vmap_unlocked fail"); + return -EFAULT; + } + buf->vaddr = map.vaddr; + + mmap_buf = (struct isp4vid_vb2_buf *)buf->dbuf->priv; + buf->gpu_addr = mmap_buf->gpu_addr; + + dev_dbg(buf->dev, "map dmabuf of isp user bo 0x%llx size %ld", + buf->gpu_addr, buf->size); + + return 0; +} + +#ifdef CONFIG_HAS_DMA +struct isp4vid_vb2_amdgpu_attachment { + struct sg_table sgt; + enum dma_data_direction dma_dir; +}; + +static int isp4vid_vb2_dmabuf_ops_attach(struct dma_buf *dbuf, + struct dma_buf_attachment *dbuf_attach) +{ + struct isp4vid_vb2_buf *buf = dbuf->priv; + int num_pages = PAGE_ALIGN(buf->size) / PAGE_SIZE; + struct isp4vid_vb2_amdgpu_attachment *attach; + void *vaddr = buf->vaddr; + struct scatterlist *sg; + struct sg_table *sgt; + int ret; + int i; + + attach = kzalloc(sizeof(*attach), GFP_KERNEL); + if (!attach) + return -ENOMEM; + + sgt = &attach->sgt; + ret = sg_alloc_table(sgt, num_pages, GFP_KERNEL); + if (ret) { + kfree(attach); + return ret; + } + for_each_sgtable_sg(sgt, sg, i) { + struct page *page = vmalloc_to_page(vaddr); + + if (!page) { + sg_free_table(sgt); + kfree(attach); + return -ENOMEM; + } + sg_set_page(sg, page, PAGE_SIZE, 0); + vaddr = ((char *)vaddr) + PAGE_SIZE; + } + + attach->dma_dir = DMA_NONE; + dbuf_attach->priv = attach; + + return 0; +} + +static void +isp4vid_vb2_dmabuf_ops_detach(struct dma_buf *dbuf, + struct dma_buf_attachment *dbuf_attach) +{ + struct isp4vid_vb2_amdgpu_attachment *attach = dbuf_attach->priv; + struct sg_table *sgt; + + if (!attach) { + pr_err("fail invalid attach handler\n"); + return; + } + + sgt = &attach->sgt; + + /* release the scatterlist cache */ + if (attach->dma_dir != DMA_NONE) + dma_unmap_sgtable(dbuf_attach->dev, sgt, attach->dma_dir, 0); + sg_free_table(sgt); + kfree(attach); + dbuf_attach->priv = NULL; +} + +static struct sg_table +*isp4vid_vb2_dmabuf_ops_map(struct dma_buf_attachment *dbuf_attach, + enum dma_data_direction dma_dir) +{ + struct isp4vid_vb2_amdgpu_attachment *attach = dbuf_attach->priv; + struct sg_table *sgt; + + sgt = &attach->sgt; + /* return previously mapped sg table */ + if (attach->dma_dir == dma_dir) + return sgt; + + /* release any previous cache */ + if (attach->dma_dir != DMA_NONE) { + dma_unmap_sgtable(dbuf_attach->dev, sgt, attach->dma_dir, 0); + attach->dma_dir = DMA_NONE; + } + + /* mapping to the client with new direction */ + if (dma_map_sgtable(dbuf_attach->dev, sgt, dma_dir, 0)) { + dev_err(dbuf_attach->dev, "fail to map scatterlist"); + return ERR_PTR(-EIO); + } + + attach->dma_dir = dma_dir; + + return sgt; +} + +static void isp4vid_vb2_dmabuf_ops_unmap(struct dma_buf_attachment *dbuf_attach, + struct sg_table *sgt, + enum dma_data_direction dma_dir) +{ + /* nothing to be done here */ +} + +static int isp4vid_vb2_dmabuf_ops_vmap(struct dma_buf *dbuf, + struct iosys_map *map) +{ + struct isp4vid_vb2_buf *buf = dbuf->priv; + + iosys_map_set_vaddr(map, buf->vaddr); + + return 0; +} + +static void isp4vid_vb2_dmabuf_ops_release(struct dma_buf *dbuf) +{ + struct isp4vid_vb2_buf *buf = dbuf->priv; + + /* drop reference obtained in vb2_isp4vid_get_dmabuf */ + if (buf->is_expbuf) + isp4vid_vb2_put(dbuf->priv); + else + dev_dbg(buf->dev, "ignore buf release for implicit case"); +} + +static int isp4vid_vb2_dmabuf_ops_mmap(struct dma_buf *dbuf, + struct vm_area_struct *vma) +{ + return isp4vid_vb2_mmap(dbuf->priv, vma); +} + +static const struct dma_buf_ops vb2_isp4vid_dmabuf_ops = { + .attach = isp4vid_vb2_dmabuf_ops_attach, + .detach = isp4vid_vb2_dmabuf_ops_detach, + .map_dma_buf = isp4vid_vb2_dmabuf_ops_map, + .unmap_dma_buf = isp4vid_vb2_dmabuf_ops_unmap, + .vmap = isp4vid_vb2_dmabuf_ops_vmap, + .mmap = isp4vid_vb2_dmabuf_ops_mmap, + .release = isp4vid_vb2_dmabuf_ops_release, +}; + +static struct dma_buf *isp4vid_get_dmabuf(struct vb2_buffer *vb, + void *buf_priv, + unsigned long flags) +{ + struct isp4vid_vb2_buf *buf = buf_priv; + DEFINE_DMA_BUF_EXPORT_INFO(exp_info); + struct dma_buf *dbuf; + + if (!buf) { + pr_err("fail invalid buf handle\n"); + return ERR_PTR(-EINVAL); + } + + exp_info.ops = &vb2_isp4vid_dmabuf_ops; + exp_info.size = buf->size; + exp_info.flags = flags; + exp_info.priv = buf; + + if (WARN_ON(!buf->vaddr)) + return NULL; + + dbuf = dma_buf_export(&exp_info); + if (IS_ERR(dbuf)) + return NULL; + + return dbuf; +} + +static struct dma_buf *isp4vid_vb2_get_dmabuf(struct vb2_buffer *vb, + void *buf_priv, + unsigned long flags) +{ + struct isp4vid_vb2_buf *buf = buf_priv; + struct dma_buf *dbuf; + + if (buf->dbuf) { + dev_dbg(buf->dev, + "dbuf already created, reuse implicit dbuf\n"); + dbuf = buf->dbuf; + } else { + dbuf = isp4vid_get_dmabuf(vb, buf_priv, flags); + dev_dbg(buf->dev, "created new dbuf\n"); + } + buf->is_expbuf = true; + refcount_inc(&buf->refcount); + + dev_dbg(buf->dev, "buf exported, refcount %d\n", + buf->refcount.refs.counter); + + return dbuf; +} + +#endif + +static void isp4vid_vb2_put_userptr(void *buf_priv) +{ + struct isp4vid_vb2_buf *buf = buf_priv; + + if (!buf->vec->is_pfns) { + unsigned long vaddr = (unsigned long)buf->vaddr & PAGE_MASK; + unsigned int n_pages; + + n_pages = frame_vector_count(buf->vec); + if (vaddr) + vm_unmap_ram((void *)vaddr, n_pages); + if (buf->dma_dir == DMA_FROM_DEVICE || + buf->dma_dir == DMA_BIDIRECTIONAL) { + struct page **pages; + + pages = frame_vector_pages(buf->vec); + if (!WARN_ON_ONCE(IS_ERR(pages))) { + unsigned int i; + + for (i = 0; i < n_pages; i++) + set_page_dirty_lock(pages[i]); + } + } + } else { + iounmap((__force void __iomem *)buf->vaddr); + } + vb2_destroy_framevec(buf->vec); + kfree(buf); +} + +static void *isp4vid_vb2_get_userptr(struct vb2_buffer *vb, struct device *dev, + unsigned long vaddr, unsigned long size) +{ + struct isp4vid_vb2_buf *buf; + struct frame_vector *vec; + int n_pages, offset, i; + int ret = -ENOMEM; + + buf = kzalloc(sizeof(*buf), GFP_KERNEL); + if (!buf) + return ERR_PTR(-ENOMEM); + + buf->dev = dev; + buf->dma_dir = vb->vb2_queue->dma_dir; + offset = vaddr & ~PAGE_MASK; + buf->size = size; + vec = vb2_create_framevec(vaddr, size, + buf->dma_dir == DMA_FROM_DEVICE || + buf->dma_dir == DMA_BIDIRECTIONAL); + if (IS_ERR(vec)) { + kfree(buf); + return vec; + } + buf->vec = vec; + n_pages = frame_vector_count(vec); + if (frame_vector_to_pages(vec) < 0) { + unsigned long *nums = frame_vector_pfns(vec); + + /* + * We cannot get page pointers for these pfns. Check memory is + * physically contiguous and use direct mapping. + */ + for (i = 1; i < n_pages; i++) + if (nums[i - 1] + 1 != nums[i]) + goto err_destroy_free; + buf->vaddr = (__force void *) + ioremap(__pfn_to_phys(nums[0]), size + offset); + } else { + buf->vaddr = vm_map_ram(frame_vector_pages(vec), n_pages, -1); + } + + if (!buf->vaddr) + goto err_destroy_free; + + buf->vaddr = ((char *)buf->vaddr) + offset; + return buf; + +err_destroy_free: + vb2_destroy_framevec(vec); + kfree(buf); + return ERR_PTR(ret); +} + +static void isp4vid_vb2_put(void *buf_priv) +{ + struct isp4vid_vb2_buf *buf = (struct isp4vid_vb2_buf *)buf_priv; + struct amdgpu_bo *bo = (struct amdgpu_bo *)buf->bo; + + dev_dbg(buf->dev, + "release isp user bo 0x%llx size %ld refcount %d is_expbuf %d", + buf->gpu_addr, buf->size, + buf->refcount.refs.counter, buf->is_expbuf); + + if (refcount_dec_and_test(&buf->refcount)) { + amdgpu_bo_free_isp_user(bo); + + // put implicit dmabuf here, detach_dmabuf will not be called + if (!buf->is_expbuf) + dma_buf_put(buf->dbuf); + + vfree(buf->vaddr); + kfree(buf); + buf = NULL; + } else { + dev_warn(buf->dev, "ignore buffer free, refcount %u > 0", + refcount_read(&buf->refcount)); + } +} + +static void *isp4vid_vb2_alloc(struct vb2_buffer *vb, struct device *dev, + unsigned long size) +{ + struct isp4vid_dev *isp_vdev = vb2_get_drv_priv(vb->vb2_queue); + struct isp4vid_vb2_buf *buf = NULL; + struct amdgpu_bo *bo; + u64 gpu_addr; + u32 ret; + + buf = kzalloc(sizeof(*buf), GFP_KERNEL | vb->vb2_queue->gfp_flags); + if (!buf) + return ERR_PTR(-ENOMEM); + + buf->dev = dev; + buf->size = size; + buf->vaddr = vmalloc_user(buf->size); + if (!buf->vaddr) { + kfree(buf); + return ERR_PTR(-ENOMEM); + } + + buf->dma_dir = vb->vb2_queue->dma_dir; + buf->handler.refcount = &buf->refcount; + buf->handler.put = isp4vid_vb2_put; + buf->handler.arg = buf; + + // get implicit dmabuf + buf->dbuf = isp4vid_get_dmabuf(vb, buf, 0); + if (!buf->dbuf) { + dev_err(dev, "fail to get dmabuf\n"); + return ERR_PTR(-EINVAL); + } + + // create isp user BO and obtain gpu_addr + ret = amdgpu_bo_create_isp_user(isp_vdev->amdgpu_dev, buf->dbuf, + AMDGPU_GEM_DOMAIN_GTT, &bo, &gpu_addr); + if (ret) { + dev_err(dev, "fail to create BO\n"); + return ERR_PTR(-EINVAL); + } + + buf->bo = (void *)bo; + buf->gpu_addr = gpu_addr; + + refcount_set(&buf->refcount, 1); + + dev_dbg(dev, "allocated isp user bo 0x%llx size %ld refcount %d", + buf->gpu_addr, buf->size, buf->refcount.refs.counter); + + return buf; +} + +const struct vb2_mem_ops isp4vid_vb2_memops = { + .alloc = isp4vid_vb2_alloc, + .put = isp4vid_vb2_put, + .get_userptr = isp4vid_vb2_get_userptr, + .put_userptr = isp4vid_vb2_put_userptr, +#ifdef CONFIG_HAS_DMA + .get_dmabuf = isp4vid_vb2_get_dmabuf, +#endif + .map_dmabuf = isp4vid_vb2_map_dmabuf, + .unmap_dmabuf = isp4vid_vb2_unmap_dmabuf, + .attach_dmabuf = isp4vid_vb2_attach_dmabuf, + .detach_dmabuf = isp4vid_vb2_detach_dmabuf, + .vaddr = isp4vid_vb2_vaddr, + .mmap = isp4vid_vb2_mmap, + .num_users = isp4vid_vb2_num_users, +}; + +static const struct v4l2_pix_format isp4vid_fmt_default = { + .width = 1920, + .height = 1080, + .pixelformat = V4L2_PIX_FMT_NV12, + .field = V4L2_FIELD_NONE, + .colorspace = V4L2_COLORSPACE_SRGB, +}; + +static void isp4vid_capture_return_all_buffers(struct isp4vid_dev *isp_vdev, + enum vb2_buffer_state state) +{ + struct isp4vid_capture_buffer *vbuf, *node; + + mutex_lock(&isp_vdev->buf_list_lock); + + list_for_each_entry_safe(vbuf, node, &isp_vdev->buf_list, list) { + list_del(&vbuf->list); + vb2_buffer_done(&vbuf->vb2.vb2_buf, state); + } + mutex_unlock(&isp_vdev->buf_list_lock); + + dev_dbg(isp_vdev->dev, "call vb2_buffer_done(%d)\n", state); +} + +static int isp4vid_vdev_link_validate(struct media_link *link) +{ + return 0; +} + +static const struct media_entity_operations isp4vid_vdev_ent_ops = { + .link_validate = isp4vid_vdev_link_validate, +}; + +static const struct v4l2_file_operations isp4vid_vdev_fops = { + .owner = THIS_MODULE, + .open = v4l2_fh_open, + .release = vb2_fop_release, + .read = vb2_fop_read, + .poll = vb2_fop_poll, + .unlocked_ioctl = video_ioctl2, + .mmap = vb2_fop_mmap, +}; + +static int isp4vid_ioctl_querycap(struct file *file, void *fh, + struct v4l2_capability *cap) +{ + struct isp4vid_dev *isp_vdev = video_drvdata(file); + + strscpy(cap->driver, ISP4VID_ISP_DRV_NAME, sizeof(cap->driver)); + snprintf(cap->card, sizeof(cap->card), "%s", ISP4VID_ISP_DRV_NAME); + snprintf(cap->bus_info, sizeof(cap->bus_info), + "platform:%s", ISP4VID_ISP_DRV_NAME); + + cap->capabilities |= (V4L2_CAP_STREAMING | + V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_IO_MC); + + dev_dbg(isp_vdev->dev, "%s|capabilities=0x%X", + isp_vdev->vdev.name, cap->capabilities); + + return 0; +} + +static int isp4vid_g_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct isp4vid_dev *isp_vdev = video_drvdata(file); + + f->fmt.pix = isp_vdev->format; + + return 0; +} + +static int isp4vid_try_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct isp4vid_dev *isp_vdev = video_drvdata(file); + struct v4l2_pix_format *format = &f->fmt.pix; + unsigned int i; + + if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + + /* + * Check if the hardware supports the requested format, use the default + * format otherwise. + */ + for (i = 0; i < ARRAY_SIZE(isp4vid_formats); i++) + if (isp4vid_formats[i] == format->pixelformat) + break; + + if (i == ARRAY_SIZE(isp4vid_formats)) + format->pixelformat = ISP4VID_DEFAULT_FMT; + + switch (format->pixelformat) { + case V4L2_PIX_FMT_NV12: { + const struct v4l2_frmsize_discrete *fsz = + v4l2_find_nearest_size(isp4vid_frmsize, + ARRAY_SIZE(isp4vid_frmsize), + width, height, + format->width, format->height); + + format->width = fsz->width; + format->height = fsz->height; + + format->bytesperline = format->width; + format->sizeimage = format->bytesperline * + format->height * 3 / 2; + } + break; + case V4L2_PIX_FMT_YUYV: { + const struct v4l2_frmsize_discrete *fsz = + v4l2_find_nearest_size(isp4vid_frmsize, + ARRAY_SIZE(isp4vid_frmsize), + width, height, + format->width, format->height); + + format->width = fsz->width; + format->height = fsz->height; + + format->bytesperline = format->width * 2; + format->sizeimage = format->bytesperline * format->height; + } + break; + default: + dev_err(isp_vdev->dev, "%s|unsupported fmt=%u", + isp_vdev->vdev.name, format->pixelformat); + return -EINVAL; + } + + if (format->field == V4L2_FIELD_ANY) + format->field = isp4vid_fmt_default.field; + + if (format->colorspace == V4L2_COLORSPACE_DEFAULT) + format->colorspace = isp4vid_fmt_default.colorspace; + + return 0; +} + +static int isp4vid_set_fmt_2_isp(struct v4l2_subdev *sdev, + struct v4l2_pix_format *pix_fmt) +{ + struct v4l2_subdev_format fmt = {0}; + + switch (pix_fmt->pixelformat) { + case V4L2_PIX_FMT_NV12: + fmt.format.code = MEDIA_BUS_FMT_YUYV8_1_5X8; + break; + case V4L2_PIX_FMT_YUYV: + fmt.format.code = MEDIA_BUS_FMT_YUYV8_1X16; + break; + default: + return -EINVAL; + }; + fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE; + fmt.pad = ISP4VID_PAD_VIDEO_OUTPUT; + fmt.format.width = pix_fmt->width; + fmt.format.height = pix_fmt->height; + return v4l2_subdev_call(sdev, pad, set_fmt, NULL, &fmt); +} + +static int isp4vid_s_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct isp4vid_dev *isp_vdev = video_drvdata(file); + u32 pitch; + int ret; + + /* Do not change the format while stream is on */ + if (vb2_is_busy(&isp_vdev->vbq)) + return -EBUSY; + + if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + + ret = isp4vid_try_fmt_vid_cap(file, priv, f); + if (ret) + return ret; + + dev_dbg(isp_vdev->dev, "%s|width height:%ux%u->%ux%u", + isp_vdev->vdev.name, + isp_vdev->format.width, isp_vdev->format.height, + f->fmt.pix.width, f->fmt.pix.height); + dev_dbg(isp_vdev->dev, "%s|pixelformat:0x%x-0x%x", + isp_vdev->vdev.name, isp_vdev->format.pixelformat, + f->fmt.pix.pixelformat); + dev_dbg(isp_vdev->dev, "%s|bytesperline:%u->%u", + isp_vdev->vdev.name, isp_vdev->format.bytesperline, + f->fmt.pix.bytesperline); + dev_dbg(isp_vdev->dev, "%s|sizeimage:%u->%u", + isp_vdev->vdev.name, isp_vdev->format.sizeimage, + f->fmt.pix.sizeimage); + + isp_vdev->format = f->fmt.pix; + + switch (isp_vdev->format.pixelformat) { + case V4L2_PIX_FMT_NV12: + pitch = isp_vdev->format.width; + break; + case V4L2_PIX_FMT_YUYV: + pitch = isp_vdev->format.width * 2; + break; + default: + dev_err(isp_vdev->dev, "%s|unsupported fmt=0x%x\n", + isp_vdev->vdev.name, isp_vdev->format.pixelformat); + return -EINVAL; + } + + ret = isp4vid_set_fmt_2_isp(isp_vdev->isp_sdev, &isp_vdev->format); + + return ret; +} + +static int isp4vid_enum_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_fmtdesc *f) +{ + struct isp4vid_dev *isp_vdev = video_drvdata(file); + + switch (f->index) { + case 0: + f->pixelformat = V4L2_PIX_FMT_NV12; + break; + case 1: + f->pixelformat = V4L2_PIX_FMT_YUYV; + break; + default: + return -EINVAL; + } + + dev_dbg(isp_vdev->dev, "%s|index=%d, pixelformat=0x%X", + isp_vdev->vdev.name, f->index, f->pixelformat); + + return 0; +} + +static int isp4vid_enum_framesizes(struct file *file, void *fh, + struct v4l2_frmsizeenum *fsize) +{ + struct isp4vid_dev *isp_vdev = video_drvdata(file); + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(isp4vid_formats); i++) { + if (isp4vid_formats[i] == fsize->pixel_format) + break; + } + if (i == ARRAY_SIZE(isp4vid_formats)) + return -EINVAL; + + if (fsize->index < ARRAY_SIZE(isp4vid_frmsize)) { + fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE; + fsize->discrete = isp4vid_frmsize[fsize->index]; + dev_dbg(isp_vdev->dev, "%s|size[%d]=%dx%d", + isp_vdev->vdev.name, fsize->index, + fsize->discrete.width, fsize->discrete.height); + } else { + return -EINVAL; + } + + return 0; +} + +static int isp4vid_ioctl_enum_frameintervals(struct file *file, void *priv, + struct v4l2_frmivalenum *fival) +{ + struct isp4vid_dev *isp_vdev = video_drvdata(file); + int i; + + if (fival->index >= ARRAY_SIZE(isp4vid_tpfs)) + return -EINVAL; + + for (i = 0; i < ARRAY_SIZE(isp4vid_formats); i++) + if (isp4vid_formats[i] == fival->pixel_format) + break; + if (i == ARRAY_SIZE(isp4vid_formats)) + return -EINVAL; + + for (i = 0; i < ARRAY_SIZE(isp4vid_frmsize); i++) + if (isp4vid_frmsize[i].width == fival->width && + isp4vid_frmsize[i].height == fival->height) + break; + if (i == ARRAY_SIZE(isp4vid_frmsize)) + return -EINVAL; + + fival->type = V4L2_FRMIVAL_TYPE_DISCRETE; + fival->discrete = isp4vid_tpfs[fival->index]; + v4l2_simplify_fraction(&fival->discrete.numerator, + &fival->discrete.denominator, 8, 333); + + dev_dbg(isp_vdev->dev, "%s|interval[%d]=%d/%d", + isp_vdev->vdev.name, fival->index, + fival->discrete.numerator, + fival->discrete.denominator); + + return 0; +} + +static int isp4vid_ioctl_g_param(struct file *file, void *priv, + struct v4l2_streamparm *param) +{ + struct isp4vid_dev *isp_vdev = video_drvdata(file); + + if (param->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + + param->parm.capture.capability = V4L2_CAP_TIMEPERFRAME; + param->parm.capture.timeperframe = isp_vdev->timeperframe; + param->parm.capture.readbuffers = 0; + + dev_dbg(isp_vdev->dev, "%s|timeperframe=%d/%d", isp_vdev->vdev.name, + param->parm.capture.timeperframe.numerator, + param->parm.capture.timeperframe.denominator); + return 0; +} + +static const struct v4l2_ioctl_ops isp4vid_vdev_ioctl_ops = { + /* VIDIOC_QUERYCAP handler */ + .vidioc_querycap = isp4vid_ioctl_querycap, + + /* VIDIOC_ENUM_FMT handlers */ + .vidioc_enum_fmt_vid_cap = isp4vid_enum_fmt_vid_cap, + + /* VIDIOC_G_FMT handlers */ + .vidioc_g_fmt_vid_cap = isp4vid_g_fmt_vid_cap, + + /* VIDIOC_S_FMT handlers */ + .vidioc_s_fmt_vid_cap = isp4vid_s_fmt_vid_cap, + + /* VIDIOC_TRY_FMT handlers */ + .vidioc_try_fmt_vid_cap = isp4vid_try_fmt_vid_cap, + + /* Buffer handlers */ + .vidioc_reqbufs = vb2_ioctl_reqbufs, + .vidioc_querybuf = vb2_ioctl_querybuf, + .vidioc_qbuf = vb2_ioctl_qbuf, + .vidioc_expbuf = vb2_ioctl_expbuf, + .vidioc_dqbuf = vb2_ioctl_dqbuf, + .vidioc_create_bufs = vb2_ioctl_create_bufs, + .vidioc_prepare_buf = vb2_ioctl_prepare_buf, + + /* Stream on/off */ + .vidioc_streamon = vb2_ioctl_streamon, + .vidioc_streamoff = vb2_ioctl_streamoff, + + /* Stream type-dependent parameter ioctls */ + .vidioc_g_parm = isp4vid_ioctl_g_param, + + /* Debugging ioctls */ + .vidioc_enum_framesizes = isp4vid_enum_framesizes, + + /* VIDIOC_ENUM_FRAMEINTERVALS */ + .vidioc_enum_frameintervals = isp4vid_ioctl_enum_frameintervals, + +}; + +static unsigned int isp4vid_get_image_size(struct v4l2_pix_format *fmt) +{ + switch (fmt->pixelformat) { + case V4L2_PIX_FMT_NV12: + return fmt->width * fmt->height * 3 / 2; + case V4L2_PIX_FMT_YUYV: + return fmt->width * fmt->height * 2; + default: + return 0; + } +}; + +static int isp4vid_qops_queue_setup(struct vb2_queue *vq, + unsigned int *nbuffers, + unsigned int *nplanes, unsigned int sizes[], + struct device *alloc_devs[]) +{ + struct isp4vid_dev *isp_vdev = vb2_get_drv_priv(vq); + unsigned int q_num_bufs = vb2_get_num_buffers(vq); + + if (*nplanes > 1) { + dev_err(isp_vdev->dev, + "fail to setup queue, no mplane supported %u\n", + *nplanes); + return -EINVAL; + }; + + if (*nplanes == 1) { + unsigned int size; + + size = isp4vid_get_image_size(&isp_vdev->format); + if (sizes[0] < size) { + dev_err(isp_vdev->dev, + "fail for small plane size %u, %u expected\n", + sizes[0], size); + return -EINVAL; + } + } + + if (q_num_bufs + *nbuffers < ISP4VID_VIDEO_BUF_NUM) + *nbuffers = ISP4VID_VIDEO_BUF_NUM - q_num_bufs; + + switch (isp_vdev->format.pixelformat) { + case V4L2_PIX_FMT_NV12: + case V4L2_PIX_FMT_YUYV: { + *nplanes = 1; + sizes[0] = max(sizes[0], isp_vdev->format.sizeimage); + isp_vdev->format.sizeimage = sizes[0]; + } + break; + default: + dev_err(isp_vdev->dev, "%s|unsupported fmt=%u\n", + isp_vdev->vdev.name, isp_vdev->format.pixelformat); + return -EINVAL; + } + + dev_dbg(isp_vdev->dev, "%s|*nbuffers=%u *nplanes=%u sizes[0]=%u\n", + isp_vdev->vdev.name, + *nbuffers, *nplanes, sizes[0]); + + return 0; +} + +static void isp4vid_qops_buffer_queue(struct vb2_buffer *vb) +{ + struct isp4vid_capture_buffer *buf = + container_of(vb, struct isp4vid_capture_buffer, vb2.vb2_buf); + struct isp4vid_dev *isp_vdev = vb2_get_drv_priv(vb->vb2_queue); + + struct isp4vid_vb2_buf *priv_buf = vb->planes[0].mem_priv; + struct isp4if_img_buf_info *img_buf = &buf->img_buf; + + dev_dbg(isp_vdev->dev, "%s|index=%u", isp_vdev->vdev.name, vb->index); + + dev_dbg(isp_vdev->dev, "queue isp user bo 0x%llx size=%lu", + priv_buf->gpu_addr, + priv_buf->size); + + switch (isp_vdev->format.pixelformat) { + case V4L2_PIX_FMT_NV12: { + u32 y_size = isp_vdev->format.sizeimage / 3 * 2; + u32 uv_size = isp_vdev->format.sizeimage / 3; + + img_buf->planes[0].len = y_size; + img_buf->planes[0].sys_addr = priv_buf->vaddr; + img_buf->planes[0].mc_addr = priv_buf->gpu_addr; + + dev_dbg(isp_vdev->dev, "img_buf[0]: mc=0x%llx size=%u", + img_buf->planes[0].mc_addr, + img_buf->planes[0].len); + + img_buf->planes[1].len = uv_size; + img_buf->planes[1].sys_addr = + (void *)((u64)priv_buf->vaddr + y_size); + img_buf->planes[1].mc_addr = priv_buf->gpu_addr + y_size; + + dev_dbg(isp_vdev->dev, "img_buf[1]: mc=0x%llx size=%u", + img_buf->planes[1].mc_addr, + img_buf->planes[1].len); + + img_buf->planes[2].len = 0; + } + break; + case V4L2_PIX_FMT_YUYV: { + img_buf->planes[0].len = isp_vdev->format.sizeimage; + img_buf->planes[0].sys_addr = priv_buf->vaddr; + img_buf->planes[0].mc_addr = priv_buf->gpu_addr; + + dev_dbg(isp_vdev->dev, "img_buf[0]: mc=0x%llx size=%u", + img_buf->planes[0].mc_addr, + img_buf->planes[0].len); + + img_buf->planes[1].len = 0; + img_buf->planes[2].len = 0; + } + break; + default: + dev_err(isp_vdev->dev, "%s|unsupported fmt=%u", + isp_vdev->vdev.name, isp_vdev->format.pixelformat); + return; + } + + if (isp_vdev->stream_started) + isp_vdev->ops->send_buffer(isp_vdev, img_buf); + + mutex_lock(&isp_vdev->buf_list_lock); + list_add_tail(&buf->list, &isp_vdev->buf_list); + mutex_unlock(&isp_vdev->buf_list_lock); +} + +static void isp4vid_qops_buffer_cleanup(struct vb2_buffer *vb) +{ + struct isp4vid_dev *isp_vdev = vb2_get_drv_priv(vb->vb2_queue); + struct isp4vid_vb2_buf *buf = vb->planes[0].mem_priv; + + dev_dbg(isp_vdev->dev, "%s|index=%u vb->memory %u", + isp_vdev->vdev.name, vb->index, vb->memory); + + if (!buf) { + dev_err(isp_vdev->dev, "Invalid buf handle"); + return; + } + + // release implicit dmabuf reference here for vb2 buffer + // of type MMAP and is exported + if (vb->memory == VB2_MEMORY_MMAP && buf->is_expbuf) { + dma_buf_put(buf->dbuf); + dev_dbg(isp_vdev->dev, + "put dmabuf for vb->memory %d expbuf %d", + vb->memory, + buf->is_expbuf); + } +} + +static int isp4vid_qops_start_streaming(struct vb2_queue *vq, + unsigned int count) +{ + struct isp4vid_dev *isp_vdev = vb2_get_drv_priv(vq); + struct isp4vid_capture_buffer *isp_buf; + struct v4l2_subdev *isp_subdev = NULL; + struct media_entity *entity; + struct v4l2_subdev *subdev; + struct media_pad *pad; + int ret = 0; + + if (isp_vdev->stream_started) { + dev_dbg(isp_vdev->dev, + "%s do nothing for already streaming\n", + isp_vdev->vdev.name); + return 0; + } + isp_vdev->sequence = 0; + ret = v4l2_pipeline_pm_get(&isp_vdev->vdev.entity); + if (ret) { + dev_err(isp_vdev->dev, "power up isp fail %d\n", ret); + return ret; + } + + entity = &isp_vdev->vdev.entity; + while (1) { + pad = &entity->pads[0]; + if (!(pad->flags & MEDIA_PAD_FL_SINK)) + break; + + pad = media_pad_remote_pad_first(pad); + if (!pad || !is_media_entity_v4l2_subdev(pad->entity)) + break; + + entity = pad->entity; + subdev = media_entity_to_v4l2_subdev(entity); + + if (entity->function == MEDIA_ENT_F_PROC_VIDEO_ISP) { + ret = v4l2_subdev_call(subdev, video, pre_streamon, 0); + /* The isp s_stream should be called last! */ + isp_subdev = subdev; + } else { + ret = v4l2_subdev_call(subdev, video, s_stream, 1); + } + + if (ret < 0 && ret != -ENOIOCTLCMD) { + dev_dbg(isp_vdev->dev, "fail start streaming: %s %d\n", + subdev->name, ret); + return ret; + } + } + + if (isp_subdev) { + ret = v4l2_subdev_call(isp_subdev, video, s_stream, 1); + if (ret < 0 && ret != -ENOIOCTLCMD) { + dev_dbg(isp_vdev->dev, "fail start stream: %s %d\n", + isp_subdev->name, ret); + return ret; + } + } + + list_for_each_entry(isp_buf, &isp_vdev->buf_list, list) { + isp_vdev->ops->send_buffer(isp_vdev, &isp_buf->img_buf); + } + + /* Start the media pipeline */ + ret = video_device_pipeline_start(&isp_vdev->vdev, &isp_vdev->pipe); + if (ret) { + dev_err(isp_vdev->dev, "video_device_pipeline_start fail:%d", + ret); + isp4vid_capture_return_all_buffers(isp_vdev, + VB2_BUF_STATE_QUEUED); + return ret; + } + isp_vdev->stream_started = true; + + return 0; +} + +static void isp4vid_qops_stop_streaming(struct vb2_queue *vq) +{ + struct isp4vid_dev *isp_vdev = vb2_get_drv_priv(vq); + struct v4l2_subdev *subdev, *isp_subdev = NULL; + struct media_entity *entity; + struct media_pad *pad; + int ret; + + if (!isp_vdev->stream_started) { + dev_dbg(isp_vdev->dev, + "%s stop_streaming, do none for not started\n", + isp_vdev->vdev.name); + return; + } + dev_dbg(isp_vdev->dev, "%s stop_streaming\n", + isp_vdev->vdev.name); + + entity = &isp_vdev->vdev.entity; + while (1) { + pad = &entity->pads[0]; + if (!(pad->flags & MEDIA_PAD_FL_SINK)) + break; + + pad = media_pad_remote_pad_first(pad); + if (!pad || !is_media_entity_v4l2_subdev(pad->entity)) + break; + + entity = pad->entity; + subdev = media_entity_to_v4l2_subdev(entity); + + if (entity->function == MEDIA_ENT_F_PROC_VIDEO_ISP) { + /* + * isp subdev to call isp post_streamoff + * after s_stream sequence + */ + isp_subdev = subdev; + } + ret = v4l2_subdev_call(subdev, video, s_stream, 0); + + if (ret < 0 && ret != -ENOIOCTLCMD) + dev_dbg(isp_vdev->dev, "fail start streaming: %s %d\n", + subdev->name, ret); + } + + if (isp_subdev) { + ret = v4l2_subdev_call(isp_subdev, video, post_streamoff); + if (ret < 0 && ret != -ENOIOCTLCMD) + dev_dbg(isp_vdev->dev, "fail start stream: %s %d\n", + isp_subdev->name, ret); + } + + isp_vdev->stream_started = false; + v4l2_pipeline_pm_put(&isp_vdev->vdev.entity); + + /* Stop the media pipeline */ + video_device_pipeline_stop(&isp_vdev->vdev); + + /* Release all active buffers */ + isp4vid_capture_return_all_buffers(isp_vdev, VB2_BUF_STATE_ERROR); +} + +static int isp4vid_fill_buffer_size(struct isp4vid_dev *isp_vdev) +{ + int ret = 0; + + switch (isp_vdev->format.pixelformat) { + case V4L2_PIX_FMT_NV12: + isp_vdev->format.bytesperline = isp_vdev->format.width; + isp_vdev->format.sizeimage = isp_vdev->format.bytesperline * + isp_vdev->format.height * 3 / 2; + break; + case V4L2_PIX_FMT_YUYV: + isp_vdev->format.bytesperline = isp_vdev->format.width; + isp_vdev->format.sizeimage = isp_vdev->format.bytesperline * + isp_vdev->format.height * 2; + break; + default: + dev_err(isp_vdev->dev, "fail for invalid default format 0x%x", + isp_vdev->format.pixelformat); + ret = -EINVAL; + break; + } + + return ret; +} + +static const struct vb2_ops isp4vid_qops = { + .queue_setup = isp4vid_qops_queue_setup, + .buf_cleanup = isp4vid_qops_buffer_cleanup, + .buf_queue = isp4vid_qops_buffer_queue, + .start_streaming = isp4vid_qops_start_streaming, + .stop_streaming = isp4vid_qops_stop_streaming, + .wait_prepare = vb2_ops_wait_prepare, + .wait_finish = vb2_ops_wait_finish, +}; + +int isp4vid_dev_init(struct isp4vid_dev *isp_vdev, + struct v4l2_subdev *isp_sdev, + const struct isp4vid_ops *ops, + void *amdgpu_dev) +{ + const char *vdev_name = isp4vid_video_dev_name; + struct v4l2_device *v4l2_dev; + struct video_device *vdev; + struct vb2_queue *q; + int ret; + + if (!isp_vdev || !isp_sdev || !isp_sdev->v4l2_dev || !amdgpu_dev) + return -EINVAL; + + v4l2_dev = isp_sdev->v4l2_dev; + vdev = &isp_vdev->vdev; + + isp_vdev->isp_sdev = isp_sdev; + isp_vdev->amdgpu_dev = amdgpu_dev; + isp_vdev->dev = v4l2_dev->dev; + isp_vdev->ops = ops; + + /* Initialize the vb2_queue struct */ + mutex_init(&isp_vdev->vbq_lock); + q = &isp_vdev->vbq; + q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + q->io_modes = VB2_MMAP | VB2_DMABUF; + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + q->buf_struct_size = sizeof(struct isp4vid_capture_buffer); + q->min_queued_buffers = 2; + q->ops = &isp4vid_qops; + q->drv_priv = isp_vdev; + q->mem_ops = &isp4vid_vb2_memops; + q->lock = &isp_vdev->vbq_lock; + q->dev = v4l2_dev->dev; + ret = vb2_queue_init(q); + if (ret) { + dev_err(v4l2_dev->dev, "vb2_queue_init error:%d", ret); + return ret; + } + /* Initialize buffer list and its lock */ + mutex_init(&isp_vdev->buf_list_lock); + INIT_LIST_HEAD(&isp_vdev->buf_list); + + /* Set default frame format */ + isp_vdev->format = isp4vid_fmt_default; + isp_vdev->timeperframe = ISP4VID_ISP_TPF_DEFAULT; + v4l2_simplify_fraction(&isp_vdev->timeperframe.numerator, + &isp_vdev->timeperframe.denominator, 8, 333); + + ret = isp4vid_fill_buffer_size(isp_vdev); + if (ret) { + dev_err(v4l2_dev->dev, "fail to fill buffer size: %d\n", ret); + return ret; + } + + ret = isp4vid_set_fmt_2_isp(isp_sdev, &isp_vdev->format); + if (ret) { + dev_err(v4l2_dev->dev, "fail init format :%d\n", ret); + return ret; + } + + /* Initialize the video_device struct */ + isp_vdev->vdev.entity.name = vdev_name; + isp_vdev->vdev.entity.function = MEDIA_ENT_F_IO_V4L; + isp_vdev->vdev_pad.flags = MEDIA_PAD_FL_SINK; + ret = media_entity_pads_init(&isp_vdev->vdev.entity, 1, + &isp_vdev->vdev_pad); + + if (ret) { + dev_err(v4l2_dev->dev, "init media entity pad fail:%d\n", ret); + return ret; + } + + vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE | + V4L2_CAP_STREAMING | V4L2_CAP_IO_MC; + vdev->entity.ops = &isp4vid_vdev_ent_ops; + vdev->release = video_device_release_empty; + vdev->fops = &isp4vid_vdev_fops; + vdev->ioctl_ops = &isp4vid_vdev_ioctl_ops; + vdev->lock = NULL; + vdev->queue = q; + vdev->v4l2_dev = v4l2_dev; + vdev->vfl_dir = VFL_DIR_RX; + strscpy(vdev->name, vdev_name, sizeof(vdev->name)); + video_set_drvdata(vdev, isp_vdev); + + ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1); + if (ret) + dev_err(v4l2_dev->dev, "register video device fail:%d\n", ret); + + return ret; +} + +void isp4vid_dev_deinit(struct isp4vid_dev *isp_vdev) +{ + video_unregister_device(&isp_vdev->vdev); +} diff --git a/drivers/media/platform/amd/isp4/isp4_video.h b/drivers/media/platform/amd/isp4/isp4_video.h new file mode 100644 index 000000000000..4d6705174d34 --- /dev/null +++ b/drivers/media/platform/amd/isp4/isp4_video.h @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2025 Advanced Micro Devices, Inc. + */ + +#ifndef _ISP4_VIDEO_H_ +#define _ISP4_VIDEO_H_ + +#include +#include +#include +#include +#include "isp4_interface.h" + +enum isp4vid_buf_done_status { + /* It means no corresponding image buf in fw response */ + ISP4VID_BUF_DONE_STATUS_ABSENT, + ISP4VID_BUF_DONE_STATUS_SUCCESS, + ISP4VID_BUF_DONE_STATUS_FAILED +}; + +struct isp4vid_buf_done_info { + enum isp4vid_buf_done_status status; + struct isp4if_img_buf_info buf; +}; + +/* call back parameter for CB_EVT_ID_FRAME_DONE */ +struct isp4vid_framedone_param { + s32 poc; + s32 cam_id; + s64 time_stamp; + struct isp4vid_buf_done_info preview; +}; + +struct isp4vid_capture_buffer { + /* + * struct vb2_v4l2_buffer must be the first element + * the videobuf2 framework will allocate this struct based on + * buf_struct_size and use the first sizeof(struct vb2_buffer) bytes of + * memory as a vb2_buffer + */ + struct vb2_v4l2_buffer vb2; + struct isp4if_img_buf_info img_buf; + struct list_head list; +}; + +struct isp4vid_dev; + +struct isp4vid_ops { + int (*send_buffer)(struct isp4vid_dev *vid, + struct isp4if_img_buf_info *img_buf); +}; + +struct isp4vid_dev { + struct video_device vdev; + struct media_pad vdev_pad; + struct v4l2_pix_format format; + + /* mutex that protects vbq */ + struct mutex vbq_lock; + struct vb2_queue vbq; + + /* mutex that protects buf_list */ + struct mutex buf_list_lock; + struct list_head buf_list; + + u32 sequence; + bool stream_started; + struct task_struct *kthread; + + struct media_pipeline pipe; + struct device *dev; + void *amdgpu_dev; + struct v4l2_subdev *isp_sdev; + struct v4l2_fract timeperframe; + + /* Callback operations */ + const struct isp4vid_ops *ops; +}; + +int isp4vid_dev_init(struct isp4vid_dev *isp_vdev, + struct v4l2_subdev *isp_sdev, + const struct isp4vid_ops *ops, + void *amdgpu_dev); + +void isp4vid_dev_deinit(struct isp4vid_dev *isp_vdev); + +s32 isp4vid_notify(void *cb_ctx, struct isp4vid_framedone_param *evt_param); + +void isp4vid_frmsize_range(struct v4l2_frmsize_discrete *min, + struct v4l2_frmsize_discrete *max); + +#endif From patchwork Sun Jun 8 14:49:14 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Du, Bin" X-Patchwork-Id: 894858 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2082.outbound.protection.outlook.com [40.107.93.82]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 629E324E4AD; Sun, 8 Jun 2025 14:50:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.93.82 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749394220; cv=fail; b=sxTjtAEij3NhuRsrShkxppgEQetBcpZr/bArqQLpjRmu2wUiFRC6T1ia7Unxvnt/poy2I8zNY9xlQ+49itLjU6SOyQYOLy/+rDPkkXa9JBTtb7h3BlkBAivpgli7yMYlspbL49aIUdZCcrQJ6H8zYiZ2Jnm2o/eKLWhIA5lQHL0= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749394220; c=relaxed/simple; bh=qL/EjjlzzhjIrh1w/93MXxF8OhKfxN/EHvCZbIjZKKA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=HAnWUc/tZgzqB6Ak/tK1y98C/WRvjWu65gX6F733qSgHKSWLp4jQ6GQipZnXHOaCeY1p4SA2yKUho0qRcHkXX0kMxGeDht3bdtQK+7UfSps9SleK3n4tn7YSDsspBPz+kUo50Oor6NiG1q4O2cshjk3/myQeIfU6Rh6QgkYBWm0= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com; spf=fail smtp.mailfrom=amd.com; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b=sYIuB8a2; arc=fail smtp.client-ip=40.107.93.82 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=amd.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="sYIuB8a2" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=ZX7Yl+AYeQ5Ls9iKnj2JPO7BtiJpoGo1/n/XEBIouN6qGpOPhys0/GtxTiwVJSw38KoZtAWmssNg64lO+pimFwmE3JqbvzDrHmWUV7SOUTcFueBAMDQEVPhg04ANoteMQ2wNC4Q09Z7wMB2MjvBpYuW96RXvYsaIr464IAr3MDBDjOHPcJgg2JeV755aNUATMsYNQiJDsxxO1/qhyYi1FTHKUgD04OQFeuny9bBF4+Q7IVz10DHWty8UT1O2Lzoj/gSkJsCCzJr9iH+MC177c75qnk/UDra+3LqTuvBOZKgEU7qgOxrUgj+mc4CzZzBsGTQmormO8Nd5O1USDA8XTA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=WrzMMVXAnmsDF+Xra1QS1B6ip+/6NjYNc4GJU6EyPcM=; b=tW75FWpYfSICVx1AutFOUULCuHBWq72WHRMZlIwbs0UVyvqopT/Prk4d/xGnRtMU1yracSvmVPNJGzCU7TPcGYwgbHFWyDX9Akt/Xf5ye/UXDNxkFP8pCfR2Nrx5f/H/c+HlZHtGcuFwwvpkN3H43LkMg2d9cfQ9B4XGEESRpo2OX3aNGUl7gdyTpX/PcyJFonTqPSbTDGCbe64bRymXlI3z1h1HIgpdcpzmj2UAO2oMet0bX+L9rmvwCRv6BegEHDoLoeAftaVtwtZ0x+c6BsH2MHqMMWnQHgcqSeZPTyhSKv2hTUZgz9BfUpCZki2YBEpioO9HE7kBDBl21FtEFg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=WrzMMVXAnmsDF+Xra1QS1B6ip+/6NjYNc4GJU6EyPcM=; b=sYIuB8a2QtPPUcpaNByaV6KLiJ3QpB7mtDKzWJzzEVBA1NmJo4hB3cm93JbVL+4lU8GpXPDlQ8E0olEkwsW4s/59Am2uCUj+Fg7QO6chvuQBr0X/tS2ujnx0s/HV/axLB3jPiqmHf8/UdnZOEpBez6U5KdIzlnQoGa3a6fhrWTE= Received: from MW4PR04CA0326.namprd04.prod.outlook.com (2603:10b6:303:82::31) by IA1PR12MB6435.namprd12.prod.outlook.com (2603:10b6:208:3ad::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8792.38; Sun, 8 Jun 2025 14:50:10 +0000 Received: from CO1PEPF000044F2.namprd05.prod.outlook.com (2603:10b6:303:82:cafe::d5) by MW4PR04CA0326.outlook.office365.com (2603:10b6:303:82::31) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8792.34 via Frontend Transport; Sun, 8 Jun 2025 14:50:10 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1PEPF000044F2.mail.protection.outlook.com (10.167.241.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8835.15 via Frontend Transport; Sun, 8 Jun 2025 14:50:08 +0000 Received: from 555e2b870847.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Sun, 8 Jun 2025 09:50:02 -0500 From: Bin Du To: , , , , , , , CC: , , , , , , , , "Bin Du" Subject: [PATCH v1 7/9] media: platform: amd: isp4 debug fs logging and more descriptive errors Date: Sun, 8 Jun 2025 22:49:14 +0800 Message-ID: <20250608144916.222835-8-Bin.Du@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250608144916.222835-1-Bin.Du@amd.com> References: <20250608144916.222835-1-Bin.Du@amd.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044F2:EE_|IA1PR12MB6435:EE_ X-MS-Office365-Filtering-Correlation-Id: 0a5a4e25-5a0c-421b-8b9e-08dda69bc376 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|36860700013|1800799024|376014; X-Microsoft-Antispam-Message-Info: ubr5IdyvEAGJvUTbWGSOb2490GfK7k22gM1AgXV8uafzWe4wsEVsLtp2jf788KwKkIlh7ACkJAVEhFsrRJ/wAYGpgVf6tgZcXZwOvgnHTbjoSKbfBljGE4I8egsj1K1DjjcmRiMJqe1XN4spy6uGSQqj7dDm7g4eGaC21fOejNoi1KDeK4iFQKWXGIR+kyQyMpkujVLdskUYA1AkIeJq0DQX6I/ArpDk7dGl3NOwWj9Mj36N1IP1HkCT+Xo2zA9HsGGHCQ64mG9ogjB08Y5RuA5gihb9YLc+fsJ7+csMxs8M+fZwofM0uU3Zk466juuLf4x6SW/isPe0nB4QiqYid0/Wgqi+lgYmLh5nag49dQRCbMzeYi8EIQX+rmGWYCCP/AHOO5jiTuGFCzPGoZaH0enzuYy9iSw2Xk5rvx8PZ6MGtxH0WpzI5o8w5hXM60cj859P3Be5E5eUtODo7mvJPg4NmOgOtCMkOTAGqzyei9rstJ7/Gaufv8IwASp7+e8jZQl3dWoYy+YsbIhL6DzgP9jtaovOu4P5og600PYR3WtfABUcz3AD9dhwX86USkkYc6QiZqd3SeyV9GXY+5KH433Fob9Iee1Z+TwtHc6STMWJVxTE3t7GGIJo5GNxJcXlZJ2+dMVY35/Mk27VSrJO0e16o12/aLVr6hrouYrsiwaD8qzW0Q1SL0MQavURLPT+pFzEWydXfuCKbIT2WWRPWvGn3B7zR2Dm6GHFIR4uYB5IsRhqhHxO4Pi0dGzdnmaOYFQ4kQjlouts4X/eevWTYVMbJHBBPRvrcaR1tMJQiES/BHPk7wIIltySPv7JGpSq/ZEusaj+kIDPEZB+ugClNQPCSPCrZzJaRDPD5PJX464CZ9re6up7avs6YkLfnfZcIhrODQzElDiQ9Fo4yuHvBp0yee5IjNpoUOiw4dusZI9TjnIMgYsK4ck4xvsb/dKAoZdZRFYr5tMjoAcPmYWpgHLnOGhWT2cEL4cruQqWo63v0mi3JtDNpo81QBFXSadzbyurX8XrBcQQHl0nlxl3LD3ZYuZxxceQobF5HIKpFI1IypfxCbn7RMvjv4DPENFfyo5ZiXyiGBNCSjc8KsWLM5ag+vll7BLggsD5lmZ+JJGwbjWtuorihMnoDfWP+RhI1zJZGivzIJZva5d8mQiWCVCbIgrGzFN4knXae2wltZhyhPfRZMKLEcbETUBBFZuJjFMw2L+NQt6NbV0m0jbOq2IUqtCs+rhsKJ9jFnriLvy9O7lUFXB7qn0NfdUCXpRqLAbgeL3rFPM9PG6Oln8+9USHLhCSWqeJXaqKTcKxk/P9ePF/YaxrRENc6cNw0LV0jtTAvAO3pJUP4Cg/A3YqwSQbo1facVPQgiq6faMu7fbtIHgF2OYgXY6ykjRu1EaKQB21hv50I/wKUbo2Vf0sfyH5C5CKZtGPl629NDpjWr1SIXhXolILhwRoc8pXDb2TEJwF5k73fHxBHjFgAn5cyfm7c+YINb+NQFbUkX+sQOkqXYGfQykVG7e7m8b4Tn9L X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(82310400026)(36860700013)(1800799024)(376014); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jun 2025 14:50:08.4472 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0a5a4e25-5a0c-421b-8b9e-08dda69bc376 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6435 Signed-off-by: Bin Du Signed-off-by: Svetoslav Stoilov Change-Id: I3ce167dbeb612b94c89df0b48f7ffa0988b5336f --- drivers/media/platform/amd/isp4/Makefile | 1 + drivers/media/platform/amd/isp4/isp4.c | 5 + drivers/media/platform/amd/isp4/isp4_debug.c | 272 ++++++++++++++++++ drivers/media/platform/amd/isp4/isp4_debug.h | 41 +++ .../media/platform/amd/isp4/isp4_interface.c | 37 ++- drivers/media/platform/amd/isp4/isp4_subdev.c | 29 +- 6 files changed, 365 insertions(+), 20 deletions(-) create mode 100644 drivers/media/platform/amd/isp4/isp4_debug.c create mode 100644 drivers/media/platform/amd/isp4/isp4_debug.h diff --git a/drivers/media/platform/amd/isp4/Makefile b/drivers/media/platform/amd/isp4/Makefile index a68f18fe79b4..da1e047cdb7d 100644 --- a/drivers/media/platform/amd/isp4/Makefile +++ b/drivers/media/platform/amd/isp4/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_AMD_ISP4) += amd_capture.o amd_capture-objs := isp4_subdev.o \ + isp4_debug.o \ isp4_phy.o \ isp4_interface.o \ isp4.o \ diff --git a/drivers/media/platform/amd/isp4/isp4.c b/drivers/media/platform/amd/isp4/isp4.c index 3beb35293504..f7e716ec47da 100644 --- a/drivers/media/platform/amd/isp4/isp4.c +++ b/drivers/media/platform/amd/isp4/isp4.c @@ -10,6 +10,7 @@ #include "amdgpu_object.h" #include "isp4.h" +#include "isp4_debug.h" #include "isp4_hw.h" #define ISP4_DRV_NAME "amd_isp_capture" @@ -325,6 +326,8 @@ static int isp4_capture_probe(struct platform_device *pdev) pm_runtime_set_suspended(dev); pm_runtime_enable(dev); + isp_debugfs_create(isp_dev); + return 0; err_unreg_video_dev_notifier: @@ -342,6 +345,8 @@ static void isp4_capture_remove(struct platform_device *pdev) { struct isp4_device *isp_dev = platform_get_drvdata(pdev); + isp_debugfs_remove(isp_dev); + v4l2_async_nf_unregister(&isp_dev->notifier); v4l2_async_nf_cleanup(&isp_dev->notifier); v4l2_device_unregister_subdev(&isp_dev->isp_sdev.sdev); diff --git a/drivers/media/platform/amd/isp4/isp4_debug.c b/drivers/media/platform/amd/isp4/isp4_debug.c new file mode 100644 index 000000000000..0b8b1ad87525 --- /dev/null +++ b/drivers/media/platform/amd/isp4/isp4_debug.c @@ -0,0 +1,272 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2025 Advanced Micro Devices, Inc. + */ + +#include "isp4.h" +#include "isp4_debug.h" +#include "isp4_hw.h" +#include "isp4_interface.h" + +#define ISP4DBG_FW_LOG_RINGBUF_SIZE (2 * 1024 * 1024) +#define ISP4DBG_MACRO_2_STR(X) #X +#define ISP4DBG_MAX_ONE_TIME_LOG_LEN 510 + +#ifdef CONFIG_DEBUG_FS + +void isp_debugfs_create(struct isp4_device *isp_dev) +{ + isp_dev->isp_sdev.debugfs_dir = debugfs_create_dir("amd_isp", NULL); + debugfs_create_bool("fw_log_enable", 0644, + isp_dev->isp_sdev.debugfs_dir, + &isp_dev->isp_sdev.enable_fw_log); + isp_dev->isp_sdev.fw_log_output = + devm_kzalloc(&isp_dev->pdev->dev, + ISP4DBG_FW_LOG_RINGBUF_SIZE + 32, + GFP_KERNEL); +} + +void isp_debugfs_remove(struct isp4_device *isp_dev) +{ + debugfs_remove_recursive(isp_dev->isp_sdev.debugfs_dir); + isp_dev->isp_sdev.debugfs_dir = NULL; +} + +static u32 isp_fw_fill_rb_log(struct isp4_subdev *isp, u8 *sys, u32 rb_size) +{ + struct isp4_interface *ispif = &isp->ispif; + struct device *dev = isp->dev; + u8 *buf = isp->fw_log_output; + u32 rd_ptr, wr_ptr; + u32 total_cnt = 0; + u32 offset = 0; + u32 cnt; + + if (!sys || rb_size == 0) + return 0; + + mutex_lock(&ispif->isp4if_mutex); + + rd_ptr = isp4hw_rreg(ISP4_GET_ISP_REG_BASE(isp), ISP_LOG_RB_RPTR0); + wr_ptr = isp4hw_rreg(ISP4_GET_ISP_REG_BASE(isp), ISP_LOG_RB_WPTR0); + + do { + if (wr_ptr > rd_ptr) + cnt = wr_ptr - rd_ptr; + else if (wr_ptr < rd_ptr) + cnt = rb_size - rd_ptr; + else + goto unlock_and_quit; + + if (cnt > rb_size) { + dev_err(dev, "fail bad fw log size %u\n", cnt); + goto unlock_and_quit; + } + + memcpy(buf + offset, (u8 *)(sys + rd_ptr), cnt); + + offset += cnt; + total_cnt += cnt; + rd_ptr = (rd_ptr + cnt) % rb_size; + } while (rd_ptr < wr_ptr); + + isp4hw_wreg(ISP4_GET_ISP_REG_BASE(isp), ISP_LOG_RB_RPTR0, rd_ptr); + +unlock_and_quit: + mutex_unlock(&ispif->isp4if_mutex); + return total_cnt; +} + +void isp_fw_log_print(struct isp4_subdev *isp) +{ + struct isp4_interface *ispif = &isp->ispif; + char *fw_log_buf = isp->fw_log_output; + u32 cnt; + + if (!isp->enable_fw_log || !fw_log_buf) + return; + + cnt = isp_fw_fill_rb_log(isp, ispif->fw_log_buf->sys_addr, + ispif->fw_log_buf->mem_size); + + if (cnt) { + char temp_ch; + char *str; + char *end; + char *line_end; + + str = (char *)fw_log_buf; + end = ((char *)fw_log_buf + cnt); + fw_log_buf[cnt] = 0; + + while (str < end) { + line_end = strchr(str, 0x0A); + if ((line_end && (str + ISP4DBG_MAX_ONE_TIME_LOG_LEN) >= line_end) || + (!line_end && (str + ISP4DBG_MAX_ONE_TIME_LOG_LEN) >= end)) { + if (line_end) + *line_end = 0; + + if (*str != '\0') + dev_dbg(isp->dev, + "%s", str); + + if (line_end) { + *line_end = 0x0A; + str = line_end + 1; + } else { + break; + } + } else { + u32 tmp_len = ISP4DBG_MAX_ONE_TIME_LOG_LEN; + + temp_ch = str[tmp_len]; + str[tmp_len] = 0; + dev_dbg(isp->dev, "%s", str); + str[tmp_len] = temp_ch; + str = &str[tmp_len]; + } + } + } +} +#endif + +char *isp4dbg_get_buf_src_str(u32 src) +{ + switch (src) { + case BUFFER_SOURCE_STREAM: + return ISP4DBG_MACRO_2_STR(BUFFER_SOURCE_STREAM); + default: + return "Unknown buf source"; + } +} + +char *isp4dbg_get_buf_done_str(u32 status) +{ + switch (status) { + case BUFFER_STATUS_INVALID: + return ISP4DBG_MACRO_2_STR(BUFFER_STATUS_INVALID); + case BUFFER_STATUS_SKIPPED: + return ISP4DBG_MACRO_2_STR(BUFFER_STATUS_SKIPPED); + case BUFFER_STATUS_EXIST: + return ISP4DBG_MACRO_2_STR(BUFFER_STATUS_EXIST); + case BUFFER_STATUS_DONE: + return ISP4DBG_MACRO_2_STR(BUFFER_STATUS_DONE); + case BUFFER_STATUS_LACK: + return ISP4DBG_MACRO_2_STR(BUFFER_STATUS_LACK); + case BUFFER_STATUS_DIRTY: + return ISP4DBG_MACRO_2_STR(BUFFER_STATUS_DIRTY); + case BUFFER_STATUS_MAX: + return ISP4DBG_MACRO_2_STR(BUFFER_STATUS_MAX); + default: + return "Unknown Buf Done Status"; + } +}; + +char *isp4dbg_get_img_fmt_str(int fmt /* enum isp4fw_image_format * */) +{ + switch (fmt) { + case IMAGE_FORMAT_NV12: + return "NV12"; + case IMAGE_FORMAT_YUV422INTERLEAVED: + return "YUV422INTERLEAVED"; + default: + return "unknown fmt"; + } +} + +void isp4dbg_show_bufmeta_info(struct device *dev, char *pre, + void *in, void *orig_buf) +{ + struct isp4if_img_buf_info *orig; + struct isp4fw_buffer_meta_info *p; + + if (!in) + return; + + if (!pre) + pre = ""; + + p = (struct isp4fw_buffer_meta_info *)in; + orig = (struct isp4if_img_buf_info *)orig_buf; + + dev_dbg(dev, "%s(%s) en:%d,stat:%s(%u),src:%s\n", pre, + isp4dbg_get_img_fmt_str(p->image_prop.image_format), + p->enabled, isp4dbg_get_buf_done_str(p->status), p->status, + isp4dbg_get_buf_src_str(p->source)); + + dev_dbg(dev, "%p,0x%llx(%u) %p,0x%llx(%u) %p,0x%llx(%u)\n", + orig->planes[0].sys_addr, orig->planes[0].mc_addr, + orig->planes[0].len, orig->planes[1].sys_addr, + orig->planes[1].mc_addr, orig->planes[1].len, + orig->planes[2].sys_addr, orig->planes[2].mc_addr, + orig->planes[2].len); +} + +char *isp4dbg_get_buf_type(u32 type) +{ + /* enum isp4fw_buffer_type */ + switch (type) { + case BUFFER_TYPE_PREVIEW: + return ISP4DBG_MACRO_2_STR(BUFFER_TYPE_PREVIEW); + case BUFFER_TYPE_META_INFO: + return ISP4DBG_MACRO_2_STR(BUFFER_TYPE_META_INFO); + case BUFFER_TYPE_MEM_POOL: + return ISP4DBG_MACRO_2_STR(BUFFER_TYPE_MEM_POOL); + default: + return "unknown type"; + } +} + +char *isp4dbg_get_cmd_str(u32 cmd) +{ + switch (cmd) { + case CMD_ID_START_STREAM: + return ISP4DBG_MACRO_2_STR(CMD_ID_START_STREAM); + case CMD_ID_STOP_STREAM: + return ISP4DBG_MACRO_2_STR(CMD_ID_STOP_STREAM); + case CMD_ID_SEND_BUFFER: + return ISP4DBG_MACRO_2_STR(CMD_ID_SEND_BUFFER); + case CMD_ID_SET_STREAM_CONFIG: + return ISP4DBG_MACRO_2_STR(CMD_ID_SET_STREAM_CONFIG); + case CMD_ID_SET_OUT_CHAN_PROP: + return ISP4DBG_MACRO_2_STR(CMD_ID_SET_OUT_CHAN_PROP); + case CMD_ID_ENABLE_OUT_CHAN: + return ISP4DBG_MACRO_2_STR(CMD_ID_ENABLE_OUT_CHAN); + default: + return "unknown cmd"; + }; +} + +char *isp4dbg_get_resp_str(u32 cmd) +{ + switch (cmd) { + case RESP_ID_CMD_DONE: + return ISP4DBG_MACRO_2_STR(RESP_ID_CMD_DONE); + case RESP_ID_NOTI_FRAME_DONE: + return ISP4DBG_MACRO_2_STR(RESP_ID_NOTI_FRAME_DONE); + default: + return "unknown respid"; + }; +} + +char *isp4dbg_get_if_stream_str(u32 stream /* enum fw_cmd_resp_stream_id */) +{ + switch (stream) { + case ISP4IF_STREAM_ID_GLOBAL: + return "STREAM_GLOBAL"; + case ISP4IF_STREAM_ID_1: + return "STREAM1"; + default: + return "unknown streamID"; + } +} + +char *isp4dbg_get_out_ch_str(int ch /* enum isp4fw_pipe_out_ch */) +{ + switch ((enum isp4fw_pipe_out_ch)ch) { + case ISP_PIPE_OUT_CH_PREVIEW: + return "prev"; + default: + return "unknown channel"; + } +} diff --git a/drivers/media/platform/amd/isp4/isp4_debug.h b/drivers/media/platform/amd/isp4/isp4_debug.h new file mode 100644 index 000000000000..acf99bf129ae --- /dev/null +++ b/drivers/media/platform/amd/isp4/isp4_debug.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2025 Advanced Micro Devices, Inc. + */ + +#ifndef _ISP4_DEBUG_H_ +#define _ISP4_DEBUG_H_ + +#include +#include + +#include "isp4_subdev.h" + +#ifdef CONFIG_DEBUG_FS +struct isp4_device; + +void isp_debugfs_create(struct isp4_device *isp_dev); +void isp_debugfs_remove(struct isp4_device *isp_dev); +void isp_fw_log_print(struct isp4_subdev *isp); + +#else + +/*to avoid checkpatch warning*/ +#define isp_debugfs_create(cam) cam +#define isp_debugfs_remove(cam) cam +#define isp_fw_log_print(isp) isp + +#endif /* CONFIG_DEBUG_FS */ + +void isp4dbg_show_bufmeta_info(struct device *dev, char *pre, void *p, + void *orig_buf /* struct sys_img_buf_handle* */); +char *isp4dbg_get_img_fmt_str(int fmt /* enum _image_format_t * */); +char *isp4dbg_get_out_ch_str(int ch /* enum _isp_pipe_out_ch_t */); +char *isp4dbg_get_cmd_str(u32 cmd); +char *isp4dbg_get_buf_type(u32 type);/* enum _buffer_type_t */ +char *isp4dbg_get_resp_str(u32 resp); +char *isp4dbg_get_buf_src_str(u32 src); +char *isp4dbg_get_buf_done_str(u32 status); +char *isp4dbg_get_if_stream_str(u32 stream); + +#endif diff --git a/drivers/media/platform/amd/isp4/isp4_interface.c b/drivers/media/platform/amd/isp4/isp4_interface.c index d46d7487a994..2a57707925cf 100644 --- a/drivers/media/platform/amd/isp4/isp4_interface.c +++ b/drivers/media/platform/amd/isp4/isp4_interface.c @@ -7,6 +7,7 @@ #include "amdgpu_object.h" +#include "isp4_debug.h" #include "isp4_fw_cmd_resp.h" #include "isp4_hw.h" #include "isp4_hw_reg.h" @@ -392,7 +393,8 @@ static int isp4if_insert_isp_fw_cmd(struct isp4_interface *ispif, len = rb_config->val_size; if (isp4if_is_cmdq_rb_full(ispif, stream)) { - dev_err(dev, "fail no cmdslot (%d)\n", stream); + dev_err(dev, "fail no cmdslot %s(%d)\n", + isp4dbg_get_if_stream_str(stream), stream); return -EINVAL; } @@ -400,13 +402,15 @@ static int isp4if_insert_isp_fw_cmd(struct isp4_interface *ispif, rd_ptr = isp4hw_rreg(ispif->mmio, rreg); if (rd_ptr > len) { - dev_err(dev, "fail (%u),rd_ptr %u(should<=%u),wr_ptr %u\n", + dev_err(dev, "fail %s(%u),rd_ptr %u(should<=%u),wr_ptr %u\n", + isp4dbg_get_if_stream_str(stream), stream, rd_ptr, len, wr_ptr); return -EINVAL; } if (wr_ptr > len) { - dev_err(dev, "fail (%u),wr_ptr %u(should<=%u), rd_ptr %u\n", + dev_err(dev, "fail %s(%u),wr_ptr %u(should<=%u), rd_ptr %u\n", + isp4dbg_get_if_stream_str(stream), stream, wr_ptr, len, rd_ptr); return -EINVAL; } @@ -501,7 +505,8 @@ static int isp4if_send_fw_cmd(struct isp4_interface *ispif, rd_ptr = isp4hw_rreg(ispif->mmio, rreg); wr_ptr = isp4hw_rreg(ispif->mmio, wreg); dev_err(dev, - "failed to get free cmdq slot, stream (%d)\n", + "failed to get free cmdq slot, stream %s(%d)\n", + isp4dbg_get_if_stream_str(stream), stream); return -ETIMEDOUT; } @@ -553,8 +558,8 @@ static int isp4if_send_fw_cmd(struct isp4_interface *ispif, ret = isp4if_insert_isp_fw_cmd(ispif, stream, &cmd); if (ret) { - dev_err(dev, "fail for insert_isp_fw_cmd camId (0x%08x)\n", - cmd_id); + dev_err(dev, "fail for insert_isp_fw_cmd camId %s(0x%08x)\n", + isp4dbg_get_cmd_str(cmd_id), cmd_id); if (cmd_ele) { isp4if_rm_cmd_from_cmdq(ispif, cmd_ele->seq_num, cmd_ele->cmd_id); @@ -783,13 +788,15 @@ int isp4if_f2h_resp(struct isp4_interface *ispif, wr_ptr_dbg = wr_ptr; if (rd_ptr > len) { - dev_err(dev, "fail (%u),rd_ptr %u(should<=%u),wr_ptr %u\n", + dev_err(dev, "fail %s(%u),rd_ptr %u(should<=%u),wr_ptr %u\n", + isp4dbg_get_if_stream_str(stream), stream, rd_ptr, len, wr_ptr); return -EINVAL; } if (wr_ptr > len) { - dev_err(dev, "fail (%u),wr_ptr %u(should<=%u), rd_ptr %u\n", + dev_err(dev, "fail %s(%u),wr_ptr %u(should<=%u), rd_ptr %u\n", + isp4dbg_get_if_stream_str(stream), stream, wr_ptr, len, rd_ptr); return -EINVAL; } @@ -804,7 +811,8 @@ int isp4if_f2h_resp(struct isp4_interface *ispif, isp4hw_wreg(GET_ISP4IF_REG_BASE(ispif), rreg, rd_ptr); } else { - dev_err(dev, "(%u),rd %u(should<=%u),wr %u\n", + dev_err(dev, "%s(%u),rd %u(should<=%u),wr %u\n", + isp4dbg_get_if_stream_str(stream), stream, rd_ptr, len, wr_ptr); return -EINVAL; } @@ -832,7 +840,8 @@ int isp4if_f2h_resp(struct isp4_interface *ispif, isp4hw_wreg(GET_ISP4IF_REG_BASE(ispif), rreg, rd_ptr); } else { - dev_err(dev, "(%u),rd %u(should<=%u),wr %u\n", + dev_err(dev, "%s(%u),rd %u(should<=%u),wr %u\n", + isp4dbg_get_if_stream_str(stream), stream, rd_ptr, len, wr_ptr); return -EINVAL; } @@ -855,7 +864,8 @@ int isp4if_f2h_resp(struct isp4_interface *ispif, isp4hw_wreg(GET_ISP4IF_REG_BASE(ispif), rreg, rd_ptr); } else { - dev_err(dev, "(%u),rd %u(should<=%u),wr %u\n", + dev_err(dev, "%s(%u),rd %u(should<=%u),wr %u\n", + isp4dbg_get_if_stream_str(stream), stream, rd_ptr, len, wr_ptr); return -EINVAL; } @@ -872,9 +882,10 @@ int isp4if_f2h_resp(struct isp4_interface *ispif, checksum, response->resp_check_sum, rd_ptr_dbg, wr_ptr_dbg); - dev_err(dev, "(%u), seqNo %u, resp_id (0x%x)\n", - stream, + dev_err(dev, "%s(%u), seqNo %u, resp_id %s(0x%x)\n", + isp4dbg_get_if_stream_str(stream), stream, response->resp_seq_num, + isp4dbg_get_resp_str(response->resp_id), response->resp_id); return -EINVAL; diff --git a/drivers/media/platform/amd/isp4/isp4_subdev.c b/drivers/media/platform/amd/isp4/isp4_subdev.c index 816fa3a127f5..11210b13cd02 100644 --- a/drivers/media/platform/amd/isp4/isp4_subdev.c +++ b/drivers/media/platform/amd/isp4/isp4_subdev.c @@ -7,6 +7,7 @@ #include #include +#include "isp4_debug.h" #include "isp4_fw_cmd_resp.h" #include "isp4_hw.h" #include "isp4_interface.h" @@ -304,7 +305,9 @@ static int isp4sd_setup_output(struct isp4_subdev *isp_subdev, return -EINVAL; } - dev_dbg(dev, "channel: w:h=%u:%u,lp:%u,cp%u\n", + dev_dbg(dev, "channel:%s,fmt %s,w:h=%u:%u,lp:%u,cp%u\n", + isp4dbg_get_out_ch_str(cmd_ch_prop.ch), + isp4dbg_get_img_fmt_str(cmd_ch_prop.image_prop.image_format), cmd_ch_prop.image_prop.width, cmd_ch_prop.image_prop.height, cmd_ch_prop.image_prop.luma_pitch, cmd_ch_prop.image_prop.chroma_pitch); @@ -327,6 +330,9 @@ static int isp4sd_setup_output(struct isp4_subdev *isp_subdev, return ret; } + dev_dbg(dev, "enable channel %s\n", + isp4dbg_get_out_ch_str(cmd_ch_en.ch)); + if (!sensor_info->start_stream_cmd_sent) { ret = isp4sd_kickoff_stream(isp_subdev, out_prop->width, out_prop->height); @@ -489,8 +495,9 @@ static void isp4sd_fw_resp_cmd_done(struct isp4_subdev *isp_subdev, isp4if_rm_cmd_from_cmdq(ispif, para->cmd_seq_num, para->cmd_id); struct device *dev = isp_subdev->dev; - dev_dbg(dev, "stream %d,cmd (0x%08x)(%d),seq %u, ele %p\n", + dev_dbg(dev, "stream %d,cmd %s(0x%08x)(%d),seq %u, ele %p\n", stream_id, + isp4dbg_get_cmd_str(para->cmd_id), para->cmd_id, para->cmd_status, para->cmd_seq_num, ele); @@ -551,8 +558,9 @@ isp4sd_preview_done(struct isp4_subdev *isp_subdev, pcb->preview.status = ISP4VID_BUF_DONE_STATUS_SUCCESS; } } else if (meta->preview.enabled) { - dev_err(dev, "fail bad preview status %u\n", - meta->preview.status); + dev_err(dev, "fail bad preview status %u(%s)\n", + meta->preview.status, + isp4dbg_get_buf_done_str(meta->preview.status)); } return prev; @@ -612,14 +620,18 @@ static void isp4sd_fw_resp_frame_done(struct isp4_subdev *isp_subdev, pcb.poc = meta->poc; pcb.cam_id = 0; - dev_dbg(dev, "ts:%llu,streamId:%d,poc:%u,preview_en:%u,(%i)\n", + dev_dbg(dev, "ts:%llu,streamId:%d,poc:%u,preview_en:%u,%s(%i)\n", ktime_get_ns(), stream_id, meta->poc, meta->preview.enabled, + isp4dbg_get_buf_done_str(meta->preview.status), meta->preview.status); prev = isp4sd_preview_done(isp_subdev, meta, &pcb); - if (pcb.preview.status != ISP4VID_BUF_DONE_STATUS_ABSENT) + if (pcb.preview.status != ISP4VID_BUF_DONE_STATUS_ABSENT) { + isp4dbg_show_bufmeta_info(dev, "prev", &meta->preview, + &pcb.preview.buf); isp4vid_notify(&isp_subdev->isp_vdev, &pcb); + } isp4if_dealloc_buffer_node(prev); @@ -640,6 +652,8 @@ static void isp4sd_fw_resp_func(struct isp4_subdev *isp_subdev, if (ispif->status < ISP4IF_STATUS_FW_RUNNING) return; + isp_fw_log_print(isp_subdev); + while (true) { s32 ret; @@ -657,7 +671,8 @@ static void isp4sd_fw_resp_func(struct isp4_subdev *isp_subdev, &resp.param.frame_done); break; default: - dev_err(dev, "-><- fail respid (0x%x)\n", + dev_err(dev, "-><- fail respid %s(0x%x)\n", + isp4dbg_get_resp_str(resp.resp_id), resp.resp_id); break; } From patchwork Sun Jun 8 14:49:15 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Du, Bin" X-Patchwork-Id: 895008 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2089.outbound.protection.outlook.com [40.107.243.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6B43025393B; Sun, 8 Jun 2025 14:50:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.243.89 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749394220; cv=fail; b=W1spMkP6tZ1EG2PKCrzr+2OgG2595yWTOUvykSG942xlU26hf3L4MsYtpKzxdsyCMLkoMgh0mRk6pMHCD6uQwQUu6EP/88GVsP16vxsxHszQUcCKOmt0724/FZnHMPmb4na/fhMDtcWHlo38J9Fbkej1jCoRR3/I3C8GUoXtISA= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749394220; c=relaxed/simple; bh=c4AybrZEjBCt3Sq4sJTj47YFvSv1vyh81SpSxn6lFKM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=mDF+1eh9AQ253tshMy1uB6rwaGUNeOE60z707O2mEw08Caa3VjQHn7ZJnI3xcA5QAdDMET88R2IjAWWyjFfZhTyCnqpa66l645BTKh4tMCirkyxcFRwDgdvU9IWakJyz7kyjCV52kc4WLUznUIj5G+k8TJAcP/KKkltSPxvbOyI= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com; spf=fail smtp.mailfrom=amd.com; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b=LHSiZ/xz; arc=fail smtp.client-ip=40.107.243.89 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=amd.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="LHSiZ/xz" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=Anq1IOE81MRYeYaUWvXqjBYs/x1NOxuE43Udk61lxIWg40ERPGNOq4riuVa8Xg1qZwiSgCjFLfgXIf5lFmwJW3747JPrbB4SUBIeV1erFYh8IGpBZBhV/RHVqPlpLE3FwY5DXGSb346VPo7PN4kENqk5AGBMBKyANdoBSuXmQaKx6DtstILBCfyngeFCuXAB6FdfuYZUKlUa1trPO1gy9KrAz97EVzJdIgYeUXSLaFqnU7zXgBMjEyImVA8VspiazzGTXKdTXcc0d5URKmfEDDaWcbJc7eiy2wHq7TqkVHaCvBfOBsznciO5m8hHyiaJyPUOTJ54o+vfgGlkEZz8QA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=neMntWBsOQc7CRKXf42kqprZHr9zfVWBcfssPvT5Z7I=; b=p2HG6w+O5ex+doW34MJMz5HIi8TndnOC5rJ4lWKKrabnKog2XoMRsJW31KpFo3TnQQVEMNs/qAEa2ZiRQj3GOQTYqMJchU6697+jeFMqUzOhkqOa19MCB/JpvL9fOgAYNvCAynXex0w4EVTE6VWhWCzvrCXUHexfn/YBUANdiWvIfRffWTjecV0VdfM/VSeNN1VZ1/+m2hN9vE+dBqR04yrElB/yJk6E4pRVEBKMfyLNgz4OHPUTzkA3O4JtrkqRYncO1eaJLsEXle0NahJzyx0AIz5V/nZcuhatRGpe7kGNo/ZS02gG8D3eZ6EFDnxsGU+jlcrrxVy/aq/D0UsOBw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=neMntWBsOQc7CRKXf42kqprZHr9zfVWBcfssPvT5Z7I=; b=LHSiZ/xzX+0nUq4/S4ZzP7ggNwAq7uAke84D71UA/632zOFO9g3aurNw2Yk5G8OKo7jkaRWPF0RTjxLXzAP7mQGeX1g7QD1W4vlmVx+ZA5eW8KQ/n4b7W8xoZeifKMxbJ5AosoWjPFML4PMq63qGuyLz1Hp0ijBRGN3alLADWTo= Received: from MW4PR04CA0315.namprd04.prod.outlook.com (2603:10b6:303:82::20) by PH7PR12MB8780.namprd12.prod.outlook.com (2603:10b6:510:26b::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8792.34; Sun, 8 Jun 2025 14:50:11 +0000 Received: from CO1PEPF000044F2.namprd05.prod.outlook.com (2603:10b6:303:82:cafe::f5) by MW4PR04CA0315.outlook.office365.com (2603:10b6:303:82::20) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8746.31 via Frontend Transport; Sun, 8 Jun 2025 14:50:11 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1PEPF000044F2.mail.protection.outlook.com (10.167.241.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8835.15 via Frontend Transport; Sun, 8 Jun 2025 14:50:11 +0000 Received: from 555e2b870847.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Sun, 8 Jun 2025 09:50:06 -0500 From: Bin Du To: , , , , , , , CC: , , , , , , , , "Bin Du" Subject: [PATCH v1 8/9] Documentation: add documentation of AMD isp 4 driver Date: Sun, 8 Jun 2025 22:49:15 +0800 Message-ID: <20250608144916.222835-9-Bin.Du@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250608144916.222835-1-Bin.Du@amd.com> References: <20250608144916.222835-1-Bin.Du@amd.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044F2:EE_|PH7PR12MB8780:EE_ X-MS-Office365-Filtering-Correlation-Id: 96306e75-5c2c-4b8e-195f-08dda69bc545 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700013|1800799024|82310400026|376014; X-Microsoft-Antispam-Message-Info: Tdo06X6Vvz0NwVZJW4J3KHBAYFL85ZgKnLnn1hxqDt+bjWbEGKTWZMoaAVKelFS2oiGcHbym4TQQUvnoKom/K1ETF4niOd4fdmdkkluYn58nepUQ78z8IrZM/V7e0vw+ZMCb38hhcvJrs7lNjk1Rx0NSBbJVV5fo5zbYIzA3GKrfLBfXcE3dZbs8ecjHOWOgxy1gFGpJA+Hlrx5+9THO/W0mVoW2GGogXS62CTHNu3a+mDdU3xgneBXm8Qbz0/GSpiUrQXXDRMi676HuobIiBs4ri1gsVauFJ7D9O6CJdLzvsqH73SdTibBut3kOeXF4Qc2pLf+EqPpzUvIlFg6RV8ZIxWwM76k3tthzfLKvM3EJICTrrxXv/LsjcW1MoXdSnFMi+82cTduZ3nIsFJC9Plarq8oolNKqDWOyXVcyhccti072dOBC9koCDZpj3C+zlzWavodtgnIa/wIUI1IZgpg05Ia82P1rp10wpASWvNHk8Ph87NDaJIyTiMUy2NoAYPT2bNn7iLmCxKSVHFUO/pc5MGcePNVVOlwEQ+NwGMgVJh49WtcETQr3dsFp4HtYP1+1/IAslYY3pAAc2+JlM3OlxniJKWJ8GsIPSlKPC86YPoOukH3Up52F3o+msL+tfELxtMYrQCDF/LeetlIywArtuVPyF0fxE6TJOkvjg4lCkM5sGHVlJlAllkjSAL0Bo0P41ZvOe7rOuIWMmFoho7Kfx8ZG7pEyC4+xOXFCYtG7Dlq6X/bRHQz2IDlBwjiNAthtXMgdAduEnP/D4zncUiiZldcZQAhwqJznlue2nhKSaa4yoWW3ti2LmzkmRWfn3Wc5HnEPjHxtMoLcJkK8K2M+VJQzL8J9Krru7Yczw94LG06ElmT5YX9hdU3599LCPzQUguIMF333i8mkEasfC12WH0gom0Oa8aVXaI6elY6Swff8x5KJs3hrkwT7Dz9qF47x2jjadPLEjTeqg6Ax9Zm8TKIqt0txKMPoKeVARvUAzw7h8A6sGQSBnOx43KXvH7cP7Ogg5VKqm0Ne6d3Wdp9orfS1B2qtUtF9Zq9/I+qliIWmsR2PjJ4ndU2PzZHNUCp0UoXUbJVVsYwpYEyxuIMP1w2J/VYwnQrD9qkDABZSKoWcfA1IbX78aWJhYH0MzpWVJEvB42YzYfLyjBqX8SBQCqhVgejY1AA25bbQfep/bc8vQteZReZTL5HFTMmbFf7Ing6IBvYJ39tI//iZAKCc01Kum35hPJfpMfTw7U31Zory2hpN23C5NHQKZ3idFhHsbqRVu2+vTJs2LKIkpzHcJw4awIMQeDveg0AN+YWcsiRfCDvH3MkKtzNSgW6f7Mj+TwnK1lCBdFFHovAZwrh1MPfsxK+mVxID2B2DAz2NCqYJeY+u5L9iuWdxmf8mtQMNhVmTy2LVXYdJwg/BecECpSLQ4M7iyuPAfBuDeRsPxkZloXKcyBxSVU820bxJBSt9x6ge/4ANgwsgZ0MKJgPVG3GWk9gqPqZu0t99NPzOhddKz29VT9v06NBaspGi X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(36860700013)(1800799024)(82310400026)(376014); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jun 2025 14:50:11.5409 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 96306e75-5c2c-4b8e-195f-08dda69bc545 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB8780 Add documentation for AMD isp 4 and describe the main components Signed-off-by: Bin Du Signed-off-by: Svetoslav Stoilov Change-Id: I61dfb3a39e5ae372ed48f156a81ae81ee17734b2 --- Documentation/admin-guide/media/amdisp4-1.rst | 60 +++++++++++++++++++ Documentation/admin-guide/media/amdisp4.dot | 8 +++ 2 files changed, 68 insertions(+) create mode 100644 Documentation/admin-guide/media/amdisp4-1.rst create mode 100644 Documentation/admin-guide/media/amdisp4.dot diff --git a/Documentation/admin-guide/media/amdisp4-1.rst b/Documentation/admin-guide/media/amdisp4-1.rst new file mode 100644 index 000000000000..c933e7ae171d --- /dev/null +++ b/Documentation/admin-guide/media/amdisp4-1.rst @@ -0,0 +1,60 @@ +.. SPDX-License-Identifier: GPL-2.0 + +.. include:: + +========================================= +AMD Image Signal Processor (amdisp4) +========================================= + +Introduction +============ + +This file documents the driver for the AMD ISP4 that is part of +AMD Ryzen AI Max 385 SoC. + +The driver is located under drivers/media/platform/amd/isp4 and uses +the Media-Controller API. + +Topology +======== +.. _amdisp4_topology_graph: + +.. kernel-figure:: amdisp4.dot + :alt: Diagram of the media pipeline topology + :align: center + + + +The driver has 1 sub-device: + +- isp: used to resize and process bayer raw frames in to yuv. + +The driver has 1 video device: + +- n00000004 [style=bold] + n00000004 [label="Preview\n/dev/video0", shape=box, style=filled, fillcolor=yellow] + n0000000a [label="{{} | ov05c10 22-0010\n/dev/v4l-subdev0 | { 0}}", shape=Mrecord, style=filled, fillcolor=green] + n0000000a:port0 -> n00000001:port0 [style=bold] +} From patchwork Sun Jun 8 14:49:16 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Du, Bin" X-Patchwork-Id: 895007 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2078.outbound.protection.outlook.com [40.107.237.78]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1C8E625394B; Sun, 8 Jun 2025 14:50:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.237.78 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749394223; cv=fail; b=JiwFuJxQdFuSunNtrwJYcPGINDwymFsszmFXTGjIxupkPxiiK2v36RpolQQi4C2eXgDhtL7pQYZEYviomNUgS96LavVrCOPpbhclQHnqyw4UZ0z5H2jFpeDV/R5DLzx2/Z9vUBt5OswCQhtleI5QKqyGokmU1RUM+2IAZp/XeyA= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749394223; c=relaxed/simple; bh=aWK1OUF1jH7AgPWeSeDAyHAuSvulQBQJLWrdq74sWxQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=S8tSJAoVShGEIrJds6PTIknjDu+MKHJfCAIdUt0uKymUrF968PkKkXh50FOtJLhWxFVh9qlxQ0VNdsU76zjvJ/AT/3xTHFiUKARez3eZLCrU8/K6wBgtQWx+BztD+V03E/Ygjb/9qEMtGBJ5nwZMqYSlCRmFeZCVaEe2aMQUuWI= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com; spf=fail smtp.mailfrom=amd.com; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b=IPQm2PDy; arc=fail smtp.client-ip=40.107.237.78 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=amd.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="IPQm2PDy" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=nF1DCU7KpP0JTlqodTU7BxzcZuX17sLghHaqhScrc+mA/bGp4CvudMfoyEq272ZlJpr3tirM9WKy5uTyC/m+tiWqeiTWNgTVwiRM7N7qwSxjNhUwBKEVQhXS9ahmLycYY48nii/4zwK1BFSirGrGLigU89veUceMXHKuj0fckYbQ5D9idLOHRxkJrikp9fOp2tHGOaGGDqGvu00CRIz47LxNjKcaCd9e+lX1ox+CAsiDNFBbS1SqghsJsfmQtB67RgZHDaVfb/xMskeQySaBPbfl8RJ67dscVi3OM8d1Bm9pSgtFB9OMO9+0nAmivpNNA1rggHkfefCIpQDLyxGq+Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=cKyumb23X64NDqw+1Ucot2U4KTo4HZ7P2r8lXshFAMU=; b=D7JrnCGvKLFNTk5vLqHYzVd9QdjamloTyMTCENJsHJhYEjMWF9xDRankN2y0E4Z9iQ91xzjYKoLMKf9qkvR/IonDZITVMR7B8L0WlZeEBsmutApvYC98KLNAMu4teHktLtxgp223qro53sryDaHnto1mcU0riJLxEaIPMQGWDuhuekM6FltDvO7MHDLtYT9NHt0qIINHE5vyc6X4fR3V1TFuD+WQ0M0YME4m7f8K1mh7D44/pNlaPcpeLg1QFkZEc1g9Cn2aSv9Ru83eVv8fyO5IikTJkbH7eP2vdAVOtn8LBi4BEpXTroV4tKdvr10V/gwfCYX1XFt0ocfbojE/Zw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=cKyumb23X64NDqw+1Ucot2U4KTo4HZ7P2r8lXshFAMU=; b=IPQm2PDym7qS3Bix8QQvcPm6FsPQYEQ/Vl4xex78kN0xSSHkmpA8jvNNFdUpZ+0xTGetbWCBLpgC7gfajxAuW7t6+mzm4RSJBiTBZaII63Bd3nwdD1lgZLFQG6fsJH6KKYbAiF1VkM/Lj0hSUbo4X+yphfsRi5dDZd1kmhW7kEY= Received: from SJ0PR05CA0202.namprd05.prod.outlook.com (2603:10b6:a03:330::27) by MW3PR12MB4395.namprd12.prod.outlook.com (2603:10b6:303:5c::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8792.34; Sun, 8 Jun 2025 14:50:17 +0000 Received: from CO1PEPF000044EE.namprd05.prod.outlook.com (2603:10b6:a03:330:cafe::2d) by SJ0PR05CA0202.outlook.office365.com (2603:10b6:a03:330::27) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8835.14 via Frontend Transport; Sun, 8 Jun 2025 14:50:17 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1PEPF000044EE.mail.protection.outlook.com (10.167.241.68) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8835.15 via Frontend Transport; Sun, 8 Jun 2025 14:50:16 +0000 Received: from 555e2b870847.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Sun, 8 Jun 2025 09:50:10 -0500 From: Bin Du To: , , , , , , , CC: , , , , , , , , "Bin Du" Subject: [PATCH v1 9/9] MAINTAINERS: add entry for AMD isp 4 driver Date: Sun, 8 Jun 2025 22:49:16 +0800 Message-ID: <20250608144916.222835-10-Bin.Du@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250608144916.222835-1-Bin.Du@amd.com> References: <20250608144916.222835-1-Bin.Du@amd.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044EE:EE_|MW3PR12MB4395:EE_ X-MS-Office365-Filtering-Correlation-Id: 8982f6e7-71b2-4fc9-5672-08dda69bc86c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|36860700013|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: u2I/3i3Kv+nW3CkV+LkQoizcRErQgiH21tLUr0UETsRlGr3pGeZ1ozvV7v/w/HHvbgcK4TS1XKMPmN0o1GbjuTRDV/UgzUGzDF56SHjkMBmFl7cW/eMYDxxfx4zbw+GkTCWFQlxT4pP2zQ2kylUAzIpqr3bQ5+fEgcc3aS9G/eWfkuZx3HeS09mGs+jNqTiMH8u2Atut2d/E7a2hgbHILI7JWO30GgGNOuuim2JIhy4gxILKYdq4xY3rM0vUakHrtEFHUS4x5eCOJ/r/DvoqC5JthaSKiC1q3mpRPGmHrRpPN6eV+q20PdfuPk0o7ksnzoUulPsZcLq1PXDSKWf7UhgBAaNm1/+MmwCVriLjchZcQ11ZTkUGeoo7fQGCqZNrtxHGOFMdFTGvG5rGmTXbX6oj0wJPcxUsFwhYmjZURamBb9Om8W1IIvPfGbNg6WrmcS6K0a8dv80M6cmCmhYLqf/B1YN8hNC8dRQALxxSUtTASZdM61toX8+abHKfh9/twGp6/A2BnxF2+H//tU+GZCqQCgOzogYSiy90Yi0IB100zCzuafD0jEIkZLuEosFR+LAjN5R2do033kU4qnrRE9DZdVu1ZckNmEYzlLWyDoY8dK8ILCMmP72gByRF0jFNUq2kX0QUxVGXEADgi47OSE/UVNsmyHukFypOg1p19XfWAeDd97roy0QREc6HNBa8NTP+kYVkH8dEzLNp5Vk0CLFVlgLysNWfgEg5HvYFfNqbjPbcPRw3gNGkuz5YOGWClGxYBemh/sywnSunhdKnfCOCljQR6luLrtLuLjXUgMd04D8O8siTRwzo1y+JMMS4YUQE92lNytlU8z0abDFa6dCxMIpLz4qhKY/sSTDGxb6z3FGPquYfn5WUuIjhViPeE92sBt6r57kpya3o4Dmj3B7yDw44M7Styfb/QBSgfRgY+5JvZvsg7aDGidVZODJsmOa09xZB4goDf2tKj4b/oliQLMkzudAJuOe+LfZo4yJpEm1Hr2EtswoXQpUca1YK9X57RtJBGsuyga3qR5Ebz4fCRVtVdgaTy8o7/TvHBpr05sdU8+P+3Qo06EvUKru5maEE1P0i9c8EubwLLc1NBLBfgUjqHAKMdnm92TlPtnjFnaAqaJEVCF3LiZ5pJpwKWq40mN22YK9wV/udjvHmNuVn4OWh8dL7nfm4nzgqwYpkljIfEZeTbXGnuMluIoVJgN9f8LY+RIjk8Ml+oXIdchgaZ802rugbQveR0Y9OSOJJZ5T41mfQrI4YQfBezMiI988f1uraOadpdlTzrFIYv3RV1ohTeqn0R3KtIMeK29twzm2LCBYbO3/Kt2b5s8+ebIbxdzKyyRnKieOrmwYtW/t0y6cZ4G1LEI7Z16iSxN/kId2jR5LKLEAf4XzGarzUPrXG7FmmS5T5+ptppq7Q22o0CONdgBdQDpKMaZICiLptTsqYPwT2Et63mUVExmQUIUPdFm0RjuB1Wl3K2vCGN7fXePB1iVyPPxlNGWDqt4QammHtGhNSPfXEBv4VWem8 X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(376014)(36860700013)(82310400026)(1800799024); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jun 2025 14:50:16.7705 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8982f6e7-71b2-4fc9-5672-08dda69bc86c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044EE.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4395 Signed-off-by: Bin Du Signed-off-by: Svetoslav Stoilov Change-Id: I715f1318f02e4a689fefc98fc983caca9c448ef2 --- MAINTAINERS | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 10893c91b1c1..15070afb14b5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1107,6 +1107,16 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux.git F: drivers/iommu/amd/ F: include/linux/amd-iommu.h +AMD ISP4 DRIVER +M: Bin Du +M: Nirujogi Pratap +L: linux-media@vger.kernel.org +S: Maintained +T: git git://linuxtv.org/media.git +F: drivers/media/platform/amd/Kconfig +F: drivers/media/platform/amd/Makefile +F: drivers/media/platform/amd/isp4/* + AMD KFD M: Felix Kuehling L: amd-gfx@lists.freedesktop.org