From patchwork Wed Jun 11 13:31:33 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 896344 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0D43928C2B4; Wed, 11 Jun 2025 13:31:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749648715; cv=none; b=LfMMqHElNMU9N1ktGxDzlsvsGPZ9PfXcrpYa5H8pbYV7Bgrhwl0EoZOI8i/ZDjmvsvVmqftPfeSvUbjpsK9XdGBoy/q97DEpXySJgZ5cabgFuosOnKWS259o+OJh+ifKzINArFNvdScudNjePBKxvRgsvEcNK9/6zhFgSSXa2X8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749648715; c=relaxed/simple; bh=v+moNxRvidlpxyDzSFcUYvlY02SUk5i5xzP/sgNlv84=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=iCZoGct4BJQKXrVzjKpOhCI2DUIjp1+j9fzInHWgm8KQ7fmvV4uNqXuMBXlK13f1xNTQDPsA+5323hFxPtCeFgQ8fNLlrKQvisSq5V024jdj+KAe8JOlHNJs1LwmDNM+2gutwgxwlILNsa/QT9V0/lBnwz/DlCfvLCDhwgw5yRQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=hu2bw+M7; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="hu2bw+M7" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 29DC1C4CEF0; Wed, 11 Jun 2025 13:31:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749648714; bh=v+moNxRvidlpxyDzSFcUYvlY02SUk5i5xzP/sgNlv84=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hu2bw+M7NelTABhKBxTAY6byOPqO/7gOUwW/UyT3GSfruoP9lr0AmI6LqMYKMPg8B E+IpRWxeGHoef5zFSt459pr3KKa5XJAgUtRL2LJL1MUZ0EFqG3bAtLrQH6p1uXn1mb W28tfDwAsi+0KbipQrmzkAJ5BuTREYjXkkwr5nOCBYKtJAQM8+wlDxk6uK0XI4H6ds V8LSIW12utbRs72CoapP4jLW3wOhwdfcJ2xRbZ4pUDbrTXGpaE3lEPDoOmaJUF4a+e S6V6T4hOKkmGR828BFC3iYoL6pZwWXlE5v9vXpYmF/uCMR0maFbz3za449pPan6zaQ Ih0ZSrrTTfB7Q== From: Michael Walle To: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Arnd Bergmann , Greg Kroah-Hartman , Linus Walleij , Liam Girdwood , Mark Brown , Julien Panis Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Michael Walle Subject: [PATCH v1 1/5] dt-bindings: mfd: ti,tps6594: Add TI TPS652G1 PMIC Date: Wed, 11 Jun 2025 15:31:33 +0200 Message-Id: <20250611133137.1686183-2-mwalle@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250611133137.1686183-1-mwalle@kernel.org> References: <20250611133137.1686183-1-mwalle@kernel.org> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The TPS652G1 is a stripped down version of the TPS65224. From a software point of view, it lacks any voltage monitoring, the watchdog, the ESM and the ADC. Signed-off-by: Michael Walle --- Documentation/devicetree/bindings/mfd/ti,tps6594.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/ti,tps6594.yaml b/Documentation/devicetree/bindings/mfd/ti,tps6594.yaml index 6341b6070366..a48cb00afe43 100644 --- a/Documentation/devicetree/bindings/mfd/ti,tps6594.yaml +++ b/Documentation/devicetree/bindings/mfd/ti,tps6594.yaml @@ -22,6 +22,7 @@ properties: - ti,tps6593-q1 - ti,tps6594-q1 - ti,tps65224-q1 + - ti,tps652g1 reg: description: I2C slave address or SPI chip select number. From patchwork Wed Jun 11 13:31:34 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 895602 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 80C42288C37; Wed, 11 Jun 2025 13:31:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749648718; cv=none; b=oGcz7pOy9QPtS2b9DQPTmBYoNRyEx8Oc3b4rFQ+ChAkY3bo9+xO3d62Srw6e92PCogax/eLEkhf7UfoqzUe4+3BRKAgDfr/scnTIDpoRFx/gS6VqUFY4n0zRfRXV5yvfBZJp+v3+vjy4J0zpn5HcdUFFn6QlevQtsAIu0GJ8icU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749648718; c=relaxed/simple; bh=1g8W1abvL7Vcuqx0UYFfKEzwpdKegawahvzBf/6GJ5s=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=dNL8tGcRtxwhiHXfsDUZShvCIIoC/aqbeb2auhGk6gYha8OWDAnnpBs/U1BNfYqhkXjGlSN4SvROVG+jpH5aeGXz/KM8KqF1D1qqaX6QiteDT9Qi7oIrrNYkFgJAz4gqY4vZcjoY11IfzxHHU8FGeArA2NIaAKW9lYtqnuoWkog= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=sJex5V86; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="sJex5V86" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5714DC4CEEE; Wed, 11 Jun 2025 13:31:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749648718; bh=1g8W1abvL7Vcuqx0UYFfKEzwpdKegawahvzBf/6GJ5s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=sJex5V86L4QtJgQedfVjdgZJTnxcbYBpB26YuMUbtj75YRNOjA5douqkl+Ltkjn1x 72Y1jmeRg7ntECkQUTTWvBNZct+7VwH+EiV8yFoZYLHSDCDzK7kso53FqW9vf3FTp/ KLXNyN0Hw4TF1dPgDdx/cI7u91FpqB7rrnXrDbQNuyLb98fE2mEJpv52kbU3r3cKNN gHDebKD+YIkrHO278CrmhpkXcqUhnaVVbAwK4I+yeon+wnPbZUnjlzIdNIshjz/1fs Tq38+ePFGxMq6Xo+NJLglpO9exU4dpX/LEr4nql068ckFxzKPkeCNlZoqv00O2onsg wSUDUXPYvH2Qg== From: Michael Walle To: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Arnd Bergmann , Greg Kroah-Hartman , Linus Walleij , Liam Girdwood , Mark Brown , Julien Panis Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Michael Walle Subject: [PATCH v1 2/5] mfd: tps6594: Add TI TPS652G1 support Date: Wed, 11 Jun 2025 15:31:34 +0200 Message-Id: <20250611133137.1686183-3-mwalle@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250611133137.1686183-1-mwalle@kernel.org> References: <20250611133137.1686183-1-mwalle@kernel.org> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The TPS652G1 is a stripped down version of the TPS65224. From a software point of view, it lacks any voltage monitoring, the watchdog, the ESM and the ADC. Signed-off-by: Michael Walle --- drivers/mfd/tps6594-core.c | 88 ++++++++++++++++++++++++++++++++++--- drivers/mfd/tps6594-i2c.c | 10 ++++- drivers/mfd/tps6594-spi.c | 10 ++++- include/linux/mfd/tps6594.h | 1 + 4 files changed, 99 insertions(+), 10 deletions(-) diff --git a/drivers/mfd/tps6594-core.c b/drivers/mfd/tps6594-core.c index a7223e873cd1..c16c37e36617 100644 --- a/drivers/mfd/tps6594-core.c +++ b/drivers/mfd/tps6594-core.c @@ -1,6 +1,11 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Core functions for TI TPS65224/TPS6594/TPS6593/LP8764 PMICs + * Core functions for following TI PMICs: + * - LP8764 + * - TPS65224 + * - TPS652G1 + * - TPS6593 + * - TPS6594 * * Copyright (C) 2023 BayLibre Incorporated - https://www.baylibre.com/ */ @@ -414,6 +419,61 @@ static const unsigned int tps65224_irq_reg[] = { TPS6594_REG_INT_FSM_ERR, }; +/* TPS652G1 Resources */ + +static const struct mfd_cell tps652g1_common_cells[] = { + MFD_CELL_RES("tps6594-pfsm", tps65224_pfsm_resources), + MFD_CELL_RES("tps6594-pinctrl", tps65224_pinctrl_resources), + MFD_CELL_NAME("tps6594-regulator"), +}; + +static const struct regmap_irq tps652g1_irqs[] = { + /* INT_GPIO register */ + REGMAP_IRQ_REG(TPS65224_IRQ_GPIO1, 2, TPS65224_BIT_GPIO1_INT), + REGMAP_IRQ_REG(TPS65224_IRQ_GPIO2, 2, TPS65224_BIT_GPIO2_INT), + REGMAP_IRQ_REG(TPS65224_IRQ_GPIO3, 2, TPS65224_BIT_GPIO3_INT), + REGMAP_IRQ_REG(TPS65224_IRQ_GPIO4, 2, TPS65224_BIT_GPIO4_INT), + REGMAP_IRQ_REG(TPS65224_IRQ_GPIO5, 2, TPS65224_BIT_GPIO5_INT), + REGMAP_IRQ_REG(TPS65224_IRQ_GPIO6, 2, TPS65224_BIT_GPIO6_INT), + + /* INT_STARTUP register */ + REGMAP_IRQ_REG(TPS65224_IRQ_VSENSE, 3, TPS65224_BIT_VSENSE_INT), + REGMAP_IRQ_REG(TPS65224_IRQ_ENABLE, 3, TPS6594_BIT_ENABLE_INT), + REGMAP_IRQ_REG(TPS65224_IRQ_PB_SHORT, 3, TPS65224_BIT_PB_SHORT_INT), + REGMAP_IRQ_REG(TPS65224_IRQ_FSD, 3, TPS6594_BIT_FSD_INT), + REGMAP_IRQ_REG(TPS65224_IRQ_SOFT_REBOOT, 3, TPS6594_BIT_SOFT_REBOOT_INT), + + /* INT_MISC register */ + REGMAP_IRQ_REG(TPS65224_IRQ_BIST_PASS, 4, TPS6594_BIT_BIST_PASS_INT), + REGMAP_IRQ_REG(TPS65224_IRQ_EXT_CLK, 4, TPS6594_BIT_EXT_CLK_INT), + REGMAP_IRQ_REG(TPS65224_IRQ_REG_UNLOCK, 4, TPS65224_BIT_REG_UNLOCK_INT), + REGMAP_IRQ_REG(TPS65224_IRQ_TWARN, 4, TPS6594_BIT_TWARN_INT), + REGMAP_IRQ_REG(TPS65224_IRQ_PB_LONG, 4, TPS65224_BIT_PB_LONG_INT), + REGMAP_IRQ_REG(TPS65224_IRQ_PB_FALL, 4, TPS65224_BIT_PB_FALL_INT), + REGMAP_IRQ_REG(TPS65224_IRQ_PB_RISE, 4, TPS65224_BIT_PB_RISE_INT), + REGMAP_IRQ_REG(TPS65224_IRQ_ADC_CONV_READY, 4, TPS65224_BIT_ADC_CONV_READY_INT), + + /* INT_MODERATE_ERR register */ + REGMAP_IRQ_REG(TPS65224_IRQ_TSD_ORD, 5, TPS6594_BIT_TSD_ORD_INT), + REGMAP_IRQ_REG(TPS65224_IRQ_BIST_FAIL, 5, TPS6594_BIT_BIST_FAIL_INT), + REGMAP_IRQ_REG(TPS65224_IRQ_REG_CRC_ERR, 5, TPS6594_BIT_REG_CRC_ERR_INT), + REGMAP_IRQ_REG(TPS65224_IRQ_RECOV_CNT, 5, TPS6594_BIT_RECOV_CNT_INT), + + /* INT_SEVERE_ERR register */ + REGMAP_IRQ_REG(TPS65224_IRQ_TSD_IMM, 6, TPS6594_BIT_TSD_IMM_INT), + REGMAP_IRQ_REG(TPS65224_IRQ_VCCA_OVP, 6, TPS6594_BIT_VCCA_OVP_INT), + REGMAP_IRQ_REG(TPS65224_IRQ_PFSM_ERR, 6, TPS6594_BIT_PFSM_ERR_INT), + REGMAP_IRQ_REG(TPS65224_IRQ_BG_XMON, 6, TPS65224_BIT_BG_XMON_INT), + + /* INT_FSM_ERR register */ + REGMAP_IRQ_REG(TPS65224_IRQ_IMM_SHUTDOWN, 7, TPS6594_BIT_IMM_SHUTDOWN_INT), + REGMAP_IRQ_REG(TPS65224_IRQ_ORD_SHUTDOWN, 7, TPS6594_BIT_ORD_SHUTDOWN_INT), + REGMAP_IRQ_REG(TPS65224_IRQ_MCU_PWR_ERR, 7, TPS6594_BIT_MCU_PWR_ERR_INT), + REGMAP_IRQ_REG(TPS65224_IRQ_SOC_PWR_ERR, 7, TPS6594_BIT_SOC_PWR_ERR_INT), + REGMAP_IRQ_REG(TPS65224_IRQ_COMM_ERR, 7, TPS6594_BIT_COMM_ERR_INT), + REGMAP_IRQ_REG(TPS65224_IRQ_I2C2_ERR, 7, TPS65224_BIT_I2C2_ERR_INT), +}; + static inline unsigned int tps6594_get_irq_reg(struct regmap_irq_chip_data *data, unsigned int base, int index) { @@ -443,7 +503,7 @@ static int tps6594_handle_post_irq(void *irq_drv_data) * a new interrupt. */ if (tps->use_crc) { - if (tps->chip_id == TPS65224) { + if (tps->chip_id == TPS65224 || tps->chip_id == TPS652G1) { regmap_reg = TPS6594_REG_INT_FSM_ERR; mask_val = TPS6594_BIT_COMM_ERR_INT; } else { @@ -481,6 +541,18 @@ static struct regmap_irq_chip tps65224_irq_chip = { .handle_post_irq = tps6594_handle_post_irq, }; +static struct regmap_irq_chip tps652g1_irq_chip = { + .ack_base = TPS6594_REG_INT_BUCK, + .ack_invert = 1, + .clear_ack = 1, + .init_ack_masked = 1, + .num_regs = ARRAY_SIZE(tps65224_irq_reg), + .irqs = tps652g1_irqs, + .num_irqs = ARRAY_SIZE(tps652g1_irqs), + .get_irq_reg = tps65224_get_irq_reg, + .handle_post_irq = tps6594_handle_post_irq, +}; + static const struct regmap_range tps6594_volatile_ranges[] = { regmap_reg_range(TPS6594_REG_INT_TOP, TPS6594_REG_STAT_READBACK_ERR), regmap_reg_range(TPS6594_REG_RTC_STATUS, TPS6594_REG_RTC_STATUS), @@ -507,7 +579,7 @@ static int tps6594_check_crc_mode(struct tps6594 *tps, bool primary_pmic) int ret; unsigned int regmap_reg, mask_val; - if (tps->chip_id == TPS65224) { + if (tps->chip_id == TPS65224 || tps->chip_id == TPS652G1) { regmap_reg = TPS6594_REG_CONFIG_2; mask_val = TPS65224_BIT_I2C1_SPI_CRC_EN; } else { @@ -537,7 +609,7 @@ static int tps6594_set_crc_feature(struct tps6594 *tps) int ret; unsigned int regmap_reg, mask_val; - if (tps->chip_id == TPS65224) { + if (tps->chip_id == TPS65224 || tps->chip_id == TPS652G1) { regmap_reg = TPS6594_REG_CONFIG_2; mask_val = TPS65224_BIT_I2C1_SPI_CRC_EN; } else { @@ -628,6 +700,10 @@ int tps6594_device_init(struct tps6594 *tps, bool enable_crc) irq_chip = &tps65224_irq_chip; n_cells = ARRAY_SIZE(tps65224_common_cells); cells = tps65224_common_cells; + } else if (tps->chip_id == TPS652G1) { + irq_chip = &tps652g1_irq_chip; + n_cells = ARRAY_SIZE(tps652g1_common_cells); + cells = tps652g1_common_cells; } else { irq_chip = &tps6594_irq_chip; n_cells = ARRAY_SIZE(tps6594_common_cells); @@ -651,8 +727,8 @@ int tps6594_device_init(struct tps6594 *tps, bool enable_crc) if (ret) return dev_err_probe(dev, ret, "Failed to add common child devices\n"); - /* No RTC for LP8764 and TPS65224 */ - if (tps->chip_id != LP8764 && tps->chip_id != TPS65224) { + /* No RTC for LP8764, TPS65224 and TPS652G1 */ + if (tps->chip_id != LP8764 && tps->chip_id != TPS65224 && tps->chip_id != TPS652G1) { ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, tps6594_rtc_cells, ARRAY_SIZE(tps6594_rtc_cells), NULL, 0, regmap_irq_get_domain(tps->irq_data)); diff --git a/drivers/mfd/tps6594-i2c.c b/drivers/mfd/tps6594-i2c.c index 4ab91c34d9fb..7ff7516286fd 100644 --- a/drivers/mfd/tps6594-i2c.c +++ b/drivers/mfd/tps6594-i2c.c @@ -1,6 +1,11 @@ // SPDX-License-Identifier: GPL-2.0 /* - * I2C access driver for TI TPS65224/TPS6594/TPS6593/LP8764 PMICs + * I2C access driver for the following TI PMICs: + * - LP8764 + * - TPS65224 + * - TPS652G1 + * - TPS6593 + * - TPS6594 * * Copyright (C) 2023 BayLibre Incorporated - https://www.baylibre.com/ */ @@ -197,6 +202,7 @@ static const struct of_device_id tps6594_i2c_of_match_table[] = { { .compatible = "ti,tps6593-q1", .data = (void *)TPS6593, }, { .compatible = "ti,lp8764-q1", .data = (void *)LP8764, }, { .compatible = "ti,tps65224-q1", .data = (void *)TPS65224, }, + { .compatible = "ti,tps652g1", .data = (void *)TPS652G1, }, {} }; MODULE_DEVICE_TABLE(of, tps6594_i2c_of_match_table); @@ -222,7 +228,7 @@ static int tps6594_i2c_probe(struct i2c_client *client) return dev_err_probe(dev, -EINVAL, "Failed to find matching chip ID\n"); tps->chip_id = (unsigned long)match->data; - if (tps->chip_id == TPS65224) + if (tps->chip_id == TPS65224 || tps->chip_id == TPS652G1) tps6594_i2c_regmap_config.volatile_table = &tps65224_volatile_table; tps->regmap = devm_regmap_init(dev, NULL, client, &tps6594_i2c_regmap_config); diff --git a/drivers/mfd/tps6594-spi.c b/drivers/mfd/tps6594-spi.c index 6ebccb79f0cc..944b7313a1d9 100644 --- a/drivers/mfd/tps6594-spi.c +++ b/drivers/mfd/tps6594-spi.c @@ -1,6 +1,11 @@ // SPDX-License-Identifier: GPL-2.0 /* - * SPI access driver for TI TPS65224/TPS6594/TPS6593/LP8764 PMICs + * SPI access driver for the following TI PMICs: + * - LP8764 + * - TPS65224 + * - TPS652G1 + * - TPS6593 + * - TPS6594 * * Copyright (C) 2023 BayLibre Incorporated - https://www.baylibre.com/ */ @@ -82,6 +87,7 @@ static const struct of_device_id tps6594_spi_of_match_table[] = { { .compatible = "ti,tps6593-q1", .data = (void *)TPS6593, }, { .compatible = "ti,lp8764-q1", .data = (void *)LP8764, }, { .compatible = "ti,tps65224-q1", .data = (void *)TPS65224, }, + { .compatible = "ti,tps652g1", .data = (void *)TPS652G1, }, {} }; MODULE_DEVICE_TABLE(of, tps6594_spi_of_match_table); @@ -107,7 +113,7 @@ static int tps6594_spi_probe(struct spi_device *spi) return dev_err_probe(dev, -EINVAL, "Failed to find matching chip ID\n"); tps->chip_id = (unsigned long)match->data; - if (tps->chip_id == TPS65224) + if (tps->chip_id == TPS65224 || tps->chip_id == TPS652G1) tps6594_spi_regmap_config.volatile_table = &tps65224_volatile_table; tps->regmap = devm_regmap_init(dev, NULL, spi, &tps6594_spi_regmap_config); diff --git a/include/linux/mfd/tps6594.h b/include/linux/mfd/tps6594.h index 16543fd4d83e..021db8875963 100644 --- a/include/linux/mfd/tps6594.h +++ b/include/linux/mfd/tps6594.h @@ -19,6 +19,7 @@ enum pmic_id { TPS6593, LP8764, TPS65224, + TPS652G1, }; /* Macro to get page index from register address */ From patchwork Wed Jun 11 13:31:35 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 896343 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A3D2F289E1F; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="fryDemnV" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7C94AC4CEF0; Wed, 11 Jun 2025 13:31:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749648721; bh=t3yyyPtYSSN5S7rDQcxHS9f6gCwsZYMm59++llawt4E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fryDemnVQpv+tVyuQG3jhK4aB+IcuJ8h5sce9KHrLR8v1mmyxdznhjHTnqomCwhQP jjm+elQ7E/f+MVuVYwyNA0MV1ehwZ+hxB/tBR0BY1saX6vUlXurpNGIDBwQgvoRIKn LHyG7IDBrCthi9vz8EjYEtEhGeHUumDOdLSUqibG6+rqOeoBrWIACB878XNmm78duj IwNkDuWgOJuvH7FYiry2YaOYizmsedXTfaDgYwMaT0RvM/VCTlHPqPur1TDDIq7qSE RNRhVkat6NNupzgjRwvxnVla1csOlhnEEYxSXrKEYSnQuTrmnERTYsY40QuvEmU7lZ DgExRtRteV5Yg== From: Michael Walle To: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Arnd Bergmann , Greg Kroah-Hartman , Linus Walleij , Liam Girdwood , Mark Brown , Julien Panis Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Michael Walle Subject: [PATCH v1 3/5] misc: tps6594-pfsm: Add TI TPS652G1 PMIC PFSM Date: Wed, 11 Jun 2025 15:31:35 +0200 Message-Id: <20250611133137.1686183-4-mwalle@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250611133137.1686183-1-mwalle@kernel.org> References: <20250611133137.1686183-1-mwalle@kernel.org> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The TPS652G1 is a stripped down TPS65224, but the PFSM is the same. Thus, handle it the same way as the TPS65224 in the driver. Signed-off-by: Michael Walle --- drivers/misc/tps6594-pfsm.c | 31 +++++++++++++++++++++---------- 1 file changed, 21 insertions(+), 10 deletions(-) diff --git a/drivers/misc/tps6594-pfsm.c b/drivers/misc/tps6594-pfsm.c index 6db1c9d48f8f..44fa81d6cec2 100644 --- a/drivers/misc/tps6594-pfsm.c +++ b/drivers/misc/tps6594-pfsm.c @@ -1,6 +1,12 @@ // SPDX-License-Identifier: GPL-2.0 /* - * PFSM (Pre-configurable Finite State Machine) driver for TI TPS65224/TPS6594/TPS6593/LP8764 PMICs + * PFSM (Pre-configurable Finite State Machine) driver for the following + * PMICs: + * - LP8764 + * - TPS65224 + * - TPS652G1 + * - TPS6594 + * - TPS6593 * * Copyright (C) 2023 BayLibre Incorporated - https://www.baylibre.com/ */ @@ -141,7 +147,7 @@ static long tps6594_pfsm_ioctl(struct file *f, unsigned int cmd, unsigned long a switch (cmd) { case PMIC_GOTO_STANDBY: /* Disable LP mode on TPS6594 Family PMIC */ - if (pfsm->chip_id != TPS65224) { + if (pfsm->chip_id != TPS65224 && pfsm->chip_id != TPS652G1) { ret = regmap_clear_bits(pfsm->regmap, TPS6594_REG_RTC_CTRL_2, TPS6594_BIT_LP_STANDBY_SEL); @@ -154,8 +160,8 @@ static long tps6594_pfsm_ioctl(struct file *f, unsigned int cmd, unsigned long a TPS6594_BIT_TRIGGER_I2C(0), TPS6594_BIT_TRIGGER_I2C(0)); break; case PMIC_GOTO_LP_STANDBY: - /* TPS65224 does not support LP STANDBY */ - if (pfsm->chip_id == TPS65224) + /* TPS65224/TPS652G1 does not support LP STANDBY */ + if (pfsm->chip_id == TPS65224 || pfsm->chip_id == TPS652G1) return ret; /* Enable LP mode */ @@ -179,8 +185,8 @@ static long tps6594_pfsm_ioctl(struct file *f, unsigned int cmd, unsigned long a TPS6594_BIT_NSLEEP1B | TPS6594_BIT_NSLEEP2B); break; case PMIC_SET_MCU_ONLY_STATE: - /* TPS65224 does not support MCU_ONLY_STATE */ - if (pfsm->chip_id == TPS65224) + /* TPS65224/TPS652G1 does not support MCU_ONLY_STATE */ + if (pfsm->chip_id == TPS65224 || pfsm->chip_id == TPS652G1) return ret; if (copy_from_user(&state_opt, argp, sizeof(state_opt))) @@ -206,7 +212,7 @@ static long tps6594_pfsm_ioctl(struct file *f, unsigned int cmd, unsigned long a return -EFAULT; /* Configure wake-up destination */ - if (pfsm->chip_id == TPS65224) { + if (pfsm->chip_id == TPS65224 || pfsm->chip_id == TPS652G1) { regmap_reg = TPS65224_REG_STARTUP_CTRL; mask = TPS65224_MASK_STARTUP_DEST; } else { @@ -230,9 +236,14 @@ static long tps6594_pfsm_ioctl(struct file *f, unsigned int cmd, unsigned long a return ret; /* Modify NSLEEP1-2 bits */ - ret = regmap_clear_bits(pfsm->regmap, TPS6594_REG_FSM_NSLEEP_TRIGGERS, - pfsm->chip_id == TPS65224 ? - TPS6594_BIT_NSLEEP1B : TPS6594_BIT_NSLEEP2B); + if (pfsm->chip_id == TPS65224 || pfsm->chip_id == TPS652G1) + ret = regmap_clear_bits(pfsm->regmap, + TPS6594_REG_FSM_NSLEEP_TRIGGERS, + TPS6594_BIT_NSLEEP1B); + else + ret = regmap_clear_bits(pfsm->regmap, + TPS6594_REG_FSM_NSLEEP_TRIGGERS, + TPS6594_BIT_NSLEEP2B); break; } From patchwork Wed Jun 11 13:31:36 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 895601 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 217C9289E1F; Wed, 11 Jun 2025 13:32:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749648725; cv=none; b=IaQWkKXpVaOYDzwMi17rbowYiB+8Ee+3djwMgnmxxICC0ZhQ3/qWbUaX4yoEM40ylaqMiN14RMkpRwFox1vW0cZXfL+kFb9kCpajRFSiPv4asNdYlQ4qjMCRkGJeOzgfV3DjuX/B3VAp4pt2MC2AagxJP1tpQkwfIIWm7TEz44I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749648725; c=relaxed/simple; bh=CgXQt18/fwfG+U7n7eKXWqZxA7sWPstObh3sA0/OouM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=EtUc0s95EpM4QDd7m6TUKXLKI+x1kjAHfTQdHGiimtnXN8TQB82f/jOa5J3UwxAVqQ1mWecmQrLiaGyQSRdVYVJ+DUx2Dg/NmFK3aeQ6Lp5aCSn1cIyKBNnjrRH//IWPicVEiqtlKZkFCMIuJTaDQoBIu8wVRzzOFIjByoy3cQM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=hlmMHru7; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="hlmMHru7" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A5A7EC4CEF4; Wed, 11 Jun 2025 13:32:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749648724; bh=CgXQt18/fwfG+U7n7eKXWqZxA7sWPstObh3sA0/OouM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hlmMHru7HFol1ghdl033YDScAmzNCNRHC1Meyb+2Raiy9hPFW3VCruL1iMGndhiFb nwT8Iu2DFfzExQ6BfVb8tWyIACwXyKVFLkb1+jv+cqivdD9owBJxuMfvf1AGxOZZrG c6PpsjwN6RkJqkimDPOZN/aI4/vowpYZtuRZSOnInR0wJlj3SJy6sP0NlD8oM+jIIi KQ60GZLySmtFyj341o1yCpQG8oUeK5c8wQJRjckYqo0259eOaeC075zxbzFyikwolJ kIMRai+aUepw7o13lvmw6AIvol9YIAiqvfKMbKDDbXLzjRAc8P30C23rchLxIcmc9X NIF1eNFwpURWA== From: Michael Walle To: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Arnd Bergmann , Greg Kroah-Hartman , Linus Walleij , Liam Girdwood , Mark Brown , Julien Panis Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Michael Walle Subject: [PATCH v1 4/5] pinctrl: pinctrl-tps6594: Add TPS652G1 PMIC pinctrl and GPIO Date: Wed, 11 Jun 2025 15:31:36 +0200 Message-Id: <20250611133137.1686183-5-mwalle@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250611133137.1686183-1-mwalle@kernel.org> References: <20250611133137.1686183-1-mwalle@kernel.org> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The TPS652G1 is a stripped down version of the TPS65224. Compared to the TPS65224 it lacks some pin mux functions, like the ADC, voltage monitoring and the second I2C bus. Signed-off-by: Michael Walle --- drivers/pinctrl/pinctrl-tps6594.c | 35 +++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/pinctrl/pinctrl-tps6594.c b/drivers/pinctrl/pinctrl-tps6594.c index 54cc810f79d6..6726853110d1 100644 --- a/drivers/pinctrl/pinctrl-tps6594.c +++ b/drivers/pinctrl/pinctrl-tps6594.c @@ -226,6 +226,10 @@ static const char *const tps65224_nerr_mcu_func_group_names[] = { "GPIO5", }; +static const char *const tps652g1_cs_spi_func_group_names[] = { + "GPIO1", +}; + struct tps6594_pinctrl_function { struct pinfunction pinfunction; u8 muxval; @@ -287,6 +291,18 @@ static const struct tps6594_pinctrl_function tps65224_pinctrl_functions[] = { FUNCTION(tps65224, nerr_mcu, TPS65224_PINCTRL_NERR_MCU_FUNCTION), }; +static const struct tps6594_pinctrl_function tps652g1_pinctrl_functions[] = { + FUNCTION(tps65224, gpio, TPS6594_PINCTRL_GPIO_FUNCTION), + FUNCTION(tps65224, sda_i2c2_sdo_spi, TPS65224_PINCTRL_SDA_I2C2_SDO_SPI_FUNCTION), + FUNCTION(tps65224, nsleep2, TPS65224_PINCTRL_NSLEEP2_FUNCTION), + FUNCTION(tps65224, nint, TPS65224_PINCTRL_NINT_FUNCTION), + FUNCTION(tps652g1, cs_spi, TPS65224_PINCTRL_SCL_I2C2_CS_SPI_FUNCTION), + FUNCTION(tps65224, nsleep1, TPS65224_PINCTRL_NSLEEP1_FUNCTION), + FUNCTION(tps65224, pb, TPS65224_PINCTRL_PB_FUNCTION), + FUNCTION(tps65224, wkup, TPS65224_PINCTRL_WKUP_FUNCTION), + FUNCTION(tps65224, syncclkin, TPS65224_PINCTRL_SYNCCLKIN_FUNCTION), +}; + struct tps6594_pinctrl { struct tps6594 *tps; struct gpio_regmap *gpio_regmap; @@ -300,6 +316,16 @@ struct tps6594_pinctrl { struct muxval_remap *remap; }; +static struct tps6594_pinctrl tps652g1_template_pinctrl = { + .funcs = tps652g1_pinctrl_functions, + .func_cnt = ARRAY_SIZE(tps652g1_pinctrl_functions), + .pins = tps65224_pins, + .num_pins = ARRAY_SIZE(tps65224_pins), + .mux_sel_mask = TPS65224_MASK_GPIO_SEL, + .remap = tps65224_muxval_remap, + .remap_cnt = ARRAY_SIZE(tps65224_muxval_remap), +}; + static struct tps6594_pinctrl tps65224_template_pinctrl = { .funcs = tps65224_pinctrl_functions, .func_cnt = ARRAY_SIZE(tps65224_pinctrl_functions), @@ -475,6 +501,15 @@ static int tps6594_pinctrl_probe(struct platform_device *pdev) return -ENOMEM; switch (tps->chip_id) { + case TPS652G1: + pctrl_desc->pins = tps65224_pins; + pctrl_desc->npins = ARRAY_SIZE(tps65224_pins); + + *pinctrl = tps652g1_template_pinctrl; + + config.ngpio = ARRAY_SIZE(tps65224_gpio_func_group_names); + config.ngpio_per_reg = TPS65224_NGPIO_PER_REG; + break; case TPS65224: pctrl_desc->pins = tps65224_pins; pctrl_desc->npins = ARRAY_SIZE(tps65224_pins); From patchwork Wed Jun 11 13:31:37 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 896342 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F01182BCF7B; Wed, 11 Jun 2025 13:32:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749648728; cv=none; b=GZw2kWLm8HdRWfpGuNVrghMysISuHN+4ygKCPvzAZJpQXpnfXsWPMpyR86MByPs4U8WQW9fqH1FyU/2AG+UycW4TDCz/JbNfXgDVLIcxCA49pqc0TgVZRs5YKR/xlLDbtwey9ZNSeq/OPxlP461F2WbGEhWzlV3qQ785xfbmdVI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749648728; c=relaxed/simple; bh=XiSy6EA+nY4FGmZhH6fU8zZo9na9VIQe0Qv5BQB5i4Q=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=fu2tnuJ+3srdC6kXil0iIxzEpp3+2L1c9eHht7ka16C7Xx1eHO5LRgU32cTXf2xXN1qLkgk+Fv2c2bD+7t9DyYF5pQXsGa4BY3EWV8CN1YI3005b2zqHuf0DEJqju68ZqpYWSIVB5Dn+MagAtGg8Z/5HW52TvpRM0pgywCWYLHo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=PgmfmKQR; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="PgmfmKQR" Received: by smtp.kernel.org (Postfix) with ESMTPSA id CC86FC4CEEE; Wed, 11 Jun 2025 13:32:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749648727; bh=XiSy6EA+nY4FGmZhH6fU8zZo9na9VIQe0Qv5BQB5i4Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PgmfmKQRS/2BiTQLkQf3VrOESp1mSELSO8JW8xYjcW9+8Azsf7eVB/1mgqeyvXqLM Dw959O/+9soTBcH2N9EAcTdbDTM1uLvmEv/6VRFWrfBGhqcjoyALC9D4SKTWKSWcvb OdbIf3V780ZLj1+gxwzpNBVpvYzpbowc1rLuKsWwvnNlhdErmWlqL+oxNpOblHniq7 +ycrYK0IhBNh80rl8UfuWzhwLhQlhEdCeZ4CZxe9ZSYH+JKsfzCGC+4HhX/w7t6R0/ 55b46pcOrkuXz7GqscwjpnMFOQC6uuiEhs+3F8iU4eosaLvI/zytb8akJtk+tTbuSU Egvy3QKmSW1MA== From: Michael Walle To: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Arnd Bergmann , Greg Kroah-Hartman , Linus Walleij , Liam Girdwood , Mark Brown , Julien Panis Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Michael Walle Subject: [PATCH v1 5/5] regulator: tps6594-regulator: Add TI TPS652G1 PMIC regulators Date: Wed, 11 Jun 2025 15:31:37 +0200 Message-Id: <20250611133137.1686183-6-mwalle@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250611133137.1686183-1-mwalle@kernel.org> References: <20250611133137.1686183-1-mwalle@kernel.org> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The TI TPS652G1 is a stripped down version of the TPS65224 PMIC. It doesn't feature the multiphase buck converter nor any voltage monitoring. Due to the latter there are no interrupts serviced. In case of the TPS652G1 any interrupt related setup is just skipped. Signed-off-by: Michael Walle --- drivers/regulator/tps6594-regulator.c | 41 +++++++++++++++++++++------ 1 file changed, 33 insertions(+), 8 deletions(-) diff --git a/drivers/regulator/tps6594-regulator.c b/drivers/regulator/tps6594-regulator.c index 51264c869aa0..401bc9ca4cd6 100644 --- a/drivers/regulator/tps6594-regulator.c +++ b/drivers/regulator/tps6594-regulator.c @@ -578,6 +578,7 @@ static int tps6594_regulator_probe(struct platform_device *pdev) const struct tps6594_regulator_irq_type **ldos_irq_types; const struct regulator_desc *ldo_regs; size_t interrupt_count; + const struct regulator_desc *buck_cfg; if (tps->chip_id == TPS65224) { bucks_irq_types = tps65224_bucks_irq_types; @@ -586,6 +587,12 @@ static int tps6594_regulator_probe(struct platform_device *pdev) ldos_irq_types = tps65224_ldos_irq_types; ldo_regs = tps65224_ldo_regs; multi_phase_cnt = ARRAY_SIZE(tps65224_multi_regs); + buck_cfg = tps65224_buck_regs; + } else if (tps->chip_id == TPS652G1) { + ldo_regs = tps65224_ldo_regs; + /* TPS652G1 doesn't have multi phase buck converters */ + multi_phase_cnt = 0; + buck_cfg = tps65224_buck_regs; } else { bucks_irq_types = tps6594_bucks_irq_types; interrupt_count = ARRAY_SIZE(tps6594_buck1_irq_types); @@ -593,6 +600,7 @@ static int tps6594_regulator_probe(struct platform_device *pdev) ldos_irq_types = tps6594_ldos_irq_types; ldo_regs = tps6594_ldo_regs; multi_phase_cnt = ARRAY_SIZE(tps6594_multi_regs); + buck_cfg = buck_regs; } enum { @@ -657,18 +665,24 @@ static int tps6594_regulator_probe(struct platform_device *pdev) nr_buck = ARRAY_SIZE(tps65224_buck_regs); nr_ldo = ARRAY_SIZE(tps65224_ldo_regs); nr_types = TPS65224_REGS_INT_NB; + } else if (tps->chip_id == TPS652G1) { + nr_buck = ARRAY_SIZE(tps65224_buck_regs); + nr_ldo = ARRAY_SIZE(tps65224_ldo_regs); } else { nr_buck = ARRAY_SIZE(buck_regs); nr_ldo = (tps->chip_id == LP8764) ? 0 : ARRAY_SIZE(tps6594_ldo_regs); nr_types = REGS_INT_NB; } - reg_irq_nb = nr_types * (nr_buck + nr_ldo); + if (tps->chip_id != TPS652G1) { + reg_irq_nb = nr_types * (nr_buck + nr_ldo); - irq_data = devm_kmalloc_array(tps->dev, reg_irq_nb, - sizeof(struct tps6594_regulator_irq_data), GFP_KERNEL); - if (!irq_data) - return -ENOMEM; + irq_data = devm_kmalloc_array(tps->dev, reg_irq_nb, + sizeof(struct tps6594_regulator_irq_data), + GFP_KERNEL); + if (!irq_data) + return -ENOMEM; + } for (i = 0; i < multi_phase_cnt; i++) { if (!buck_multi[i]) @@ -680,6 +694,10 @@ static int tps6594_regulator_probe(struct platform_device *pdev) "failed to register %s regulator\n", pdev->name); + /* skip interrupts */ + if (tps->chip_id == TPS652G1) + continue; + /* config multiphase buck12+buck34 */ if (i == MULTI_BUCK12_34) buck_idx = 2; @@ -718,14 +736,15 @@ static int tps6594_regulator_probe(struct platform_device *pdev) if (buck_configured[i]) continue; - const struct regulator_desc *buck_cfg = (tps->chip_id == TPS65224) ? - tps65224_buck_regs : buck_regs; - rdev = devm_regulator_register(&pdev->dev, &buck_cfg[i], &config); if (IS_ERR(rdev)) return dev_err_probe(tps->dev, PTR_ERR(rdev), "failed to register %s regulator\n", pdev->name); + /* skip interrupts */ + if (tps->chip_id == TPS652G1) + continue; + error = tps6594_request_reg_irqs(pdev, rdev, irq_data, bucks_irq_types[i], interrupt_count, &irq_idx); if (error) @@ -741,6 +760,10 @@ static int tps6594_regulator_probe(struct platform_device *pdev) "failed to register %s regulator\n", pdev->name); + /* skip interrupts */ + if (tps->chip_id == TPS652G1) + continue; + error = tps6594_request_reg_irqs(pdev, rdev, irq_data, ldos_irq_types[i], interrupt_count, &irq_idx); @@ -752,6 +775,8 @@ static int tps6594_regulator_probe(struct platform_device *pdev) if (tps->chip_id == TPS65224) { irq_types = tps65224_ext_regulator_irq_types; irq_count = ARRAY_SIZE(tps65224_ext_regulator_irq_types); + } else if (tps->chip_id == TPS652G1) { + irq_count = 0; } else { irq_types = tps6594_ext_regulator_irq_types; if (tps->chip_id == LP8764)