From patchwork Fri Jun 13 21:49:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Pandruvada X-Patchwork-Id: 896577 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8104819D08F; Fri, 13 Jun 2025 21:49:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.8 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749851367; cv=none; b=uOc+xq9IOaNUPUWvLY+YYhX0ibT65uqhvJD7XjMzx+ekx7YeL0PNnVXvnYALkQugqtspszZtJokEDqC/2QTGh+rhCOEgZA2LIGasTNJv/RPavTINE1ThxiK0IYIOMonFKKnGP2otJ88Nf+wldt6l/ktklLXPCGX9W1IjpDKKMKU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749851367; c=relaxed/simple; bh=urs2hnsQJwCZzHIoPIJEarCIpXTJCaDwpM2e4xSJVyc=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=u/YI5d+Z9RnJzKJtXVTe/di+UmBJbwxUTRNX65MAiytOinmihEB00CTZIHlJlHTdLyjbYIcbD+b2NzMBJS0mRdeI4yGW9e3b1PfZTiDEAgLZnVGLxs4jhZgE1gOPJaf3iaar+z5PVC03cUm8KuKCxUVrf6TY4zis4j1sQqQPVcM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Q4z/nB58; arc=none smtp.client-ip=192.198.163.8 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Q4z/nB58" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1749851366; x=1781387366; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=urs2hnsQJwCZzHIoPIJEarCIpXTJCaDwpM2e4xSJVyc=; b=Q4z/nB5850L7JfUcljvc7U9zje6GZwdAc5uNn4lQjFNZaFEOMBL3pLsE VCqEj53vsDk1wQY3fS+qEqHuPeoqNYEsUjfYFQ7M3APM5IUOeFiBYvPlR ix7du1flNgLx061K6XxnQ3BNUuRwf2+ZTkfCQKz//3kxvmGXJDMAd9F1E f7O6ivXJW9Tyb/nUqkP6sCadnBsudo499D54oJcnbLTc+MW6mhT6DXSDG BP/Cb33iSsOe9/VHlf8AJFNGHIHDd/jODdonRkHRGyZ2roMp4DtE2Hn/I A1hBxHPDggKD0Dr+GJtf63ynkk0IGaOXP6ncYZYe2xhSYYzzcqA3g0N/8 w==; X-CSE-ConnectionGUID: BSKCO3aJTcKqNLp1E8BT8A== X-CSE-MsgGUID: wbr7WKfuRI26ofq73j1wMQ== X-IronPort-AV: E=McAfee;i="6800,10657,11463"; a="69656422" X-IronPort-AV: E=Sophos;i="6.16,234,1744095600"; d="scan'208";a="69656422" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jun 2025 14:49:25 -0700 X-CSE-ConnectionGUID: Zvo5RG4cQJKuN76Zzv4ItA== X-CSE-MsgGUID: +AG4nj0NRtSGdenQ6e++oA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,234,1744095600"; d="scan'208";a="178822019" Received: from spandruv-desk.jf.intel.com ([10.54.75.16]) by orviesa002.jf.intel.com with ESMTP; 13 Jun 2025 14:49:24 -0700 From: Srinivas Pandruvada To: rui.zhang@intel.com, daniel.lezcano@linaro.org, rafael@kernel.org, lukasz.luba@arm.com Cc: linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Srinivas Pandruvada Subject: [PATCH v2 1/2] thermal: intel: int340x: Add throttling control interface to PTC Date: Fri, 13 Jun 2025 14:49:22 -0700 Message-ID: <20250613214923.2910397-1-srinivas.pandruvada@linux.intel.com> X-Mailer: git-send-email 2.48.1 Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Firmware-based thermal temperature control loops may aggressively throttle performance to prevent temperature overshoots relative to the defined target temperature. This can negatively impact performance. User space may prefer to prioritize performance, even if it results in temperature overshoots with in acceptable range. For example, user space might tolerate temperature overshoots when the device is placed on a desk, as opposed to when it's on a lap. To accommodate such scenarios, an optional attribute is provided to specify a tolerance level for temperature overshoots while maintaining acceptable performance. Attribute: thermal_tolerance: This attribute ranges from 0 to 7, where 0 represents the most aggressive control to avoid any temperature overshoots, and 7 represents a more graceful approach, favoring performance even at the expense of temperature overshoots. Note: This level may not scale linearly. For example, a value of 3 does not necessarily imply a 50% improvement in performance compared to a value of 0. Signed-off-by: Srinivas Pandruvada Reviewed-by: Zhang Rui --- v2: - Changed commit description - Change "gain" to "thermal_tolerance" analogous to latency_tolerance. - Dropped "min_performance" attribute for next patch set Documentation/driver-api/thermal/intel_dptf.rst | 9 +++++++++ .../intel/int340x_thermal/platform_temperature_control.c | 8 +++++++- 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/Documentation/driver-api/thermal/intel_dptf.rst b/Documentation/driver-api/thermal/intel_dptf.rst index ec5769accae0..c51ac793dc06 100644 --- a/Documentation/driver-api/thermal/intel_dptf.rst +++ b/Documentation/driver-api/thermal/intel_dptf.rst @@ -206,6 +206,15 @@ All these controls needs admin privilege to update. Update a new temperature target in milli degree celsius for hardware to use for the temperature control. +``thermal_tolerance`` (RW) + This attribute ranges from 0 to 7, where 0 represents + the most aggressive control to avoid any temperature overshoots, and + 7 represents a more graceful approach, favoring performance even at + the expense of temperature overshoots. + Note: This level may not scale linearly. For example, a value of 3 does + not necessarily imply a 50% improvement in performance compared to a + value of 0. + Given that this is platform temperature control, it is expected that a single user-level manager owns and manages the controls. If multiple user-level software applications attempt to write different targets, it diff --git a/drivers/thermal/intel/int340x_thermal/platform_temperature_control.c b/drivers/thermal/intel/int340x_thermal/platform_temperature_control.c index 2d6504514893..7850e91a6e2c 100644 --- a/drivers/thermal/intel/int340x_thermal/platform_temperature_control.c +++ b/drivers/thermal/intel/int340x_thermal/platform_temperature_control.c @@ -49,7 +49,7 @@ struct mmio_reg { }; #define MAX_ATTR_GROUP_NAME_LEN 32 -#define PTC_MAX_ATTRS 3 +#define PTC_MAX_ATTRS 4 struct ptc_data { u32 offset; @@ -57,6 +57,7 @@ struct ptc_data { struct attribute *ptc_attrs[PTC_MAX_ATTRS]; struct device_attribute temperature_target_attr; struct device_attribute enable_attr; + struct device_attribute thermal_tolerance_attr; char group_name[MAX_ATTR_GROUP_NAME_LEN]; }; @@ -78,6 +79,7 @@ static u32 ptc_offsets[PTC_MAX_INSTANCES] = {0x5B20, 0x5B28, 0x5B30}; static const char * const ptc_strings[] = { "temperature_target", "enable", + "thermal_tolerance", NULL }; @@ -177,6 +179,8 @@ PTC_SHOW(temperature_target); PTC_STORE(temperature_target); PTC_SHOW(enable); PTC_STORE(enable); +PTC_SHOW(thermal_tolerance); +PTC_STORE(thermal_tolerance); #define ptc_init_attribute(_name)\ do {\ @@ -193,9 +197,11 @@ static int ptc_create_groups(struct pci_dev *pdev, int instance, struct ptc_data ptc_init_attribute(temperature_target); ptc_init_attribute(enable); + ptc_init_attribute(thermal_tolerance); data->ptc_attrs[index++] = &data->temperature_target_attr.attr; data->ptc_attrs[index++] = &data->enable_attr.attr; + data->ptc_attrs[index++] = &data->thermal_tolerance_attr.attr; data->ptc_attrs[index] = NULL; snprintf(data->group_name, MAX_ATTR_GROUP_NAME_LEN, From patchwork Fri Jun 13 21:49:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Srinivas Pandruvada X-Patchwork-Id: 896129 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5511B266562; 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X-CSE-ConnectionGUID: ixqproggTZKZWBeVWr0HhQ== X-CSE-MsgGUID: Q8cffoPSQ46Tmxm+7mJejw== X-IronPort-AV: E=McAfee;i="6800,10657,11463"; a="69656426" X-IronPort-AV: E=Sophos;i="6.16,234,1744095600"; d="scan'208";a="69656426" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jun 2025 14:49:25 -0700 X-CSE-ConnectionGUID: dnpmjTXnSy6PWHEflWr+wA== X-CSE-MsgGUID: LceKpaVyTqyvPTIxy8J1/w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,234,1744095600"; d="scan'208";a="178822022" Received: from spandruv-desk.jf.intel.com ([10.54.75.16]) by orviesa002.jf.intel.com with ESMTP; 13 Jun 2025 14:49:24 -0700 From: Srinivas Pandruvada To: rui.zhang@intel.com, daniel.lezcano@linaro.org, rafael@kernel.org, lukasz.luba@arm.com Cc: linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Srinivas Pandruvada Subject: [PATCH v2 2/2] thermal: intel: int340x: Allow temperature override Date: Fri, 13 Jun 2025 14:49:23 -0700 Message-ID: <20250613214923.2910397-2-srinivas.pandruvada@linux.intel.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250613214923.2910397-1-srinivas.pandruvada@linux.intel.com> References: <20250613214923.2910397-1-srinivas.pandruvada@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add debugfs interface to override hardware provide temperature. This interface can be used primarily for debug. Alternatively this can be also used to use hardware control loops to manage temperature for virtual sensors. Virtual sensors are soft sensors created by kernel/ user space aggregating other sensors. There are three attributes to override the maximum three instances of platform temperature control. /sys/kernel/debug/platform_temperature_control/ ├── temperature_0 ├── temperature_1 └── temperature_2 These are write only attributes requires admin privilege. Any value greater than 0, will override the temperature. A value of 0 will stop overriding the temperature. Signed-off-by: Srinivas Pandruvada Reviewed-by: Zhang Rui --- v2: - correct platform spelling - Move the ptc_create_debugfs under PROC_THERMAL_FEATURE_PTC mask .../platform_temperature_control.c | 64 +++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/drivers/thermal/intel/int340x_thermal/platform_temperature_control.c b/drivers/thermal/intel/int340x_thermal/platform_temperature_control.c index 7850e91a6e2c..0ccc72c93499 100644 --- a/drivers/thermal/intel/int340x_thermal/platform_temperature_control.c +++ b/drivers/thermal/intel/int340x_thermal/platform_temperature_control.c @@ -38,6 +38,7 @@ #include #include +#include #include #include "processor_thermal_device.h" @@ -53,6 +54,7 @@ struct mmio_reg { struct ptc_data { u32 offset; + struct pci_dev *pdev; struct attribute_group ptc_attr_group; struct attribute *ptc_attrs[PTC_MAX_ATTRS]; struct device_attribute temperature_target_attr; @@ -215,6 +217,63 @@ static int ptc_create_groups(struct pci_dev *pdev, int instance, struct ptc_data } static struct ptc_data ptc_instance[PTC_MAX_INSTANCES]; +static struct dentry *ptc_debugfs; + +#define PTC_TEMP_OVERRIDE_ENABLE_INDEX 4 +#define PTC_TEMP_OVERRIDE_INDEX 5 + +static ssize_t ptc_temperature_write(struct file *file, const char __user *data, + size_t count, loff_t *ppos) +{ + struct ptc_data *ptc_instance = file->private_data; + struct pci_dev *pdev = ptc_instance->pdev; + char buf[32]; + ssize_t len; + u32 value; + + len = min(count, sizeof(buf) - 1); + if (copy_from_user(buf, data, len)) + return -EFAULT; + + buf[len] = '\0'; + if (kstrtouint(buf, 0, &value)) + return -EINVAL; + + if (ptc_mmio_regs[PTC_TEMP_OVERRIDE_INDEX].units) + value /= ptc_mmio_regs[PTC_TEMP_OVERRIDE_INDEX].units; + + if (value > ptc_mmio_regs[PTC_TEMP_OVERRIDE_INDEX].mask) + return -EINVAL; + + if (!value) { + ptc_mmio_write(pdev, ptc_instance->offset, PTC_TEMP_OVERRIDE_ENABLE_INDEX, 0); + } else { + ptc_mmio_write(pdev, ptc_instance->offset, PTC_TEMP_OVERRIDE_INDEX, value); + ptc_mmio_write(pdev, ptc_instance->offset, PTC_TEMP_OVERRIDE_ENABLE_INDEX, 1); + } + + return count; +} + +static const struct file_operations ptc_fops = { + .open = simple_open, + .write = ptc_temperature_write, + .llseek = generic_file_llseek, +}; + +static void ptc_create_debugfs(void) +{ + ptc_debugfs = debugfs_create_dir("platform_temperature_control", NULL); + + debugfs_create_file("temperature_0", 0200, ptc_debugfs, &ptc_instance[0], &ptc_fops); + debugfs_create_file("temperature_1", 0200, ptc_debugfs, &ptc_instance[1], &ptc_fops); + debugfs_create_file("temperature_2", 0200, ptc_debugfs, &ptc_instance[2], &ptc_fops); +} + +static void ptc_delete_debugfs(void) +{ + debugfs_remove_recursive(ptc_debugfs); +} int proc_thermal_ptc_add(struct pci_dev *pdev, struct proc_thermal_device *proc_priv) { @@ -223,8 +282,11 @@ int proc_thermal_ptc_add(struct pci_dev *pdev, struct proc_thermal_device *proc_ for (i = 0; i < PTC_MAX_INSTANCES; i++) { ptc_instance[i].offset = ptc_offsets[i]; + ptc_instance[i].pdev = pdev; ptc_create_groups(pdev, i, &ptc_instance[i]); } + + ptc_create_debugfs(); } return 0; @@ -240,6 +302,8 @@ void proc_thermal_ptc_remove(struct pci_dev *pdev) for (i = 0; i < PTC_MAX_INSTANCES; i++) sysfs_remove_group(&pdev->dev.kobj, &ptc_instance[i].ptc_attr_group); + + ptc_delete_debugfs(); } } EXPORT_SYMBOL_GPL(proc_thermal_ptc_remove);