From patchwork Sun Jun 15 03:57:57 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cool Lee X-Patchwork-Id: 896829 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F264D261594; Sun, 15 Jun 2025 03:58:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749959905; cv=none; b=HqEERH9OATCq7thQyUpf8gdgkmP+vJTec3kK+PFpV+44CWneLC8d/CUKBIwP4p0I6g1IZ4Z3MX8XHDIxmz5JUW4EO7rfiHBLCKjS+ylmtzD4rpxuFJdCrqbpG4zCc2arsCWGJHlgcjZmMXmC6ysOD3IfyQeKyqwXxNEtilTP3gY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749959905; c=relaxed/simple; bh=VjgsOmIJ9Mb0Jav/XPstTX5AuEcJo/LGKS32VPtQbK4=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=mzczqHE64ImG/q9jhy3EvM4krowm9bnVTpVraljFTnRVRUhBVUsg3VMIwoTWqYjxh21PQKc3kVy0fI15Tfz0Dd1a64xz/H1RmWlxS6VP0JY/RRgXa2aznxn9iW3M6Yc1oKtnN/QyNHQnSfI3WB+aulub5E4tnynrjzgqti8I7Rs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Sun, 15 Jun 2025 11:58:03 +0800 Received: from mail.aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Sun, 15 Jun 2025 11:58:03 +0800 From: Cool Lee To: , , , , , , , , , Subject: [PATCH 2/8] mmc: sdhci-of-aspeed: Add runtime tuning Date: Sun, 15 Jun 2025 11:57:57 +0800 Message-ID: <20250615035803.3752235-3-cool_lee@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250615035803.3752235-1-cool_lee@aspeedtech.com> References: <20250615035803.3752235-1-cool_lee@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add support for runtime tuning in the Aspeed SDHCI driver. Using the timing phase register to adjust the clock phase with mmc tuning command to find the left and right boundary. Signed-off-by: Cool Lee --- drivers/mmc/host/sdhci-of-aspeed.c | 68 ++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/drivers/mmc/host/sdhci-of-aspeed.c b/drivers/mmc/host/sdhci-of-aspeed.c index 01bc574272eb..5e5ae1894456 100644 --- a/drivers/mmc/host/sdhci-of-aspeed.c +++ b/drivers/mmc/host/sdhci-of-aspeed.c @@ -24,6 +24,7 @@ #define ASPEED_SDC_PHASE 0xf4 #define ASPEED_SDC_S1_PHASE_IN GENMASK(25, 21) #define ASPEED_SDC_S0_PHASE_IN GENMASK(20, 16) +#define ASPEED_SDC_S0_PHASE_IN_SHIFT 16 #define ASPEED_SDC_S1_PHASE_OUT GENMASK(15, 11) #define ASPEED_SDC_S1_PHASE_IN_EN BIT(10) #define ASPEED_SDC_S1_PHASE_OUT_EN GENMASK(9, 8) @@ -375,6 +376,72 @@ static void aspeed_sdhci_reset(struct sdhci_host *host, u8 mask) sdhci_reset(host, mask); } +static int aspeed_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) +{ + struct sdhci_pltfm_host *pltfm_priv; + struct aspeed_sdhci *sdhci; + struct aspeed_sdc *sdc; + struct device *dev; + + u32 val, left, right, edge; + u32 window, oldwindow = 0, center; + u32 in_phase, out_phase, enable_mask, inverted = 0; + + dev = mmc_dev(host->mmc); + pltfm_priv = sdhci_priv(host); + sdhci = sdhci_pltfm_priv(pltfm_priv); + sdc = sdhci->parent; + + out_phase = readl(sdc->regs + ASPEED_SDC_PHASE) & ASPEED_SDC_S0_PHASE_OUT; + + enable_mask = ASPEED_SDC_S0_PHASE_OUT_EN | ASPEED_SDC_S0_PHASE_IN_EN; + + /* + * There are two window upon clock rising and falling edge. + * Iterate each tap delay to find the valid window and choose the + * bigger one, set the tap delay at the middle of window. + */ + for (edge = 0; edge < 2; edge++) { + if (edge == 1) + inverted = ASPEED_SDHCI_TAP_PARAM_INVERT_CLK; + + val = (out_phase | enable_mask | (inverted << ASPEED_SDC_S0_PHASE_IN_SHIFT)); + + /* find the left boundary */ + for (left = 0; left < ASPEED_SDHCI_NR_TAPS + 1; left++) { + in_phase = val | (left << ASPEED_SDC_S0_PHASE_IN_SHIFT); + writel(in_phase, sdc->regs + ASPEED_SDC_PHASE); + + if (!mmc_send_tuning(host->mmc, opcode, NULL)) + break; + } + + /* find the right boundary */ + for (right = left + 1; right < ASPEED_SDHCI_NR_TAPS + 1; right++) { + in_phase = val | (right << ASPEED_SDC_S0_PHASE_IN_SHIFT); + writel(in_phase, sdc->regs + ASPEED_SDC_PHASE); + + if (mmc_send_tuning(host->mmc, opcode, NULL)) + break; + } + + window = right - left; + dev_info(dev, "tuning window = %d\n", window); + + if (window > oldwindow) { + oldwindow = window; + center = (((right - 1) + left) / 2) | inverted; + } + } + + val = (out_phase | enable_mask | (center << ASPEED_SDC_S0_PHASE_IN_SHIFT)); + writel(val, sdc->regs + ASPEED_SDC_PHASE); + + dev_info(dev, "tuning result=%x\n", val); + + return mmc_send_tuning(host->mmc, opcode, NULL); +} + static const struct sdhci_ops aspeed_sdhci_ops = { .read_l = aspeed_sdhci_readl, .set_clock = aspeed_sdhci_set_clock, @@ -383,6 +450,7 @@ static const struct sdhci_ops aspeed_sdhci_ops = { .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, .reset = aspeed_sdhci_reset, .set_uhs_signaling = sdhci_set_uhs_signaling, + .platform_execute_tuning = aspeed_sdhci_execute_tuning, }; static const struct sdhci_pltfm_data aspeed_sdhci_pdata = { From patchwork Sun Jun 15 03:57:59 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cool Lee X-Patchwork-Id: 896828 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CEDA0262FE9; Sun, 15 Jun 2025 03:58:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749959909; cv=none; b=HJY4M11qVYWyAoVS56NgEDYEsjg3kz5fq5RwxnHqx0+BMk0NJfG/wbaQ8AHMWwUf4YLJdjP+XbQk0GXn4G1bKNCW1OIk1SFUSZ5U/mzhkrkxgkevyTCgKzSemooVHEUm/yAI3cV4d0aply51caQlK6ksuoO02pKuibp92J3nAhI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749959909; c=relaxed/simple; bh=kj0fa6FUnZIfFY0VTTCuMa2DO67jndNJVpVLb3+Bfbk=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=kfJo63cDZAeVK8vKT8UeMAwebm6IkUX5qIfdWgT/d2xkxbflyhl+DLRyCE9C/iicgVY1rDP5aOmwfmffqCHG+I1BQa0DfAI13IF7dlFT+E85eAfE5+kZHuNnx5CKNXRaIaHgqcaOSP6evTNEgcrTZ6S9vy1rykL4+s44vhEsR6c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Sun, 15 Jun 2025 11:58:04 +0800 Received: from mail.aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Sun, 15 Jun 2025 11:58:04 +0800 From: Cool Lee To: , , , , , , , , , Subject: [PATCH 4/8] mmc: sdhci-of-aspeed: Get max clockk by using default api Date: Sun, 15 Jun 2025 11:57:59 +0800 Message-ID: <20250615035803.3752235-5-cool_lee@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250615035803.3752235-1-cool_lee@aspeedtech.com> References: <20250615035803.3752235-1-cool_lee@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Don't limit clock frequency by f_max. Signed-off-by: Cool Lee --- drivers/mmc/host/sdhci-of-aspeed.c | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/drivers/mmc/host/sdhci-of-aspeed.c b/drivers/mmc/host/sdhci-of-aspeed.c index 10160a706334..2bdd93a3f91f 100644 --- a/drivers/mmc/host/sdhci-of-aspeed.c +++ b/drivers/mmc/host/sdhci-of-aspeed.c @@ -288,14 +288,6 @@ static void aspeed_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) sdhci_enable_clk(host, clk); } -static unsigned int aspeed_sdhci_get_max_clock(struct sdhci_host *host) -{ - if (host->mmc->f_max) - return host->mmc->f_max; - - return sdhci_pltfm_clk_get_max_clock(host); -} - static void aspeed_sdhci_set_bus_width(struct sdhci_host *host, int width) { struct sdhci_pltfm_host *pltfm_priv; @@ -446,7 +438,7 @@ static int aspeed_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) static const struct sdhci_ops aspeed_sdhci_ops = { .read_l = aspeed_sdhci_readl, .set_clock = aspeed_sdhci_set_clock, - .get_max_clock = aspeed_sdhci_get_max_clock, + .get_max_clock = sdhci_pltfm_clk_get_max_clock, .set_bus_width = aspeed_sdhci_set_bus_width, .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, .reset = aspeed_sdhci_reset, From patchwork Sun Jun 15 03:58:01 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cool Lee X-Patchwork-Id: 896827 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DF3DE264608; Sun, 15 Jun 2025 03:58:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749959913; cv=none; b=e3vj0luoGXvReqYKlk9fq/eGI2VHnNNa+qbHckdykp5oDH3tCwUsS601YqoSxrRDXJifwXcvhIy8m8hu64spS7L47oln3Sfc5yOanHeXcIcwRlGky63KSj5tSXSSaqDfyqfPcDX+ourdeWpHJqJVnuspFARDpLStSXuIra1mPMY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749959913; c=relaxed/simple; bh=bHUS/Tk9LMBg9lQIuPHoyB6SeTAcyZ0KY8ozl+YM+RE=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Eo+8XUk3vvwwKnOft3OdPE98YIq0UjBMPLLpXpvldzmtCTrV7njTWerEbNijRWMvKAgFjHOZoZE4HDnqaGfXw3wqcn9hCvLSyCSKcCpRc03vKKk2DHaGK6EoIVS5ofMNci/Ba1t8r+w8lnQebaPsnEjJFl6bzVT+MTt7tfiBQu8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Sun, 15 Jun 2025 11:58:04 +0800 Received: from mail.aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Sun, 15 Jun 2025 11:58:04 +0800 From: Cool Lee To: , , , , , , , , , Subject: [PATCH 6/8] mmc: sdhci-of-aspeed: Add output timing phase tuning Date: Sun, 15 Jun 2025 11:58:01 +0800 Message-ID: <20250615035803.3752235-7-cool_lee@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250615035803.3752235-1-cool_lee@aspeedtech.com> References: <20250615035803.3752235-1-cool_lee@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Enhance auto tuning with input and output calibration. Signed-off-by: Cool Lee --- drivers/mmc/host/sdhci-of-aspeed.c | 48 ++++++++++++++++++++++++++++-- 1 file changed, 46 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/sdhci-of-aspeed.c b/drivers/mmc/host/sdhci-of-aspeed.c index 22dde915e51b..92687fc30d1d 100644 --- a/drivers/mmc/host/sdhci-of-aspeed.c +++ b/drivers/mmc/host/sdhci-of-aspeed.c @@ -25,6 +25,7 @@ #define ASPEED_SDC_S1_PHASE_IN GENMASK(25, 21) #define ASPEED_SDC_S0_PHASE_IN GENMASK(20, 16) #define ASPEED_SDC_S0_PHASE_IN_SHIFT 16 +#define ASPEED_SDC_S0_PHASE_OUT_SHIFT 3 #define ASPEED_SDC_S1_PHASE_OUT GENMASK(15, 11) #define ASPEED_SDC_S1_PHASE_IN_EN BIT(10) #define ASPEED_SDC_S1_PHASE_OUT_EN GENMASK(9, 8) @@ -422,7 +423,7 @@ static int aspeed_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) } window = right - left; - dev_info(dev, "tuning window = %d\n", window); + dev_dbg(dev, "tuning window[%d][%d~%d] = %d\n", edge, left, right, window); if (window > oldwindow) { oldwindow = window; @@ -433,7 +434,50 @@ static int aspeed_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) val = (out_phase | enable_mask | (center << ASPEED_SDC_S0_PHASE_IN_SHIFT)); writel(val, sdc->regs + ASPEED_SDC_PHASE); - dev_info(dev, "tuning result=%x\n", val); + dev_dbg(dev, "input tuning result=%x\n", val); + + inverted = 0; + out_phase = val & ~ASPEED_SDC_S0_PHASE_OUT; + in_phase = out_phase; + oldwindow = 0; + + for (edge = 0; edge < 2; edge++) { + if (edge == 1) + inverted = ASPEED_SDHCI_TAP_PARAM_INVERT_CLK; + + val = (in_phase | enable_mask | (inverted << ASPEED_SDC_S0_PHASE_OUT_SHIFT)); + + /* find the left boundary */ + for (left = 0; left < ASPEED_SDHCI_NR_TAPS + 1; left++) { + out_phase = val | (left << ASPEED_SDC_S0_PHASE_OUT_SHIFT); + writel(out_phase, sdc->regs + ASPEED_SDC_PHASE); + + if (!mmc_send_tuning(host->mmc, opcode, NULL)) + break; + } + + /* find the right boundary */ + for (right = left + 1; right < ASPEED_SDHCI_NR_TAPS + 1; right++) { + out_phase = val | (right << ASPEED_SDC_S0_PHASE_OUT_SHIFT); + writel(out_phase, sdc->regs + ASPEED_SDC_PHASE); + + if (mmc_send_tuning(host->mmc, opcode, NULL)) + break; + } + + window = right - left; + dev_info(dev, "tuning window[%d][%d~%d] = %d\n", edge, left, right, window); + + if (window > oldwindow) { + oldwindow = window; + center = (((right - 1) + left) / 2) | inverted; + } + } + + val = (in_phase | enable_mask | (center << ASPEED_SDC_S0_PHASE_OUT_SHIFT)); + writel(val, sdc->regs + ASPEED_SDC_PHASE); + + dev_dbg(dev, "output tuning result=%x\n", val); return mmc_send_tuning(host->mmc, opcode, NULL); } From patchwork Sun Jun 15 03:58:03 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cool Lee X-Patchwork-Id: 896826 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E468F26528E; Sun, 15 Jun 2025 03:58:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749959919; cv=none; b=r+a5cElkhvl+YcfpYs/1cIrD8Vh2Yjmj3Oa4doyOQKNKcl8/Q13Xwl0a/w+JOmaZD73j70HdQ/Yx9BQcIhCncelLbqiG7suk3N+Z51BqAqH3zf07hfsReN3+Fkvl+AvDsildlKYDZiwq8x8dW8merZBEQfUyGnZVc71yt6Dk7q4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749959919; c=relaxed/simple; bh=lSminI9thQ4D1Cmx3meEA7cWQlap1VEYZBL1D6u9zH0=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=MVwSi+vihrnq4ToRMynWKvNTgy5yGeyVunGL2buxRjfJyzWir8WzQSnWnFbnnWrbevURfABgQQ7xYhXWDzdr61Makf/BixLB4zF4EtV/Tz5qFs6b0ZZLsBGEqlvds0m1ezylhCXcU8qSRoJl0W6QQBDA9WpGB1yDcnGt+2IUwZE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Sun, 15 Jun 2025 11:58:04 +0800 Received: from mail.aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Sun, 15 Jun 2025 11:58:04 +0800 From: Cool Lee To: , , , , , , , , , Subject: [PATCH 8/8] mmc: sdhci-of-aspeed: Add sdr50 support Date: Sun, 15 Jun 2025 11:58:03 +0800 Message-ID: <20250615035803.3752235-9-cool_lee@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250615035803.3752235-1-cool_lee@aspeedtech.com> References: <20250615035803.3752235-1-cool_lee@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add support for SDR50 mode in the Aspeed SDHCI driver by setting capability shadow register. Signed-off-by: Cool Lee --- drivers/mmc/host/sdhci-of-aspeed.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/mmc/host/sdhci-of-aspeed.c b/drivers/mmc/host/sdhci-of-aspeed.c index 365c02215273..ec6833295b6a 100644 --- a/drivers/mmc/host/sdhci-of-aspeed.c +++ b/drivers/mmc/host/sdhci-of-aspeed.c @@ -41,6 +41,7 @@ #define ASPEED_SDC_CAP1_1_8V (0 * 32 + 26) /* SDIO{14,24} */ #define ASPEED_SDC_CAP2_SDR104 (1 * 32 + 1) +#define ASPEED_SDC_CAP2_SDR50 (1 * 32 + 0) struct aspeed_sdc { struct clk *clk; @@ -427,11 +428,17 @@ static int aspeed_sdhci_probe(struct platform_device *pdev) sdhci_get_of_property(pdev); if (of_property_read_bool(np, "mmc-hs200-1_8v") || + of_property_read_bool(np, "sd-uhs-sdr50") || of_property_read_bool(np, "sd-uhs-sdr104")) { aspeed_sdc_set_slot_capability(host, dev->parent, ASPEED_SDC_CAP1_1_8V, true, slot); } + if (of_property_read_bool(np, "sd-uhs-sdr50")) { + aspeed_sdc_set_slot_capability(host, dev->parent, ASPEED_SDC_CAP2_SDR50, + true, slot); + } + if (of_property_read_bool(np, "sd-uhs-sdr104")) { aspeed_sdc_set_slot_capability(host, dev->parent, ASPEED_SDC_CAP2_SDR104, true, slot);