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Acked-by: Rob Herring (Arm) Acked-by: Arnd Bergmann Reviewed-by: Linus Walleij Reviewed-by: Youngmin Nam Tested-by: Youngmin Nam Signed-off-by: Will McVicker --- drivers/of/irq.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/of/irq.c b/drivers/of/irq.c index f8ad79b9b1c9..5adda1dac3cf 100644 --- a/drivers/of/irq.c +++ b/drivers/of/irq.c @@ -519,6 +519,7 @@ int of_irq_count(struct device_node *dev) return nr; } +EXPORT_SYMBOL_GPL(of_irq_count); /** * of_irq_to_resource_table - Fill in resource table with node's IRQ info From patchwork Wed Jun 18 21:08:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will McVicker X-Patchwork-Id: 897888 Received: from mail-pf1-f202.google.com (mail-pf1-f202.google.com [209.85.210.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 46853263892 for ; Wed, 18 Jun 2025 21:09:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Wed, 18 Jun 2025 14:09:06 -0700 (PDT) Date: Wed, 18 Jun 2025 14:08:40 -0700 In-Reply-To: <20250618210851.661527-1-willmcvicker@google.com> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250618210851.661527-1-willmcvicker@google.com> X-Mailer: git-send-email 2.50.0.rc2.761.g2dc52ea45b-goog Message-ID: <20250618210851.661527-4-willmcvicker@google.com> Subject: [PATCH 3/6] clocksource/drivers/exynos_mct: Set local timer interrupts as percpu From: Will McVicker To: Catalin Marinas , Will Deacon , Daniel Lezcano , Thomas Gleixner , Krzysztof Kozlowski , Alim Akhtar , Rob Herring , Saravana Kannan Cc: Will McVicker , Donghoon Yu , Hosung Kim , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, John Stultz , Youngmin Nam , Peter Griffin , Tudor Ambarus , " =?utf-8?q?Andr=C3=A9_Draszik?= " , Conor Dooley , linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org From: Hosung Kim To allow the CPU to handle it's own clock events, we need to set the IRQF_PERCPU flag. This prevents the local timer interrupts from migrating to other CPUs. Signed-off-by: Hosung Kim [Original commit from https://android.googlesource.com/kernel/gs/+/03267fad19f093bac979ca78309483e9eb3a8d16] Reviewed-by: Peter Griffin Reviewed-by: Youngmin Nam Tested-by: Youngmin Nam Signed-off-by: Will McVicker --- drivers/clocksource/exynos_mct.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c index 96361d5dc57d..a5ef7d64b1c2 100644 --- a/drivers/clocksource/exynos_mct.c +++ b/drivers/clocksource/exynos_mct.c @@ -596,7 +596,8 @@ static int __init exynos4_timer_interrupts(struct device_node *np, irq_set_status_flags(mct_irq, IRQ_NOAUTOEN); if (request_irq(mct_irq, exynos4_mct_tick_isr, - IRQF_TIMER | IRQF_NOBALANCING, + IRQF_TIMER | IRQF_NOBALANCING | + IRQF_PERCPU, pcpu_mevt->name, pcpu_mevt)) { pr_err("exynos-mct: cannot register IRQ (cpu%d)\n", cpu); From patchwork Wed Jun 18 21:08:42 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will McVicker X-Patchwork-Id: 897887 Received: from mail-pg1-f201.google.com (mail-pg1-f201.google.com [209.85.215.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A7BC266F15 for ; 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Wed, 18 Jun 2025 14:09:15 -0700 (PDT) Date: Wed, 18 Jun 2025 14:08:42 -0700 In-Reply-To: <20250618210851.661527-1-willmcvicker@google.com> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250618210851.661527-1-willmcvicker@google.com> X-Mailer: git-send-email 2.50.0.rc2.761.g2dc52ea45b-goog Message-ID: <20250618210851.661527-6-willmcvicker@google.com> Subject: [PATCH 5/6] clocksource/drivers/exynos_mct: Add module support From: Will McVicker To: Catalin Marinas , Will Deacon , Daniel Lezcano , Thomas Gleixner , Krzysztof Kozlowski , Alim Akhtar , Rob Herring , Saravana Kannan Cc: Will McVicker , Donghoon Yu , Hosung Kim , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, John Stultz , Youngmin Nam , Peter Griffin , Tudor Ambarus , " =?utf-8?q?Andr=C3=A9_Draszik?= " , Conor Dooley , linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org From: Donghoon Yu On Arm64 platforms the Exynos MCT driver can be built as a module. On boot (and even after boot) the arch_timer is used as the clocksource and tick timer. Once the MCT driver is loaded, it can be used as the wakeup source for the arch_timer. Signed-off-by: Donghoon Yu Signed-off-by: Youngmin Nam [original commit from https://android.googlesource.com/kernel/gs/+/8a52a8288ec7d88ff78f0b37480dbb0e9c65bbfd] Reviewed-by: Youngmin Nam Tested-by: Youngmin Nam Signed-off-by: Will McVicker --- drivers/clocksource/Kconfig | 3 +- drivers/clocksource/exynos_mct.c | 51 ++++++++++++++++++++++++++------ 2 files changed, 44 insertions(+), 10 deletions(-) diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 645f517a1ac2..d657c8ddc96b 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -451,7 +451,8 @@ config ATMEL_TCB_CLKSRC Support for Timer Counter Blocks on Atmel SoCs. config CLKSRC_EXYNOS_MCT - bool "Exynos multi core timer driver" if COMPILE_TEST + tristate "Exynos multi core timer driver" if ARM64 + default y if ARCH_EXYNOS || COMPILE_TEST depends on ARM || ARM64 depends on ARCH_ARTPEC || ARCH_EXYNOS || COMPILE_TEST help diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c index 62febeb4e1de..5075ebe052a7 100644 --- a/drivers/clocksource/exynos_mct.c +++ b/drivers/clocksource/exynos_mct.c @@ -15,9 +15,11 @@ #include #include #include +#include #include #include #include +#include #include #include @@ -217,6 +219,7 @@ static struct clocksource mct_frc = { .mask = CLOCKSOURCE_MASK(32), .flags = CLOCK_SOURCE_IS_CONTINUOUS, .resume = exynos4_frc_resume, + .owner = THIS_MODULE, }; /* @@ -241,7 +244,7 @@ static cycles_t exynos4_read_current_timer(void) } #endif -static int __init exynos4_clocksource_init(bool frc_shared) +static int exynos4_clocksource_init(bool frc_shared) { /* * When the frc is shared, the main processor should have already @@ -336,6 +339,7 @@ static struct clock_event_device mct_comp_device = { .set_state_oneshot = mct_set_state_shutdown, .set_state_oneshot_stopped = mct_set_state_shutdown, .tick_resume = mct_set_state_shutdown, + .owner = THIS_MODULE, }; static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id) @@ -476,6 +480,7 @@ static int exynos4_mct_starting_cpu(unsigned int cpu) evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERCPU; evt->rating = MCT_CLKEVENTS_RATING; + evt->owner = THIS_MODULE; exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET); @@ -511,7 +516,7 @@ static int exynos4_mct_dying_cpu(unsigned int cpu) return 0; } -static int __init exynos4_timer_resources(struct device_node *np) +static int exynos4_timer_resources(struct device_node *np) { struct clk *mct_clk, *tick_clk; @@ -539,7 +544,7 @@ static int __init exynos4_timer_resources(struct device_node *np) * @local_idx: array mapping CPU numbers to local timer indices * @nr_local: size of @local_idx array */ -static int __init exynos4_timer_interrupts(struct device_node *np, +static int exynos4_timer_interrupts(struct device_node *np, unsigned int int_type, const u32 *local_idx, size_t nr_local) @@ -652,7 +657,7 @@ static int __init exynos4_timer_interrupts(struct device_node *np, return err; } -static int __init mct_init_dt(struct device_node *np, unsigned int int_type) +static int mct_init_dt(struct device_node *np, unsigned int int_type) { bool frc_shared = of_property_read_bool(np, "samsung,frc-shared"); u32 local_idx[MCT_NR_LOCAL] = {0}; @@ -700,15 +705,43 @@ static int __init mct_init_dt(struct device_node *np, unsigned int int_type) return exynos4_clockevent_init(); } - -static int __init mct_init_spi(struct device_node *np) +static int mct_init_spi(struct device_node *np) { return mct_init_dt(np, MCT_INT_SPI); } -static int __init mct_init_ppi(struct device_node *np) +static int mct_init_ppi(struct device_node *np) { return mct_init_dt(np, MCT_INT_PPI); } -TIMER_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init_spi); -TIMER_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init_ppi); + +static int exynos4_mct_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + int (*mct_init)(struct device_node *np); + + mct_init = of_device_get_match_data(dev); + if (!mct_init) + return -EINVAL; + + return mct_init(dev->of_node); +} + +static const struct of_device_id exynos4_mct_match_table[] = { + { .compatible = "samsung,exynos4210-mct", .data = &mct_init_spi, }, + { .compatible = "samsung,exynos4412-mct", .data = &mct_init_ppi, }, + {} +}; +MODULE_DEVICE_TABLE(of, exynos4_mct_match_table); + +static struct platform_driver exynos4_mct_driver = { + .probe = exynos4_mct_probe, + .driver = { + .name = "exynos-mct", + .of_match_table = exynos4_mct_match_table, + }, +}; +module_platform_driver(exynos4_mct_driver); + +MODULE_DESCRIPTION("Exynos Multi Core Timer Driver"); +MODULE_LICENSE("GPL");