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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b31f1258932sm410011a12.64.2025.06.19.17.19.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Jun 2025 17:19:20 -0700 (PDT) From: Anjelique Melendez To: amitk@kernel.org, thara.gopinath@gmail.com, rafael@kernel.org, daniel.lezcano@linaro.org Cc: rui.zhang@intel.com, lukasz.luba@arm.com, david.collins@oss.qualcomm.com, stefan.schmidt@linaro.org, quic_tsoni@quicinc.com, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org, dmitry.baryshkov@oss.qualcomm.com Subject: [PATCH v5 1/5] thermal: qcom-spmi-temp-alarm: enable stage 2 shutdown when required Date: Thu, 19 Jun 2025 17:19:14 -0700 Message-Id: <20250620001918.4090853-2-anjelique.melendez@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250620001918.4090853-1-anjelique.melendez@oss.qualcomm.com> References: <20250620001918.4090853-1-anjelique.melendez@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjIwMDAwMCBTYWx0ZWRfX0TZQNq7+fENI 7AyR9KlWu4G09aGy5rNq+gZsyzBx/4fbtAOTmjGpTsDoHZpPYy5NcrCe3gnj3LH+M73XdzsHUBk G5jXv8Gsf/WcRu7psHfGVcxEwhyGSWwSGT/qsVNwI5eQnpSRXMZEQBFRHNlWJMEzEf71x1DcNXj IPlIskBWhX9L99pnya976oxijkn6yVCOip+AexsQtNPpBr+l9Lu8os/PT9zCOMPQ2N0q9+WQoyW NqVW/3FG71G4m67OhhoMHieNfQrOWHy5Kjkw3Hu+iM6upqFsFCAXdo0CZcIu2Ka3zsQ77eNCSss GmythZHEEQRe/NxEeh92NO51C2hV6Z4QJHO0TKcG6En17HzlgFx0G8pyr8lmCAO9zaaVgE92vLC G5k5jNeWeDYG1TBCuBzxgbT6uOXWZGTR2WMSrYXQ9hEGvfRGFCrqCbSMQU+7oa/Gh5Bdu6F1 X-Proofpoint-GUID: bsG4NNHTaOhIund60ZGviMfFRpxaj3zk X-Authority-Analysis: v=2.4 cv=btJMBFai c=1 sm=1 tr=0 ts=6854a90b cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=6IFa9wvqVegA:10 a=EUspDBNiAAAA:8 a=e8SBnR8fKgZMydxn7aMA:9 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-ORIG-GUID: bsG4NNHTaOhIund60ZGviMfFRpxaj3zk X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-06-19_08,2025-06-18_03,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 adultscore=0 lowpriorityscore=0 mlxscore=0 suspectscore=0 clxscore=1015 malwarescore=0 spamscore=0 mlxlogscore=999 bulkscore=0 priorityscore=1501 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506200000 From: David Collins Certain TEMP_ALARM GEN2 PMIC peripherals need over-temperature stage 2 automatic PMIC partial shutdown to be enabled in order to avoid repeated faults in the event of reaching over-temperature stage 3. Modify the stage 2 shutdown control logic to ensure that stage 2 shutdown is enabled on all affected PMICs. Read the digital major and minor revision registers to identify these PMICs. Signed-off-by: David Collins Signed-off-by: Anjelique Melendez --- drivers/thermal/qcom/qcom-spmi-temp-alarm.c | 32 +++++++++++++++++++-- 1 file changed, 29 insertions(+), 3 deletions(-) diff --git a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c index a81e7d6e865f..47248a843591 100644 --- a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c +++ b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2011-2015, 2017, 2020, The Linux Foundation. All rights reserved. + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ #include @@ -16,6 +17,7 @@ #include "../thermal_hwmon.h" +#define QPNP_TM_REG_DIG_MINOR 0x00 #define QPNP_TM_REG_DIG_MAJOR 0x01 #define QPNP_TM_REG_TYPE 0x04 #define QPNP_TM_REG_SUBTYPE 0x05 @@ -78,6 +80,7 @@ struct qpnp_tm_chip { /* protects .thresh, .stage and chip registers */ struct mutex lock; bool initialized; + bool require_s2_shutdown; struct iio_channel *adc; const long (*temp_map)[THRESH_COUNT][STAGE_COUNT]; @@ -255,7 +258,7 @@ static int qpnp_tm_update_critical_trip_temp(struct qpnp_tm_chip *chip, skip: reg |= chip->thresh; - if (disable_s2_shutdown) + if (disable_s2_shutdown && !chip->require_s2_shutdown) reg |= SHUTDOWN_CTRL1_OVERRIDE_S2; return qpnp_tm_write(chip, QPNP_TM_REG_SHUTDOWN_CTRL1, reg); @@ -350,8 +353,8 @@ static int qpnp_tm_probe(struct platform_device *pdev) { struct qpnp_tm_chip *chip; struct device_node *node; - u8 type, subtype, dig_major; - u32 res; + u8 type, subtype, dig_major, dig_minor; + u32 res, dig_revision; int ret, irq; node = pdev->dev.of_node; @@ -402,6 +405,12 @@ static int qpnp_tm_probe(struct platform_device *pdev) return dev_err_probe(&pdev->dev, ret, "could not read dig_major\n"); + ret = qpnp_tm_read(chip, QPNP_TM_REG_DIG_MINOR, &dig_minor); + if (ret < 0) { + dev_err(&pdev->dev, "could not read dig_minor\n"); + return ret; + } + if (type != QPNP_TM_TYPE || (subtype != QPNP_TM_SUBTYPE_GEN1 && subtype != QPNP_TM_SUBTYPE_GEN2)) { dev_err(&pdev->dev, "invalid type 0x%02x or subtype 0x%02x\n", @@ -415,6 +424,23 @@ static int qpnp_tm_probe(struct platform_device *pdev) else chip->temp_map = &temp_map_gen1; + if (chip->subtype == QPNP_TM_SUBTYPE_GEN2) { + dig_revision = (dig_major << 8) | dig_minor; + /* + * Check if stage 2 automatic partial shutdown must remain + * enabled to avoid potential repeated faults upon reaching + * over-temperature stage 3. + */ + switch (dig_revision) { + case 0x0001: + case 0x0002: + case 0x0100: + case 0x0101: + chip->require_s2_shutdown = true; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b31f1258932sm410011a12.64.2025.06.19.17.19.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Jun 2025 17:19:23 -0700 (PDT) From: Anjelique Melendez To: amitk@kernel.org, thara.gopinath@gmail.com, rafael@kernel.org, daniel.lezcano@linaro.org Cc: rui.zhang@intel.com, lukasz.luba@arm.com, david.collins@oss.qualcomm.com, stefan.schmidt@linaro.org, quic_tsoni@quicinc.com, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org, dmitry.baryshkov@oss.qualcomm.com Subject: [PATCH v5 3/5] thermal: qcom-spmi-temp-alarm: Prepare to support additional Temp Alarm subtypes Date: Thu, 19 Jun 2025 17:19:16 -0700 Message-Id: <20250620001918.4090853-4-anjelique.melendez@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250620001918.4090853-1-anjelique.melendez@oss.qualcomm.com> References: <20250620001918.4090853-1-anjelique.melendez@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjIwMDAwMCBTYWx0ZWRfX3jM860OMHj6V myeowXNCqAE1Kq6aBHXO793dx3zu+a3jLSpRYI2ugKb3/1FXgiVmty9BXxPuqVM1cx/rDcnyIix 2qtgBLcW0VBNRKFhF2I+IHEso/kqj9kaN2fRSLOt1VPgvvtqYKCD1ifDqJi99ofp2aprBWcur3O i2WfXmN3/bAlmm6ddU9nwrDT4jtv+co45zPq6uQ8YChpOz5/Np2EuiLupndUA0Th+oAzMANW6DP /IP4VX+EICYTF0QaIK9eTmJfadCoQc/2ay4Bk01TyE4Ic99O2zq3sN7rQAEQiFQB3dm1Hv9VayY Ckl4GvM/S1cjleaZbXRHpSskkiFOUG3zNZUyZL7C6dzGwrdwL9gjCtYoQ6JZVAhkZUEp8Mvcslk +WCc7OL39v/5k36/czAAG1OryBwR7PMgPjaTc7H1bXJOZaQV1LnR6NtHVFZHx2nLha8LWAh5 X-Proofpoint-GUID: 3RVdWTo8S6uLTcBK8SYGeXZJps5Gp4Oq X-Proofpoint-ORIG-GUID: 3RVdWTo8S6uLTcBK8SYGeXZJps5Gp4Oq X-Authority-Analysis: v=2.4 cv=FrIF/3rq c=1 sm=1 tr=0 ts=6854a90d cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=6IFa9wvqVegA:10 a=EUspDBNiAAAA:8 a=VcnGJyyLPHPoHGOjSs8A:9 a=OpyuDcXvxspvyRM73sMx:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-06-19_08,2025-06-18_03,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 spamscore=0 priorityscore=1501 lowpriorityscore=0 adultscore=0 mlxlogscore=999 bulkscore=0 impostorscore=0 malwarescore=0 phishscore=0 mlxscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506200000 In preparation to support newer temp alarm subtypes, add the "ops", "sync_thresholds" and "configure_trip_temps" references to spmi_temp_alarm_data. This will allow for each Temp Alarm subtype to define its own thermal_zone_device_ops and properly initialize and configure thermal trip temperature. Signed-off-by: Anjelique Melendez --- drivers/thermal/qcom/qcom-spmi-temp-alarm.c | 96 ++++++++++++++------- 1 file changed, 67 insertions(+), 29 deletions(-) diff --git a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c index fdabde39a7e5..5991067d3484 100644 --- a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c +++ b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c @@ -71,8 +71,11 @@ static const long temp_map_gen2_v1[THRESH_COUNT][STAGE_COUNT] = { struct qpnp_tm_chip; struct spmi_temp_alarm_data { + const struct thermal_zone_device_ops *ops; const long (*temp_map)[THRESH_COUNT][STAGE_COUNT]; + int (*sync_thresholds)(struct qpnp_tm_chip *chip); int (*get_temp_stage)(struct qpnp_tm_chip *chip); + int (*configure_trip_temps)(struct qpnp_tm_chip *chip); }; struct qpnp_tm_chip { @@ -310,64 +313,97 @@ static irqreturn_t qpnp_tm_isr(int irq, void *data) return IRQ_HANDLED; } +/* Read the hardware default stage threshold temperatures */ +static int qpnp_tm_sync_thresholds(struct qpnp_tm_chip *chip) +{ + u8 reg, threshold; + int ret; + + ret = qpnp_tm_read(chip, QPNP_TM_REG_SHUTDOWN_CTRL1, ®); + if (ret < 0) + return ret; + + threshold = reg & SHUTDOWN_CTRL1_THRESHOLD_MASK; + memcpy(chip->temp_thresh_map, chip->data->temp_map[threshold], + sizeof(chip->temp_thresh_map)); + + return ret; +} + +static int qpnp_tm_configure_trip_temp(struct qpnp_tm_chip *chip) +{ + int crit_temp, ret; + + ret = thermal_zone_get_crit_temp(chip->tz_dev, &crit_temp); + if (ret) + crit_temp = THERMAL_TEMP_INVALID; + + mutex_lock(&chip->lock); + ret = qpnp_tm_update_critical_trip_temp(chip, crit_temp); + mutex_unlock(&chip->lock); + + return ret; +} + static const struct spmi_temp_alarm_data spmi_temp_alarm_data = { + .ops = &qpnp_tm_sensor_ops, .temp_map = &temp_map_gen1, + .sync_thresholds = qpnp_tm_sync_thresholds, + .configure_trip_temps = qpnp_tm_configure_trip_temp, .get_temp_stage = qpnp_tm_gen1_get_temp_stage, }; static const struct spmi_temp_alarm_data spmi_temp_alarm_gen2_data = { + .ops = &qpnp_tm_sensor_ops, .temp_map = &temp_map_gen1, + .sync_thresholds = qpnp_tm_sync_thresholds, + .configure_trip_temps = qpnp_tm_configure_trip_temp, .get_temp_stage = qpnp_tm_gen2_get_temp_stage, }; static const struct spmi_temp_alarm_data spmi_temp_alarm_gen2_rev1_data = { + .ops = &qpnp_tm_sensor_ops, .temp_map = &temp_map_gen2_v1, + .sync_thresholds = qpnp_tm_sync_thresholds, + .configure_trip_temps = qpnp_tm_configure_trip_temp, .get_temp_stage = qpnp_tm_gen2_get_temp_stage, }; /* - * This function initializes the internal temp value based on only the - * current thermal stage and threshold. Setup threshold control and - * disable shutdown override. + * This function intializes the internal temp value based on only the + * current thermal stage and threshold. */ -static int qpnp_tm_init(struct qpnp_tm_chip *chip) +static int qpnp_tm_threshold_init(struct qpnp_tm_chip *chip) { - int crit_temp; - u8 threshold; - u8 reg = 0; int ret; - mutex_lock(&chip->lock); - - ret = qpnp_tm_read(chip, QPNP_TM_REG_SHUTDOWN_CTRL1, ®); + ret = chip->data->sync_thresholds(chip); if (ret < 0) - goto out; - - threshold = reg & SHUTDOWN_CTRL1_THRESHOLD_MASK; - memcpy(chip->temp_thresh_map, chip->data->temp_map[threshold], - sizeof(chip->temp_thresh_map)); - - chip->temp = DEFAULT_TEMP; + return ret; ret = chip->data->get_temp_stage(chip); if (ret < 0) - goto out; + return ret; chip->stage = ret; + chip->temp = DEFAULT_TEMP; if (chip->stage) chip->temp = qpnp_tm_decode_temp(chip, chip->stage); - mutex_unlock(&chip->lock); - - ret = thermal_zone_get_crit_temp(chip->tz_dev, &crit_temp); - if (ret) - crit_temp = THERMAL_TEMP_INVALID; + return ret; +} - mutex_lock(&chip->lock); +/* + * This function intalizes threshold control and disables shutdown override. + */ +static int qpnp_tm_init(struct qpnp_tm_chip *chip) +{ + int ret; + u8 reg = 0; - ret = qpnp_tm_update_critical_trip_temp(chip, crit_temp); + ret = chip->data->configure_trip_temps(chip); if (ret < 0) - goto out; + return ret; /* Enable the thermal alarm PMIC module in always-on mode. */ reg = ALARM_CTRL_FORCE_ENABLE; @@ -375,8 +411,6 @@ static int qpnp_tm_init(struct qpnp_tm_chip *chip) chip->initialized = true; -out: - mutex_unlock(&chip->lock); return ret; } @@ -476,13 +510,17 @@ static int qpnp_tm_probe(struct platform_device *pdev) } } + ret = qpnp_tm_threshold_init(chip); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, "threshold init failed\n"); + /* * Register the sensor before initializing the hardware to be able to * read the trip points. get_temp() returns the default temperature * before the hardware initialization is completed. */ chip->tz_dev = devm_thermal_of_zone_register( - &pdev->dev, 0, chip, &qpnp_tm_sensor_ops); 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b31f1258932sm410011a12.64.2025.06.19.17.19.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Jun 2025 17:19:26 -0700 (PDT) From: Anjelique Melendez To: amitk@kernel.org, thara.gopinath@gmail.com, rafael@kernel.org, daniel.lezcano@linaro.org Cc: rui.zhang@intel.com, lukasz.luba@arm.com, david.collins@oss.qualcomm.com, stefan.schmidt@linaro.org, quic_tsoni@quicinc.com, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org, dmitry.baryshkov@oss.qualcomm.com Subject: [PATCH v5 5/5] thermal: qcom-spmi-temp-alarm: add support for LITE PMIC peripherals Date: Thu, 19 Jun 2025 17:19:18 -0700 Message-Id: <20250620001918.4090853-6-anjelique.melendez@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250620001918.4090853-1-anjelique.melendez@oss.qualcomm.com> References: <20250620001918.4090853-1-anjelique.melendez@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 9XCZyW_TAYhTZ70hQwTIqInyJB6Wp8En X-Authority-Analysis: v=2.4 cv=edY9f6EH c=1 sm=1 tr=0 ts=6854a911 cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=6IFa9wvqVegA:10 a=EUspDBNiAAAA:8 a=rhdsTsYyw6L1dzp8dgcA:9 a=3WC7DwWrALyhR5TkjVHa:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjIwMDAwMCBTYWx0ZWRfX4uHW/TvZ3iw3 0iuYAAMga9SlmrSSKzLaXQZZp3OjG1I6pmO3XO9OT0pPpkz7iXVszvGPnLo2lHzCE8jPaLAcCNW QDDC0SmNIJ8E4gAyw2gNZBqO2c52W4m6RqJtmzbkUMLcgKyvB9jv0l0/UQis8agtwrgZqmRJjXy T+uDyuZw7cZCZ3nWOpqX9BZrzidKGgKRmopYU6LA0s7H/TVrVfdEg1TgwzNbm/CMoXHBw7gDrhc k2XGr9YLfvGSWKMlEtbQ+wKej71Lmcw7COxOj3tvL3A+M/gD482TtrJTHEWDxTXPoKVr7OWgDmj XW7g6V9nv+8lvp3gfFScyKqdLVYlZeyErk5dbugSKrZYLgy7Rbxd2NL/8iEFpWZqKc6QH+IJHLC yXld5TkHVzvmsPA/8DU/8W6EzksNldOTk2dSTl4a00CYC49HbyDYpIKn66bGJi2Fm1BKrHxr X-Proofpoint-GUID: 9XCZyW_TAYhTZ70hQwTIqInyJB6Wp8En X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-06-19_08,2025-06-18_03,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 priorityscore=1501 suspectscore=0 spamscore=0 bulkscore=0 impostorscore=0 mlxscore=0 clxscore=1015 mlxlogscore=999 malwarescore=0 phishscore=0 adultscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506200000 Add support for TEMP_ALARM LITE PMIC peripherals. This subtype utilizes a pair of registers to configure a warning interrupt threshold temperature and an automatic hardware shutdown threshold temperature. Signed-off-by: David Collins Signed-off-by: Anjelique Melendez Reviewed-by: Dmitry Baryshkov --- drivers/thermal/qcom/qcom-spmi-temp-alarm.c | 208 +++++++++++++++++++- 1 file changed, 207 insertions(+), 1 deletion(-) diff --git a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c index 0e0b0a8b2367..71310f67f59a 100644 --- a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c +++ b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c @@ -23,6 +23,7 @@ #define QPNP_TM_REG_TYPE 0x04 #define QPNP_TM_REG_SUBTYPE 0x05 #define QPNP_TM_REG_STATUS 0x08 +#define QPNP_TM_REG_IRQ_STATUS 0x10 #define QPNP_TM_REG_SHUTDOWN_CTRL1 0x40 #define QPNP_TM_REG_ALARM_CTRL 0x46 @@ -30,14 +31,20 @@ #define QPNP_TM_REG_TEMP_DAC_STG1 0x47 #define QPNP_TM_REG_TEMP_DAC_STG2 0x48 #define QPNP_TM_REG_TEMP_DAC_STG3 0x49 +#define QPNP_TM_REG_LITE_TEMP_CFG1 0x50 +#define QPNP_TM_REG_LITE_TEMP_CFG2 0x51 #define QPNP_TM_TYPE 0x09 #define QPNP_TM_SUBTYPE_GEN1 0x08 #define QPNP_TM_SUBTYPE_GEN2 0x09 +#define QPNP_TM_SUBTYPE_LITE 0xC0 #define STATUS_GEN1_STAGE_MASK GENMASK(1, 0) #define STATUS_GEN2_STATE_MASK GENMASK(6, 4) +/* IRQ status only needed for TEMP_ALARM_LITE */ +#define IRQ_STATUS_MASK BIT(0) + #define SHUTDOWN_CTRL1_OVERRIDE_S2 BIT(6) #define SHUTDOWN_CTRL1_THRESHOLD_MASK GENMASK(1, 0) @@ -45,6 +52,8 @@ #define ALARM_CTRL_FORCE_ENABLE BIT(7) +#define LITE_TEMP_CFG_THRESHOLD_MASK GENMASK(3, 2) + #define THRESH_COUNT 4 #define STAGE_COUNT 3 @@ -89,6 +98,19 @@ static const long temp_dac_max[STAGE_COUNT] = { 119375, 159375, 159375 }; +/* + * TEMP_ALARM_LITE has two stages: warning and shutdown with independently + * configured threshold temperatures. + */ + +static const long temp_lite_warning_map[THRESH_COUNT] = { + 115000, 125000, 135000, 145000 +}; + +static const long temp_lite_shutdown_map[THRESH_COUNT] = { + 135000, 145000, 160000, 175000 +}; + /* Temperature in Milli Celsius reported during stage 0 if no ADC is present */ #define DEFAULT_TEMP 37000 @@ -196,6 +218,24 @@ static int qpnp_tm_gen2_get_temp_stage(struct qpnp_tm_chip *chip) return alarm_state_map[ret]; } +/** + * qpnp_tm_lite_get_temp_stage() - return over-temperature stage + * @chip: Pointer to the qpnp_tm chip + * + * Return: alarm interrupt state on success, or errno on failure. + */ +static int qpnp_tm_lite_get_temp_stage(struct qpnp_tm_chip *chip) +{ + u8 reg = 0; + int ret; + + ret = qpnp_tm_read(chip, QPNP_TM_REG_IRQ_STATUS, ®); + if (ret < 0) + return ret; + + return reg & IRQ_STATUS_MASK; +} + /* * This function updates the internal temp value based on the * current thermal stage and threshold as well as the previous stage @@ -377,6 +417,98 @@ static const struct thermal_zone_device_ops qpnp_tm_gen2_rev2_sensor_ops = { .set_trip_temp = qpnp_tm_gen2_rev2_set_trip_temp, }; +static int qpnp_tm_lite_set_temp_thresh(struct qpnp_tm_chip *chip, unsigned int trip, int temp) +{ + int ret, temp_cfg, i; + const long *temp_map; + u8 reg, thresh; + u16 addr; + + WARN_ON(!mutex_is_locked(&chip->lock)); + + if (trip >= STAGE_COUNT) { + dev_err(chip->dev, "invalid TEMP_LITE trip = %d\n", trip); + return -EINVAL; + } + + switch (trip) { + case 0: + temp_map = temp_lite_warning_map; + addr = QPNP_TM_REG_LITE_TEMP_CFG1; + break; + case 1: + /* + * The second trip point is purely in software to facilitate + * a controlled shutdown after the warning threshold is crossed + * but before the automatic hardware shutdown threshold is + * crossed. + */ + return 0; + case 2: + temp_map = temp_lite_shutdown_map; + addr = QPNP_TM_REG_LITE_TEMP_CFG2; + break; + default: + return 0; + } + + if (temp < temp_map[THRESH_MIN] || temp > temp_map[THRESH_MAX]) { + dev_err(chip->dev, "invalid TEMP_LITE temp = %d\n", temp); + return -EINVAL; + } + + thresh = 0; + temp_cfg = temp_map[thresh]; + for (i = THRESH_MAX; i >= THRESH_MIN; i--) { + if (temp >= temp_map[i]) { + thresh = i; + temp_cfg = temp_map[i]; + break; + } + } + + if (temp_cfg == chip->temp_thresh_map[trip]) + return 0; + + ret = qpnp_tm_read(chip, addr, ®); + if (ret < 0) { + dev_err(chip->dev, "LITE_TEMP_CFG read failed, ret=%d\n", ret); + return ret; + } + + reg &= ~LITE_TEMP_CFG_THRESHOLD_MASK; + reg |= FIELD_PREP(LITE_TEMP_CFG_THRESHOLD_MASK, thresh); + + ret = qpnp_tm_write(chip, addr, reg); + if (ret < 0) { + dev_err(chip->dev, "LITE_TEMP_CFG write failed, ret=%d\n", ret); + return ret; + } + + chip->temp_thresh_map[trip] = temp_cfg; + + return 0; +} + +static int qpnp_tm_lite_set_trip_temp(struct thermal_zone_device *tz, + const struct thermal_trip *trip, int temp) +{ + unsigned int trip_index = THERMAL_TRIP_PRIV_TO_INT(trip->priv); + struct qpnp_tm_chip *chip = thermal_zone_device_priv(tz); + int ret; + + mutex_lock(&chip->lock); + ret = qpnp_tm_lite_set_temp_thresh(chip, trip_index, temp); + mutex_unlock(&chip->lock); + + return ret; +} + +static const struct thermal_zone_device_ops qpnp_tm_lite_sensor_ops = { + .get_temp = qpnp_tm_get_temp, + .set_trip_temp = qpnp_tm_lite_set_trip_temp, +}; + static irqreturn_t qpnp_tm_isr(int irq, void *data) { struct qpnp_tm_chip *chip = data; @@ -472,6 +604,70 @@ static int qpnp_tm_gen2_rev2_sync_thresholds(struct qpnp_tm_chip *chip) return 0; } +/* Configure TEMP_LITE registers based on DT thermal_zone trips */ +static int qpnp_tm_lite_configure_trip_temps_cb(struct thermal_trip *trip, void *data) +{ + struct qpnp_tm_chip *chip = data; + int ret; + + mutex_lock(&chip->lock); + trip->priv = THERMAL_INT_TO_TRIP_PRIV(chip->ntrips); + ret = qpnp_tm_lite_set_temp_thresh(chip, chip->ntrips, trip->temperature); + chip->ntrips++; + mutex_unlock(&chip->lock); + + return ret; +} + +static int qpnp_tm_lite_configure_trip_temps(struct qpnp_tm_chip *chip) +{ + int ret; + + ret = thermal_zone_for_each_trip(chip->tz_dev, qpnp_tm_lite_configure_trip_temps_cb, chip); + if (ret < 0) + return ret; + + /* Verify that trips are strictly increasing. */ + if (chip->temp_thresh_map[2] <= chip->temp_thresh_map[0]) { + dev_err(chip->dev, "Threshold 2=%ld <= threshold 0=%ld\n", + chip->temp_thresh_map[2], chip->temp_thresh_map[0]); + return -EINVAL; + } + + return 0; +} + +/* Read the hardware default TEMP_LITE stage threshold temperatures */ +static int qpnp_tm_lite_sync_thresholds(struct qpnp_tm_chip *chip) +{ + int ret, thresh; + u8 reg = 0; + + /* + * Store the warning trip temp in temp_thresh_map[0] and the shutdown trip + * temp in temp_thresh_map[2]. The second trip point is purely in software + * to facilitate a controlled shutdown after the warning threshold is + * crossed but before the automatic hardware shutdown threshold is + * crossed. Thus, there is no register to read for the second trip + * point. + */ + ret = qpnp_tm_read(chip, QPNP_TM_REG_LITE_TEMP_CFG1, ®); + if (ret < 0) + return ret; + + thresh = FIELD_GET(LITE_TEMP_CFG_THRESHOLD_MASK, reg); + chip->temp_thresh_map[0] = temp_lite_warning_map[thresh]; + + ret = qpnp_tm_read(chip, QPNP_TM_REG_LITE_TEMP_CFG2, ®); + if (ret < 0) + return ret; + + thresh = FIELD_GET(LITE_TEMP_CFG_THRESHOLD_MASK, reg); + chip->temp_thresh_map[2] = temp_lite_shutdown_map[thresh]; + + return 0; +} + static const struct spmi_temp_alarm_data spmi_temp_alarm_data = { .ops = &qpnp_tm_sensor_ops, .temp_map = &temp_map_gen1, @@ -503,6 +699,13 @@ static const struct spmi_temp_alarm_data spmi_temp_alarm_gen2_rev2_data = { .get_temp_stage = qpnp_tm_gen2_get_temp_stage, }; +static const struct spmi_temp_alarm_data spmi_temp_alarm_lite_data = { + .ops = &qpnp_tm_lite_sensor_ops, + .sync_thresholds = qpnp_tm_lite_sync_thresholds, + .configure_trip_temps = qpnp_tm_lite_configure_trip_temps, + .get_temp_stage = qpnp_tm_lite_get_temp_stage, +}; + /* * This function intializes the internal temp value based on only the * current thermal stage and threshold. @@ -611,7 +814,8 @@ static int qpnp_tm_probe(struct platform_device *pdev) } if (type != QPNP_TM_TYPE || (subtype != QPNP_TM_SUBTYPE_GEN1 - && subtype != QPNP_TM_SUBTYPE_GEN2)) { + && subtype != QPNP_TM_SUBTYPE_GEN2 + && subtype != QPNP_TM_SUBTYPE_LITE)) { dev_err(&pdev->dev, "invalid type 0x%02x or subtype 0x%02x\n", type, subtype); return -ENODEV; @@ -626,6 +830,8 @@ static int qpnp_tm_probe(struct platform_device *pdev) chip->data = &spmi_temp_alarm_gen2_rev1_data; else if (subtype == QPNP_TM_SUBTYPE_GEN2) chip->data = &spmi_temp_alarm_gen2_data; + else if (subtype == QPNP_TM_SUBTYPE_LITE) + chip->data = &spmi_temp_alarm_lite_data; else return -ENODEV;