From patchwork Fri Jun 20 18:17:05 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will McVicker X-Patchwork-Id: 898669 Received: from mail-pf1-f202.google.com (mail-pf1-f202.google.com [209.85.210.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A84C2EBB8A for ; Fri, 20 Jun 2025 18:17:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.202 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750443465; cv=none; b=LY7kJOnYiRWtk0UUob4uh677AH1RXlnAUryBqwoEz7l9D8bLqo5C+9SFfXt2n1IUuYri0p5tpsupvIPl4vTaBbNFVk/QB4qM4mky86NFbSBRAktI+3yjAzF/BrD2tuMmeLR3IqA8C2trjhFcMj9y2ST0v4xjH9WINhMlqClDkdY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750443465; c=relaxed/simple; bh=E5gNelm91XMJ+AZCHJOExXs098uttzq+1BtKy9LZWyY=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=YY/vLfBhc51ITobvixPEzosGFZa784A+cSoKt0VagK9TzuzD9ijH/KUy9RwyfLCktSYKBaWyLp8R/SdyNyUzW517Y70hgsn+DvNCQUJS7DJKno24g2h+remrQjY2XS13ZYK4Pz5Eu1Z95qbzw3DJI+rHu5v8IUfsba6s7KfcE64= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--willmcvicker.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=FA5gbIpT; arc=none smtp.client-ip=209.85.210.202 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--willmcvicker.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="FA5gbIpT" Received: by mail-pf1-f202.google.com with SMTP id d2e1a72fcca58-748f3d4c7e7so1763729b3a.3 for ; Fri, 20 Jun 2025 11:17:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1750443463; x=1751048263; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=CMP7Kl6yow8Faa+m4ttvJDoB9/AivqWlJaRr2H7xdgs=; b=FA5gbIpT3eGmw5TCQRoNCphA4HGwPyXSGfUyi3jfnw5gfDmi31+PKgXC6mxizVfwLZ UTg4b/TtHRWSsHUAseVXbxm9uAICxsiKzbgI8aJLDRgd+l3ITvUgO/q6bpCenvhS/TMC 8D6wHZ9fhdMCk1v8XekthBMUafOJ4dCrtDDDNUJcBRw9MXYtVImFrmHOJKG9JkmclmeO ZI3DvFerS0kJEQrpZg78U0Ojy8QVX3YO7mM2lbIy+PD+RpPpDtuA/1843dlmN087L/+w +0FtaMKfv6E29NWqumfzQH0GH9yDpiWrczZfBSEiflH/xgygxeBlxLb833C60huFB9sq BfGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1750443463; x=1751048263; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=CMP7Kl6yow8Faa+m4ttvJDoB9/AivqWlJaRr2H7xdgs=; b=XVdKRPANA2fb3HcXo2lC+CfEbzkL1Hrly4IxROw/pgZMen7Qi7bdi7Mzgwn9DO3be9 ciG0xjs311vNXAvj7bCeNTL17hrEC4KnjDBFb62ZxWBqM5kkS+G2Hs/UWuWOyTJFUISU 2i3wP7RgH6Iwh0O6FF1zGEG3TLS/B+49lXF6coW45UYEOuqGcMjr53qVKTWV4w7bhyDi 9Ppicq6uGmsQUZ7gUXwCZCvEMgcgqVxjdM+I8p1r1MsLaudrCIrxalyg8wQDm5/usz+N CKiXJA4Jke8sWEeAeGrvSiLlWZ07FR/oB5ZV7Iz3y6e0/oEOHTBhdCn0smUCRA9hcfTu FrvQ== X-Forwarded-Encrypted: i=1; AJvYcCWN8NlUjx87qwg592zi1cVEgIIyUvgM2mHy8403GvUuZJnoIqdzhFd1GPNo9IWfz2h8VkyYHUKkdB1uYfO4QWEPkg==@vger.kernel.org X-Gm-Message-State: AOJu0Yz1azmUT2iTUpHxD8U1RexKkJ/aEx+6Fmekzk87SyYFgEfSsyTJ o8X0F6tX/TwTxTy6m3TfomlzmmET/Zd7QnHU2oNP9/evYO56Fru5A8LhD4IQyV05Unnflct9nrY LxPBrxxvnGJZBSpEObNuu/ELzIiy0qg== X-Google-Smtp-Source: AGHT+IGm/vFj5hrKzWy2Z3pEyDUaKOhhI+CR5MlaibQ4Zvsy25uFRQsZYTONpTVOibGjQMqu8859Np1afVaE2rSP3T8= X-Received: from pfbef10.prod.google.com ([2002:a05:6a00:2c8a:b0:749:10a2:4f64]) (user=willmcvicker job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a00:2da0:b0:748:6a1f:6d3b with SMTP id d2e1a72fcca58-7490d7b8df9mr5222155b3a.19.1750443463199; Fri, 20 Jun 2025 11:17:43 -0700 (PDT) Date: Fri, 20 Jun 2025 11:17:05 -0700 In-Reply-To: <20250620181719.1399856-1-willmcvicker@google.com> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250620181719.1399856-1-willmcvicker@google.com> X-Mailer: git-send-email 2.50.0.rc2.761.g2dc52ea45b-goog Message-ID: <20250620181719.1399856-3-willmcvicker@google.com> Subject: [PATCH v4 2/6] clocksource/drivers/exynos_mct: Don't register as a sched_clock on arm64 From: Will McVicker To: Catalin Marinas , Will Deacon , Daniel Lezcano , Thomas Gleixner , Krzysztof Kozlowski , Alim Akhtar , Rob Herring , Saravana Kannan Cc: Will McVicker , Donghoon Yu , Hosung Kim , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, John Stultz , Youngmin Nam , Peter Griffin , Tudor Ambarus , " =?utf-8?q?Andr=C3=A9_Draszik?= " , Conor Dooley , linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org The MCT register is unfortunately very slow to access, but importantly does not halt in the c2 idle state. So for ARM64, we can improve performance by not registering the MCT for sched_clock, allowing the system to use the faster ARM architected timer for sched_clock instead. The MCT is still registered as a clocksource, and a clockevent in order to be a wakeup source for the arch_timer to exit the "c2" idle state. Since ARM32 SoCs don't have an architected timer, the MCT must continue to be used for sched_clock. Detailed discussion on this topic can be found at [1]. [1] https://lore.kernel.org/linux-samsung-soc/1400188079-21832-1-git-send-email-chirantan@chromium.org/ [Original commit from https://android.googlesource.com/kernel/gs/+/630817f7080e92c5e0216095ff52f6eb8dd00727 Signed-off-by: Donghoon Yu Signed-off-by: Youngmin Nam Reviewed-by: Youngmin Nam Acked-by: John Stultz Tested-by: Youngmin Nam Signed-off-by: Will McVicker --- drivers/clocksource/exynos_mct.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c index da09f467a6bb..96361d5dc57d 100644 --- a/drivers/clocksource/exynos_mct.c +++ b/drivers/clocksource/exynos_mct.c @@ -219,12 +219,18 @@ static struct clocksource mct_frc = { .resume = exynos4_frc_resume, }; +/* + * Since ARM devices do not have an architected timer, they need to continue + * using the MCT as the main clocksource for timekeeping, sched_clock, and the + * delay timer. For AARCH64 SoCs, the architected timer is the preferred + * clocksource due to it's superior performance. + */ +#if defined(CONFIG_ARM) static u64 notrace exynos4_read_sched_clock(void) { return exynos4_read_count_32(); } -#if defined(CONFIG_ARM) static struct delay_timer exynos4_delay_timer; static cycles_t exynos4_read_current_timer(void) @@ -250,12 +256,13 @@ static int __init exynos4_clocksource_init(bool frc_shared) exynos4_delay_timer.read_current_timer = &exynos4_read_current_timer; exynos4_delay_timer.freq = clk_rate; register_current_timer_delay(&exynos4_delay_timer); + + sched_clock_register(exynos4_read_sched_clock, 32, clk_rate); #endif if (clocksource_register_hz(&mct_frc, clk_rate)) panic("%s: can't register clocksource\n", mct_frc.name); - sched_clock_register(exynos4_read_sched_clock, 32, clk_rate); return 0; } From patchwork Fri Jun 20 18:17:07 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will McVicker X-Patchwork-Id: 898668 Received: from mail-pf1-f202.google.com (mail-pf1-f202.google.com [209.85.210.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 810FF2ECD33 for ; Fri, 20 Jun 2025 18:17:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.202 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750443471; cv=none; b=jITdn6JTknZOtaVomdO+9JyuycgnqZcJOD2id+LJE/gpZfW0nimKQDxEUd0uw1MIzH7Rd3xv1IIGDU1w0s4Bl6Qsd+nwyO7aacTvd4bmUBo8V/4nVO53iGHx7baC3WZJDcm1KxZ8M7ONPVhryjGwYhtzjRvD315HB/glB2aw5Aw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750443471; c=relaxed/simple; bh=qdxcwdOlQ3EdsQcn5czc5e/96PPBxIfgnyOOP8Kx86M=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=iU3VUBIzercopWlVBtimZO3sa/B3WtA7KYJVMxxCd2dm+d5fgFcMZ62cJFnst0Mc6xhxSuMIN9Gd8VUZpp5gyOe6Fy8C/cCGBalzMlsIvuoJEn9oKx56MC4l0xSNe0ex+hyKaHPMK5AG+kYdYjULp4lyP0UmlqNB88moJQGfVWE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--willmcvicker.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=yjTuIaNq; arc=none smtp.client-ip=209.85.210.202 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--willmcvicker.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="yjTuIaNq" Received: by mail-pf1-f202.google.com with SMTP id d2e1a72fcca58-74880a02689so1735928b3a.0 for ; Fri, 20 Jun 2025 11:17:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1750443469; x=1751048269; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=KucomvysAjkq7Mc20S0WzT2rldg2A7wys58v4bjZBcg=; b=yjTuIaNqXautQ/wHGc8RJ8CQ1oUw61wmO4b9F2Q8Q0E+DhQ1LDgTMG/N3Ye0JYkpXQ bDjMHulvLr1LrFioiP8ZS3DEaEsBJ5lrNbvG3KIFDYbwC09j64zDun8RLf9U0PH2B1iT O/+5ejXOwvKb6yR30AM/hvlYxsNWbv7Ft2NfKa/jDIknBsEyhTlDDM6QB8YrHxmakRVG Wfq7tJ7T3cB9tAefTWmwUvrET8BkJvm6t4PRVpDLVEWqulZM+mBytBOWmyu6N2THUNCK dFMyCWWvW+36SmXZZgD1C6kVqJsgRFGCU568XKN2pbFZg7iE3N/Kc1RpOovoWiNr3odm NmnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1750443469; x=1751048269; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=KucomvysAjkq7Mc20S0WzT2rldg2A7wys58v4bjZBcg=; b=VGcHQkqOrW9XrlJjeAAuce6cHLHfLofToNrJSfUUomiK7oPjk7enioq9XlKEV9vSL4 c8QFGEFK0DiIn5B1qK3QJx7yKgH+7OSr+ydY+XheA2ddQWJXYFsYeu+9eBoGtAhHebUn L2MJmd7bWRc0CD/f0S4WgXm/pyDj9IE949zPuUfWePw3la5Uw3drBRTXzGPJhe9qZ7ZM FUZ9YfWG5pN3cKePSMKItdw4unkpHu1XCwzImcEjQrIYhfGoF+VWaBBmE5vxsYuVGjek QoatBXWu2AGGscxueUFtehBXR6HikZu0f6ZZKAlj+QRFqK1w8VQfk/MMTTyTb0VnuzVZ e/eg== X-Forwarded-Encrypted: i=1; AJvYcCWyiX85gCceIs9rixlXMZemglkPVeaNlMP8J0UlKJgJEcWaph7EU5tlv9tCTVVxRfB86aDnwdYGIfaaYnq5arfqgQ==@vger.kernel.org X-Gm-Message-State: AOJu0YzhsSpUgIOnbNyVMegbR689NkBLVb/MlW6wTQTGM/hI1Lu36mGT xBWRf1rk6pIwGpYDm0MCSSVkOAIgd9Rj1gCVf5xRxpwd/OpGjCKBcJGnQwUsoTdfo81XcWN9H0K 6CAuZDfRaiqGtDyfA+UOBQeeqStiS7Q== X-Google-Smtp-Source: AGHT+IHpdvlqIvd5OPMBnBWNmW/55tcTKxbpdQaDGPMx3/p+0hFPHDCPkEbjUA750R9QqBN1jh56itwHNkqhRDPQ52g= X-Received: from pge20.prod.google.com ([2002:a05:6a02:2d14:b0:b2f:637a:a7d0]) (user=willmcvicker job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a20:9f8b:b0:1f5:7ea8:a791 with SMTP id adf61e73a8af0-22026c30688mr5635494637.10.1750443468893; Fri, 20 Jun 2025 11:17:48 -0700 (PDT) Date: Fri, 20 Jun 2025 11:17:07 -0700 In-Reply-To: <20250620181719.1399856-1-willmcvicker@google.com> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250620181719.1399856-1-willmcvicker@google.com> X-Mailer: git-send-email 2.50.0.rc2.761.g2dc52ea45b-goog Message-ID: <20250620181719.1399856-5-willmcvicker@google.com> Subject: [PATCH v4 4/6] clocksource/drivers/exynos_mct: Fix uninitialized irq name warning From: Will McVicker To: Catalin Marinas , Will Deacon , Daniel Lezcano , Thomas Gleixner , Krzysztof Kozlowski , Alim Akhtar , Rob Herring , Saravana Kannan Cc: Will McVicker , Donghoon Yu , Hosung Kim , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, John Stultz , Youngmin Nam , Peter Griffin , Tudor Ambarus , " =?utf-8?q?Andr=C3=A9_Draszik?= " , Conor Dooley , linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org The Exynos MCT driver doesn't set the clocksource name until the CPU hotplug state is setup which happens after the IRQs are requested. This results in an empty IRQ name which leads to the below warning at proc_create() time. When this happens, the userdata partition fails to mount and the device gets stuck in an endless loop printing the error: root '/dev/disk/by-partlabel/userdata' doesn't exist or does not contain a /dev. To fix this, we just need to initialize the name before requesting the IRQs. Warning from Pixel 6 kernel log: [ T430] name len 0 [ T430] WARNING: CPU: 6 PID: 430 at fs/proc/generic.c:407 __proc_create+0x258/0x2b4 [ T430] Modules linked in: dwc3_exynos(E+) [ T430] ufs_exynos(E+) phy_exynos_ufs(E) [ T430] phy_exynos5_usbdrd(E) exynos_usi(E+) exynos_mct(E+) s3c2410_wdt(E) [ T430] arm_dsu_pmu(E) simplefb(E) [ T430] CPU: 6 UID: 0 PID: 430 Comm: (udev-worker) Tainted: ... 6.14.0-next-20250331-4k-00008-g59adf909e40e #1 ... [ T430] Tainted: [W]=WARN, [E]=UNSIGNED_MODULE [ T430] Hardware name: Raven (DT) [...] [ T430] Call trace: [ T430] __proc_create+0x258/0x2b4 (P) [ T430] proc_mkdir+0x40/0xa0 [ T430] register_handler_proc+0x118/0x140 [ T430] __setup_irq+0x460/0x6d0 [ T430] request_threaded_irq+0xcc/0x1b0 [ T430] mct_init_dt+0x244/0x604 [exynos_mct ...] [ T430] mct_init_spi+0x18/0x34 [exynos_mct ...] [ T430] exynos4_mct_probe+0x30/0x4c [exynos_mct ...] [ T430] platform_probe+0x6c/0xe4 [ T430] really_probe+0xf4/0x38c [...] [ T430] driver_register+0x6c/0x140 [ T430] __platform_driver_register+0x28/0x38 [ T430] exynos4_mct_driver_init+0x24/0xfe8 [exynos_mct ...] [ T430] do_one_initcall+0x84/0x3c0 [ T430] do_init_module+0x58/0x208 [ T430] load_module+0x1de0/0x2500 [ T430] init_module_from_file+0x8c/0xdc Reviewed-by: Peter Griffin Reviewed-by: Youngmin Nam Tested-by: Youngmin Nam Signed-off-by: Will McVicker --- drivers/clocksource/exynos_mct.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c index a5ef7d64b1c2..62febeb4e1de 100644 --- a/drivers/clocksource/exynos_mct.c +++ b/drivers/clocksource/exynos_mct.c @@ -465,8 +465,6 @@ static int exynos4_mct_starting_cpu(unsigned int cpu) per_cpu_ptr(&percpu_mct_tick, cpu); struct clock_event_device *evt = &mevt->evt; - snprintf(mevt->name, sizeof(mevt->name), "mct_tick%d", cpu); - evt->name = mevt->name; evt->cpumask = cpumask_of(cpu); evt->set_next_event = exynos4_tick_set_next_event; @@ -567,6 +565,14 @@ static int __init exynos4_timer_interrupts(struct device_node *np, for (i = MCT_L0_IRQ; i < nr_irqs; i++) mct_irqs[i] = irq_of_parse_and_map(np, i); + for_each_possible_cpu(cpu) { + struct mct_clock_event_device *mevt = + per_cpu_ptr(&percpu_mct_tick, cpu); + + snprintf(mevt->name, sizeof(mevt->name), "mct_tick%d", + cpu); + } + if (mct_int_type == MCT_INT_PPI) { err = request_percpu_irq(mct_irqs[MCT_L0_IRQ], From patchwork Fri Jun 20 18:17:09 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will McVicker X-Patchwork-Id: 898667 Received: from mail-pg1-f202.google.com (mail-pg1-f202.google.com [209.85.215.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 084062ED84A for ; Fri, 20 Jun 2025 18:17:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.202 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750443477; cv=none; b=bGMD9cYXCizveLqIiOsZpdmoYFJgF6bYRKScq873OetFWWubDVfJYyHWzIkRkJ9pou6p6/zdwWN+rGeR9doRCbaLgE/N4bZuFb6K/lgPCNxW2Mmn+jGTBqS3P6AzXB5RuDib4Q05CHrk/glwahp3z6HZbsW+XR3WuQ0taV6Wp0o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750443477; c=relaxed/simple; bh=FXb5Ooh1SoKLFB+GF1YDuF7hepy8ALKLUWQZf6h1mvk=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=tVORXoATKcRbmepcOeysLAV8v7Q1zY10UeXR7RdDKx+gzyyF7ZNZdkrCbBkfOFPMDOPWe3tCiAORuV9GEXFoEEJON3YUivCnSPHFw+HppyEkuSOSDs2AKpi6V3o0Vz+F+jC+zB8Ubgy2ZldtGR41fcZ4wMsNdMNtILo3LXUIjz8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--willmcvicker.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=s+a/oUsk; arc=none smtp.client-ip=209.85.215.202 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--willmcvicker.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="s+a/oUsk" Received: by mail-pg1-f202.google.com with SMTP id 41be03b00d2f7-b2eea1c2e97so1667803a12.2 for ; Fri, 20 Jun 2025 11:17:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1750443475; x=1751048275; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=qsGE8lw3KH/D0SLaONE7VxsA+KaDyJNSSOZHiKLjPmQ=; b=s+a/oUskKmcHuRT2SSVKgz62vOwzlPIDfpB2UmecpycwElDkDzMHteeJ7S/IPoihGS HYsbDLMELB4M2PSQyLSY+joLpN8OlXQ5RRw9+GZGvseZr4jXVEDXt5aXgc+wDoxygoO7 KxZUmmCAM2exo89e2d4g1DF77yiGQw4g2ZaIS0vCiLaazsGaP/qDU9k7ajMa1NhTAcgq JrDSd7/VwjfyF2zqKMWK+rLUz+hW+MvoHZkLZPlGUBg8jk2Bnj0yd4XKKUCXaTpSHgP4 m7e8CMSj5K0gghN0QcA1BQfqBfd+gh0VHXJPPJO0LdMIQf8XXDzhH4JOzJxgZObQ8pIH 1NbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1750443475; x=1751048275; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=qsGE8lw3KH/D0SLaONE7VxsA+KaDyJNSSOZHiKLjPmQ=; b=Cump6qC8PnYYFNJ9ywqeGjZeuLg6JOdefxkSVLPcdv2IIVXI2jVDdw/lsYiajwa+k2 CrEiGlnu87+EDOKbO1jVPof+RChBBJFkQtfGnSRHSUxBhYAiAFp9nFrXMB8aVKCYJ5j5 VB7Q03Rge0kYtNgWQ76PJRKS7eTMoJY/Ccc0maoNuPVoXhPVDW2pGtPu58Nkl3RycEAI irEIYwynbm0K0TAHhxwJr3ggjYKMVUtfMQk+fproBqR6uIUjyGfSS/WP+G4JE+fV46Kl b2h7sLghM5B0oPNcHA6aV4/f+V/0NMT3gHRh+7zqzWct0YpMGX1mUxH41IIRZ/2lEFib +zQg== X-Forwarded-Encrypted: i=1; AJvYcCV0OdnD45CiksZhbkoaPSwHotpSP4mbTpwQ9klSbbM1YVS1oKJCAr2ak6FM27OJqkRiPzz3wKYvkJYhQEyoj5HWhg==@vger.kernel.org X-Gm-Message-State: AOJu0Yz3mUXNFv1z5qUuNQRSlgfhuKb6qXgNkwN96S80ZuwItehCfmkD CcxJNI2+2EL0dYD7JxDnFLhBvVkj7DOli4CLV8FVIuO+e60lqApmnEKheDVM32egf+N5+rqwoJp TpPdof0qfA3wsWrok9aRAGVbzJHRJ+w== X-Google-Smtp-Source: AGHT+IHypcBEXCfetti6ZSKrWADvOCJp2Q3YDfRe9x9eHf0/IU91QwPfM1r/wCQjgAiUHhCtBoksoPLTGqQX3VT8HmY= X-Received: from pfiv28.prod.google.com ([2002:aa7:99dc:0:b0:746:2ceb:2ec0]) (user=willmcvicker job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a20:7f8a:b0:220:eef:e8f0 with SMTP id adf61e73a8af0-22026e479cdmr6696633637.23.1750443475053; Fri, 20 Jun 2025 11:17:55 -0700 (PDT) Date: Fri, 20 Jun 2025 11:17:09 -0700 In-Reply-To: <20250620181719.1399856-1-willmcvicker@google.com> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250620181719.1399856-1-willmcvicker@google.com> X-Mailer: git-send-email 2.50.0.rc2.761.g2dc52ea45b-goog Message-ID: <20250620181719.1399856-7-willmcvicker@google.com> Subject: [PATCH v4 6/6] arm64: exynos: Drop select CLKSRC_EXYNOS_MCT From: Will McVicker To: Catalin Marinas , Will Deacon , Daniel Lezcano , Thomas Gleixner , Krzysztof Kozlowski , Alim Akhtar , Rob Herring , Saravana Kannan Cc: Will McVicker , Donghoon Yu , Hosung Kim , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, John Stultz , Youngmin Nam , Peter Griffin , Tudor Ambarus , " =?utf-8?q?Andr=C3=A9_Draszik?= " , Conor Dooley , linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org Since the Exynos MCT driver can be built as a module for some Arm64 SoCs like gs101, drop force-selecting it as a built-in driver by ARCH_EXYNOS and instead depend on `default y if ARCH_EXYNOS` to select it automatically. This allows platforms like Android to build the driver as a module if desired. Reviewed-by: Youngmin Nam Tested-by: Youngmin Nam Signed-off-by: Will McVicker --- arch/arm64/Kconfig.platforms | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index a541bb029aa4..46825b02d099 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -109,7 +109,6 @@ config ARCH_BLAIZE config ARCH_EXYNOS bool "Samsung Exynos SoC family" select COMMON_CLK_SAMSUNG - select CLKSRC_EXYNOS_MCT select EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS select EXYNOS_PMU select PINCTRL