From patchwork Sat Jun 21 21:05:21 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xi Pardee X-Patchwork-Id: 898951 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E695427145B; Sat, 21 Jun 2025 21:05:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750539939; cv=none; b=KqUVpJGMGREuZz515u4TNoMuqpzMWfWjjlhd9GdfoinUe/sDC+U4DXVKO23r6A+U3xQwIpiFR9zG5U6ThdYm6VkwbnCSIr2sNWNiZWhQaJoZFuM5UubnMdlZ7PL1vSYyZdd61OGNVKrRfE6/ySQ3R2SgRfcZNsUnQn9Hn0kJUvY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750539939; c=relaxed/simple; bh=gili3zJVF7ZQ9a+PUONOkac6Rm442IXQ0FJb+Dn1TgA=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=kWaFP7EzCjqxAyuzIGG7noVYv+lVxemN95w315mUUD98S3U6XZadcvXl0YZiFD3P6dFD3rumehRiqMRZbKII2/BKCckUUNGVQUq0ENH9tx2bnJKI4/DGEGCc/qytrQhXxcmFnjfo8lUDdpkh+WoWXBhOMjJHGGGWom2ClZrpfG0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=h8GIuL/U; arc=none smtp.client-ip=198.175.65.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="h8GIuL/U" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1750539938; x=1782075938; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=gili3zJVF7ZQ9a+PUONOkac6Rm442IXQ0FJb+Dn1TgA=; b=h8GIuL/UEOHFqLJu1dyoGuEERjQEiL7eTU+Y6PjhhXu94VgRfY+DLz2s EJZJKa3ogPSKcFD2stTNgrXlrFX1LjHi2Z0SfbBA41JC9QvxpADeGCV1o 9IaOnwMEsLqKVlNOJp7krxbH8nZtkvgq5I8nRdsI+codcmhcd6HCVSaxS PkPkRNDqFlJnb6Z+sOklQ9TGgEgvdvHWlMdxczYLLmQwBU3Ta4q/UMUnI hr6A1di8keubbCfKsPSlekN3z6tUu6E3StkYYKVnmOdZLuQeUAz/baig/ wAsEtipwBNMa4K0Re1/vvqIPayh0DX5WbyT2mGNizzpkx4krpaC+mY9+2 Q==; X-CSE-ConnectionGUID: hb2PXp8WSNOsnG5BHNkCVg== X-CSE-MsgGUID: 8aIPXom8SEKZdxwN3Q5yVA== X-IronPort-AV: E=McAfee;i="6800,10657,11470"; a="63826248" X-IronPort-AV: E=Sophos;i="6.16,254,1744095600"; d="scan'208";a="63826248" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jun 2025 14:05:36 -0700 X-CSE-ConnectionGUID: 0bKJoyXJR8yuNDQ2ZOhVYA== X-CSE-MsgGUID: p3GtArLsR46iChr1FrJeuQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,254,1744095600"; d="scan'208";a="155775322" Received: from mdroper-mobl2.amr.corp.intel.com (HELO xpardee-desk.intel.com) ([10.124.222.74]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jun 2025 14:05:33 -0700 From: Xi Pardee To: xi.pardee@linux.intel.com, irenic.rajneesh@gmail.com, david.e.box@linux.intel.com, hdegoede@redhat.com, ilpo.jarvinen@linux.intel.com, platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v1 1/5] platform/x86:intel/pmc: Enable SSRAM support for Lunar Lake Date: Sat, 21 Jun 2025 14:05:21 -0700 Message-ID: <20250621210529.237964-2-xi.pardee@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250621210529.237964-1-xi.pardee@linux.intel.com> References: <20250621210529.237964-1-xi.pardee@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Enable Lunar Lake platforms to achieve PMC information from Intel PMC SSRAM Telemetry driver and substate requirements data from telemetry region. Signed-off-by: Xi Pardee --- drivers/platform/x86/intel/pmc/lnl.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/platform/x86/intel/pmc/lnl.c b/drivers/platform/x86/intel/pmc/lnl.c index da513c234714b..e08a77c778c2c 100644 --- a/drivers/platform/x86/intel/pmc/lnl.c +++ b/drivers/platform/x86/intel/pmc/lnl.c @@ -13,6 +13,10 @@ #include "core.h" +#define SOCM_LPM_REQ_GUID 0x15099748 + +static const u8 LNL_LPM_REG_INDEX[] = {0, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 20}; + static const struct pmc_bit_map lnl_ltr_show_map[] = { {"SOUTHPORT_A", CNP_PMC_LTR_SPA}, {"SOUTHPORT_B", CNP_PMC_LTR_SPB}, @@ -528,6 +532,16 @@ static const struct pmc_reg_map lnl_socm_reg_map = { .lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET, .s0ix_blocker_maps = lnl_blk_maps, .s0ix_blocker_offset = LNL_S0IX_BLOCKER_OFFSET, + .lpm_reg_index = LNL_LPM_REG_INDEX, +}; + +static struct pmc_info lnl_pmc_info_list[] = { + { + .guid = SOCM_LPM_REQ_GUID, + .devid = PMC_DEVID_LNL_SOCM, + .map = &lnl_socm_reg_map, + }, + {} }; #define LNL_NPU_PCI_DEV 0x643e @@ -557,6 +571,8 @@ static int lnl_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_in } struct pmc_dev_info lnl_pmc_dev = { + .pci_func = 2, + .regmap_list = lnl_pmc_info_list, .map = &lnl_socm_reg_map, .suspend = cnl_suspend, .resume = lnl_resume, From patchwork Sat Jun 21 21:05:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xi Pardee X-Patchwork-Id: 898950 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C35DE271A9D; Sat, 21 Jun 2025 21:05:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750539941; cv=none; b=Jg/5jyaEWBJUYoRXYmwUwvUONCA8JNgsj7BnQGdXI7CIQ9kdBNMAaeAxCmD34Nfn5PN85o3bQIn5d7+kGml3gwrN+cjFlo29S+QS/oCEaoHvK0QOcIT30lofLrceGcaajqSjSIhaFbR5vRDwUNwJB4zp0xHg2/khAKF/6MLPImI= ARC-Message-Signature: i=1; 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d="scan'208";a="155775326" Received: from mdroper-mobl2.amr.corp.intel.com (HELO xpardee-desk.intel.com) ([10.124.222.74]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jun 2025 14:05:37 -0700 From: Xi Pardee To: xi.pardee@linux.intel.com, irenic.rajneesh@gmail.com, david.e.box@linux.intel.com, hdegoede@redhat.com, ilpo.jarvinen@linux.intel.com, platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v1 3/5] platform/x86:intel/pmc: Improve function to show substate header Date: Sat, 21 Jun 2025 14:05:23 -0700 Message-ID: <20250621210529.237964-4-xi.pardee@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250621210529.237964-1-xi.pardee@linux.intel.com> References: <20250621210529.237964-1-xi.pardee@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Refactor pmc_core_substate_req_header_show() to accept a new argument. This is a preparation patch to introduce a new way to show Low Power Mode substate requirement data for platforms starting from Panther Lake. Increased the size for the name column as the Low Power Mode requirement register name is longer in newer platforms. Signed-off-by: Xi Pardee --- drivers/platform/x86/intel/pmc/core.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/intel/pmc/core.c index a1dd80bdbd413..47cc5120e7dd6 100644 --- a/drivers/platform/x86/intel/pmc/core.c +++ b/drivers/platform/x86/intel/pmc/core.c @@ -828,17 +828,20 @@ static int pmc_core_substate_l_sts_regs_show(struct seq_file *s, void *unused) } DEFINE_SHOW_ATTRIBUTE(pmc_core_substate_l_sts_regs); -static void pmc_core_substate_req_header_show(struct seq_file *s, int pmc_index) +static void pmc_core_substate_req_header_show(struct seq_file *s, int pmc_index, char *name) { struct pmc_dev *pmcdev = s->private; int mode; - seq_printf(s, "%30s |", "Element"); + seq_printf(s, "%40s |", "Element"); pmc_for_each_mode(mode, pmcdev) seq_printf(s, " %9s |", pmc_lpm_modes[mode]); - seq_printf(s, " %9s |", "Status"); - seq_printf(s, " %11s |\n", "Live Status"); + if (!strcmp(name, "Status")) { + seq_printf(s, " %9s |", name); + seq_printf(s, " %11s |\n", "Live Status"); + } else + seq_printf(s, " %9s |\n", name); } static int pmc_core_substate_req_regs_show(struct seq_file *s, void *unused) @@ -872,7 +875,7 @@ static int pmc_core_substate_req_regs_show(struct seq_file *s, void *unused) continue; /* Display the header */ - pmc_core_substate_req_header_show(s, pmc_index); + pmc_core_substate_req_header_show(s, pmc_index, "Status"); /* Loop over maps */ for (mp = 0; mp < num_maps; mp++) { @@ -910,7 +913,7 @@ static int pmc_core_substate_req_regs_show(struct seq_file *s, void *unused) } /* Display the element name in the first column */ - seq_printf(s, "pmc%d: %26s |", pmc_index, map[i].name); + seq_printf(s, "pmc%d: %34s |", pmc_index, map[i].name); /* Loop over the enabled states and display if required */ pmc_for_each_mode(mode, pmcdev) { From patchwork Sat Jun 21 21:05:25 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xi Pardee X-Patchwork-Id: 898949 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6D7F2273D7F; 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a="63826263" X-IronPort-AV: E=Sophos;i="6.16,254,1744095600"; d="scan'208";a="63826263" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jun 2025 14:05:43 -0700 X-CSE-ConnectionGUID: tC0UU2EmRqqfqw525sJZHg== X-CSE-MsgGUID: KTnUx5w6QIeXuFN7eQvtiQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,254,1744095600"; d="scan'208";a="155775328" Received: from mdroper-mobl2.amr.corp.intel.com (HELO xpardee-desk.intel.com) ([10.124.222.74]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jun 2025 14:05:41 -0700 From: Xi Pardee To: xi.pardee@linux.intel.com, irenic.rajneesh@gmail.com, david.e.box@linux.intel.com, hdegoede@redhat.com, ilpo.jarvinen@linux.intel.com, platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v1 5/5] platform/x86:intel/pmc: Enable SSRAM support for Panther Lake Date: Sat, 21 Jun 2025 14:05:25 -0700 Message-ID: <20250621210529.237964-6-xi.pardee@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250621210529.237964-1-xi.pardee@linux.intel.com> References: <20250621210529.237964-1-xi.pardee@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Enable Panther Lake platforms to achieve PMC information from Intel PMC SSRAM Telemetry driver and substate requirements data from telemetry region. Signed-off-by: Xi Pardee --- drivers/platform/x86/intel/pmc/core.h | 2 ++ drivers/platform/x86/intel/pmc/ptl.c | 30 +++++++++++++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/drivers/platform/x86/intel/pmc/core.h b/drivers/platform/x86/intel/pmc/core.h index d8c7b28493055..cdb32f2203cff 100644 --- a/drivers/platform/x86/intel/pmc/core.h +++ b/drivers/platform/x86/intel/pmc/core.h @@ -301,6 +301,8 @@ enum ppfear_regs { #define PTL_PMC_LTR_CUR_ASLT 0x1C28 #define PTL_PMC_LTR_CUR_PLT 0x1C2C #define PTL_PCD_PMC_MMIO_REG_LEN 0x31A8 +#define PTL_NUM_S0IX_BLOCKER 106 +#define PTL_BLK_REQ_OFFSET 55 /* SSRAM PMC Device ID */ /* LNL */ diff --git a/drivers/platform/x86/intel/pmc/ptl.c b/drivers/platform/x86/intel/pmc/ptl.c index 394515af60d60..48be79b4e769f 100644 --- a/drivers/platform/x86/intel/pmc/ptl.c +++ b/drivers/platform/x86/intel/pmc/ptl.c @@ -10,6 +10,17 @@ #include "core.h" +/* PMC SSRAM PMT Telemetry GUIDS */ +#define PCDP_LPM_REQ_GUID 0x47179370 + +/* + * Die Mapping to Product. + * Product PCDDie + * PTL-H PCD-H + * PTL-P PCD-P + * PTL-U PCD-P + */ + static const struct pmc_bit_map ptl_pcdp_pfear_map[] = { {"PMC_0", BIT(0)}, {"FUSE_OSSE", BIT(1)}, @@ -515,6 +526,22 @@ static const struct pmc_reg_map ptl_pcdp_reg_map = { .lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET, .s0ix_blocker_maps = ptl_pcdp_blk_maps, .s0ix_blocker_offset = LNL_S0IX_BLOCKER_OFFSET, + .num_s0ix_blocker = PTL_NUM_S0IX_BLOCKER, + .blocker_req_offset = PTL_BLK_REQ_OFFSET, +}; + +static struct pmc_info ptl_pmc_info_list[] = { + { + .guid = PCDP_LPM_REQ_GUID, + .devid = PMC_DEVID_PTL_PCDH, + .map = &ptl_pcdp_reg_map, + }, + { + .guid = PCDP_LPM_REQ_GUID, + .devid = PMC_DEVID_PTL_PCDP, + .map = &ptl_pcdp_reg_map, + }, + {} }; #define PTL_NPU_PCI_DEV 0xb03e @@ -543,6 +570,9 @@ static int ptl_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_in } struct pmc_dev_info ptl_pmc_dev = { + .pci_func = 2, + .telem_info = SUB_REQ_BLK, + .regmap_list = ptl_pmc_info_list, .map = &ptl_pcdp_reg_map, .suspend = cnl_suspend, .resume = ptl_resume,