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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-237d83937b1sm101371455ad.52.2025.06.23.23.04.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jun 2025 23:04:52 -0700 (PDT) From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Alexander Shishkin Cc: Tingwei Zhang , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, jie.gan@oss.qualcomm.com Subject: [PATCH v3 02/10] coresight: core: add a new API to retrieve the helper device Date: Tue, 24 Jun 2025 14:04:30 +0800 Message-Id: <20250624060438.7469-3-jie.gan@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250624060438.7469-1-jie.gan@oss.qualcomm.com> References: <20250624060438.7469-1-jie.gan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Authority-Analysis: v=2.4 cv=QINoRhLL c=1 sm=1 tr=0 ts=685a4006 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=6IFa9wvqVegA:10 a=EUspDBNiAAAA:8 a=Bv2r1u00ER1ubdDhqu4A:9 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-ORIG-GUID: 8qYXMsK1eFUsiD02jN6QgXwu5CPC-F7w X-Proofpoint-GUID: 8qYXMsK1eFUsiD02jN6QgXwu5CPC-F7w X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjI0MDA1MCBTYWx0ZWRfX0hT2d9Q11O7Q YgBzptyt6p+V5G05kJT286Krtm6PZdmLXqZlOSVRM61Oi94KMO/VOR4LLB1tAD9nWUQaNrBbbI8 yK7YjmTuIkcvWTKes0z7Kmb8H/zfNvjZnIfVRd2zXDcDISu/onH/30jSf/QUzlw9hNhLWFY2vU5 kgUlblCF5LtkjwsWeDYEOE/M5NHZiQ6bjtBwY1OHe94nhXXua+yEcC0ev0PhWSJj/K7FiPxwA0J vFPJexF1NBfzFg0fXtEk4kxC/560tk4SVwVNzCn9tCHze7Lk555RV8NFEAXXLcoH7Y7kUFw5kl9 i8IH2ErKDZezgAaz90PsBzU/C2xAccFIYpAZXdjHZKW41Hi8NH95lQ1mGu2u7KS7O2rc4KE91De fkXeJtM+86wsWYlVWjjvZlf2nJr8jjOQRs1wEGEY5QhuMUTYoGP6ygR8jaaiRncl8XGR1QXf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-06-24_02,2025-06-23_07,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 priorityscore=1501 malwarescore=0 adultscore=0 mlxscore=0 clxscore=1015 mlxlogscore=999 bulkscore=0 suspectscore=0 phishscore=0 impostorscore=0 lowpriorityscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506240050 Retrieving the helper device of the specific coresight device based on its helper_subtype because a single coresight device may has multiple types of the helper devices. Signed-off-by: Jie Gan --- drivers/hwtracing/coresight/coresight-core.c | 30 ++++++++++++++++++++ drivers/hwtracing/coresight/coresight-priv.h | 2 ++ 2 files changed, 32 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index 8aad2823e28a..c785f8e86777 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -579,6 +579,36 @@ struct coresight_device *coresight_get_sink(struct coresight_path *path) } EXPORT_SYMBOL_GPL(coresight_get_sink); +/** + * coresight_get_helper: find the helper device of the assigned csdev. + * + * @csdev: The csdev the helper device is conntected to. + * @type: helper_subtype of the expected helper device. + * + * Retrieve the helper device for the specific csdev based on its + * helper_subtype. + * + * Return: the helper's csdev upon success or NULL for fail. + */ +struct coresight_device *coresight_get_helper(struct coresight_device *csdev, + int type) +{ + int i; + struct coresight_device *helper; + + for (i = 0; i < csdev->pdata->nr_outconns; ++i) { + helper = csdev->pdata->out_conns[i]->dest_dev; + if (!helper || !coresight_is_helper(helper)) + continue; + + if (helper->subtype.helper_subtype == type) + return helper; + } + + return NULL; +} +EXPORT_SYMBOL_GPL(coresight_get_helper); + /** * coresight_get_port_helper: get the in-port number of the helper device * that is connected to the csdev. diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h index 07a5f03de81d..5b912eb60401 100644 --- a/drivers/hwtracing/coresight/coresight-priv.h +++ b/drivers/hwtracing/coresight/coresight-priv.h @@ -158,6 +158,8 @@ void coresight_path_assign_trace_id(struct coresight_path *path, enum cs_mode mode); int coresight_get_port_helper(struct coresight_device *csdev, struct coresight_device *helper); +struct coresight_device *coresight_get_helper(struct coresight_device *csdev, + int type); #if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM3X) int etm_readl_cp14(u32 off, unsigned int *val); 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-237d83937b1sm101371455ad.52.2025.06.23.23.04.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jun 2025 23:05:01 -0700 (PDT) From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Alexander Shishkin Cc: Tingwei Zhang , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, jie.gan@oss.qualcomm.com Subject: [PATCH v3 04/10] coresight: ctcu: enable byte-cntr for TMC ETR devices Date: Tue, 24 Jun 2025 14:04:32 +0800 Message-Id: <20250624060438.7469-5-jie.gan@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250624060438.7469-1-jie.gan@oss.qualcomm.com> References: <20250624060438.7469-1-jie.gan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Authority-Analysis: v=2.4 cv=QINoRhLL c=1 sm=1 tr=0 ts=685a4010 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=6IFa9wvqVegA:10 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=VuEiWhZmLyiD4YjWg_QA:9 a=uG9DUKGECoFWVXl0Dc02:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: 5GO7MQLqwD5MuVq0dpV4xC68ob66D6v- X-Proofpoint-GUID: 5GO7MQLqwD5MuVq0dpV4xC68ob66D6v- X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjI0MDA1MCBTYWx0ZWRfXzB2L5lK++Xz2 zX3PDjMFxL+b+Mk7GVisoL32ZSRE4zpv/1FmFpgVeohiyMRsb3o11lI1zWDguCEFTYsRRL3Gj2j a8fw8WLUGZPDsJu0YVuzMTIbx5zP4K9S63fa8gQFKqQrVmITvXYV8Yth/G/DOvotfNEmSq7dDXw 4GqpEy3CYaDsGL6VKZpgiE3PpAIzRG5B209fh/J2lUzj/0nj5EW9vy9RhFdhdDN7CiJDsQFh6dU OooxhcYyMcjFnrJbhyhm7tkTz4HKBhLJOE1T4ZERoBCvJBWa1n0P7GQdYYBXXOkeE6EFMKS7wkp suSWxLthiXC/R2YQzFT3CUjGAtlDRqM0D5Bz1j5SABbmF+0lEMtE5Y4Q1fDN7qkzh/kqL9W94Fe j86h6r4RbZTBUooKRVp2BqNhNo/dJRK8Mx5wA3078TK2By8qWmV7b/fzlQafPR1pDqF6IaLZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-06-24_02,2025-06-23_07,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 priorityscore=1501 malwarescore=0 adultscore=0 mlxscore=0 clxscore=1015 mlxlogscore=999 bulkscore=0 suspectscore=0 phishscore=0 impostorscore=0 lowpriorityscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506240050 The byte-cntr function provided by the CTCU device is used to transfer data from the ETR buffer to the userspace. An interrupt is triggered if the data size exceeds the threshold set in the BYTECNTRVAL register. The interrupt handler counts the number of triggered interruptions and the read function will read the data from the ETR buffer. Signed-off-by: Jie Gan --- .../testing/sysfs-bus-coresight-devices-ctcu | 5 + drivers/hwtracing/coresight/Makefile | 2 +- .../coresight/coresight-ctcu-byte-cntr.c | 102 ++++++++++++++++++ .../hwtracing/coresight/coresight-ctcu-core.c | 94 +++++++++++++++- drivers/hwtracing/coresight/coresight-ctcu.h | 52 ++++++++- 5 files changed, 249 insertions(+), 6 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-ctcu create mode 100644 drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-ctcu b/Documentation/ABI/testing/sysfs-bus-coresight-devices-ctcu new file mode 100644 index 000000000000..e21f5bcb8097 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-ctcu @@ -0,0 +1,5 @@ +What: /sys/bus/coresight/devices//irq_val +Date: June 2025 +KernelVersion: 6.16 +Contact: Tingwei Zhang (QUIC) ; Jinlong Mao (QUIC) ; Jie Gan +Description: (RW) Configure the IRQ value for byte-cntr register. diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile index 4e7cc3c5bf99..3568d9768567 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -54,5 +54,5 @@ coresight-cti-y := coresight-cti-core.o coresight-cti-platform.o \ obj-$(CONFIG_ULTRASOC_SMB) += ultrasoc-smb.o obj-$(CONFIG_CORESIGHT_DUMMY) += coresight-dummy.o obj-$(CONFIG_CORESIGHT_CTCU) += coresight-ctcu.o -coresight-ctcu-y := coresight-ctcu-core.o +coresight-ctcu-y := coresight-ctcu-core.o coresight-ctcu-byte-cntr.o obj-$(CONFIG_CORESIGHT_KUNIT_TESTS) += coresight-kunit-tests.o diff --git a/drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c b/drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c new file mode 100644 index 000000000000..d3b6eb7a89fb --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include + +#include "coresight-ctcu.h" +#include "coresight-priv.h" +#include "coresight-tmc.h" + +static irqreturn_t byte_cntr_handler(int irq, void *data) +{ + struct ctcu_byte_cntr *byte_cntr_data = (struct ctcu_byte_cntr *)data; + + atomic_inc(&byte_cntr_data->irq_cnt); + wake_up(&byte_cntr_data->wq); + + byte_cntr_data->irq_num++; + + return IRQ_HANDLED; +} + +/* Start the byte-cntr function when the path is enabled. */ +void ctcu_byte_cntr_start(struct coresight_device *csdev, struct coresight_path *path) +{ + struct ctcu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + struct coresight_device *sink = coresight_get_sink(path); + struct ctcu_byte_cntr *byte_cntr_data; + int port_num; + + if (!sink) + return; + + port_num = coresight_get_port_helper(sink, csdev); + if (port_num < 0) + return; + + byte_cntr_data = &drvdata->byte_cntr_data[port_num]; + /* Don't start byte-cntr function when threshold is not set. */ + if (!byte_cntr_data->thresh_val || byte_cntr_data->enable) + return; + + guard(raw_spinlock_irqsave)(&byte_cntr_data->spin_lock); + byte_cntr_data->enable = true; + byte_cntr_data->reading_buf = false; +} + +/* Stop the byte-cntr function when the path is disabled. */ +void ctcu_byte_cntr_stop(struct coresight_device *csdev, struct coresight_path *path) +{ + struct ctcu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + struct coresight_device *sink = coresight_get_sink(path); + struct ctcu_byte_cntr *byte_cntr_data; + int port_num; + + if (!sink || coresight_get_mode(sink) == CS_MODE_SYSFS) + return; + + port_num = coresight_get_port_helper(sink, csdev); + if (port_num < 0) + return; + + byte_cntr_data = &drvdata->byte_cntr_data[port_num]; + guard(raw_spinlock_irqsave)(&byte_cntr_data->spin_lock); + byte_cntr_data->enable = false; +} + +void ctcu_byte_cntr_init(struct device *dev, struct ctcu_drvdata *drvdata, int etr_num) +{ + struct ctcu_byte_cntr *byte_cntr_data; + struct device_node *nd = dev->of_node; + int byte_cntr_irq, ret, i; + + for (i = 0; i < etr_num; i++) { + byte_cntr_data = &drvdata->byte_cntr_data[i]; + byte_cntr_irq = of_irq_get_byname(nd, byte_cntr_data->irq_name); + if (byte_cntr_irq < 0) { + dev_err(dev, "Failed to get IRQ from DT for %s\n", + byte_cntr_data->irq_name); + continue; + } + + ret = devm_request_irq(dev, byte_cntr_irq, byte_cntr_handler, + IRQF_TRIGGER_RISING | IRQF_SHARED, + dev_name(dev), byte_cntr_data); + if (ret) { + dev_err(dev, "Failed to register IRQ for %s\n", + byte_cntr_data->irq_name); + continue; + } + + byte_cntr_data->byte_cntr_irq = byte_cntr_irq; + disable_irq(byte_cntr_data->byte_cntr_irq); + init_waitqueue_head(&byte_cntr_data->wq); + } +} diff --git a/drivers/hwtracing/coresight/coresight-ctcu-core.c b/drivers/hwtracing/coresight/coresight-ctcu-core.c index 28ea4a216345..721836d42523 100644 --- a/drivers/hwtracing/coresight/coresight-ctcu-core.c +++ b/drivers/hwtracing/coresight/coresight-ctcu-core.c @@ -15,6 +15,7 @@ #include #include #include +#include #include "coresight-ctcu.h" #include "coresight-priv.h" @@ -45,17 +46,23 @@ DEFINE_CORESIGHT_DEVLIST(ctcu_devs, "ctcu"); #define CTCU_ATID_REG_BIT(traceid) (traceid % 32) #define CTCU_ATID_REG_SIZE 0x10 +#define CTCU_ETR0_IRQCTRL 0x6c +#define CTCU_ETR1_IRQCTRL 0x70 #define CTCU_ETR0_ATID0 0xf8 #define CTCU_ETR1_ATID0 0x108 static const struct ctcu_etr_config sa8775p_etr_cfgs[] = { { - .atid_offset = CTCU_ETR0_ATID0, - .port_num = 0, + .atid_offset = CTCU_ETR0_ATID0, + .irq_ctrl_offset = CTCU_ETR0_IRQCTRL, + .irq_name = "etr0", + .port_num = 0, }, { - .atid_offset = CTCU_ETR1_ATID0, - .port_num = 1, + .atid_offset = CTCU_ETR1_ATID0, + .irq_ctrl_offset = CTCU_ETR1_IRQCTRL, + .irq_name = "etr1", + .port_num = 1, }, }; @@ -64,6 +71,76 @@ static const struct ctcu_config sa8775p_cfgs = { .num_etr_config = ARRAY_SIZE(sa8775p_etr_cfgs), }; +static void ctcu_program_register(struct ctcu_drvdata *drvdata, u32 val, u32 offset) +{ + CS_UNLOCK(drvdata->base); + ctcu_writel(drvdata, val, offset); + CS_LOCK(drvdata->base); +} + +static ssize_t irq_val_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct ctcu_drvdata *drvdata = dev_get_drvdata(dev->parent); + int i, len = 0; + + for (i = 0; i < ETR_MAX_NUM; i++) { + if (drvdata->byte_cntr_data[i].irq_ctrl_offset) + len += scnprintf(buf + len, PAGE_SIZE - len, "%u ", + drvdata->byte_cntr_data[i].thresh_val); + } + + len += scnprintf(buf + len, PAGE_SIZE - len, "\n"); + + return len; +} + +/* Program a valid value into IRQCTRL register will enable byte-cntr interrupt */ +static ssize_t irq_val_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t size) +{ + struct ctcu_drvdata *drvdata = dev_get_drvdata(dev->parent); + u32 thresh_vals[ETR_MAX_NUM] = { 0 }; + u32 irq_ctrl_offset; + int num, i; + + num = sscanf(buf, "%i %i", &thresh_vals[0], &thresh_vals[1]); + if (num <= 0 || num > ETR_MAX_NUM) + return -EINVAL; + + /* Threshold 0 disables the interruption. */ + guard(raw_spinlock_irqsave)(&drvdata->spin_lock); + for (i = 0; i < num; i++) { + /* A small threshold will result in a large number of interruptions */ + if (thresh_vals[i] && thresh_vals[i] < SZ_4K) + return -EINVAL; + + if (drvdata->byte_cntr_data[i].irq_ctrl_offset) { + drvdata->byte_cntr_data[i].thresh_val = thresh_vals[i]; + irq_ctrl_offset = drvdata->byte_cntr_data[i].irq_ctrl_offset; + /* A one value for IRQCTRL register represents 8 bytes */ + ctcu_program_register(drvdata, thresh_vals[i] / 8, irq_ctrl_offset); + } + } + + return size; +} +static DEVICE_ATTR_RW(irq_val); + +static struct attribute *ctcu_attrs[] = { + &dev_attr_irq_val.attr, + NULL, +}; + +static struct attribute_group ctcu_attr_grp = { + .attrs = ctcu_attrs, +}; + +static const struct attribute_group *ctcu_attr_grps[] = { + &ctcu_attr_grp, + NULL, +}; + static void ctcu_program_atid_register(struct ctcu_drvdata *drvdata, u32 reg_offset, u8 bit, bool enable) { @@ -143,6 +220,8 @@ static int ctcu_enable(struct coresight_device *csdev, enum cs_mode mode, void * { struct coresight_path *path = (struct coresight_path *)data; + ctcu_byte_cntr_start(csdev, path); + return ctcu_set_etr_traceid(csdev, path, true); } @@ -150,6 +229,8 @@ static int ctcu_disable(struct coresight_device *csdev, void *data) { struct coresight_path *path = (struct coresight_path *)data; + ctcu_byte_cntr_stop(csdev, path); + return ctcu_set_etr_traceid(csdev, path, false); } @@ -200,7 +281,11 @@ static int ctcu_probe(struct platform_device *pdev) for (i = 0; i < cfgs->num_etr_config; i++) { etr_cfg = &cfgs->etr_cfgs[i]; drvdata->atid_offset[i] = etr_cfg->atid_offset; + drvdata->byte_cntr_data[i].irq_name = etr_cfg->irq_name; + drvdata->byte_cntr_data[i].irq_ctrl_offset = + etr_cfg->irq_ctrl_offset; } + ctcu_byte_cntr_init(dev, drvdata, cfgs->num_etr_config); } } @@ -212,6 +297,7 @@ static int ctcu_probe(struct platform_device *pdev) desc.subtype.helper_subtype = CORESIGHT_DEV_SUBTYPE_HELPER_CTCU; desc.pdata = pdata; desc.dev = dev; + desc.groups = ctcu_attr_grps; desc.ops = &ctcu_ops; desc.access = CSDEV_ACCESS_IOMEM(base); diff --git a/drivers/hwtracing/coresight/coresight-ctcu.h b/drivers/hwtracing/coresight/coresight-ctcu.h index e9594c38dd91..8ae93c75c8df 100644 --- a/drivers/hwtracing/coresight/coresight-ctcu.h +++ b/drivers/hwtracing/coresight/coresight-ctcu.h @@ -5,19 +5,27 @@ #ifndef _CORESIGHT_CTCU_H #define _CORESIGHT_CTCU_H + +#include #include "coresight-trace-id.h" /* Maximum number of supported ETR devices for a single CTCU. */ #define ETR_MAX_NUM 2 +#define BYTE_CNTR_TIMEOUT (5 * HZ) + /** * struct ctcu_etr_config * @atid_offset: offset to the ATID0 Register. - * @port_num: in-port number of CTCU device that connected to ETR. + * @port_num: in-port number of the CTCU device that connected to ETR. + * @irq_ctrl_offset: offset to the BYTECNTRVAL register. + * @irq_name: IRQ name in dt node. */ struct ctcu_etr_config { const u32 atid_offset; const u32 port_num; + const u32 irq_ctrl_offset; + const char *irq_name; }; struct ctcu_config { @@ -25,15 +33,57 @@ struct ctcu_config { int num_etr_config; }; +/** + * struct ctcu_byte_cntr + * @enable: indicates that byte_cntr function is enabled or not. + * @reading: indicates that its byte-cntr reading. + * @reading_buf: indicates that byte-cntr is reading buffer. + * @thresh_val: threshold to trigger a interruption. + * @total_size: total size of transferred data. + * @byte_cntr_irq: IRQ number. + * @irq_cnt: IRQ count. + * @irq_num: number of the byte_cntr IRQ for one session. + * @wq: workqueue of reading ETR data. + * @read_work: work of reading ETR data. + * @spin_lock: spinlock of byte cntr data. + * the byte cntr is stopped. + * @irq_ctrl_offset: offset to the BYTECNTVAL Register. + * @irq_name: IRQ name in DT. + */ +struct ctcu_byte_cntr { + bool enable; + bool reading; + bool reading_buf; + u32 thresh_val; + u64 total_size; + int byte_cntr_irq; + atomic_t irq_cnt; + int irq_num; + wait_queue_head_t wq; + struct work_struct read_work; + raw_spinlock_t spin_lock; + u32 irq_ctrl_offset; + const char *irq_name; +}; + struct ctcu_drvdata { void __iomem *base; struct clk *apb_clk; struct device *dev; struct coresight_device *csdev; + struct ctcu_byte_cntr byte_cntr_data[ETR_MAX_NUM]; raw_spinlock_t spin_lock; u32 atid_offset[ETR_MAX_NUM]; /* refcnt for each traceid of each sink */ u8 traceid_refcnt[ETR_MAX_NUM][CORESIGHT_TRACE_ID_RES_TOP]; }; +/* Generic functions */ +int ctcu_get_active_port(struct coresight_device *sink, struct coresight_device *helper); + +/* Byte-cntr functions */ +void ctcu_byte_cntr_start(struct coresight_device *csdev, struct coresight_path *path); +void ctcu_byte_cntr_stop(struct coresight_device *csdev, struct coresight_path *path); +void ctcu_byte_cntr_init(struct device *dev, struct ctcu_drvdata *drvdata, int port_num); + #endif From patchwork Tue Jun 24 06:04:34 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Gan X-Patchwork-Id: 899495 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 558A325393A for ; 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-237d83937b1sm101371455ad.52.2025.06.23.23.05.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jun 2025 23:05:10 -0700 (PDT) From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Alexander Shishkin Cc: Tingwei Zhang , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, jie.gan@oss.qualcomm.com Subject: [PATCH v3 06/10] coresight: tmc: add create/delete functions for etr_buf_node Date: Tue, 24 Jun 2025 14:04:34 +0800 Message-Id: <20250624060438.7469-7-jie.gan@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250624060438.7469-1-jie.gan@oss.qualcomm.com> References: <20250624060438.7469-1-jie.gan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: XduDLCSWvyzdQfrMQh9Pf6vr744CxBIj X-Authority-Analysis: v=2.4 cv=Id+HWXqa c=1 sm=1 tr=0 ts=685a4025 cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=6IFa9wvqVegA:10 a=EUspDBNiAAAA:8 a=k3jFKW3szlTOC2bxmxAA:9 a=x9snwWr2DeNwDh03kgHS:22 X-Proofpoint-GUID: XduDLCSWvyzdQfrMQh9Pf6vr744CxBIj X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjI0MDA1MSBTYWx0ZWRfX9khk5jtuUZen BgdeKjfJxq/NmDP6h3DSlZxs/zST4nRL61u1AvfkcekTvibNJX4QEtykdrEf8YLUseQAx2hPhBF Kq4fGIWVQpieAwipqVz48YwpTWz2WQm25EaZQi+ivhlxb6p45pJQ09PEhnPjLpEnFERG+0PG5NQ MO77KJm17icZwxITBD65kdjQ3ypFKGf+Gqmy954C4tl29URzBr+NvRZMzmAJ8Zmi7tjS5eeyJgI GWUq5mXfiYJurtd4mi7dXdG/VJpMQsKZoc2ady3/X9mJWXarkhr0OYfFHu2f6L5adOION/9zaz7 BgSvBR+bw0/2PJwRoXn24a6B4CcqSibS8hojE25YYoxxwpxr+rFIszkJa3jDYCoKpCoNZ6vapn+ HyH2N9GmVN1O5mhISDmvdy9Kao+tXLwmQwX39HRkT7QAe7i8yMJBt3YfHPlq9JVMwWcWcIJ2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-06-24_02,2025-06-23_07,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 priorityscore=1501 mlxlogscore=999 phishscore=0 bulkscore=0 clxscore=1015 impostorscore=0 mlxscore=0 lowpriorityscore=0 malwarescore=0 suspectscore=0 adultscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506240051 Create and insert or remove the etr_buf_node to/from the etr_buf_list. Signed-off-by: Jie Gan --- .../hwtracing/coresight/coresight-tmc-etr.c | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index b07fcdb3fe1a..4609df80ae38 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1909,6 +1909,55 @@ const struct coresight_ops tmc_etr_cs_ops = { .panic_ops = &tmc_etr_sync_ops, }; +static void tmc_delete_etr_buf_node(struct tmc_drvdata *drvdata) +{ + struct etr_buf_node *nd, *next; + + list_for_each_entry_safe(nd, next, &drvdata->etr_buf_list, node) { + if (nd->sysfs_buf == drvdata->sysfs_buf) { + list_del(&nd->node); + kfree(nd); + } else { + /* Free allocated buffers which are not utilized by ETR */ + list_del(&nd->node); + tmc_free_etr_buf(nd->sysfs_buf); + nd->sysfs_buf = NULL; + kfree(nd); + } + } +} + +static int tmc_create_etr_buf_node(struct tmc_drvdata *drvdata, struct etr_buf *alloc_buf) +{ + struct etr_buf_node *sysfs_buf_node; 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-237d83937b1sm101371455ad.52.2025.06.23.23.05.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jun 2025 23:05:19 -0700 (PDT) From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Alexander Shishkin Cc: Tingwei Zhang , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, jie.gan@oss.qualcomm.com Subject: [PATCH v3 08/10] coresight: tmc: add a switch buffer function for byte-cntr Date: Tue, 24 Jun 2025 14:04:36 +0800 Message-Id: <20250624060438.7469-9-jie.gan@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250624060438.7469-1-jie.gan@oss.qualcomm.com> References: <20250624060438.7469-1-jie.gan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: PJ2R9jT8GqeiW6gyJ3RRNRFP9OwONfr9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjI0MDA1MSBTYWx0ZWRfX19CPq0cOsY9p gU2+hkG1JI78Uxi+jadFT+m0BUcz5us9fNFQ5ZKYLR3ZLNwDrF4GJ8ZuaFpBpfCYFoooFjIZnl5 XfPqkGHx9Bk0g1yJuMcuCTgBc3jwkYHkibb3HUCwuz/kavFVn8DvWZxK1i6mOOScD2aY76MXBRL QAxXULuDgh0pVw6ZD+VLbnrxCoZINv03gWv9OK5Lk1WajRT6Qqj03aYMZH8FYpTKrzRv36ZZzqE psTN+nPChblxNUbIo7BcOuqQGSvzDCJ79BztOESX6x1zknccLGP7J6XaigWOvpOUD6MEcLFGIHD JVyDf2BcyrEEPcjm0MIOsmW8Ldj1Mmw+4BaAbX99lAF3vU3NvOutwlaKCkszs62xleqc3EE2/K6 RmGnSCVgAs/RXkzMXmzzIhUt4ZVFvpAh+fbAZKOBa4Ec3HHU0YVsNbtmEG7xrMiLdLWRLaKx X-Authority-Analysis: v=2.4 cv=L4kdQ/T8 c=1 sm=1 tr=0 ts=685a4027 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=6IFa9wvqVegA:10 a=EUspDBNiAAAA:8 a=wDWrKlMOwBuH9W2KgGoA:9 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-GUID: PJ2R9jT8GqeiW6gyJ3RRNRFP9OwONfr9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-06-24_02,2025-06-23_07,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 malwarescore=0 bulkscore=0 clxscore=1015 suspectscore=0 adultscore=0 priorityscore=1501 impostorscore=0 lowpriorityscore=0 spamscore=0 phishscore=0 mlxlogscore=999 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506240051 Switching the sysfs_buf when current buffer is full or the timeout is triggered and resets rrp and rwp registers after switched the buffer. Disable the ETR device if it cannot find an available buffer to switch. Signed-off-by: Jie Gan --- .../hwtracing/coresight/coresight-tmc-etr.c | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index 2b73bd8074bb..3e3e1b5e78ca 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1287,6 +1287,58 @@ static struct etr_buf *tmc_etr_get_sysfs_buffer(struct coresight_device *csdev) return ret ? ERR_PTR(ret) : drvdata->sysfs_buf; } +static bool tmc_byte_cntr_switch_buffer(struct tmc_drvdata *drvdata, + struct ctcu_byte_cntr *byte_cntr_data) +{ + struct etr_buf_node *nd, *next, *curr_node, *picked_node; + struct etr_buf *curr_buf = drvdata->sysfs_buf; + bool found_free_buf = false; + + if (WARN_ON(!drvdata || !byte_cntr_data)) + return found_free_buf; + + /* Stop the ETR before we start the switching process */ + if (coresight_get_mode(drvdata->csdev) == CS_MODE_SYSFS) + __tmc_etr_disable_hw(drvdata); + + list_for_each_entry_safe(nd, next, &drvdata->etr_buf_list, node) { + /* curr_buf is free for next round */ + if (nd->sysfs_buf == curr_buf) { + nd->is_free = true; + curr_node = nd; + } + + if (!found_free_buf && nd->is_free && nd->sysfs_buf != curr_buf) { + if (nd->reading) + continue; + + picked_node = nd; + found_free_buf = true; + } + } + + if (found_free_buf) { + curr_node->reading = true; + curr_node->pos = 0; + drvdata->reading_node = curr_node; + drvdata->sysfs_buf = picked_node->sysfs_buf; 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-237d83937b1sm101371455ad.52.2025.06.23.23.05.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jun 2025 23:05:28 -0700 (PDT) From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Alexander Shishkin Cc: Tingwei Zhang , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, jie.gan@oss.qualcomm.com, Konrad Dybcio Subject: [PATCH v3 10/10] arm64: dts: qcom: sa8775p: Add interrupts to CTCU device Date: Tue, 24 Jun 2025 14:04:38 +0800 Message-Id: <20250624060438.7469-11-jie.gan@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250624060438.7469-1-jie.gan@oss.qualcomm.com> References: <20250624060438.7469-1-jie.gan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjI0MDA1MSBTYWx0ZWRfX+M/xfKtIP/2D aFPIZU5a7lfYyrLs21tN0p6I7DNd33xiZWqo56TVpomWoavzdcnOMrw0vfwde13s+Vhf1KCr6jI fcnMROIsdZvQTcrypfPsH3suvM2du/HkxA0vezzPukMv6TPLllffT2j8U47oNVQ4yOP/ooqgb59 rN6cRvaROUIq/mlFu6cmBEAg/S/7kscQjftSVMFUrsS/zVdTbQva64lKBbvn5TbCh8pj+/hspM/ crmEr3GFEKJjd3jEO9UGyG9BrxNEiPTObCuwQxwlj7Sad2ggHfRIwaK/PBTsIu4qVSxbxMms/Ss HbtBcogvMAR6qVvjOTJrGWk8NxWGuBqweIHadwofG46Uwvgnnv45bYAaCDXzV7QcMN86wE9u5Qx iPmmSYxurXYNgHCtQBY1hBBT3Qz/U5jY9gE/CIBwrbpDT7s8mx1sL9NZfO+8fxFSUk5YV1HK X-Proofpoint-ORIG-GUID: pjQzyaEK39DKCrjNp7VEgOX7O9IAtlcu X-Proofpoint-GUID: pjQzyaEK39DKCrjNp7VEgOX7O9IAtlcu X-Authority-Analysis: v=2.4 cv=A8BsP7WG c=1 sm=1 tr=0 ts=685a402a cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=6IFa9wvqVegA:10 a=EUspDBNiAAAA:8 a=gBkj9RZkAcI1HbXH1KoA:9 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-06-24_02,2025-06-23_07,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 mlxlogscore=818 malwarescore=0 spamscore=0 bulkscore=0 phishscore=0 adultscore=0 impostorscore=0 suspectscore=0 mlxscore=0 clxscore=1015 priorityscore=1501 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506240051 Add interrupts to enable byte-cntr function for TMC ETR devices. Reviewed-by: Konrad Dybcio Signed-off-by: Jie Gan --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index fed34717460f..44da72cebcf4 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -2762,6 +2762,11 @@ ctcu@4001000 { clocks = <&aoss_qmp>; clock-names = "apb"; + interrupts = , + ; + interrupt-names = "etr0", + "etr1"; + in-ports { #address-cells = <1>; #size-cells = <0>;