From patchwork Wed May 13 09:30:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gokul Sriram Palanisamy X-Patchwork-Id: 189169 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 013D8C2D0FD for ; Wed, 13 May 2020 09:32:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DAFC220753 for ; Wed, 13 May 2020 09:32:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727030AbgEMJbk (ORCPT ); Wed, 13 May 2020 05:31:40 -0400 Received: from alexa-out-blr-02.qualcomm.com ([103.229.18.198]:57562 "EHLO alexa-out-blr-02.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726492AbgEMJbk (ORCPT ); Wed, 13 May 2020 05:31:40 -0400 Received: from ironmsg01-blr.qualcomm.com ([10.86.208.130]) by alexa-out-blr-02.qualcomm.com with ESMTP/TLS/AES256-SHA; 13 May 2020 15:01:35 +0530 Received: from gokulsri-linux.qualcomm.com ([10.201.2.207]) by ironmsg01-blr.qualcomm.com with ESMTP; 13 May 2020 15:01:07 +0530 Received: by gokulsri-linux.qualcomm.com (Postfix, from userid 432570) id 361C021257; Wed, 13 May 2020 15:01:05 +0530 (IST) From: Gokul Sriram Palanisamy To: gokulsri@codeaurora.org, sboyd@kernel.org, agross@kernel.org, bjorn.andersson@linaro.org, david.brown@linaro.org, devicetree@vger.kernel.org, jassisinghbrar@gmail.com, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-remoteproc@vger.kernel.org, mark.rutland@arm.com, mturquette@baylibre.com, ohad@wizery.com, robh+dt@kernel.org, sricharan@codeaurora.org, nprakash@codeaurora.org Subject: [PATCH V5 01/10] remoteproc: qcom: Add PRNG proxy clock Date: Wed, 13 May 2020 15:00:56 +0530 Message-Id: <1589362265-22702-2-git-send-email-gokulsri@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1589362265-22702-1-git-send-email-gokulsri@codeaurora.org> References: <1589362265-22702-1-git-send-email-gokulsri@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org PRNG clock is needed by the secure PIL, support for the same is added in subsequent patches. Signed-off-by: Gokul Sriram Palanisamy Signed-off-by: Sricharan R Signed-off-by: Nikhil Prakash V --- drivers/remoteproc/qcom_q6v5_wcss.c | 65 +++++++++++++++++++++++++++---------- 1 file changed, 47 insertions(+), 18 deletions(-) diff --git a/drivers/remoteproc/qcom_q6v5_wcss.c b/drivers/remoteproc/qcom_q6v5_wcss.c index fff681a..0700d68 100644 --- a/drivers/remoteproc/qcom_q6v5_wcss.c +++ b/drivers/remoteproc/qcom_q6v5_wcss.c @@ -91,19 +91,6 @@ enum { WCSS_QCS404, }; -struct wcss_data { - const char *firmware_name; - int crash_reason_smem; - u32 version; - bool aon_reset_required; - bool wcss_q6_reset_required; - const char *ssr_name; - const char *sysmon_name; - int ssctl_id; - const struct rproc_ops *ops; - bool requires_force_stop; -}; - struct q6v5_wcss { struct device *dev; @@ -128,6 +115,7 @@ struct q6v5_wcss { struct clk *qdsp6ss_xo_cbcr; struct clk *qdsp6ss_core_gfmux; struct clk *lcc_bcr_sleep; + struct clk *prng_clk; struct regulator *cx_supply; struct qcom_rproc_glink glink_subdev; @@ -151,6 +139,21 @@ struct q6v5_wcss { bool requires_force_stop; }; +struct wcss_data { + int (*init_clock)(struct q6v5_wcss *wcss); + int (*init_regulator)(struct q6v5_wcss *wcss); + const char *firmware_name; + int crash_reason_smem; + u32 version; + bool aon_reset_required; + bool wcss_q6_reset_required; + const char *ssr_name; + const char *sysmon_name; + int ssctl_id; + const struct rproc_ops *ops; + bool requires_force_stop; +}; + static int q6v5_wcss_reset(struct q6v5_wcss *wcss) { int ret; @@ -240,6 +243,12 @@ static int q6v5_wcss_start(struct rproc *rproc) struct q6v5_wcss *wcss = rproc->priv; int ret; + ret = clk_prepare_enable(wcss->prng_clk); + if (ret) { + dev_err(wcss->dev, "prng clock enable failed\n"); + return ret; + } + qcom_q6v5_prepare(&wcss->q6v5); /* Release Q6 and WCSS reset */ @@ -732,6 +741,7 @@ static int q6v5_wcss_stop(struct rproc *rproc) return ret; } + clk_disable_unprepare(wcss->prng_clk); qcom_q6v5_unprepare(&wcss->q6v5); return 0; @@ -889,7 +899,21 @@ static int q6v5_alloc_memory_region(struct q6v5_wcss *wcss) return 0; } -static int q6v5_wcss_init_clock(struct q6v5_wcss *wcss) +static int ipq8074_init_clock(struct q6v5_wcss *wcss) +{ + int ret; + + wcss->prng_clk = devm_clk_get(wcss->dev, "prng"); + if (IS_ERR(wcss->prng_clk)) { + ret = PTR_ERR(wcss->prng_clk); + if (ret != -EPROBE_DEFER) + dev_err(wcss->dev, "Failed to get prng clock\n"); + return ret; + } + return 0; +} + +static int qcs404_init_clock(struct q6v5_wcss *wcss) { int ret; @@ -979,7 +1003,7 @@ static int q6v5_wcss_init_clock(struct q6v5_wcss *wcss) return 0; } -static int q6v5_wcss_init_regulator(struct q6v5_wcss *wcss) +static int qcs404_init_regulator(struct q6v5_wcss *wcss) { wcss->cx_supply = devm_regulator_get(wcss->dev, "cx"); if (IS_ERR(wcss->cx_supply)) @@ -1023,12 +1047,14 @@ static int q6v5_wcss_probe(struct platform_device *pdev) if (ret) goto free_rproc; - if (wcss->version == WCSS_QCS404) { - ret = q6v5_wcss_init_clock(wcss); + if (desc->init_clock) { + ret = desc->init_clock(wcss); if (ret) goto free_rproc; + } - ret = q6v5_wcss_init_regulator(wcss); + if (desc->init_regulator) { + ret = desc->init_regulator(wcss); if (ret) goto free_rproc; } @@ -1073,6 +1099,7 @@ static int q6v5_wcss_remove(struct platform_device *pdev) } static const struct wcss_data wcss_ipq8074_res_init = { + .init_clock = ipq8074_init_clock, .firmware_name = "IPQ8074/q6_fw.mdt", .crash_reason_smem = WCSS_CRASH_REASON, .aon_reset_required = true, @@ -1082,6 +1109,8 @@ static const struct wcss_data wcss_ipq8074_res_init = { }; static const struct wcss_data wcss_qcs404_res_init = { + .init_clock = qcs404_init_clock, + .init_regulator = qcs404_init_regulator, .crash_reason_smem = WCSS_CRASH_REASON, .firmware_name = "wcnss.mdt", .version = WCSS_QCS404, From patchwork Wed May 13 09:31:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gokul Sriram Palanisamy X-Patchwork-Id: 189170 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53D6FCA90AF for ; Wed, 13 May 2020 09:32:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3DAA9206F5 for ; Wed, 13 May 2020 09:32:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732279AbgEMJbs (ORCPT ); Wed, 13 May 2020 05:31:48 -0400 Received: from alexa-out-blr-02.qualcomm.com ([103.229.18.198]:57562 "EHLO alexa-out-blr-02.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729707AbgEMJbr (ORCPT ); Wed, 13 May 2020 05:31:47 -0400 Received: from ironmsg01-blr.qualcomm.com ([10.86.208.130]) by alexa-out-blr-02.qualcomm.com with ESMTP/TLS/AES256-SHA; 13 May 2020 15:01:36 +0530 Received: from gokulsri-linux.qualcomm.com ([10.201.2.207]) by ironmsg01-blr.qualcomm.com with ESMTP; 13 May 2020 15:01:09 +0530 Received: by gokulsri-linux.qualcomm.com (Postfix, from userid 432570) id D72CF21779; Wed, 13 May 2020 15:01:06 +0530 (IST) From: Gokul Sriram Palanisamy To: gokulsri@codeaurora.org, sboyd@kernel.org, agross@kernel.org, bjorn.andersson@linaro.org, david.brown@linaro.org, devicetree@vger.kernel.org, jassisinghbrar@gmail.com, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-remoteproc@vger.kernel.org, mark.rutland@arm.com, mturquette@baylibre.com, ohad@wizery.com, robh+dt@kernel.org, sricharan@codeaurora.org, nprakash@codeaurora.org Subject: [PATCH V5 05/10] remoteproc: qcom: Update regmap offsets for halt register Date: Wed, 13 May 2020 15:01:00 +0530 Message-Id: <1589362265-22702-6-git-send-email-gokulsri@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1589362265-22702-1-git-send-email-gokulsri@codeaurora.org> References: <1589362265-22702-1-git-send-email-gokulsri@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Fixed issue in reading halt-regs parameter from device-tree. Signed-off-by: Gokul Sriram Palanisamy Signed-off-by: Sricharan R --- drivers/remoteproc/qcom_q6v5_wcss.c | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/drivers/remoteproc/qcom_q6v5_wcss.c b/drivers/remoteproc/qcom_q6v5_wcss.c index 0a23aca..49f2d31 100644 --- a/drivers/remoteproc/qcom_q6v5_wcss.c +++ b/drivers/remoteproc/qcom_q6v5_wcss.c @@ -86,7 +86,7 @@ #define TCSR_WCSS_CLK_MASK 0x1F #define TCSR_WCSS_CLK_ENABLE 0x14 -#define MAX_HALT_REG 3 +#define MAX_HALT_REG 4 #define WCNSS_PAS_ID 6 @@ -154,6 +154,7 @@ struct wcss_data { u32 version; bool aon_reset_required; bool wcss_q6_reset_required; + bool bcr_reset_required; const char *ssr_name; const char *sysmon_name; int ssctl_id; @@ -868,10 +869,13 @@ static int q6v5_wcss_init_reset(struct q6v5_wcss *wcss, } } - wcss->wcss_q6_bcr_reset = devm_reset_control_get_exclusive(dev, "wcss_q6_bcr_reset"); - if (IS_ERR(wcss->wcss_q6_bcr_reset)) { - dev_err(wcss->dev, "unable to acquire wcss_q6_bcr_reset\n"); - return PTR_ERR(wcss->wcss_q6_bcr_reset); + if (desc->bcr_reset_required) { + wcss->wcss_q6_bcr_reset = devm_reset_control_get_exclusive(dev, + "wcss_q6_bcr_reset"); + if (IS_ERR(wcss->wcss_q6_bcr_reset)) { + dev_err(wcss->dev, "unable to acquire wcss_q6_bcr_reset\n"); + return PTR_ERR(wcss->wcss_q6_bcr_reset); + } } return 0; @@ -919,9 +923,9 @@ static int q6v5_wcss_init_mmio(struct q6v5_wcss *wcss, return -EINVAL; } - wcss->halt_q6 = halt_reg[0]; - wcss->halt_wcss = halt_reg[1]; - wcss->halt_nc = halt_reg[2]; + wcss->halt_q6 = halt_reg[1]; + wcss->halt_wcss = halt_reg[2]; + wcss->halt_nc = halt_reg[3]; return 0; } @@ -1166,6 +1170,7 @@ static const struct wcss_data wcss_ipq8074_res_init = { .crash_reason_smem = WCSS_CRASH_REASON, .aon_reset_required = true, .wcss_q6_reset_required = true, + .bcr_reset_required = false, .ssr_name = "q6wcss", .ops = &q6v5_wcss_ipq8074_ops, .requires_force_stop = true, @@ -1180,6 +1185,7 @@ static const struct wcss_data wcss_qcs404_res_init = { .version = WCSS_QCS404, .aon_reset_required = false, .wcss_q6_reset_required = false, + .bcr_reset_required = true, .ssr_name = "mpss", .sysmon_name = "wcnss", .ssctl_id = 0x12, From patchwork Wed May 13 09:31:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gokul Sriram Palanisamy X-Patchwork-Id: 189172 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EBC04C2D0F9 for ; Wed, 13 May 2020 09:31:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D322520675 for ; Wed, 13 May 2020 09:31:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732503AbgEMJby (ORCPT ); Wed, 13 May 2020 05:31:54 -0400 Received: from alexa-out-blr-02.qualcomm.com ([103.229.18.198]:57574 "EHLO alexa-out-blr-02.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727063AbgEMJbx (ORCPT ); Wed, 13 May 2020 05:31:53 -0400 Received: from ironmsg01-blr.qualcomm.com ([10.86.208.130]) by alexa-out-blr-02.qualcomm.com with ESMTP/TLS/AES256-SHA; 13 May 2020 15:01:36 +0530 Received: from gokulsri-linux.qualcomm.com ([10.201.2.207]) by ironmsg01-blr.qualcomm.com with ESMTP; 13 May 2020 15:01:07 +0530 Received: by gokulsri-linux.qualcomm.com (Postfix, from userid 432570) id B5B4721770; Wed, 13 May 2020 15:01:06 +0530 (IST) From: Gokul Sriram Palanisamy To: gokulsri@codeaurora.org, sboyd@kernel.org, agross@kernel.org, bjorn.andersson@linaro.org, david.brown@linaro.org, devicetree@vger.kernel.org, jassisinghbrar@gmail.com, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-remoteproc@vger.kernel.org, mark.rutland@arm.com, mturquette@baylibre.com, ohad@wizery.com, robh+dt@kernel.org, sricharan@codeaurora.org, nprakash@codeaurora.org Subject: [PATCH V5 06/10] dt-bindings: clock: qcom: Add reset for WCSSAON Date: Wed, 13 May 2020 15:01:01 +0530 Message-Id: <1589362265-22702-7-git-send-email-gokulsri@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1589362265-22702-1-git-send-email-gokulsri@codeaurora.org> References: <1589362265-22702-1-git-send-email-gokulsri@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add binding for WCSSAON reset required for Q6v5 reset on IPQ8074 SoC. Signed-off-by: Gokul Sriram Palanisamy Signed-off-by: Sricharan R Signed-off-by: Nikhil Prakash V Acked-by: Rob Herring Acked-by: Stephen Boyd --- include/dt-bindings/clock/qcom,gcc-ipq8074.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/clock/qcom,gcc-ipq8074.h b/include/dt-bindings/clock/qcom,gcc-ipq8074.h index 4de4811..04e1f57 100644 --- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h +++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h @@ -362,5 +362,6 @@ #define GCC_PCIE1_AXI_SLAVE_ARES 128 #define GCC_PCIE1_AHB_ARES 129 #define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130 +#define GCC_WCSSAON_RESET 131 #endif From patchwork Wed May 13 09:31:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gokul Sriram Palanisamy X-Patchwork-Id: 189171 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 71EEFC2D0FE for ; Wed, 13 May 2020 09:32:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5ABA3206F5 for ; Wed, 13 May 2020 09:32:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732465AbgEMJbu (ORCPT ); Wed, 13 May 2020 05:31:50 -0400 Received: from alexa-out-blr-02.qualcomm.com ([103.229.18.198]:57570 "EHLO alexa-out-blr-02.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728133AbgEMJbt (ORCPT ); Wed, 13 May 2020 05:31:49 -0400 Received: from ironmsg01-blr.qualcomm.com ([10.86.208.130]) by alexa-out-blr-02.qualcomm.com with ESMTP/TLS/AES256-SHA; 13 May 2020 15:01:36 +0530 Received: from gokulsri-linux.qualcomm.com ([10.201.2.207]) by ironmsg01-blr.qualcomm.com with ESMTP; 13 May 2020 15:01:09 +0530 Received: by gokulsri-linux.qualcomm.com (Postfix, from userid 432570) id 1C54E21773; Wed, 13 May 2020 15:01:06 +0530 (IST) From: Gokul Sriram Palanisamy To: gokulsri@codeaurora.org, sboyd@kernel.org, agross@kernel.org, bjorn.andersson@linaro.org, david.brown@linaro.org, devicetree@vger.kernel.org, jassisinghbrar@gmail.com, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-remoteproc@vger.kernel.org, mark.rutland@arm.com, mturquette@baylibre.com, ohad@wizery.com, robh+dt@kernel.org, sricharan@codeaurora.org, nprakash@codeaurora.org Subject: [PATCH V5 07/10] clk: qcom: Add WCSSAON reset Date: Wed, 13 May 2020 15:01:02 +0530 Message-Id: <1589362265-22702-8-git-send-email-gokulsri@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1589362265-22702-1-git-send-email-gokulsri@codeaurora.org> References: <1589362265-22702-1-git-send-email-gokulsri@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add WCSSAON reset required for Q6v5 on IPQ8074 SoC. Signed-off-by: Gokul Sriram Palanisamy Signed-off-by: Sricharan R Signed-off-by: Nikhil Prakash V Acked-by: Stephen Boyd --- drivers/clk/qcom/gcc-ipq8074.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index e01f5f5..1e5758f 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -4685,6 +4685,7 @@ static const struct qcom_reset_map gcc_ipq8074_resets[] = { [GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 }, [GCC_PCIE1_AHB_ARES] = { 0x76040, 5 }, [GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 }, + [GCC_WCSSAON_RESET] = { 0x59010, 0 }, }; static const struct of_device_id gcc_ipq8074_match_table[] = { From patchwork Wed May 13 09:31:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gokul Sriram Palanisamy X-Patchwork-Id: 189168 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 378E4C2D0FF for ; Wed, 13 May 2020 09:32:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 22D94206F5 for ; Wed, 13 May 2020 09:32:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732543AbgEMJcQ (ORCPT ); Wed, 13 May 2020 05:32:16 -0400 Received: from alexa-out-blr-02.qualcomm.com ([103.229.18.198]:57584 "EHLO alexa-out-blr-02.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730494AbgEMJcP (ORCPT ); Wed, 13 May 2020 05:32:15 -0400 Received: from ironmsg01-blr.qualcomm.com ([10.86.208.130]) by alexa-out-blr-02.qualcomm.com with ESMTP/TLS/AES256-SHA; 13 May 2020 15:01:35 +0530 Received: from gokulsri-linux.qualcomm.com ([10.201.2.207]) by ironmsg01-blr.qualcomm.com with ESMTP; 13 May 2020 15:01:09 +0530 Received: by gokulsri-linux.qualcomm.com (Postfix, from userid 432570) id 475522178A; Wed, 13 May 2020 15:01:07 +0530 (IST) From: Gokul Sriram Palanisamy To: gokulsri@codeaurora.org, sboyd@kernel.org, agross@kernel.org, bjorn.andersson@linaro.org, david.brown@linaro.org, devicetree@vger.kernel.org, jassisinghbrar@gmail.com, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-remoteproc@vger.kernel.org, mark.rutland@arm.com, mturquette@baylibre.com, ohad@wizery.com, robh+dt@kernel.org, sricharan@codeaurora.org, nprakash@codeaurora.org Subject: [PATCH V5 10/10] arm64: dts: qcom: Enable Q6v5 WCSS for ipq8074 SoC Date: Wed, 13 May 2020 15:01:05 +0530 Message-Id: <1589362265-22702-11-git-send-email-gokulsri@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1589362265-22702-1-git-send-email-gokulsri@codeaurora.org> References: <1589362265-22702-1-git-send-email-gokulsri@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Enable remoteproc WCSS PIL driver with glink and ssr subdevices. Also configures shared memory and enables smp2p and mailboxes required for IPC. Signed-off-by: Gokul Sriram Palanisamy Signed-off-by: Sricharan R Signed-off-by: Nikhil Prakash V --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 121 ++++++++++++++++++++++++++++++++++ 1 file changed, 121 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 4107614..7d7bafe 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -10,12 +10,66 @@ model = "Qualcomm Technologies, Inc. IPQ8074"; compatible = "qcom,ipq8074"; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + smem_region: memory@4ab00000 { + no-map; + reg = <0x0 0x4ab00000 0x0 0x00100000>; + }; + + q6_region: memory@4b000000 { + no-map; + reg = <0x0 0x4b000000 0x0 0x05f00000>; + }; + }; + firmware { scm { compatible = "qcom,scm-ipq8074", "qcom,scm"; }; }; + tcsr_mutex: hwlock@193d000 { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_regs 0 0x80>; + #hwlock-cells = <1>; + }; + + smem { + compatible = "qcom,smem"; + memory-region = <&smem_region>; + hwlocks = <&tcsr_mutex 0>; + }; + + wcss: smp2p-wcss { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + + interrupt-parent = <&intc>; + interrupts = <0 322 1>; + + mboxes = <&apcs_glb 9>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + wcss_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + qcom,smp2p-feature-ssr-ack; + #qcom,smem-state-cells = <1>; + }; + + wcss_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + soc: soc { #address-cells = <0x1>; #size-cells = <0x1>; @@ -432,6 +486,73 @@ "axi_m_sticky"; status = "disabled"; }; + + tcsr_q6: syscon@1945000 { + compatible = "syscon"; + reg = <0x01945000 0xe000>; + }; + + tcsr_mutex_regs: syscon@193d000 { + compatible = "syscon"; + reg = <0x01905000 0x8000>; + }; + + apcs_glb: mailbox@b111000 { + compatible = "qcom,ipq8074-apcs-apps-global"; + reg = <0x0b111000 0x1000>; + + #mbox-cells = <1>; + }; + + q6v5_wcss: q6v5_wcss@cd00000 { + compatible = "qcom,ipq8074-wcss-pil"; + reg = <0x0cd00000 0x4040>, + <0x004ab000 0x20>; + reg-names = "qdsp6", + "rmb"; + qca,auto-restart; + qca,extended-intc; + interrupts-extended = <&intc 0 325 1>, + <&wcss_smp2p_in 0 0>, + <&wcss_smp2p_in 1 0>, + <&wcss_smp2p_in 2 0>, + <&wcss_smp2p_in 3 0>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + resets = <&gcc GCC_WCSSAON_RESET>, + <&gcc GCC_WCSS_BCR>, + <&gcc GCC_WCSS_Q6_BCR>; + + reset-names = "wcss_aon_reset", + "wcss_reset", + "wcss_q6_reset"; + + clocks = <&gcc GCC_PRNG_AHB_CLK>; + clock-names = "prng"; + + qcom,halt-regs = <&tcsr_q6 0xa000 0xd000 0x0>; + + qcom,smem-states = <&wcss_smp2p_out 0>, + <&wcss_smp2p_out 1>; + qcom,smem-state-names = "shutdown", + "stop"; + + memory-region = <&q6_region>; + + glink-edge { + interrupts = ; + qcom,remote-pid = <1>; + mboxes = <&apcs_glb 8>; + + rpm_requests { + qcom,glink-channels = "IPCRTR"; + }; + }; + }; }; cpus {