From patchwork Fri Mar 20 18:34:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 189894 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4C3FEC4332D for ; Fri, 20 Mar 2020 18:36:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 25A1620781 for ; Fri, 20 Mar 2020 18:36:06 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="apXJslcS" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727382AbgCTSfL (ORCPT ); Fri, 20 Mar 2020 14:35:11 -0400 Received: from mail-ed1-f67.google.com ([209.85.208.67]:37553 "EHLO mail-ed1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726986AbgCTSfJ (ORCPT ); Fri, 20 Mar 2020 14:35:09 -0400 Received: by mail-ed1-f67.google.com with SMTP id b23so8333990edx.4; Fri, 20 Mar 2020 11:35:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uQ0Q+G5JHB2wM7K4BTcO70sOln2WeIX1gFNwP6RhpGg=; b=apXJslcSv6DC7tOJCgLYYYrV7Uplua56Od4xMZ0ChU3xw5lwqCUcaRvDeMQVJ718nC lIN/rx3MUNJ4VpgfEJlHp8ehGN1L8yIdGbVA57igSjDUsRsevHYfRk4NcwhEpC/qDq7C mUPGo9j8A5mlZaevqvNT3+34ex12nlDlL89Wg/Y8KUb27OwNxAP/VWpk5+i/vhrpx0EP ydt3z/yAqFx96y/MFkcHqQHwoTVTtcxfTNWETO/WAXC4rZX6yMqat78iXAbvheQkgNWh IL1Cgr0omLPpNQSd7K1H9n9n2xc3sJY5d+8Y/0ez0sU6j+smuEfkjYBAQUNuWlp/RJ1z hQ3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uQ0Q+G5JHB2wM7K4BTcO70sOln2WeIX1gFNwP6RhpGg=; b=tpkfcge3waxKDXg+PsEEnEKe4ktNUK3WPKKm3zUIuOSlG5ZpiL1R6f9/t+r9WLAahU sbxuupMr8AHJWQDKIN7P82/hoEh89ZMS4/HMxAkmG3Z+SCsnOK5TIrBEoSrTASKe4aam O0vhLVmvSb1FTq5PJtl8RVLn2PuU6qbMfjzOvenPkt1/qelurQEqZ6A+oc+CIrbiO2f0 yhljLWso5QOV7V2IvJj9aHFeaOtDpFO4wDJgWPAfr6hNqKMxch967jadKBq4VQkXPQNJ gGQatWpHokO+ICHEzrAsAYLrh97BiXNuqVZ5UQCRLb+XHm07HLdP9kGEss7xOaKFSlZk pi2A== X-Gm-Message-State: ANhLgQ2m5XTPhZcgoE78y1GZvLVHnid6dfJ3+Uupq6AqWOdVCUFLgSMh isoDMkZJZHYu87j+vAGrtFA= X-Google-Smtp-Source: ADFU+vsaA6XpAhj1+J65GLanwleRzVBh4W3oXm2qIL37/3iCYgGQ2Uue7Q0ibo2tLweZ+0IKexqPKA== X-Received: by 2002:a05:6402:2071:: with SMTP id bd17mr9532397edb.160.1584729307682; Fri, 20 Mar 2020 11:35:07 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host203-232-dynamic.53-79-r.retail.telecomitalia.it. [79.53.232.203]) by smtp.googlemail.com with ESMTPSA id y13sm172916eje.3.2020.03.20.11.35.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Mar 2020 11:35:06 -0700 (PDT) From: Ansuel Smith To: Stanimir Varbanov Cc: Ansuel Smith , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Rob Herring , Mark Rutland , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 02/12] devicetree: bindings: pci: add missing clks to qcom, pcie Date: Fri, 20 Mar 2020 19:34:44 +0100 Message-Id: <20200320183455.21311-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200320183455.21311-1-ansuelsmth@gmail.com> References: <20200320183455.21311-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Document missing clks used in ipq806x soc Signed-off-by: Ansuel Smith Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/qcom,pcie.txt | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index 981b4de12807..becdbdc0fffa 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -90,6 +90,8 @@ Definition: Should contain the following entries - "core" Clocks the pcie hw block - "phy" Clocks the pcie PHY block + - "aux" Clocks the pcie AUX block + - "ref" Clocks the pcie ref block - clock-names: Usage: required for apq8084/ipq4019 Value type: @@ -277,8 +279,10 @@ <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc PCIE_A_CLK>, <&gcc PCIE_H_CLK>, - <&gcc PCIE_PHY_CLK>; - clock-names = "core", "iface", "phy"; + <&gcc PCIE_PHY_CLK>, + <&gcc PCIE_AUX_CLK>, + <&gcc PCIE_ALT_REF_CLK>; + clock-names = "core", "iface", "phy", "aux", "ref"; resets = <&gcc PCIE_ACLK_RESET>, <&gcc PCIE_HCLK_RESET>, <&gcc PCIE_POR_RESET>, From patchwork Fri Mar 20 18:34:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 189895 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4D8A7C43333 for ; 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[79.53.232.203]) by smtp.googlemail.com with ESMTPSA id y13sm172916eje.3.2020.03.20.11.35.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Mar 2020 11:35:12 -0700 (PDT) From: Ansuel Smith To: Stanimir Varbanov Cc: Ansuel Smith , Abhishek Sahu , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Rob Herring , Mark Rutland , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 04/12] pcie: qcom: Fixed pcie_phy_clk branch issue Date: Fri, 20 Mar 2020 19:34:46 +0100 Message-Id: <20200320183455.21311-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200320183455.21311-1-ansuelsmth@gmail.com> References: <20200320183455.21311-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Following backtraces are observed in PCIe deinit operation. Hardware name: Qualcomm (Flattened Device Tree) (unwind_backtrace) from [] (show_stack+0x10/0x14) (show_stack) from [] (dump_stack+0x84/0x98) (dump_stack) from [] (warn_slowpath_common+0x9c/0xb8) (warn_slowpath_common) from [] (warn_slowpath_fmt+0x30/0x40) (warn_slowpath_fmt) from [] (clk_branch_wait+0x114/0x120) (clk_branch_wait) from [] (clk_core_disable+0xd0/0x1f4) (clk_core_disable) from [] (clk_disable+0x24/0x30) (clk_disable) from [] (qcom_pcie_deinit_v0+0x6c/0xb8) (qcom_pcie_deinit_v0) from [] (qcom_pcie_host_init+0xe0/0xe8) (qcom_pcie_host_init) from [] (dw_pcie_host_init+0x3b0/0x538) (dw_pcie_host_init) from [] (qcom_pcie_probe+0x20c/0x2e4) pcie_phy_clk is generated for PCIe controller itself and the GCC controls its branch operation. This error is coming since the assert operations turn off the parent clock before branch clock. Now this patch moves clk_disable_unprepare before assert operations. Similarly, during probe function, the clock branch operation should be done after dessert operation. Currently, it does not generate any error since bootloader enables the pcie_phy_clk but the same error is coming during probe, if bootloader disables pcie_phy_clk. Signed-off-by: Abhishek Sahu Signed-off-by: Ansuel Smith --- drivers/pci/controller/dwc/pcie-qcom.c | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 1fcc7fed8443..596731b54728 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -280,6 +280,7 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; + clk_disable_unprepare(res->phy_clk); reset_control_assert(res->pci_reset); reset_control_assert(res->axi_reset); reset_control_assert(res->ahb_reset); @@ -287,7 +288,6 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) reset_control_assert(res->phy_reset); clk_disable_unprepare(res->iface_clk); clk_disable_unprepare(res->core_clk); - clk_disable_unprepare(res->phy_clk); clk_disable_unprepare(res->aux_clk); clk_disable_unprepare(res->ref_clk); regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); @@ -325,12 +325,6 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) goto err_clk_core; } - ret = clk_prepare_enable(res->phy_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable phy clock\n"); - goto err_clk_phy; - } - ret = clk_prepare_enable(res->aux_clk); if (ret) { dev_err(dev, "cannot prepare/enable aux clock\n"); @@ -383,6 +377,12 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) return ret; } + ret = clk_prepare_enable(res->phy_clk); + if (ret) { + dev_err(dev, "cannot prepare/enable phy clock\n"); + goto err_deassert_ahb; + } + /* wait for clock acquisition */ usleep_range(1000, 1500); @@ -400,8 +400,6 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) err_clk_ref: clk_disable_unprepare(res->aux_clk); err_clk_aux: - clk_disable_unprepare(res->phy_clk); -err_clk_phy: clk_disable_unprepare(res->core_clk); err_clk_core: clk_disable_unprepare(res->iface_clk); From patchwork Fri Mar 20 18:34:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 189899 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B10DFC4332E for ; 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[79.53.232.203]) by smtp.googlemail.com with ESMTPSA id y13sm172916eje.3.2020.03.20.11.35.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Mar 2020 11:35:15 -0700 (PDT) From: Ansuel Smith To: Stanimir Varbanov Cc: Ansuel Smith , Sham Muthayyan , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Rob Herring , Mark Rutland , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 05/12] pcie: qcom: add missing reset for ipq806x Date: Fri, 20 Mar 2020 19:34:47 +0100 Message-Id: <20200320183455.21311-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200320183455.21311-1-ansuelsmth@gmail.com> References: <20200320183455.21311-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add missing ext reset used by ipq806x soc in pcie qcom driver Signed-off-by: Sham Muthayyan Signed-off-by: Ansuel Smith --- drivers/pci/controller/dwc/pcie-qcom.c | 24 ++++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 596731b54728..ecc22fd27ea6 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -95,6 +95,7 @@ struct qcom_pcie_resources_2_1_0 { struct reset_control *ahb_reset; struct reset_control *por_reset; struct reset_control *phy_reset; + struct reset_control *ext_reset; struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY]; }; @@ -272,6 +273,10 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie) if (IS_ERR(res->por_reset)) return PTR_ERR(res->por_reset); + res->ext_reset = devm_reset_control_get(dev, "ext"); + if (IS_ERR(res->ext_reset)) + return PTR_ERR(res->ext_reset); + res->phy_reset = devm_reset_control_get_exclusive(dev, "phy"); return PTR_ERR_OR_ZERO(res->phy_reset); } @@ -285,6 +290,7 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) reset_control_assert(res->axi_reset); reset_control_assert(res->ahb_reset); reset_control_assert(res->por_reset); + reset_control_assert(res->ext_reset); reset_control_assert(res->phy_reset); clk_disable_unprepare(res->iface_clk); clk_disable_unprepare(res->core_clk); @@ -301,18 +307,18 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) u32 val; int ret; + ret = reset_control_assert(res->ahb_reset); + if (ret) { + dev_err(dev, "cannot assert ahb reset\n"); + return ret; + } + ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies); if (ret < 0) { dev_err(dev, "cannot enable regulators\n"); return ret; } - ret = reset_control_assert(res->ahb_reset); - if (ret) { - dev_err(dev, "cannot assert ahb reset\n"); - goto err_assert_ahb; - } - ret = clk_prepare_enable(res->iface_clk); if (ret) { dev_err(dev, "cannot prepare/enable iface clock\n"); @@ -343,6 +349,12 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) goto err_deassert_ahb; } + ret = reset_control_deassert(res->ext_reset); + if (ret) { + dev_err(dev, "cannot assert ext reset\n"); + goto err_deassert_ahb; + } + /* enable PCIe clocks and resets */ val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); val &= ~BIT(0); From patchwork Fri Mar 20 18:34:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 189896 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98222C10F29 for ; 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[79.53.232.203]) by smtp.googlemail.com with ESMTPSA id y13sm172916eje.3.2020.03.20.11.35.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Mar 2020 11:35:22 -0700 (PDT) From: Ansuel Smith To: Stanimir Varbanov Cc: Ansuel Smith , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Rob Herring , Mark Rutland , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 08/12] devicetree: bindings: pci: add phy-tx0-term-offset to qcom, pcie Date: Fri, 20 Mar 2020 19:34:50 +0100 Message-Id: <20200320183455.21311-8-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200320183455.21311-1-ansuelsmth@gmail.com> References: <20200320183455.21311-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Document phy-tx0-term-offset propriety to qcom pcie driver Signed-off-by: Ansuel Smith --- Documentation/devicetree/bindings/pci/qcom,pcie.txt | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index 6efcef040741..8c1d014f37b0 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -254,6 +254,12 @@ - "perst-gpios" PCIe endpoint reset signal line - "wake-gpios" PCIe endpoint wake signal line +- phy-tx0-term-offset: + Usage: optional + Value type: + Definition: If not defined is 0. In ipq806x is set to 7. In newer + revision (v2.0) the offset is zero. + * Example for ipq/apq8064 pcie@1b500000 { compatible = "qcom,pcie-apq8064", "qcom,pcie-ipq8064", "snps,dw-pcie"; @@ -293,6 +299,7 @@ reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; pinctrl-0 = <&pcie_pins_default>; pinctrl-names = "default"; + phy-tx0-term-offset = <7>; }; * Example for apq8084 From patchwork Fri Mar 20 18:34:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 189897 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 858E1C4332B for ; Fri, 20 Mar 2020 18:35:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6026420775 for ; Fri, 20 Mar 2020 18:35:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="rBAXr6Sf" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727539AbgCTSfb (ORCPT ); Fri, 20 Mar 2020 14:35:31 -0400 Received: from mail-ed1-f66.google.com ([209.85.208.66]:44481 "EHLO mail-ed1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725446AbgCTSfb (ORCPT ); Fri, 20 Mar 2020 14:35:31 -0400 Received: by mail-ed1-f66.google.com with SMTP id z3so8266718edq.11; Fri, 20 Mar 2020 11:35:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tGZNkaeSgH2Ia/qzhM5CNeT0pv+X7+3+Gb2pdjSMGCU=; b=rBAXr6Sf2nZ5TYuifwsb71mUsVZl34Q5Nb/L02j2b8yzwjCUnPFUuz4XfHWFlw4was dVfwR6ftScUpNVUNOgGxJG7kcFsd63d4Pb6k7apa0UdiiQKaPEkIYRqe3txhde/xN+Dp kpH6x0wvGtKloqgHtc2G7T235cg2aAG3mo/fZp3mVC0bBSgAnbfAaDL8lixk6bhbYumH maKA9PbACjkGTMJFWGLDeu1l59O2H+hBfz4F31ruUtWui6ZTnV3lie+PsJYiBCGcONTL n/gyeYQs0cgmsT8VU6cssE3r4YHFYzlj3f8vSPcLIp/yHwJKtA7jd5o83veckyVYjcYP nlXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tGZNkaeSgH2Ia/qzhM5CNeT0pv+X7+3+Gb2pdjSMGCU=; b=rGDooNJ06IH7gOBsDvkqTG1AqDGGyJYQtsznOXkp0Tuhksiod+vEL/YKe2APn1u2Kw +aaZxLNisxRqlVIFG+tRQuNm87c4xpn93nqT/78cOBYQs/VryJ402aPj93fN0p9TqvRe CzZqcZvXWuJL+v039rWQAsYxnuDWbzHvWYmX0hW/vvuZIsN56MdkblUu1hRxcdA+VRaa v151msPYzsuK1CAdvrfYjdH7uUaPTNRBbBUcUlknnkYRVuHyhW/VyhFSPIu5vl+5XTQw xZmuXZ/+myvh9FD1SADjbfVLfiuzmIq2clZF+rSe1UZjEjt4wq7JSj/7U8PA76UEqr9I fnxg== X-Gm-Message-State: ANhLgQ2hWa9PJCdS2+brg5dkUz/SZQyZq8M3hHgHrRjevEpCPU60Lm/Y jjShIeWB3IAUlK58p+ArFlo= X-Google-Smtp-Source: ADFU+vviOQwMW3HASaguuY6rBmj6IAJbDOHwyuY4ghziSVXDR/mOHFhjkk1oj9CihWdLHFXlxW8pyw== X-Received: by 2002:a17:906:fc01:: with SMTP id ov1mr9556367ejb.65.1584729329072; Fri, 20 Mar 2020 11:35:29 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host203-232-dynamic.53-79-r.retail.telecomitalia.it. [79.53.232.203]) by smtp.googlemail.com with ESMTPSA id y13sm172916eje.3.2020.03.20.11.35.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Mar 2020 11:35:28 -0700 (PDT) From: Ansuel Smith To: Stanimir Varbanov Cc: Sham Muthayyan , Ansuel Smith , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Rob Herring , Mark Rutland , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 10/12] pcie: qcom: add Force GEN1 support Date: Fri, 20 Mar 2020 19:34:52 +0100 Message-Id: <20200320183455.21311-10-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200320183455.21311-1-ansuelsmth@gmail.com> References: <20200320183455.21311-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Sham Muthayyan Add Force GEN1 support needed in some ipq806x board that needs to limit some pcie line to gen1 for some hardware limitation Signed-off-by: Sham Muthayyan Signed-off-by: Ansuel Smith --- drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index e26ba8f63d4f..03130a3206b4 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -123,6 +123,8 @@ #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358 #define SLV_ADDR_SPACE_SZ 0x10000000 +#define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xA0 + #define DEVICE_TYPE_RC 0x4 #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3 @@ -223,6 +225,7 @@ struct qcom_pcie { struct phy *phy; struct gpio_desc *reset; const struct qcom_pcie_ops *ops; + uint32_t force_gen1; }; #define to_qcom_pcie(x) dev_get_drvdata((x)->dev) @@ -515,6 +518,11 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) /* wait for clock acquisition */ usleep_range(1000, 1500); + if (pcie->force_gen1) { + writel_relaxed((readl_relaxed( + pcie->pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2) | 1), + pcie->pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2); + } /* Set the Max TLP size to 2K, instead of using default of 4K */ @@ -1487,6 +1495,8 @@ static int qcom_pcie_probe(struct platform_device *pdev) struct dw_pcie *pci; struct qcom_pcie *pcie; int ret; + uint32_t force_gen1 = 0; + struct device_node *np = pdev->dev.of_node; pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); if (!pcie) @@ -1517,6 +1527,9 @@ static int qcom_pcie_probe(struct platform_device *pdev) goto err_pm_runtime_put; } + of_property_read_u32(np, "force_gen1", &force_gen1); + pcie->force_gen1 = force_gen1; + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "parf"); 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[79.53.232.203]) by smtp.googlemail.com with ESMTPSA id y13sm172916eje.3.2020.03.20.11.35.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Mar 2020 11:35:31 -0700 (PDT) From: Ansuel Smith To: Stanimir Varbanov Cc: Ansuel Smith , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Rob Herring , Mark Rutland , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 11/12] devicetree: bindings: pci: add force_gen1 for qcom, pcie Date: Fri, 20 Mar 2020 19:34:53 +0100 Message-Id: <20200320183455.21311-11-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200320183455.21311-1-ansuelsmth@gmail.com> References: <20200320183455.21311-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Document force_gen1 optional definition to limit pcie line to GEN1 speed Signed-off-by: Ansuel Smith --- Documentation/devicetree/bindings/pci/qcom,pcie.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index 8c1d014f37b0..766876465c42 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -260,6 +260,11 @@ Definition: If not defined is 0. In ipq806x is set to 7. In newer revision (v2.0) the offset is zero. +- force_gen1: + Usage: optional + Value type: + Definition: Set 1 to force the pcie line to GEN1 + * Example for ipq/apq8064 pcie@1b500000 { compatible = "qcom,pcie-apq8064", "qcom,pcie-ipq8064", "snps,dw-pcie";