From patchwork Mon Mar 9 09:53:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sandeep Maheswaram X-Patchwork-Id: 190075 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F010DC3F2C6 for ; Mon, 9 Mar 2020 09:54:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CA90920674 for ; Mon, 9 Mar 2020 09:54:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726680AbgCIJyQ (ORCPT ); Mon, 9 Mar 2020 05:54:16 -0400 Received: from alexa-out-blr-01.qualcomm.com ([103.229.18.197]:55522 "EHLO alexa-out-blr-01.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726609AbgCIJyN (ORCPT ); Mon, 9 Mar 2020 05:54:13 -0400 Received: from ironmsg01-blr.qualcomm.com ([10.86.208.130]) by alexa-out-blr-01.qualcomm.com with ESMTP/TLS/AES256-SHA; 09 Mar 2020 15:24:02 +0530 Received: from c-sanm-linux.qualcomm.com ([10.206.25.31]) by ironmsg01-blr.qualcomm.com with ESMTP; 09 Mar 2020 15:23:42 +0530 Received: by c-sanm-linux.qualcomm.com (Postfix, from userid 2343233) id 246562418; Mon, 9 Mar 2020 15:23:41 +0530 (IST) From: Sandeep Maheswaram To: Andy Gross , Bjorn Andersson , Kishon Vijay Abraham I , Rob Herring , Mark Rutland , Stephen Boyd , Doug Anderson , Matthias Kaehlcke Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manu Gautam , Sandeep Maheswaram Subject: [PATCH v5 1/9] dt-bindings: phy: qcom, qusb2: Convert QUSB2 phy bindings to yaml Date: Mon, 9 Mar 2020 15:23:01 +0530 Message-Id: <1583747589-17267-2-git-send-email-sanm@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1583747589-17267-1-git-send-email-sanm@codeaurora.org> References: <1583747589-17267-1-git-send-email-sanm@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Convert QUSB2 phy bindings to DT schema format using json-schema. Signed-off-by: Sandeep Maheswaram Reviewed-by: Matthias Kaehlcke Reviewed-by: Stephen Boyd Reviewed-by: Rob Herring --- .../devicetree/bindings/phy/qcom,qusb2-phy.yaml | 149 +++++++++++++++++++++ .../devicetree/bindings/phy/qcom-qusb2-phy.txt | 68 ---------- 2 files changed, 149 insertions(+), 68 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml delete mode 100644 Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt diff --git a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml new file mode 100644 index 0000000..2342cd0 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml @@ -0,0 +1,149 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/qcom,qusb2-phy.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm QUSB2 phy controller + +maintainers: + - Manu Gautam + +description: + QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets. + +properties: + compatible: + enum: + - qcom,msm8996-qusb2-phy + - qcom,msm8998-qusb2-phy + - qcom,sdm845-qusb2-phy + reg: + maxItems: 1 + + "#phy-cells": + const: 0 + + clocks: + minItems: 2 + maxItems: 3 + items: + - description: phy config clock + - description: 19.2 MHz ref clk + - description: phy interface clock (Optional) + + clock-names: + minItems: 2 + maxItems: 3 + items: + - const: cfg_ahb + - const: ref + - const: iface + + vdda-pll-supply: + description: + Phandle to 1.8V regulator supply to PHY refclk pll block. + + vdda-phy-dpdm-supply: + description: + Phandle to 3.1V regulator supply to Dp/Dm port signals. + + resets: + maxItems: 1 + description: + Phandle to reset to phy block. + + nvmem-cells: + maxItems: 1 + description: + Phandle to nvmem cell that contains 'HS Tx trim' + tuning parameter value for qusb2 phy. + + qcom,tcsr-syscon: + description: + Phandle to TCSR syscon register region. + $ref: /schemas/types.yaml#/definitions/phandle + +if: + properties: + compatible: + contains: + const: qcom,sdm845-qusb2-phy +then: + properties: + qcom,imp-res-offset-value: + description: + It is a 6 bit value that specifies offset to be + added to PHY refgen RESCODE via IMP_CTRL1 register. It is a PHY + tuning parameter that may vary for different boards of same SOC. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - minimum: 0 + maximum: 63 + default: 0 + + qcom,hstx-trim-value: + description: + It is a 4 bit value that specifies tuning for HSTX + output current. + Possible range is - 15mA to 24mA (stepsize of 600 uA). + See dt-bindings/phy/phy-qcom-qusb2.h for applicable values. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - minimum: 0 + maximum: 15 + default: 3 + + qcom,preemphasis-level: + description: + It is a 2 bit value that specifies pre-emphasis level. + Possible range is 0 to 15% (stepsize of 5%). + See dt-bindings/phy/phy-qcom-qusb2.h for applicable values. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - minimum: 0 + maximum: 3 + default: 2 + + qcom,preemphasis-width: + description: + It is a 1 bit value that specifies how long the HSTX + pre-emphasis (specified using qcom,preemphasis-level) must be in + effect. Duration could be half-bit of full-bit. + See dt-bindings/phy/phy-qcom-qusb2.h for applicable values. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - minimum: 0 + maximum: 1 + default: 0 + +required: + - compatible + - reg + - "#phy-cells" + - clocks + - clock-names + - vdda-pll-supply + - vdda-phy-dpdm-supply + - resets + + +examples: + - | + #include + hsusb_phy: phy@7411000 { + compatible = "qcom,msm8996-qusb2-phy"; + reg = <0x7411000 0x180>; + #phy-cells = <0>; + + clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, + <&gcc GCC_RX1_USB2_CLKREF_CLK>; + clock-names = "cfg_ahb", "ref"; + + vdda-pll-supply = <&pm8994_l12>; + vdda-phy-dpdm-supply = <&pm8994_l24>; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + nvmem-cells = <&qusb2p_hstx_trim>; + }; diff --git a/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt deleted file mode 100644 index fe29f9e..0000000 --- a/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt +++ /dev/null @@ -1,68 +0,0 @@ -Qualcomm QUSB2 phy controller -============================= - -QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets. - -Required properties: - - compatible: compatible list, contains - "qcom,msm8996-qusb2-phy" for 14nm PHY on msm8996, - "qcom,msm8998-qusb2-phy" for 10nm PHY on msm8998, - "qcom,sdm845-qusb2-phy" for 10nm PHY on sdm845. - - - reg: offset and length of the PHY register set. - - #phy-cells: must be 0. - - - clocks: a list of phandles and clock-specifier pairs, - one for each entry in clock-names. - - clock-names: must be "cfg_ahb" for phy config clock, - "ref" for 19.2 MHz ref clk, - "iface" for phy interface clock (Optional). - - - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block. - - vdda-phy-dpdm-supply: Phandle to 3.1V regulator supply to Dp/Dm port signals. - - - resets: Phandle to reset to phy block. - -Optional properties: - - nvmem-cells: Phandle to nvmem cell that contains 'HS Tx trim' - tuning parameter value for qusb2 phy. - - - qcom,tcsr-syscon: Phandle to TCSR syscon register region. - - qcom,imp-res-offset-value: It is a 6 bit value that specifies offset to be - added to PHY refgen RESCODE via IMP_CTRL1 register. It is a PHY - tuning parameter that may vary for different boards of same SOC. - This property is applicable to only QUSB2 v2 PHY (sdm845). - - qcom,hstx-trim-value: It is a 4 bit value that specifies tuning for HSTX - output current. - Possible range is - 15mA to 24mA (stepsize of 600 uA). - See dt-bindings/phy/phy-qcom-qusb2.h for applicable values. - This property is applicable to only QUSB2 v2 PHY (sdm845). - Default value is 22.2mA for sdm845. - - qcom,preemphasis-level: It is a 2 bit value that specifies pre-emphasis level. - Possible range is 0 to 15% (stepsize of 5%). - See dt-bindings/phy/phy-qcom-qusb2.h for applicable values. - This property is applicable to only QUSB2 v2 PHY (sdm845). - Default value is 10% for sdm845. -- qcom,preemphasis-width: It is a 1 bit value that specifies how long the HSTX - pre-emphasis (specified using qcom,preemphasis-level) must be in - effect. Duration could be half-bit of full-bit. - See dt-bindings/phy/phy-qcom-qusb2.h for applicable values. - This property is applicable to only QUSB2 v2 PHY (sdm845). - Default value is full-bit width for sdm845. - -Example: - hsusb_phy: phy@7411000 { - compatible = "qcom,msm8996-qusb2-phy"; - reg = <0x7411000 0x180>; - #phy-cells = <0>; - - clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, - <&gcc GCC_RX1_USB2_CLKREF_CLK>, - clock-names = "cfg_ahb", "ref"; - - vdda-pll-supply = <&pm8994_l12>; - vdda-phy-dpdm-supply = <&pm8994_l24>; - - resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; - nvmem-cells = <&qusb2p_hstx_trim>; - }; From patchwork Mon Mar 9 09:53:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sandeep Maheswaram X-Patchwork-Id: 190072 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 55A7BC10F29 for ; Mon, 9 Mar 2020 09:54:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2EAEF20828 for ; Mon, 9 Mar 2020 09:54:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726495AbgCIJyH (ORCPT ); Mon, 9 Mar 2020 05:54:07 -0400 Received: from alexa-out-blr-01.qualcomm.com ([103.229.18.197]:36868 "EHLO alexa-out-blr-01.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726450AbgCIJyH (ORCPT ); Mon, 9 Mar 2020 05:54:07 -0400 Received: from ironmsg01-blr.qualcomm.com ([10.86.208.130]) by alexa-out-blr-01.qualcomm.com with ESMTP/TLS/AES256-SHA; 09 Mar 2020 15:24:02 +0530 Received: from c-sanm-linux.qualcomm.com ([10.206.25.31]) by ironmsg01-blr.qualcomm.com with ESMTP; 09 Mar 2020 15:23:42 +0530 Received: by c-sanm-linux.qualcomm.com (Postfix, from userid 2343233) id D5B2F230B; Mon, 9 Mar 2020 15:23:41 +0530 (IST) From: Sandeep Maheswaram To: Andy Gross , Bjorn Andersson , Kishon Vijay Abraham I , Rob Herring , Mark Rutland , Stephen Boyd , Doug Anderson , Matthias Kaehlcke Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manu Gautam , Sandeep Maheswaram Subject: [PATCH v5 2/9] dt-bindings: phy: qcom, qusb2: Add compatibles for QUSB2 V2 phy and SC7180 Date: Mon, 9 Mar 2020 15:23:02 +0530 Message-Id: <1583747589-17267-3-git-send-email-sanm@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1583747589-17267-1-git-send-email-sanm@codeaurora.org> References: <1583747589-17267-1-git-send-email-sanm@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add compatibles for generic QUSB2 V2 phy which can be used for sdm845 and sc7180. Signed-off-by: Sandeep Maheswaram Reviewed-by: Matthias Kaehlcke Reviewed-by: Stephen Boyd Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml index 2342cd0..60124a3 100644 --- a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml @@ -15,10 +15,16 @@ description: properties: compatible: - enum: - - qcom,msm8996-qusb2-phy - - qcom,msm8998-qusb2-phy - - qcom,sdm845-qusb2-phy + oneOf: + - items: + - enum: + - qcom,msm8996-qusb2-phy + - qcom,msm8998-qusb2-phy + - items: + - enum: + - qcom,sc7180-qusb2-phy + - qcom,sdm845-qusb2-phy + - const: qcom,qusb2-v2-phy reg: maxItems: 1 From patchwork Mon Mar 9 09:53:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sandeep Maheswaram X-Patchwork-Id: 190073 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 14F4CC10F28 for ; Mon, 9 Mar 2020 09:54:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id EC2432086A for ; Mon, 9 Mar 2020 09:54:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726548AbgCIJyJ (ORCPT ); Mon, 9 Mar 2020 05:54:09 -0400 Received: from alexa-out-blr-01.qualcomm.com ([103.229.18.197]:55522 "EHLO alexa-out-blr-01.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726465AbgCIJyI (ORCPT ); Mon, 9 Mar 2020 05:54:08 -0400 Received: from ironmsg01-blr.qualcomm.com ([10.86.208.130]) by alexa-out-blr-01.qualcomm.com with ESMTP/TLS/AES256-SHA; 09 Mar 2020 15:24:02 +0530 Received: from c-sanm-linux.qualcomm.com ([10.206.25.31]) by ironmsg01-blr.qualcomm.com with ESMTP; 09 Mar 2020 15:23:44 +0530 Received: by c-sanm-linux.qualcomm.com (Postfix, from userid 2343233) id 4808B230B; Mon, 9 Mar 2020 15:23:43 +0530 (IST) From: Sandeep Maheswaram To: Andy Gross , Bjorn Andersson , Kishon Vijay Abraham I , Rob Herring , Mark Rutland , Stephen Boyd , Doug Anderson , Matthias Kaehlcke Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manu Gautam , Sandeep Maheswaram Subject: [PATCH v5 4/9] dt-bindings: phy: qcom-qusb2: Add support for overriding Phy tuning parameters Date: Mon, 9 Mar 2020 15:23:04 +0530 Message-Id: <1583747589-17267-5-git-send-email-sanm@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1583747589-17267-1-git-send-email-sanm@codeaurora.org> References: <1583747589-17267-1-git-send-email-sanm@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add support for overriding QUSB2 V2 phy tuning parameters in device tree bindings. Signed-off-by: Sandeep Maheswaram Reviewed-by: Rob Herring Reviewed-by: Stephen Boyd Reviewed-by: Matthias Kaehlcke --- .../devicetree/bindings/phy/qcom,qusb2-phy.yaml | 32 +++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml index 60124a3..144ae29 100644 --- a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml @@ -75,7 +75,7 @@ if: properties: compatible: contains: - const: qcom,sdm845-qusb2-phy + const: qcom,qusb2-v2-phy then: properties: qcom,imp-res-offset-value: @@ -89,6 +89,26 @@ then: maximum: 63 default: 0 + qcom,bias-ctrl-value: + description: + It is a 6 bit value that specifies bias-ctrl-value. It is a PHY + tuning parameter that may vary for different boards of same SOC. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - minimum: 0 + maximum: 63 + default: 0 + + qcom,charge-ctrl-value: + description: + It is a 2 bit value that specifies charge-ctrl-value. It is a PHY + tuning parameter that may vary for different boards of same SOC. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - minimum: 0 + maximum: 3 + default: 0 + qcom,hstx-trim-value: description: It is a 4 bit value that specifies tuning for HSTX @@ -124,6 +144,16 @@ then: maximum: 1 default: 0 + qcom,hsdisc-trim-value: + description: + It is a 2 bit value tuning parameter that control disconnect + threshold and may vary for different boards of same SOC. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - minimum: 0 + maximum: 3 + default: 0 + required: - compatible - reg From patchwork Mon Mar 9 09:53:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sandeep Maheswaram X-Patchwork-Id: 190071 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E88BC10F27 for ; Mon, 9 Mar 2020 09:54:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3077C20828 for ; Mon, 9 Mar 2020 09:54:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726391AbgCIJyF (ORCPT ); Mon, 9 Mar 2020 05:54:05 -0400 Received: from alexa-out-blr-01.qualcomm.com ([103.229.18.197]:36868 "EHLO alexa-out-blr-01.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725942AbgCIJyF (ORCPT ); Mon, 9 Mar 2020 05:54:05 -0400 Received: from ironmsg01-blr.qualcomm.com ([10.86.208.130]) by alexa-out-blr-01.qualcomm.com with ESMTP/TLS/AES256-SHA; 09 Mar 2020 15:24:02 +0530 Received: from c-sanm-linux.qualcomm.com ([10.206.25.31]) by ironmsg01-blr.qualcomm.com with ESMTP; 09 Mar 2020 15:23:45 +0530 Received: by c-sanm-linux.qualcomm.com (Postfix, from userid 2343233) id BE4F5230B; Mon, 9 Mar 2020 15:23:44 +0530 (IST) From: Sandeep Maheswaram To: Andy Gross , Bjorn Andersson , Kishon Vijay Abraham I , Rob Herring , Mark Rutland , Stephen Boyd , Doug Anderson , Matthias Kaehlcke Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manu Gautam , Sandeep Maheswaram Subject: [PATCH v5 6/9] phy: qcom-qusb2: Add new overriding tuning parameters in QUSB2 V2 PHY Date: Mon, 9 Mar 2020 15:23:06 +0530 Message-Id: <1583747589-17267-7-git-send-email-sanm@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1583747589-17267-1-git-send-email-sanm@codeaurora.org> References: <1583747589-17267-1-git-send-email-sanm@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Added support for overriding bias-ctrl-value,charge-ctrl-value and hsdisc-trim-value params for QUSB2 V2 PHY Signed-off-by: Sandeep Maheswaram --- drivers/phy/qualcomm/phy-qcom-qusb2.c | 51 +++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c index 44841c9..3708d43 100644 --- a/drivers/phy/qualcomm/phy-qcom-qusb2.c +++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c @@ -66,6 +66,14 @@ #define IMP_RES_OFFSET_MASK GENMASK(5, 0) #define IMP_RES_OFFSET_SHIFT 0x0 +/* QUSB2PHY_PLL_BIAS_CONTROL_2 register bits */ +#define BIAS_CTRL2_RES_OFFSET_MASK GENMASK(5, 0) +#define BIAS_CTRL2_RES_OFFSET_SHIFT 0x0 + +/* QUSB2PHY_CHG_CONTROL_2 register bits */ +#define CHG_CTRL2_OFFSET_MASK GENMASK(5, 4) +#define CHG_CTRL2_OFFSET_SHIFT 0x4 + /* QUSB2PHY_PORT_TUNE1 register bits */ #define HSTX_TRIM_MASK GENMASK(7, 4) #define HSTX_TRIM_SHIFT 0x4 @@ -73,6 +81,10 @@ #define PREEMPHASIS_EN_MASK GENMASK(1, 0) #define PREEMPHASIS_EN_SHIFT 0x0 +/* QUSB2PHY_PORT_TUNE2 register bits */ +#define HSDISC_TRIM_MASK GENMASK(1, 0) +#define HSDISC_TRIM_SHIFT 0x0 + #define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO 0x04 #define QUSB2PHY_PLL_CLOCK_INVERTERS 0x18c #define QUSB2PHY_PLL_CMODE 0x2c @@ -291,12 +303,18 @@ struct override_param { * @hstx_trim: HSTX_TRIM to be updated in TUNE1 register * @preemphasis: Amplitude Pre-Emphasis to be updated in TUNE1 register * @preemphasis_width: half/full-width Pre-Emphasis updated via TUNE1 + * @bias_ctrl: bias ctrl to be updated in BIAS_CONTROL_2 register + * @charge_ctrl: charge ctrl to be updated in CHG_CTRL2 register + * @hsdisc_trim: disconnect threshold to be updated in TUNE2 register */ struct override_params { struct override_param imp_res_offset; struct override_param hstx_trim; struct override_param preemphasis; struct override_param preemphasis_width; + struct override_param bias_ctrl; + struct override_param charge_ctrl; + struct override_param hsdisc_trim; }; /** @@ -409,6 +427,16 @@ static void qusb2_phy_override_phy_params(struct qusb2_phy *qphy) or->imp_res_offset.value << IMP_RES_OFFSET_SHIFT, IMP_RES_OFFSET_MASK); + if (or->bias_ctrl.override) + qusb2_write_mask(qphy->base, QUSB2PHY_PLL_BIAS_CONTROL_2, + or->bias_ctrl.value << BIAS_CTRL2_RES_OFFSET_SHIFT, + BIAS_CTRL2_RES_OFFSET_MASK); + + if (or->charge_ctrl.override) + qusb2_write_mask(qphy->base, QUSB2PHY_CHG_CTRL2, + or->charge_ctrl.value << CHG_CTRL2_OFFSET_SHIFT, + CHG_CTRL2_OFFSET_MASK); + if (or->hstx_trim.override) qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1], or->hstx_trim.value << HSTX_TRIM_SHIFT, @@ -430,6 +458,11 @@ static void qusb2_phy_override_phy_params(struct qusb2_phy *qphy) cfg->regs[QUSB2PHY_PORT_TUNE1], PREEMPH_WIDTH_HALF_BIT); } + + if (or->hsdisc_trim.override) + qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2], + or->hsdisc_trim.value << HSDISC_TRIM_SHIFT, + HSDISC_TRIM_MASK); } /* @@ -879,6 +912,18 @@ static int qusb2_phy_probe(struct platform_device *pdev) or->imp_res_offset.override = true; } + if (!of_property_read_u32(dev->of_node, "qcom,bias-ctrl-value", + &value)) { + or->bias_ctrl.value = (u8)value; + or->bias_ctrl.override = true; + } + + if (!of_property_read_u32(dev->of_node, "qcom,charge-ctrl-value", + &value)) { + or->charge_ctrl.value = (u8)value; + or->charge_ctrl.override = true; + } + if (!of_property_read_u32(dev->of_node, "qcom,hstx-trim-value", &value)) { or->hstx_trim.value = (u8)value; @@ -897,6 +942,12 @@ static int qusb2_phy_probe(struct platform_device *pdev) or->preemphasis_width.override = true; } + if (!of_property_read_u32(dev->of_node, "qcom,hsdisc-trim-value", + &value)) { + or->hsdisc_trim.value = (u8)value; + or->hsdisc_trim.override = true; + } + pm_runtime_set_active(dev); pm_runtime_enable(dev); /* From patchwork Mon Mar 9 09:53:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sandeep Maheswaram X-Patchwork-Id: 190074 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C9DE8C18E5A for ; Mon, 9 Mar 2020 09:54:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A23ED20863 for ; Mon, 9 Mar 2020 09:54:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726612AbgCIJyK (ORCPT ); Mon, 9 Mar 2020 05:54:10 -0400 Received: from alexa-out-blr-01.qualcomm.com ([103.229.18.197]:55522 "EHLO alexa-out-blr-01.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726556AbgCIJyK (ORCPT ); Mon, 9 Mar 2020 05:54:10 -0400 Received: from ironmsg01-blr.qualcomm.com ([10.86.208.130]) by alexa-out-blr-01.qualcomm.com with ESMTP/TLS/AES256-SHA; 09 Mar 2020 15:24:03 +0530 Received: from c-sanm-linux.qualcomm.com ([10.206.25.31]) by ironmsg01-blr.qualcomm.com with ESMTP; 09 Mar 2020 15:23:46 +0530 Received: by c-sanm-linux.qualcomm.com (Postfix, from userid 2343233) id 7D4E42418; Mon, 9 Mar 2020 15:23:45 +0530 (IST) From: Sandeep Maheswaram To: Andy Gross , Bjorn Andersson , Kishon Vijay Abraham I , Rob Herring , Mark Rutland , Stephen Boyd , Doug Anderson , Matthias Kaehlcke Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manu Gautam , Sandeep Maheswaram Subject: [PATCH v5 7/9] arm64: dts: qcom: sc7180: Add generic QUSB2 V2 Phy compatible Date: Mon, 9 Mar 2020 15:23:07 +0530 Message-Id: <1583747589-17267-8-git-send-email-sanm@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1583747589-17267-1-git-send-email-sanm@codeaurora.org> References: <1583747589-17267-1-git-send-email-sanm@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Use generic QUSB2 V2 Phy configuration for SC7180. Signed-off-by: Sandeep Maheswaram Reviewed-by: Matthias Kaehlcke Reviewed-by: Stephen Boyd --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 253274d..1d1e09d 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1277,7 +1277,7 @@ }; usb_1_hsphy: phy@88e3000 { - compatible = "qcom,sc7180-qusb2-phy"; + compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy"; reg = <0 0x088e3000 0 0x400>; status = "disabled"; #phy-cells = <0>;