From patchwork Fri Jan 24 22:42:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 190548 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C211EC47409 for ; Fri, 24 Jan 2020 22:43:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 968932081E for ; Fri, 24 Jan 2020 22:43:20 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="DH4yPU/+" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387404AbgAXWnT (ORCPT ); Fri, 24 Jan 2020 17:43:19 -0500 Received: from mail-pj1-f66.google.com ([209.85.216.66]:35045 "EHLO mail-pj1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387402AbgAXWnS (ORCPT ); Fri, 24 Jan 2020 17:43:18 -0500 Received: by mail-pj1-f66.google.com with SMTP id q39so474523pjc.0 for ; Fri, 24 Jan 2020 14:43:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XUY8OKSzBPGKXsy9C12HX4Zd6On+8bszenkjFTAhVcw=; b=DH4yPU/+4ENvZ1SHdmkXG/qDzhONJtANeKgsBWF2MKama9XzUmkblLRrT/cItCZKj8 8Y2BMYOHgoRy5Bf8ONQUvRQ9k0wgYTzO7ax770GkY60FXeHJNdvANDEoCA0UBkaZmXuq QICm4GNs/WQDglT6iZ7Ib965Jp/q1Yqp5t0JY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XUY8OKSzBPGKXsy9C12HX4Zd6On+8bszenkjFTAhVcw=; b=Tkb3PcXzdYJ+0cbTv+ptmtIfOpwZFHQljt9xwlYtjLU1CRsM9laFfhBcvmpdiFG1GH evcnOTVarGApUZGY/qoxr5nT1Xycbt/ZYpO64iK5WSiLKbdapUwxiugvQQEMIwEYqv4n x/bjGaq4m6pyXpq3JdZHThJDHOgZG8TWNmgIyOXtp1u0QlwDZef+gzwMGrAAOrOSik5r cndMzQeFs2zfAdeAAFp51L8VN69K+bBt2OPG9mx+sQPpA8bBwQsYuYIeM1SjxDrQ8b2e gOhcfqZTA2VdHf0I2PGmd58TOchuQh5PNEyZqhOa8YbSknnvDtv+wqDzdxvKnwTvuLEH ZnHA== X-Gm-Message-State: APjAAAVzQhhhnngKCYL1E+CI60gHCA4BB1FiXKofbcSNw/Nh07qRhNTp STdtNptTy7yiiceCnkbDR8vzog== X-Google-Smtp-Source: APXvYqx5KfK3OEW+qx8AJSVzFCWaLqn2Fo+x2QCA7ODGdtOJTbEJkWdllo7poK33dXuSQDkC1pMurw== X-Received: by 2002:a17:90b:342:: with SMTP id fh2mr1666659pjb.23.1579905797991; Fri, 24 Jan 2020 14:43:17 -0800 (PST) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id o2sm7690948pjo.26.2020.01.24.14.43.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jan 2020 14:43:17 -0800 (PST) From: Douglas Anderson To: Rob Herring , Andy Gross , Bjorn Andersson , Stephen Boyd Cc: Jeffrey Hugo , Taniya Das , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, harigovi@codeaurora.org, mka@chromium.org, kalyan_t@codeaurora.org, Mark Rutland , linux-clk@vger.kernel.org, hoegsberg@chromium.org, Douglas Anderson , Michael Turquette , Stephen Boyd , linux-kernel@vger.kernel.org Subject: [PATCH v2 02/10] dt-bindings: clock: Fix qcom, dispcc bindings for sdm845/sc7180 Date: Fri, 24 Jan 2020 14:42:17 -0800 Message-Id: <20200124144154.v2.2.I0c4bbb0f75a0880cd4bd90d8b267271e2375e0d0@changeid> X-Mailer: git-send-email 2.25.0.341.g760bfbb309-goog In-Reply-To: <20200124224225.22547-1-dianders@chromium.org> References: <20200124224225.22547-1-dianders@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The qcom,dispcc bindings had a few problems with them: 1. They didn't specify all the clocks that dispcc is a client of. Specifically on sc7180 there are two clocks from the DSI PHY and two from the DP PHY. On sdm845 there are actually two DSI PHYs (each of which has two clocks). These all need to be specified. 2. The sdm845.dtsi has existed for quite some time without specifying the clocks. The Linux driver was relying on global names to match things up. While we should transition things, it should be noted in the bindings. NOTE: It may be slightly controversial that I didn't re-order the clocks and name the "DSI" clocks on sc7180 to "dsi0". That would have allowed me to have a single table and just use minItems/maxItems to specify that sc7180 only had one DSI PHY. I almost did that, but it felt a little weird. Why did the DSI clock have a 0 but not the DP clock? If we add a SoC that has a 2nd DP port then we can't retroactively name old ones. What if we have a SoC that has HDMI but only one DSI lane? It felt cleaner to me to just duplicate. Also note that I updated the example. Fixes: 5d28e44ba630 ("dt-bindings: clock: Add YAML schemas for the QCOM DISPCC clock bindings") Signed-off-by: Douglas Anderson --- Changes in v2: - Patch ("dt-bindings: clock: Fix qcom,dispcc...") new for v2. .../bindings/clock/qcom,dispcc.yaml | 87 +++++++++++++++---- 1 file changed, 71 insertions(+), 16 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc.yaml index 9c58e02a1de1..560c52ce3da5 100644 --- a/Documentation/devicetree/bindings/clock/qcom,dispcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc.yaml @@ -19,18 +19,6 @@ properties: - qcom,sc7180-dispcc - qcom,sdm845-dispcc - clocks: - minItems: 1 - maxItems: 2 - items: - - description: Board XO source - - description: GPLL0 source from GCC - - clock-names: - items: - - const: xo - - const: gpll0 - '#clock-cells': const: 1 @@ -52,16 +40,83 @@ required: - '#reset-cells' - '#power-domain-cells' +if: + properties: + compatible: + contains: + const: qcom,sc7180-dispcc +then: + properties: + clocks: + items: + - description: Board XO source + - description: GPLL0 source from GCC + - description: Byte clock from DSI PHY + - description: Pixel clock from DSI PHY + - description: Link clock from DP PHY + - description: VCO DIV clock from DP PHY + + clock-names: + items: + - const: xo + - const: gpll0 + - const: dsi_phy_pll_byte + - const: dsi_phy_pll_pixel + - const: dp_phy_pll_link + - const: dp_phy_pll_vco_div + +else: + if: + # NOTE: sdm845.dtsi existed for quite some time and specified no clocks. + # The code had to use hardcoded mechanisms to find the input clocks. + # Any sdm845 device trees should be transitioned, but actual code may + # need to handle old dts files. + properties: + compatible: + contains: + const: qcom,sdm845-dispcc + then: + properties: + clocks: + items: + - description: Board XO source + - description: GPLL0 source from GCC + - description: Byte clock from DSI PHY0 + - description: Pixel clock from DSI PHY0 + - description: Byte clock from DSI PHY1 + - description: Pixel clock from DSI PHY1 + - description: Link clock from DP PHY + - description: VCO DIV clock from DP PHY + + clock-names: + items: + - const: xo + - const: gpll0 + - const: dsi0_phy_pll_byte + - const: dsi0_phy_pll_pixel + - const: dsi1_phy_pll_byte + - const: dsi1_phy_pll_pixel + - const: dp_phy_pll_link + - const: dp_phy_pll_vco_div + examples: # Example of DISPCC with clock node properties for SDM845: - | + #include + #include clock-controller@af00000 { compatible = "qcom,sdm845-dispcc"; - reg = <0xaf00000 0x10000>; - clocks = <&rpmhcc 0>, <&gcc 24>; - clock-names = "xo", "gpll0"; + reg = <0 0x0af00000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_DISP_GPLL0_CLK_SRC>, + <&dsi0_phy 0>, <&dsi0_phy 1>, + <&dsi1_phy 0>, <&dsi1_phy 1>, + <&dp_phy 0>, <&dp_phy 1>; + clock-names = "xo", "gpll0", + "dsi0_phy_pll_byte", "dsi0_phy_pll_pixel", + "dsi1_phy_pll_byte", "dsi1_phy_pll_pixel", + "dp_phy_pll_link", "dp_phy_pll_vco_div"; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; - }; + }; ... From patchwork Fri Jan 24 22:42:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 190544 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 63CB8C3F68F for ; Fri, 24 Jan 2020 22:43:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 38E852071E for ; Fri, 24 Jan 2020 22:43:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="V2NA5DrG" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387559AbgAXWnx (ORCPT ); Fri, 24 Jan 2020 17:43:53 -0500 Received: from mail-pf1-f196.google.com ([209.85.210.196]:34496 "EHLO mail-pf1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387435AbgAXWnW (ORCPT ); Fri, 24 Jan 2020 17:43:22 -0500 Received: by mail-pf1-f196.google.com with SMTP id i6so1810593pfc.1 for ; Fri, 24 Jan 2020 14:43:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WwMmfsPkXdXCpaGsa/Vhjbeiu4wcqbZZLVDwLapzju4=; b=V2NA5DrGCfEhQgH9jV86zkbxJnkeRBelGIWAFB97cPgMuGMopB1kx/VIBF3t8ZswoL XVlURC/Q7V2+fK/5NFs18VgfPm0YfDfIZql6rDGJCazPqE9rjkLyMi2Os7KONIl49Wop VsfQ5cOrJMXbbi0CifDItHNoEiHEiZAoKp2MA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WwMmfsPkXdXCpaGsa/Vhjbeiu4wcqbZZLVDwLapzju4=; b=IlvjmBTg1eHExeAdh7C6Sdli1UjIYue2DFdqeY2+vnjtc2qyMlyfaPp3Vk5RtqDR5s 9DJhUpzGho6Me2ciP3mpEHWghDdxlIGfSU5YkQw2wao+DoYQPpylLZwdbuokWFoCrFOx V0Y0k1cL/lAyT1uhtbisnZw3IwzX2OMWhAukZ/9hOSAR59bXIoMtL74+lmtxEGbE+IEo H8FRWFh0yZYxsgYqQxpmTqPynNfxjuebD269nTYNMSFdapu2txcMtkdvMPZVRlk4W4o8 sShELyGODE4RcFwp6yOIbe5pLGN9YiTOy8PhU2SeQkLCG09RkuSQ450pjdI8EZd9ksAp jm0g== X-Gm-Message-State: APjAAAXYz+QeOFABpo31n4+D+JBzIT33fuoqI9mgXrJ0lZCGgTt34+HW WpsXtrHdL5Wa6DW0UgVzsfgW8g== X-Google-Smtp-Source: APXvYqz09IB9wjq2TIbSib3i7IBWc2d69f4jcnNd7AKOKXWKfAq7g+mY64Cbl3ttZtEXDtRT6EGNZg== X-Received: by 2002:aa7:864a:: with SMTP id a10mr5567180pfo.233.1579905801319; Fri, 24 Jan 2020 14:43:21 -0800 (PST) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id o2sm7690948pjo.26.2020.01.24.14.43.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jan 2020 14:43:20 -0800 (PST) From: Douglas Anderson To: Rob Herring , Andy Gross , Bjorn Andersson , Stephen Boyd Cc: Jeffrey Hugo , Taniya Das , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, harigovi@codeaurora.org, mka@chromium.org, kalyan_t@codeaurora.org, Mark Rutland , linux-clk@vger.kernel.org, hoegsberg@chromium.org, Douglas Anderson , Michael Turquette , Stephen Boyd , linux-kernel@vger.kernel.org Subject: [PATCH v2 05/10] clk: qcom: Fix sc7180 dispcc parent data Date: Fri, 24 Jan 2020 14:42:20 -0800 Message-Id: <20200124144154.v2.5.If590c468722d2985cea63adf60c0d2b3098f37d9@changeid> X-Mailer: git-send-email 2.25.0.341.g760bfbb309-goog In-Reply-To: <20200124224225.22547-1-dianders@chromium.org> References: <20200124224225.22547-1-dianders@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The bindings file (qcom,dispcc.yaml) says that the two clocks that dispcc is a client of are named "xo" and "gpll0". That means we have to refer to them by those names. We weren't referring to "xo" properly in the driver. Then, in the patch ("dt-bindings: clock: Fix qcom,dispcc bindings for sdm845/sc7180") we clarify the names for all of the clocks that we are a client of. Fix all those too, also getting rid of the "fallback" names for them. Since sc7180 is still in infancy there is no reason to specify a fallback name. People should just get the device tree right. Since we didn't add the "test" clock to the bindings (apparently it's never used), kill it from the driver. If someone has a use for it we should add it to the bindings and bring it back. Instead of updating all of the sizes of the arrays now that the test clock is gone, switch to using the less error-prone ARRAY_SIZE. Not sure why it didn't always use that. Fixes: dd3d06622138 ("clk: qcom: Add display clock controller driver for SC7180") Signed-off-by: Douglas Anderson --- Changes in v2: - Patch ("clk: qcom: Fix sc7180 dispcc parent data") new for v2. drivers/clk/qcom/dispcc-sc7180.c | 63 ++++++++++++-------------------- 1 file changed, 24 insertions(+), 39 deletions(-) diff --git a/drivers/clk/qcom/dispcc-sc7180.c b/drivers/clk/qcom/dispcc-sc7180.c index 30c1e25d3edb..380eca3f847d 100644 --- a/drivers/clk/qcom/dispcc-sc7180.c +++ b/drivers/clk/qcom/dispcc-sc7180.c @@ -43,7 +43,7 @@ static struct clk_alpha_pll disp_cc_pll0 = { .hw.init = &(struct clk_init_data){ .name = "disp_cc_pll0", .parent_data = &(const struct clk_parent_data){ - .fw_name = "bi_tcxo", + .fw_name = "xo", }, .num_parents = 1, .ops = &clk_alpha_pll_fabia_ops, @@ -76,40 +76,32 @@ static struct clk_alpha_pll_postdiv disp_cc_pll0_out_even = { static const struct parent_map disp_cc_parent_map_0[] = { { P_BI_TCXO, 0 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data disp_cc_parent_data_0[] = { - { .fw_name = "bi_tcxo" }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, + { .fw_name = "xo" }, }; static const struct parent_map disp_cc_parent_map_1[] = { { P_BI_TCXO, 0 }, { P_DP_PHY_PLL_LINK_CLK, 1 }, { P_DP_PHY_PLL_VCO_DIV_CLK, 2 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data disp_cc_parent_data_1[] = { - { .fw_name = "bi_tcxo" }, - { .fw_name = "dp_phy_pll_link_clk", .name = "dp_phy_pll_link_clk" }, - { .fw_name = "dp_phy_pll_vco_div_clk", - .name = "dp_phy_pll_vco_div_clk"}, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, + { .fw_name = "xo" }, + { .fw_name = "dp_phy_pll_link" }, + { .fw_name = "dp_phy_pll_vco_div" }, }; static const struct parent_map disp_cc_parent_map_2[] = { { P_BI_TCXO, 0 }, { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data disp_cc_parent_data_2[] = { - { .fw_name = "bi_tcxo" }, - { .fw_name = "dsi0_phy_pll_out_byteclk", - .name = "dsi0_phy_pll_out_byteclk" }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, + { .fw_name = "xo" }, + { .fw_name = "dsi_phy_pll_byte" }, }; static const struct parent_map disp_cc_parent_map_3[] = { @@ -117,40 +109,33 @@ static const struct parent_map disp_cc_parent_map_3[] = { { P_DISP_CC_PLL0_OUT_MAIN, 1 }, { P_GPLL0_OUT_MAIN, 4 }, { P_DISP_CC_PLL0_OUT_EVEN, 5 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data disp_cc_parent_data_3[] = { - { .fw_name = "bi_tcxo" }, + { .fw_name = "xo" }, { .hw = &disp_cc_pll0.clkr.hw }, - { .fw_name = "gcc_disp_gpll0_clk_src" }, + { .fw_name = "gpll0" }, { .hw = &disp_cc_pll0_out_even.clkr.hw }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, }; static const struct parent_map disp_cc_parent_map_4[] = { { P_BI_TCXO, 0 }, { P_GPLL0_OUT_MAIN, 4 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data disp_cc_parent_data_4[] = { - { .fw_name = "bi_tcxo" }, - { .fw_name = "gcc_disp_gpll0_clk_src" }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, + { .fw_name = "xo" }, + { .fw_name = "gpll0" }, }; static const struct parent_map disp_cc_parent_map_5[] = { { P_BI_TCXO, 0 }, { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data disp_cc_parent_data_5[] = { - { .fw_name = "bi_tcxo" }, - { .fw_name = "dsi0_phy_pll_out_dsiclk", - .name = "dsi0_phy_pll_out_dsiclk" }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, + { .fw_name = "xo" }, + { .fw_name = "dsi_phy_pll_pixel" }, }; static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = { @@ -169,7 +154,7 @@ static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_ahb_clk_src", .parent_data = disp_cc_parent_data_4, - .num_parents = 3, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, @@ -183,7 +168,7 @@ static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_byte0_clk_src", .parent_data = disp_cc_parent_data_2, - .num_parents = 3, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), .flags = CLK_SET_RATE_PARENT, .ops = &clk_byte2_ops, }, @@ -203,7 +188,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_aux_clk_src", .parent_data = disp_cc_parent_data_0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -216,7 +201,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_crypto_clk_src", .parent_data = disp_cc_parent_data_1, - .num_parents = 4, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), .flags = CLK_SET_RATE_PARENT, .ops = &clk_byte2_ops, }, @@ -230,7 +215,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_link_clk_src", .parent_data = disp_cc_parent_data_1, - .num_parents = 4, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), .flags = CLK_SET_RATE_PARENT, .ops = &clk_byte2_ops, }, @@ -244,7 +229,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_pixel_clk_src", .parent_data = disp_cc_parent_data_1, - .num_parents = 4, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), .flags = CLK_SET_RATE_PARENT, .ops = &clk_dp_ops, }, @@ -259,7 +244,7 @@ static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_esc0_clk_src", .parent_data = disp_cc_parent_data_2, - .num_parents = 3, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), .ops = &clk_rcg2_ops, }, }; @@ -282,7 +267,7 @@ static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_mdp_clk_src", .parent_data = disp_cc_parent_data_3, - .num_parents = 5, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), .ops = &clk_rcg2_shared_ops, }, }; @@ -295,7 +280,7 @@ static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_pclk0_clk_src", .parent_data = disp_cc_parent_data_5, - .num_parents = 3, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), .flags = CLK_SET_RATE_PARENT, .ops = &clk_pixel_ops, }, @@ -310,7 +295,7 @@ static struct clk_rcg2 disp_cc_mdss_rot_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_rot_clk_src", .parent_data = disp_cc_parent_data_3, - .num_parents = 5, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), .ops = &clk_rcg2_shared_ops, }, }; @@ -324,7 +309,7 @@ static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_vsync_clk_src", .parent_data = disp_cc_parent_data_0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), .ops = &clk_rcg2_shared_ops, }, }; From patchwork Fri Jan 24 22:42:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 190545 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 58806C35242 for ; Fri, 24 Jan 2020 22:43:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2D34B2071E for ; Fri, 24 Jan 2020 22:43:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="jShQ2pX8" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387459AbgAXWno (ORCPT ); Fri, 24 Jan 2020 17:43:44 -0500 Received: from mail-pg1-f195.google.com ([209.85.215.195]:33704 "EHLO mail-pg1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387445AbgAXWnX (ORCPT ); Fri, 24 Jan 2020 17:43:23 -0500 Received: by mail-pg1-f195.google.com with SMTP id 6so1864392pgk.0 for ; Fri, 24 Jan 2020 14:43:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9BRqMxL/+QF9fXGxsodaUnU1nURwqkQVRb7Veb8jqnw=; b=jShQ2pX8IQIHGNrvrIOhAsqUK/C01VqaM9/g6/e7k6X2Xc4duWVu1GLO4DYADKLj8h DB1G4XhIeSlzDcjW5h0qV2Ri0rmkCIl/+sDXQ/FYpddk2u405IOAnDMRnaomXKuXhIYv rlfKquY9Gm+95wPB7AhitjDpdpTbpS0Fl/u1A= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9BRqMxL/+QF9fXGxsodaUnU1nURwqkQVRb7Veb8jqnw=; b=tjjwagdwdP3o9pDcVFTpUHF9eLe4hjhkU7rYYCbWVqYQJ/fsSeOIvm0xtQGKLoPDvQ YIbkYlmGx2MOUm2u5L+oOIV5olTYCKHfhKkdW3if++2R8lrHXi914zxBVH7Hg2OQ9eCb Ng1aU4HGQ2XdVrILiGWnwufuRnqRiJrRhQq0yx4hF6N9gn/LGg9f7h/OtarjqgXHS+01 b13OpkwYNU6xDW5+ibTZnXrjujclKxecX4lERIPLR77qXao86Ah2kSUssotBzG9uVsZw AiH711pSCEWyGvvWx07V71D1VnSZOMVx5FanQeHjsC3EEYF6Sa/Ud8OIjIfrUjMvVeH8 vlsA== X-Gm-Message-State: APjAAAWl9zOiZzN4lSUL8IAPA9S2/Kc2z6bME7/Vin0W1r9I9RDpR/47 6daNIc+5OqOmPfXkFqqkpSlZqg== X-Google-Smtp-Source: APXvYqwyIr9Hzf7MUy0r0DgFSN19tETtctZT8PEgdV9N562GI+cGiutgSkgp4ilXhVm9KOMG0sXfvw== X-Received: by 2002:aa7:928b:: with SMTP id j11mr5412125pfa.176.1579905802569; Fri, 24 Jan 2020 14:43:22 -0800 (PST) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id o2sm7690948pjo.26.2020.01.24.14.43.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jan 2020 14:43:21 -0800 (PST) From: Douglas Anderson To: Rob Herring , Andy Gross , Bjorn Andersson , Stephen Boyd Cc: Jeffrey Hugo , Taniya Das , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, harigovi@codeaurora.org, mka@chromium.org, kalyan_t@codeaurora.org, Mark Rutland , linux-clk@vger.kernel.org, hoegsberg@chromium.org, Douglas Anderson , linux-kernel@vger.kernel.org, Rob Herring Subject: [PATCH v2 06/10] arm64: dts: qcom: sdm845: Add the missing clocks on the gpucc Date: Fri, 24 Jan 2020 14:42:21 -0800 Message-Id: <20200124144154.v2.6.If8596faf02408cef4bb9f52296b911eb9ba49287@changeid> X-Mailer: git-send-email 2.25.0.341.g760bfbb309-goog In-Reply-To: <20200124224225.22547-1-dianders@chromium.org> References: <20200124224225.22547-1-dianders@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org We're transitioning over to requiring the Qualcomm GPU Clock Controller to specify all the input clocks. Let's add them for sdm845. NOTE: Until the Linux driver for sdm845's gpucc is updated, these clocks will not actually be used in Linux. It will continue to use global clock names to match things up. Of course, Linux didn't use the old "xo" clock anyway. Signed-off-by: Douglas Anderson --- Changes in v2: - Patch ("arm64: dts: qcom: sdm845: Add...gpucc") new for v2. arch/arm64/boot/dts/qcom/sdm845.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 01354533a61b..e624c91dbd6d 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1903,8 +1903,10 @@ gpucc: clock-controller@5090000 { #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + clock-names = "xo", "gpll0", "gpll0_div"; }; stm@6002000 { From patchwork Fri Jan 24 22:42:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 190546 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AFD4FC35244 for ; Fri, 24 Jan 2020 22:43:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 843E72075D for ; Fri, 24 Jan 2020 22:43:39 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="nJUnCZVZ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387488AbgAXWnj (ORCPT ); Fri, 24 Jan 2020 17:43:39 -0500 Received: from mail-pf1-f193.google.com ([209.85.210.193]:44980 "EHLO mail-pf1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387480AbgAXWn0 (ORCPT ); Fri, 24 Jan 2020 17:43:26 -0500 Received: by mail-pf1-f193.google.com with SMTP id 62so1783067pfu.11 for ; Fri, 24 Jan 2020 14:43:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Bui28Vv12xUmXWYpC+BbDFYgTGPFUNN9TS7e8X83ptU=; b=nJUnCZVZFNjMZvgzvmEPCuW8bMgT93sV0s2dZgIYVCytFK0KhhjowkK2AosMIsSyay KmsdEYHy/oKz+S9r2Kkijver4P7gSJN8tLFftGYIKJ/WG2/GJaPtQiiz5n4FA8uhSKE1 yjW6QAW2ZhSfO7AVaFhdvXiXxzrTqDyFmvByI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Bui28Vv12xUmXWYpC+BbDFYgTGPFUNN9TS7e8X83ptU=; b=nnmuYIu81HUIhPAfUfHxklQ+t+YHuiiRKCtYVcyOsismfdGkZdgARmK85MiJvDfELW Kkiu8kiatf4sI4wNjjsUe7izBLkArPQZjBaGzFLO1f58Zt1CyDlxs2BkWS9LZ3dLskAt RVqqyZXmAgsO0IPA7xA4BVptxd+BYp5RnJXUQx2si6WiY3JwXKvDvC0tO4iF8/YA8ZQp CQkjZDQ0XFxa1wcalVjTNyndMMJhKwAyO9lAJXkNfOEaq92c8iha6suXjMwi09q0+6dQ 0UhApgzPxK2Xny62+ZlhLuHvQ4Egl0WJVz4sKmiX+xCqria7lCBOgqylCyWRAceNbsdR X04Q== X-Gm-Message-State: APjAAAXQiDXBPTFibxb46+zph506J67BpQvVysAvCranLIIpNoeIn3nr uzgYsCDFuHwIWpd/470zn5LC2A== X-Google-Smtp-Source: APXvYqzS9tPcZFwCykAq9Smp2Jxt5RR3eG4xljjcnI1eH/vNH2TY407AdxHLUd4cuuKsTLeq6urYLw== X-Received: by 2002:a62:ddd0:: with SMTP id w199mr5272391pff.1.1579905805722; Fri, 24 Jan 2020 14:43:25 -0800 (PST) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id o2sm7690948pjo.26.2020.01.24.14.43.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jan 2020 14:43:25 -0800 (PST) From: Douglas Anderson To: Rob Herring , Andy Gross , Bjorn Andersson , Stephen Boyd Cc: Jeffrey Hugo , Taniya Das , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, harigovi@codeaurora.org, mka@chromium.org, kalyan_t@codeaurora.org, Mark Rutland , linux-clk@vger.kernel.org, hoegsberg@chromium.org, Douglas Anderson , linux-kernel@vger.kernel.org, Rob Herring Subject: [PATCH v2 09/10] arm64: dts: qcom: sdm845: Add the missing clock on the videocc Date: Fri, 24 Jan 2020 14:42:24 -0800 Message-Id: <20200124144154.v2.9.Id0599319487f075808baba7cba02c4c3c486dc80@changeid> X-Mailer: git-send-email 2.25.0.341.g760bfbb309-goog In-Reply-To: <20200124224225.22547-1-dianders@chromium.org> References: <20200124224225.22547-1-dianders@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org We're transitioning over to requiring the Qualcomm Video Clock Controller to specify all the input clocks. Let's add the one input clock for the videocc for sdm845. NOTE: Until the Linux driver for sdm845's video is updated, this clock will not actually be used in Linux. It will continue to use global clock names to match things up. Signed-off-by: Douglas Anderson --- Changes in v2: - Patch ("arm64: dts: qcom: sdm845: Add...videocc") new for v2. arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index e624c91dbd6d..8c41e25bd4a8 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2605,6 +2605,8 @@ video-core1 { videocc: clock-controller@ab00000 { compatible = "qcom,sdm845-videocc"; reg = <0 0x0ab00000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; #clock-cells = <1>; #power-domain-cells = <1>; #reset-cells = <1>; From patchwork Fri Jan 24 22:42:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 190547 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E627C35243 for ; Fri, 24 Jan 2020 22:43:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 248432077C for ; Fri, 24 Jan 2020 22:43:34 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="jgjD9Xxy" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387516AbgAXWnc (ORCPT ); Fri, 24 Jan 2020 17:43:32 -0500 Received: from mail-pf1-f195.google.com ([209.85.210.195]:38966 "EHLO mail-pf1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387491AbgAXWn1 (ORCPT ); Fri, 24 Jan 2020 17:43:27 -0500 Received: by mail-pf1-f195.google.com with SMTP id q10so1799083pfs.6 for ; Fri, 24 Jan 2020 14:43:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=W9Q9a9KTrafykk7sSvwstO8MsMaSjnD9xam7szWjZDw=; b=jgjD9Xxy4nlsaa7hkNYnuT4CcmzwgvwlFgpRuwAPR3fdSGa7W9GTwmxt/bvF513wuw Z1C0VQpRrsrKWTSMCQhlr/vinxMWl+ODRosOtXxAcvpaj4/Pt2tvxVpsi1JI8pLt4WjW eOgUHMcY/25hhzXZcsr7VEYgR7Z/pVuxz1tis= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=W9Q9a9KTrafykk7sSvwstO8MsMaSjnD9xam7szWjZDw=; b=LzorTe7sOv7Ns64O/sw1OGlT9IeyzK7aSN4MQYQqtTxTYJPiDtMHSjime4PhVJAJn7 0SyMyebdMByAlJnqGJ1xur1PEaNVpMAZd89a8Ye7SThhuqH9cFWfGhNq2Ibd8eJsu0Ey ImJ11WkCVPtdatiR4Ct66VFDuiUWez4Qb3PqgYDgoq7T5BoisimmxLVaAiWV/jRgQmI1 TbEO3tsMDZjOkjlyJF8+8wg+6bGp+b45AIyKve//N5TqzW5LaX1CoJnQvFk9fHIwviSv DaMdzMzGiGwysF3gxOcCGVxxpbmqs6TwFbkhHd5cVVZaZP0rpdob0rXeL8dgQV/ol0Nk shEQ== X-Gm-Message-State: APjAAAUnHDl6s2DtuQ+yekoHu4ZhOJb/7LEqRiIBObdKKeRWnisB9jvq iteq5W9XVGfYjKxmwm/z/HvcKQ== X-Google-Smtp-Source: APXvYqyvlxXWuURQFVjahxnKg8HiiJD1ty6z3PYW5nbOmdrvu0Ae1oXPHdhdKlHv1P1ziyQGUdj1Vg== X-Received: by 2002:aa7:8006:: with SMTP id j6mr5297976pfi.185.1579905806866; Fri, 24 Jan 2020 14:43:26 -0800 (PST) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id o2sm7690948pjo.26.2020.01.24.14.43.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jan 2020 14:43:26 -0800 (PST) From: Douglas Anderson To: Rob Herring , Andy Gross , Bjorn Andersson , Stephen Boyd Cc: Jeffrey Hugo , Taniya Das , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, harigovi@codeaurora.org, mka@chromium.org, kalyan_t@codeaurora.org, Mark Rutland , linux-clk@vger.kernel.org, hoegsberg@chromium.org, Douglas Anderson , linux-kernel@vger.kernel.org, Rob Herring Subject: [PATCH v2 10/10] arm64: dts: sc7180: Add clock controller nodes Date: Fri, 24 Jan 2020 14:42:25 -0800 Message-Id: <20200124144154.v2.10.I1a4b93fb005791e29a9dcf288fc8bd459a555a59@changeid> X-Mailer: git-send-email 2.25.0.341.g760bfbb309-goog In-Reply-To: <20200124224225.22547-1-dianders@chromium.org> References: <20200124224225.22547-1-dianders@chromium.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Taniya Das Add the display, video & graphics clock controller nodes supported on SC7180. NOTE: the dispcc needs input clocks from various PHYs that aren't in the device tree yet. For now we'll leave these stubbed out with <0>, which is apparently the magic way to do this. These clocks aren't really "optional" and this stubbing out method is apparently the best way to handle it. Signed-off-by: Taniya Das Signed-off-by: Douglas Anderson --- Changes in v2: - Added includes - Changed various parent names to match bindings / driver arch/arm64/boot/dts/qcom/sc7180.dtsi | 41 ++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 8011c5fe2a31..ee3b4bade66b 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -5,7 +5,9 @@ * Copyright (c) 2019, The Linux Foundation. All rights reserved. */ +#include #include +#include #include #include #include @@ -1039,6 +1041,18 @@ pinmux { }; }; + gpucc: clock-controller@5090000 { + compatible = "qcom,sc7180-gpucc"; + reg = <0 0x05090000 0 0x9000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + clock-names = "xo", "gpll0", "gpll0_div"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + qspi: spi@88dc000 { compatible = "qcom,qspi-v1"; reg = <0 0x088dc000 0 0x600>; @@ -1151,6 +1165,33 @@ usb_1_dwc3: dwc3@a600000 { }; }; + videocc: clock-controller@ab00000 { + compatible = "qcom,sc7180-videocc"; + reg = <0 0x0ab00000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,sc7180-dispcc"; + reg = <0 0x0af00000 0 0x200000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_DISP_GPLL0_CLK_SRC>, + <0>, + <0>, + <0>, + <0>; + clock-names = "xo", "gpll0", + "dsi_phy_pll_byte", "dsi_phy_pll_pixel", + "dp_phy_pll_link", "dp_phy_pll_vco_div"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sc7180-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>;