From patchwork Fri Jun 19 16:18:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Murphy X-Patchwork-Id: 191247 Delivered-To: patch@linaro.org Received: by 2002:a92:cf06:0:0:0:0:0 with SMTP id c6csp674184ilo; Fri, 19 Jun 2020 09:18:38 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwOrjR995LcbPeImll4OqwXpOLh/7JMOcHJnSUKS3pouNciJte6W74lOE+mPxG2Yu+A66R6 X-Received: by 2002:a17:906:694c:: with SMTP id c12mr4134553ejs.495.1592583518441; Fri, 19 Jun 2020 09:18:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1592583518; cv=none; d=google.com; s=arc-20160816; b=AHBfkp8aH9UZ5EPkk/nsTcbfu7FCEsKXuvJGh29RBqezqEEnkicWyC8eZ1h0PePpGt +UTxglbXaRNIG4y/iqw71+TmUyulE0pm6398fTDLW9vAOyf2DS1aZkk6eTGT7r8WrGpj JruYqLc1pndGwwgEFOrr8DWezOq87visVW541Kh6RVbbTIVXsOWd4yja42y8T12RsAYJ C+5i0BbUCuvhOS55NyvRnqLyXkgT5eqXyhm72sQ30ArHyl/UMYmcMette250LUyucrqi M/ljXmghU4OE6UJqUu7UcEZ94V/3sbVcY7jVAfftzBvNu67DuxzynPQGSlzmTq9qOyRH eXew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=6oOEWw/+n4aBbiUGAliVz63pMx5FvDg5gqLlI1ORtvE=; b=dwBQzXgCxK3sM0r2ZXFUzKd5PSx+lsmxVCAaomLr5D2uRld6xBM3oP60WpT0RWSpah s5ZvMCjc0dl0EkhJJwB9Mf4HfY1Y9ADy9QSnBdA5GEqAf1OT7+RAnPcZXDVPAknmmIZ0 1NaOSBdxCjraMNJZK0W89SBr2rDy0dGAxTf0EBcSjqZNtJs4HEOvaWO4VdRnB5OtpIdQ 33gnbd6Uih9XMGkTpNlw7DGGWwbwV7czYkNySJnc3SEUKO3OfcvhA7knRtfx4sra6aKb obdBEDRvA95GUVfrrNQl84NC/q16CZ5qlHa3vnczoZpNn6VP7omOWwdRF3DcfWXqDu3o 4HOA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=qieQzCy3; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id u2si4387680edx.353.2020.06.19.09.18.38; Fri, 19 Jun 2020 09:18:38 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=qieQzCy3; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2404661AbgFSQSf (ORCPT + 6 others); Fri, 19 Jun 2020 12:18:35 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:51114 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2391254AbgFSQSd (ORCPT ); Fri, 19 Jun 2020 12:18:33 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 05JGIQmG112309; Fri, 19 Jun 2020 11:18:26 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1592583506; bh=6oOEWw/+n4aBbiUGAliVz63pMx5FvDg5gqLlI1ORtvE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=qieQzCy3rt5CqeXUL3xDJjIgH9ceFTztXS9cofzV4nou3CoHbt1nzTO2phPILxkLT KySlGIJH7oJOP1OfnWbVT4MXqia2+6eCE5tB0LqZsEctZ118/hM/j51MmcxDrw06Pk R5VGnyfQMMGejKb/XlVH22S1ZulS77Yud5QJMPb8= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id 05JGIQg9046505; Fri, 19 Jun 2020 11:18:26 -0500 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Fri, 19 Jun 2020 11:18:25 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Fri, 19 Jun 2020 11:18:25 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 05JGIPci034807; Fri, 19 Jun 2020 11:18:25 -0500 From: Dan Murphy To: , , , , CC: , , , Dan Murphy Subject: [PATCH net-next v9 2/5] net: phy: Add a helper to return the index for of the internal delay Date: Fri, 19 Jun 2020 11:18:10 -0500 Message-ID: <20200619161813.2716-3-dmurphy@ti.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200619161813.2716-1-dmurphy@ti.com> References: <20200619161813.2716-1-dmurphy@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a helper function that will return the index in the array for the passed in internal delay value. The helper requires the array, size and delay value. The helper will then return the index for the exact match or return the index for the index to the closest smaller value. Signed-off-by: Dan Murphy --- drivers/net/phy/phy_device.c | 100 +++++++++++++++++++++++++++++++++++ include/linux/phy.h | 4 ++ 2 files changed, 104 insertions(+) -- 2.26.2 diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c index 04946de74fa0..0bb08bc0370c 100644 --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c @@ -31,6 +31,7 @@ #include #include #include +#include MODULE_DESCRIPTION("PHY library"); MODULE_AUTHOR("Andy Fleming"); @@ -2657,6 +2658,105 @@ void phy_get_pause(struct phy_device *phydev, bool *tx_pause, bool *rx_pause) } EXPORT_SYMBOL(phy_get_pause); +#if IS_ENABLED(CONFIG_OF_MDIO) +static int phy_get_int_delay_property(struct device *dev, const char *name) +{ + s32 int_delay; + int ret; + + ret = device_property_read_u32(dev, name, &int_delay); + if (ret) + return ret; + + return int_delay; +} +#else +static inline int phy_get_int_delay_property(struct device *dev, + const char *name) +{ + return -EINVAL; +} +#endif + +/** + * phy_get_delay_index - returns the index of the internal delay + * @phydev: phy_device struct + * @dev: pointer to the devices device struct + * @delay_values: array of delays the PHY supports + * @size: the size of the delay array + * @is_rx: boolean to indicate to get the rx internal delay + * + * Returns the index within the array of internal delay passed in. + * If the device property is not present then the interface type is checked + * if the interface defines use of internal delay then a 1 is returned otherwise + * a 0 is returned. + * The array must be in ascending order. If PHY does not have an ascending order + * array then size = 0 and the value of the delay property is returned. + * Return -EINVAL if the delay is invalid or cannot be found. + */ +s32 phy_get_internal_delay(struct phy_device *phydev, struct device *dev, + const int *delay_values, int size, bool is_rx) +{ + int i; + s32 delay; + + if (is_rx) { + delay = phy_get_int_delay_property(dev, "rx-internal-delay-ps"); + if (delay < 0 && size == 0) { + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || + phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) + return 1; + else + return 0; + } + + } else { + delay = phy_get_int_delay_property(dev, "tx-internal-delay-ps"); + if (delay < 0 && size == 0) { + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || + phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) + return 1; + else + return 0; + } + } + + if (delay < 0) + return delay; + + if (delay && size == 0) + return delay; + + if (delay < delay_values[0] || delay > delay_values[size - 1]) { + phydev_err(phydev, "Delay %d is out of range\n", delay); + return -EINVAL; + } + + if (delay == delay_values[0]) + return 0; + + for (i = 1; i < size; i++) { + if (delay == delay_values[i]) + return i; + + /* Find an approximate index by looking up the table */ + if (delay > delay_values[i - 1] && + delay < delay_values[i]) { + if (delay - delay_values[i - 1] < + delay_values[i] - delay) + return i - 1; + else + return i; + } + } + + phydev_err(phydev, "error finding internal delay index for %d\n", + delay); + + return -EINVAL; +} +EXPORT_SYMBOL(phy_get_internal_delay); + static bool phy_drv_supports_irq(struct phy_driver *phydrv) { return phydrv->config_intr && phydrv->ack_interrupt; diff --git a/include/linux/phy.h b/include/linux/phy.h index 8c05d0fb5c00..917bfd422e06 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -1430,6 +1430,10 @@ void phy_set_asym_pause(struct phy_device *phydev, bool rx, bool tx); bool phy_validate_pause(struct phy_device *phydev, struct ethtool_pauseparam *pp); void phy_get_pause(struct phy_device *phydev, bool *tx_pause, bool *rx_pause); + +s32 phy_get_internal_delay(struct phy_device *phydev, struct device *dev, + const int *delay_values, int size, bool is_rx); + void phy_resolve_pause(unsigned long *local_adv, unsigned long *partner_adv, bool *tx_pause, bool *rx_pause); From patchwork Fri Jun 19 16:18:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Murphy X-Patchwork-Id: 191250 Delivered-To: patch@linaro.org Received: by 2002:a92:cf06:0:0:0:0:0 with SMTP id c6csp674585ilo; Fri, 19 Jun 2020 09:19:09 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyMH9q55nCfI2wiaN6rGaZhBZohNnfSW0+ab9vDWAfJ8j4Kx605r5zLrTG96cYYxMAMaZ4N X-Received: by 2002:a17:906:68ca:: with SMTP id y10mr4282050ejr.322.1592583548997; Fri, 19 Jun 2020 09:19:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1592583548; cv=none; d=google.com; s=arc-20160816; b=pcw50Ewas7Q0JwKQaHyO3CDpv9GejCj/o7BOZAc5QrT+loLntwiV7rtaSuubxDehvX n57d0KB4uYcXKfad5Aokf+RdXy4LlCyXv7VMV8VnQuPCSYFcacuhvkeiPoM9s+MJWWoL JV5IwtMbPuoyyoqVpiJjpPgSqhyRbjI/K0g8bUMwtvie6DcMNoTOBrMh3NoEUmbhkuVN eZhdEGKo7Re8zs7bbvQDfwXfM/9gjWHGgaP8mVifsr5tjmht6Kc72J2e5bXN3XNRDAk7 c4qRxW4cG+taLzOvRrNwuAkD3rPapTrO8WPFv7ZjX5tWBqo09tR0tZmbpbVZMcL1ytwg 4LRw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=eShyx82GLaQ3xsgsj9ve463coidBb5dHGAfrzfcrN0w=; b=YCyVjlUNBceu33ntSWI51nfo/CApqkA0eFeTLbT8QgRgrqcapRt0NJryJDzFyaMAXm kuPNPpNiVDzAeqZM0DPSc/ziOu0RE0OpMNAvHF8vWids6gJOIGxk4IvWZHvhEvD3IwAI D7Ja+PGB+lbZkh48XVchAhLWSQVkElxuINxRC2ohGEmV0jNZoPaevbm37nq3TQ8ejNPy 3Wss+suNDAQefG/41e7lUNd9adAff7Ww7/lvevjoOhV4SlS/EGqW0csumKrLnNKRGDwk Fggj214y/Wg5ADntoHxJ6Ek7iCvkTz0cZnUvY0/dbhpt4zf42kbuFeIJxDEEZHZSUvz6 aAzg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=VgLFVUOA; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id e25si4072629ejc.245.2020.06.19.09.19.08; Fri, 19 Jun 2020 09:19:08 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=VgLFVUOA; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2391008AbgFSQTG (ORCPT + 6 others); Fri, 19 Jun 2020 12:19:06 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:49464 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2405581AbgFSQSg (ORCPT ); Fri, 19 Jun 2020 12:18:36 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 05JGIVeh008207; Fri, 19 Jun 2020 11:18:31 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1592583511; bh=eShyx82GLaQ3xsgsj9ve463coidBb5dHGAfrzfcrN0w=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=VgLFVUOA7txOkd46W98qaiC5poAp05crEOnfj6Q+OqWZEKb7IN4fRnXFDdHzPazeg RyzlcineoQOZ/6fO3rh6tsCz9MMPOnkWIQcUGfJoI5RdEZBpJRndUdd8bc88JCUzgX TKLp1s0rGqV2j2BRV/2Mas0/QVM+y5AI7ganKCuI= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 05JGIVpw122286 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 19 Jun 2020 11:18:31 -0500 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Fri, 19 Jun 2020 11:18:31 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Fri, 19 Jun 2020 11:18:30 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 05JGIUwc026762; Fri, 19 Jun 2020 11:18:31 -0500 From: Dan Murphy To: , , , , CC: , , , Dan Murphy Subject: [PATCH net-next v9 3/5] dt-bindings: net: Add RGMII internal delay for DP83869 Date: Fri, 19 Jun 2020 11:18:11 -0500 Message-ID: <20200619161813.2716-4-dmurphy@ti.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200619161813.2716-1-dmurphy@ti.com> References: <20200619161813.2716-1-dmurphy@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the internal delay values into the header and update the binding with the internal delay properties. Signed-off-by: Dan Murphy --- .../devicetree/bindings/net/ti,dp83869.yaml | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) -- 2.26.2 diff --git a/Documentation/devicetree/bindings/net/ti,dp83869.yaml b/Documentation/devicetree/bindings/net/ti,dp83869.yaml index 5b69ef03bbf7..71e90a3e4652 100644 --- a/Documentation/devicetree/bindings/net/ti,dp83869.yaml +++ b/Documentation/devicetree/bindings/net/ti,dp83869.yaml @@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#" title: TI DP83869 ethernet PHY allOf: - - $ref: "ethernet-controller.yaml#" + - $ref: "ethernet-phy.yaml#" maintainers: - Dan Murphy @@ -64,6 +64,18 @@ properties: Operational mode for the PHY. If this is not set then the operational mode is set by the straps. see dt-bindings/net/ti-dp83869.h for values + rx-internal-delay-ps: + description: Delay is in pico seconds + enum: [ 250, 500, 750, 1000, 1250, 1500, 1750, 2000, 2250, 2500, 2750, 3000, + 3250, 3500, 3750, 4000 ] + default: 2000 + + tx-internal-delay-ps: + description: Delay is in pico seconds + enum: [ 250, 500, 750, 1000, 1250, 1500, 1750, 2000, 2250, 2500, 2750, 3000, + 3250, 3500, 3750, 4000 ] + default: 2000 + required: - reg @@ -80,5 +92,7 @@ examples: ti,op-mode = ; ti,max-output-impedance = "true"; ti,clk-output-sel = ; + rx-internal-delay-ps = <2000>; + tx-internal-delay-ps = <2000>; }; }; From patchwork Fri Jun 19 16:18:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Murphy X-Patchwork-Id: 191248 Delivered-To: patch@linaro.org Received: by 2002:a92:cf06:0:0:0:0:0 with SMTP id c6csp674217ilo; Fri, 19 Jun 2020 09:18:41 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyQhQny58WwWDSzwz9E27w1HZ/dzEIf0TYYh7+Rp00uez1WPJN6V9WtZeBHLERDJP/LGzeN X-Received: by 2002:a17:906:5250:: with SMTP id y16mr4387650ejm.3.1592583521781; Fri, 19 Jun 2020 09:18:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1592583521; cv=none; d=google.com; s=arc-20160816; b=MHbT/CQ5yDn/wo/D16Jy/nuWjZ6Blo9mHhjIyS2NWn4+TMFk+yhywB1SSz4XyrK0I7 jlysmPVcMOUFAHu8NNhTGigLLWdomcJ4XErnXXsYonvjFjzAn+v2NuomX4r/n6psDSX8 KATO768bpPoWsO3pz5AytC+G24IrLs2e6TKZ8T4fVr4ocRHlEFZ9qMWE7RP1F/ljJmo7 TNNdwIQng2Jp+IlU2WzD8+WeapSIA+3kiOoBN8Am12RULHmyOi8PdPFUQydPEt0UNp8b N0eOo9kJ8Tuf4BHoV/WDx23gAwqqa2yI4vaFSj4SBJtQAZp2n5JtCitG4IHrlqxHmUem VlZg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=iLdvMCbgjuB3IvjEffc3VbBTcvc2wltvJLix5r4FFus=; b=wE9HmwXToOIRAtUa4g37zP0cl7XjSBXdV3bB2hRxIyoBMZzut0iFuaRvoJ7zLHZZda hyR7YmahCT/mtp0njDSQfm3cGB7VfXgAL6OUijIUGKng3lCkwn/M8eBMOVAwKAaZX4Vl ft8ByF70JDF+06P2dHEcDVD/LcWrgGvmqsz4fbAb9AxVAJhmpVC/mEjgpN6ejjIShVlA 2FlbB7FqUcLmCgJQb0uaARDZYoAOCbqT3mO8u4lcG/cW+AOQ368CeA43yQUqGLiq7WF6 UWzpVECaBPLy3EqsPAKCoXzOmKGSUBHZNTKMiQlbCTaQKESzmWkOo3IRb/t9pGn20+I/ G1PQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=VS1Razg+; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Dan Murphy --- drivers/net/phy/dp83869.c | 53 ++++++++++++++++++++++++++++++++++++--- 1 file changed, 50 insertions(+), 3 deletions(-) -- 2.26.2 diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c index 53ed3abc26c9..58103152c601 100644 --- a/drivers/net/phy/dp83869.c +++ b/drivers/net/phy/dp83869.c @@ -64,6 +64,10 @@ #define DP83869_RGMII_TX_CLK_DELAY_EN BIT(1) #define DP83869_RGMII_RX_CLK_DELAY_EN BIT(0) +/* RGMIIDCTL */ +#define DP83869_RGMII_CLK_DELAY_SHIFT 4 +#define DP83869_CLK_DELAY_DEF 7 + /* STRAP_STS1 bits */ #define DP83869_STRAP_OP_MODE_MASK GENMASK(2, 0) #define DP83869_STRAP_STS1_RESERVED BIT(11) @@ -78,9 +82,6 @@ #define DP83869_PHYCR_FIFO_DEPTH_MASK GENMASK(15, 12) #define DP83869_PHYCR_RESERVED_MASK BIT(11) -/* RGMIIDCTL bits */ -#define DP83869_RGMII_TX_CLK_DELAY_SHIFT 4 - /* IO_MUX_CFG bits */ #define DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL 0x1f @@ -108,6 +109,8 @@ enum { struct dp83869_private { int tx_fifo_depth; int rx_fifo_depth; + s32 rx_int_delay; + s32 tx_int_delay; int io_impedance; int port_mirroring; bool rxctrl_strap_quirk; @@ -177,11 +180,16 @@ static int dp83869_set_strapped_mode(struct phy_device *phydev) } #if IS_ENABLED(CONFIG_OF_MDIO) +static const int dp83869_internal_delay[] = {250, 500, 750, 1000, 1250, 1500, + 1750, 2000, 2250, 2500, 2750, 3000, + 3250, 3500, 3750, 4000}; + static int dp83869_of_init(struct phy_device *phydev) { struct dp83869_private *dp83869 = phydev->priv; struct device *dev = &phydev->mdio.dev; struct device_node *of_node = dev->of_node; + int delay_size = ARRAY_SIZE(dp83869_internal_delay); int ret; if (!of_node) @@ -235,6 +243,20 @@ static int dp83869_of_init(struct phy_device *phydev) &dp83869->tx_fifo_depth)) dp83869->tx_fifo_depth = DP83869_PHYCR_FIFO_DEPTH_4_B_NIB; + dp83869->rx_int_delay = phy_get_internal_delay(phydev, dev, + &dp83869_internal_delay[0], + delay_size, true); + if (dp83869->rx_int_delay < 0) + dp83869->rx_int_delay = + dp83869_internal_delay[DP83869_CLK_DELAY_DEF]; + + dp83869->tx_int_delay = phy_get_internal_delay(phydev, dev, + &dp83869_internal_delay[0], + delay_size, false); + if (dp83869->tx_int_delay < 0) + dp83869->tx_int_delay = + dp83869_internal_delay[DP83869_CLK_DELAY_DEF]; + return ret; } #else @@ -397,6 +419,31 @@ static int dp83869_config_init(struct phy_device *phydev) dp83869->clk_output_sel << DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT); + if (phy_interface_is_rgmii(phydev)) { + ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIIDCTL, + dp83869->rx_int_delay | + dp83869->tx_int_delay << DP83869_RGMII_CLK_DELAY_SHIFT); + if (ret) + return ret; + + val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL); + val &= ~(DP83869_RGMII_TX_CLK_DELAY_EN | + DP83869_RGMII_RX_CLK_DELAY_EN); + + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) + val |= (DP83869_RGMII_TX_CLK_DELAY_EN | + DP83869_RGMII_RX_CLK_DELAY_EN); + + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) + val |= DP83869_RGMII_TX_CLK_DELAY_EN; + + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) + val |= DP83869_RGMII_RX_CLK_DELAY_EN; + + ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL, + val); 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[23.128.96.18]) by mx.google.com with ESMTP id u2si4387680edx.353.2020.06.19.09.18.44; Fri, 19 Jun 2020 09:18:44 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=AliZagCg; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2394308AbgFSQSm (ORCPT + 6 others); Fri, 19 Jun 2020 12:18:42 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:49480 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2405618AbgFSQSl (ORCPT ); Fri, 19 Jun 2020 12:18:41 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 05JGIaLR008227; Fri, 19 Jun 2020 11:18:36 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1592583516; bh=eStPcoULgEZG94PVJtakxpfbyK9RyeLhnZbJP2L7ZFo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=AliZagCgf0d80XMVZYdSlLllnANBUYrsDVKXnYrCD4EeftsX9cWCkvpApN0XA7SBJ qtwVzRq+/vt8Bv2cuGu1edyrfBg1NWMuAZJbNOA1prgdoK1HEkhL+4nSn0c0DA4KPm 67ighbOn55aEkFgi+h/OlNhZtetTFKzPBex/Hx4U= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id 05JGIaOc046633; Fri, 19 Jun 2020 11:18:36 -0500 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Fri, 19 Jun 2020 11:18:36 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Fri, 19 Jun 2020 11:18:36 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 05JGIae7091288; Fri, 19 Jun 2020 11:18:36 -0500 From: Dan Murphy To: , , , , CC: , , , Dan Murphy Subject: [PATCH net-next v9 5/5] net: phy: DP83822: Add setting the fixed internal delay Date: Fri, 19 Jun 2020 11:18:13 -0500 Message-ID: <20200619161813.2716-6-dmurphy@ti.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200619161813.2716-1-dmurphy@ti.com> References: <20200619161813.2716-1-dmurphy@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The DP83822 can be configured to use the RGMII interface. There are independent fixed 3.5ns clock shift (aka internal delay) for the TX and RX paths. This allow either one to be set if the MII interface is RGMII and the value is set in the firmware node. Signed-off-by: Dan Murphy --- drivers/net/phy/dp83822.c | 79 ++++++++++++++++++++++++++++++++++----- 1 file changed, 69 insertions(+), 10 deletions(-) -- 2.26.2 diff --git a/drivers/net/phy/dp83822.c b/drivers/net/phy/dp83822.c index 1dd19d0cb269..37643c468e19 100644 --- a/drivers/net/phy/dp83822.c +++ b/drivers/net/phy/dp83822.c @@ -26,7 +26,9 @@ #define MII_DP83822_PHYSCR 0x11 #define MII_DP83822_MISR1 0x12 #define MII_DP83822_MISR2 0x13 +#define MII_DP83822_RCSR 0x17 #define MII_DP83822_RESET_CTRL 0x1f +#define MII_DP83822_GENCFG 0x465 #define DP83822_HW_RESET BIT(15) #define DP83822_SW_RESET BIT(14) @@ -77,6 +79,10 @@ #define DP83822_WOL_INDICATION_SEL BIT(8) #define DP83822_WOL_CLR_INDICATION BIT(11) +/* RSCR bits */ +#define DP83822_RX_CLK_SHIFT BIT(12) +#define DP83822_TX_CLK_SHIFT BIT(11) + static int dp83822_ack_interrupt(struct phy_device *phydev) { int err; @@ -255,7 +261,7 @@ static int dp83822_config_intr(struct phy_device *phydev) return phy_write(phydev, MII_DP83822_PHYSCR, physcr_status); } -static int dp83822_config_init(struct phy_device *phydev) +static int dp8382x_disable_wol(struct phy_device *phydev) { int value = DP83822_WOL_EN | DP83822_WOL_MAGIC_EN | DP83822_WOL_SECURE_ON; @@ -264,6 +270,46 @@ static int dp83822_config_init(struct phy_device *phydev) MII_DP83822_WOL_CFG, value); } +static int dp83822_config_init(struct phy_device *phydev) +{ + struct device *dev = &phydev->mdio.dev; + int rgmii_delay; + s32 rx_int_delay; + s32 tx_int_delay; + int err = 0; + + if (phy_interface_is_rgmii(phydev)) { + rx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0, + true); + + if (rx_int_delay <= 0) + rgmii_delay = 0; + else + rgmii_delay = DP83822_RX_CLK_SHIFT; + + tx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0, + false); + if (tx_int_delay <= 0) + rgmii_delay &= ~DP83822_TX_CLK_SHIFT; + else + rgmii_delay |= DP83822_TX_CLK_SHIFT; + + if (rgmii_delay) { + err = phy_set_bits_mmd(phydev, DP83822_DEVADDR, + MII_DP83822_RCSR, rgmii_delay); + if (err) + return err; + } + } + + return dp8382x_disable_wol(phydev); +} + +static int dp8382x_config_init(struct phy_device *phydev) +{ + return dp8382x_disable_wol(phydev); +} + static int dp83822_phy_reset(struct phy_device *phydev) { int err; @@ -272,9 +318,7 @@ static int dp83822_phy_reset(struct phy_device *phydev) if (err < 0) return err; - dp83822_config_init(phydev); - - return 0; + return phydev->drv->config_init(phydev); } static int dp83822_suspend(struct phy_device *phydev) @@ -318,14 +362,29 @@ static int dp83822_resume(struct phy_device *phydev) .resume = dp83822_resume, \ } +#define DP8382X_PHY_DRIVER(_id, _name) \ + { \ + PHY_ID_MATCH_MODEL(_id), \ + .name = (_name), \ + /* PHY_BASIC_FEATURES */ \ + .soft_reset = dp83822_phy_reset, \ + .config_init = dp8382x_config_init, \ + .get_wol = dp83822_get_wol, \ + .set_wol = dp83822_set_wol, \ + .ack_interrupt = dp83822_ack_interrupt, \ + .config_intr = dp83822_config_intr, \ + .suspend = dp83822_suspend, \ + .resume = dp83822_resume, \ + } + static struct phy_driver dp83822_driver[] = { DP83822_PHY_DRIVER(DP83822_PHY_ID, "TI DP83822"), - DP83822_PHY_DRIVER(DP83825I_PHY_ID, "TI DP83825I"), - DP83822_PHY_DRIVER(DP83826C_PHY_ID, "TI DP83826C"), - DP83822_PHY_DRIVER(DP83826NC_PHY_ID, "TI DP83826NC"), - DP83822_PHY_DRIVER(DP83825S_PHY_ID, "TI DP83825S"), - DP83822_PHY_DRIVER(DP83825CM_PHY_ID, "TI DP83825M"), - DP83822_PHY_DRIVER(DP83825CS_PHY_ID, "TI DP83825CS"), + DP8382X_PHY_DRIVER(DP83825I_PHY_ID, "TI DP83825I"), + DP8382X_PHY_DRIVER(DP83826C_PHY_ID, "TI DP83826C"), + DP8382X_PHY_DRIVER(DP83826NC_PHY_ID, "TI DP83826NC"), + DP8382X_PHY_DRIVER(DP83825S_PHY_ID, "TI DP83825S"), + DP8382X_PHY_DRIVER(DP83825CM_PHY_ID, "TI DP83825M"), + DP8382X_PHY_DRIVER(DP83825CS_PHY_ID, "TI DP83825CS"), }; module_phy_driver(dp83822_driver);