From patchwork Sun Jun 21 19:35:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 191295 Delivered-To: patch@linaro.org Received: by 2002:a92:1f07:0:0:0:0:0 with SMTP id i7csp443105ile; Sun, 21 Jun 2020 12:35:58 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxE3ANlnZybQSk2tRDAO7M0YpB2sE0V39VhMzLSUArCmECpCAttn4zjjPxq2CNeHGg2LcgY X-Received: by 2002:a17:906:5595:: with SMTP id y21mr13117756ejp.61.1592768158072; Sun, 21 Jun 2020 12:35:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1592768158; cv=none; d=google.com; s=arc-20160816; b=LsRM4lY3Q9S+oSkIs6d7QcatCn/ilc4MKnbMaXLEbbH17iMNh/u3fyTNrNeHU+odq5 ywUSKS2dULxAHDu/tt2hAoiaGv/HDDZsVzuptlqQkpaq583nDYL7lDD3ffRlRciroo7r hZPg0cmYyTKPi79sr46j9mubgNTfGboIDMuffzkJUAGr8wtu8Md3o4NKF1uO2iCq18sH DfSCiGG+gwYvl3owPvH9LL6DrQmRayyoHKDOYa9EoBI4TFdqnoFbDAKEZxpYfQtIgIEA Hz3jh4y98lDsvn3sX0LKPm+moLFMhJ7+oDhCpUOUvnQSMDXZeqOBAJe32/iCUsm4zGp0 P0Zg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=bhDR7iz+qpdl87dIvXubN6N0cNZInUDHwBfKjnhBFLY=; b=zh+HOq8oSphcmY8k4GHOg8dKaJAjy0Y0sMzoeAxjpdSEajVBmGhK8xx6UdeGMAkTXt kJjHwlDWr+WYxDTSvT5l7cPKLNUpSbK9ldonyTIQQzu+wQ2VyW9nelfsGCq7qgitmx0x 1iXEeC5gJsHHu0DNxT9QFNtt83GNA7ZinD/hH5XnldNaT/xQy/r8qBcWIwNDxCDDHIJo HC1c5cvM8zTEG6VWgkM3Axl6yieahzH3EXmWrtAFExGiofZmz0VKRfjN59IufOKz4yN6 05EvyfnxTP+MrZJdggjONfY6IIdG2Oxevy3E1KpWLu4lXGuVfNcc6BPWSRvPBpXvojGh w3xw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SOiXwgq6; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id g20si3105175edq.447.2020.06.21.12.35.57; Sun, 21 Jun 2020 12:35:58 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SOiXwgq6; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730311AbgFUTf5 (ORCPT + 6 others); Sun, 21 Jun 2020 15:35:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51890 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730036AbgFUTf4 (ORCPT ); Sun, 21 Jun 2020 15:35:56 -0400 Received: from mail-lf1-x143.google.com (mail-lf1-x143.google.com [IPv6:2a00:1450:4864:20::143]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5CD0CC061794 for ; Sun, 21 Jun 2020 12:35:56 -0700 (PDT) Received: by mail-lf1-x143.google.com with SMTP id t74so8400814lff.2 for ; Sun, 21 Jun 2020 12:35:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bhDR7iz+qpdl87dIvXubN6N0cNZInUDHwBfKjnhBFLY=; b=SOiXwgq6yf5bThJbs3KJRVphtiP73bWB2weIwmkw/kAINeQwFsQEUa1/LkY5uP2NlV /m1zUHCjlmj7D8WbnBFDfLuQRmrXAOmw/JUqHwn1iQCQPnT75QxkODPxz1ZCo+PCmggV M0RY+fKxPS1Y4qWANRBlloxjyU36/owRzQ6c9jKAP+GDPuYWUYww1+IT/+vG1wuuPSZx C3r0hXSAdONYEs7YkElz1Fw1BQk+n3c43n7YSKSEcEEVddFjIjw0Lv7sI9bevwDRhzIU 3lbfprmqTakUNPqsU6TiDgJG+XK11w+W+eeZVdaDKbCEk0eIWMpoJO2V0oCvult6vpPo 3MOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bhDR7iz+qpdl87dIvXubN6N0cNZInUDHwBfKjnhBFLY=; b=K/iccdY+YEV2tvOOIZU+KUKDIcQSwA7zO9tgvAwhRSNU3MB9xBTMOQdPO9n1Of1Dd4 kpl1Z7Owxd47pcghSLabd6x9OjMwiPXhRqM7ETwiA0JmVBWB3HEx0xRdocv5uDvs82g4 riMU1BFSTIaEm07hCAkokjSJgDYJ3//l62/aCHNgZ2d2gH+MyToDbz8lmyYiluFp2lx2 MVh+1AKuM2VzpsQ2RMDTncQo5ejmHrhGqGEphdTocrh06v2pIWLNTW1CE5WMaXVgLnOw CVEsj27VCORgnRs5TRiAZVUAD9FZpOg9mTp5w17671W79ibuMtA9dNC269rcZuhjwT5m DSMQ== X-Gm-Message-State: AOAM533nwMTbUboNXaG2LQHOJBzxJfLqY+h4nT9rBk/vThFi1lNjoeIe t/Vndm3taAHfjoA2VhxmqzeSgQ== X-Received: by 2002:ac2:5e71:: with SMTP id a17mr3303817lfr.150.1592768154827; Sun, 21 Jun 2020 12:35:54 -0700 (PDT) Received: from eriador.lan ([188.162.65.109]) by smtp.gmail.com with ESMTPSA id r13sm2917854lfp.80.2020.06.21.12.35.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Jun 2020 12:35:54 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Zhang Rui , Daniel Lezcano , Amit Kucheria , Jonathan Cameron , Hartmut Knaack , Lars-Peter Clausen , Peter Meerwald-Stadler Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Vinod Koul , linux-iio@vger.kernel.org Subject: [PATCH 1/5] dt-bindings: thermal: qcom: add adc-thermal monitor bindings Date: Sun, 21 Jun 2020 22:35:45 +0300 Message-Id: <20200621193549.2070434-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200621193549.2070434-1-dmitry.baryshkov@linaro.org> References: <20200621193549.2070434-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add bindings for thermal monitor, part of Qualcomm PMIC5 chips. It is a close counterpart of VADC part of those PMICs. Signed-off-by: Dmitry Baryshkov --- .../bindings/thermal/qcom-spmi-adc-tm5.yaml | 143 ++++++++++++++++++ 1 file changed, 143 insertions(+) create mode 100644 Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml -- 2.27.0 diff --git a/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml b/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml new file mode 100644 index 000000000000..16d3f61d692a --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml @@ -0,0 +1,143 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/qcom-spmi-adc-tm5.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm's SPMI PMIC ADC-TM +maintainers: + - Dmitry Baryshkov + +properties: + compatible: + const: qcom,spmi-adc-tm5 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + "#thermal-sensor-cells": + const: 1 + description: + Number of cells required to uniquely identify the thermal sensors. Since + we have multiple sensors this is set to 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + io-channels: + description: + From common IIO binding. Used to pipe PMIC ADC channel to thermal monitor + + io-channel-names: + description: + From common IIO binding. Names each of IIO channels. The name should + be equal to the sensor's subnode name. + + qcom,avg-samples: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Number of samples to be used for measurement. + enum: + - 1 + - 2 + - 4 + - 8 + - 16 + default: 1 + + qcom,decimation: + $ref: /schemas/types.yaml#/definitions/uint32 + description: This parameter is used to decrease ADC sampling rate. + enum: + - 250 + - 420 + - 840 + default: 840 + +patternProperties: + "^([-a-z0-9]*)@[0-9]+$": + type: object + description: + Represent one thermal sensor. + + properties: + reg: + description: Specify the sensor channel. + maxItems: 1 + + qcom,adc-channel: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Corresponding ADC channel ID. + + qcom,ratiometric: + $ref: /schemas/types.yaml#/definitions/flag + description: + Channel calibration type. + If this property is specified VADC will use the VDD reference + (1.875V) and GND for channel calibration. If property is not found, + channel will be calibrated with 0V and 1.25V reference channels, + also known as absolute calibration. + + qcom,hw-settle-time: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Time between AMUX getting configured and the ADC starting conversion. + + qcom,pre-scaling: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: Used for scaling the channel input signal before the signal is fed to VADC. See qcom,spi-vadc specification for the list of possible values. + minItems: 2 + maxItems: 2 + + required: + - reg + - qcom,adc-channel + + additionalProperties: + false + +required: + - compatible + - reg + - interrupts + - "#address-cells" + - "#size-cells" + - "#thermal-sensor-cells" + +additionalProperties: false + +examples: + - | + pm8150b_adc: adc@3100 { + compatible = "qcom,spmi-adc5"; + /* Other propreties are omitted */ + conn-therm@4f { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + }; + pm8150b_adc_tm: adc-tm@3500 { + compatible = "qcom,spmi-adc-tm5"; + reg = <0x3500>; + interrupts = <0x2 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + io-channels = <&pm8150b_adc ADC5_AMUX_THM3_100K_PU>; + io-channel-names = "conn-therm"; + + conn-therm@0 { + reg = <0>; + qcom,adc-channel = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + }; + + +... From patchwork Sun Jun 21 19:35:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 198735 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DB351C433E3 for ; Sun, 21 Jun 2020 19:36:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B88082080C for ; Sun, 21 Jun 2020 19:36:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="b4CYgCFi" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730387AbgFUTgA (ORCPT ); Sun, 21 Jun 2020 15:36:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51900 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730170AbgFUTf7 (ORCPT ); Sun, 21 Jun 2020 15:35:59 -0400 Received: from mail-lf1-x142.google.com (mail-lf1-x142.google.com [IPv6:2a00:1450:4864:20::142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 01AE7C061794 for ; Sun, 21 Jun 2020 12:35:58 -0700 (PDT) Received: by mail-lf1-x142.google.com with SMTP id c11so8379436lfh.8 for ; Sun, 21 Jun 2020 12:35:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5oc+8iupKokx1vIwx2BgSUJUDtArVXE3sPkQPErCBew=; b=b4CYgCFiAXg7oskXiicQUC77JqVVOFahqrL4MZK0ld3d0r86P+SmnYaya89sTWb62v gFbP7sTeFgcLLMdMfSY7h12cR9+ckeiniuy6+ufeqGztIs9Kew4xbRzC6gk6Hs7s5Xpg KQU7xuDA23OSkTmAvTM+qq6HaSnqgdIOuQ9aszZE/ineR3tHeVr5qB6YRPXNhUdorLfF EutpqoGIeNqIccy5qBxonT77hoOUEdkJGDV/inYlFZEZiQynihnbQhhda79UocfZyFlk xz4AXHAVq7ZuvtYwolp9+3vRZ5J05HQG6UDSc4hwm+t19VCyR9HqYTzMTmUhRxcCV5Qj KEVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5oc+8iupKokx1vIwx2BgSUJUDtArVXE3sPkQPErCBew=; b=PBRBzNp4GK4Ld2ktMuZBp4MpMtel+IpjTR9aO2p+5VBfu5SfHih/REJL/sQ++k3M0p gbT1L4oYYFDLfXORO4Yuot1LjwJ5nHx3y3TA8ZlZZoDQKYWfKSSd6Vlza0vTuxm5XqCT yrOateQw8XvXmkYcWmhXN7EV4j9Dgxvveby9JWhQ9PdTvVU681eQPHT29PzbcYLMA16Z YRtxS1KvksoUMsTfh24CgoAOAA5hZL7hjdKVsyPgjGcdyHtQah5L+yVMed7j36xQlrJl /3w9IA5RDRIVEH4a/lBxddxa4dRkteXMkuaZqUvuhQbK38sxgs3m5SmQiydY2qmz1rnP bdfA== X-Gm-Message-State: AOAM5306iFYFwW39ZxKE1DaDhIH2Ncz+2LUWZub4BFb1ArzULSobpWfA NANZJN7hWMavdydFbuBlvo8NIw== X-Google-Smtp-Source: ABdhPJzLm9TRwXrpMuDy8Q6DqcksIMnANVf9Yh3B00QsffrmH97mM3SlbpHT17es10eUfTIgVtBUoQ== X-Received: by 2002:a05:6512:686:: with SMTP id t6mr8018395lfe.154.1592768156464; Sun, 21 Jun 2020 12:35:56 -0700 (PDT) Received: from eriador.lan ([188.162.65.109]) by smtp.gmail.com with ESMTPSA id r13sm2917854lfp.80.2020.06.21.12.35.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Jun 2020 12:35:55 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Zhang Rui , Daniel Lezcano , Amit Kucheria , Jonathan Cameron , Hartmut Knaack , Lars-Peter Clausen , Peter Meerwald-Stadler Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Vinod Koul , linux-iio@vger.kernel.org Subject: [PATCH 2/5] iio: adc: qcom-vadc: move several adc5 functions to common file Date: Sun, 21 Jun 2020 22:35:46 +0300 Message-Id: <20200621193549.2070434-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200621193549.2070434-1-dmitry.baryshkov@linaro.org> References: <20200621193549.2070434-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org ADC-TM5 driver will make use of several functions from ADC5 driver. Move them to qcom-vadc-common driver. Signed-off-by: Dmitry Baryshkov --- drivers/iio/adc/qcom-spmi-adc5.c | 73 +++--------------------------- drivers/iio/adc/qcom-vadc-common.c | 69 +++++++++++++++++++++++++++- drivers/iio/adc/qcom-vadc-common.h | 12 ++++- 3 files changed, 85 insertions(+), 69 deletions(-) diff --git a/drivers/iio/adc/qcom-spmi-adc5.c b/drivers/iio/adc/qcom-spmi-adc5.c index 21fdcde77883..10ca0bf77160 100644 --- a/drivers/iio/adc/qcom-spmi-adc5.c +++ b/drivers/iio/adc/qcom-spmi-adc5.c @@ -143,18 +143,6 @@ struct adc5_chip { const struct adc5_data *data; }; -static const struct vadc_prescale_ratio adc5_prescale_ratios[] = { - {.num = 1, .den = 1}, - {.num = 1, .den = 3}, - {.num = 1, .den = 4}, - {.num = 1, .den = 6}, - {.num = 1, .den = 20}, - {.num = 1, .den = 8}, - {.num = 10, .den = 81}, - {.num = 1, .den = 10}, - {.num = 1, .den = 16} -}; - static int adc5_read(struct adc5_chip *adc, u16 offset, u8 *data, int len) { return regmap_bulk_read(adc->regmap, adc->base + offset, data, len); @@ -165,55 +153,6 @@ static int adc5_write(struct adc5_chip *adc, u16 offset, u8 *data, int len) return regmap_bulk_write(adc->regmap, adc->base + offset, data, len); } -static int adc5_prescaling_from_dt(u32 num, u32 den) -{ - unsigned int pre; - - for (pre = 0; pre < ARRAY_SIZE(adc5_prescale_ratios); pre++) - if (adc5_prescale_ratios[pre].num == num && - adc5_prescale_ratios[pre].den == den) - break; - - if (pre == ARRAY_SIZE(adc5_prescale_ratios)) - return -EINVAL; - - return pre; -} - -static int adc5_hw_settle_time_from_dt(u32 value, - const unsigned int *hw_settle) -{ - unsigned int i; - - for (i = 0; i < VADC_HW_SETTLE_SAMPLES_MAX; i++) { - if (value == hw_settle[i]) - return i; - } - - return -EINVAL; -} - -static int adc5_avg_samples_from_dt(u32 value) -{ - if (!is_power_of_2(value) || value > ADC5_AVG_SAMPLES_MAX) - return -EINVAL; - - return __ffs(value); -} - -static int adc5_decimation_from_dt(u32 value, - const unsigned int *decimation) -{ - unsigned int i; - - for (i = 0; i < ADC5_DECIMATION_SAMPLES_MAX; i++) { - if (value == decimation[i]) - return i; - } - - return -EINVAL; -} - static int adc5_read_voltage_data(struct adc5_chip *adc, u16 *data) { int ret; @@ -396,7 +335,7 @@ static int adc5_read_raw(struct iio_dev *indio_dev, return ret; ret = qcom_adc5_hw_scale(prop->scale_fn_type, - &adc5_prescale_ratios[prop->prescale], + prop->prescale, adc->data, adc_code_volt, val); if (ret) @@ -539,7 +478,7 @@ static int adc5_get_dt_channel_data(struct adc5_chip *adc, ret = of_property_read_u32(node, "qcom,decimation", &value); if (!ret) { - ret = adc5_decimation_from_dt(value, data->decimation); + ret = qcom_adc5_decimation_from_dt(value, data->decimation); if (ret < 0) { dev_err(dev, "%02x invalid decimation %d\n", chan, value); @@ -552,7 +491,7 @@ static int adc5_get_dt_channel_data(struct adc5_chip *adc, ret = of_property_read_u32_array(node, "qcom,pre-scaling", varr, 2); if (!ret) { - ret = adc5_prescaling_from_dt(varr[0], varr[1]); + ret = qcom_adc5_prescaling_from_dt(varr[0], varr[1]); if (ret < 0) { dev_err(dev, "%02x invalid pre-scaling <%d %d>\n", chan, varr[0], varr[1]); @@ -580,10 +519,10 @@ static int adc5_get_dt_channel_data(struct adc5_chip *adc, /* Digital controller >= 5.3 have hw_settle_2 option */ if (dig_version[0] >= ADC5_HW_SETTLE_DIFF_MINOR && dig_version[1] >= ADC5_HW_SETTLE_DIFF_MAJOR) - ret = adc5_hw_settle_time_from_dt(value, + ret = qcom_adc5_hw_settle_time_from_dt(value, data->hw_settle_2); else - ret = adc5_hw_settle_time_from_dt(value, + ret = qcom_adc5_hw_settle_time_from_dt(value, data->hw_settle_1); if (ret < 0) { @@ -598,7 +537,7 @@ static int adc5_get_dt_channel_data(struct adc5_chip *adc, ret = of_property_read_u32(node, "qcom,avg-samples", &value); if (!ret) { - ret = adc5_avg_samples_from_dt(value); + ret = qcom_adc5_avg_samples_from_dt(value); if (ret < 0) { dev_err(dev, "%02x invalid avg-samples %d\n", chan, value); diff --git a/drivers/iio/adc/qcom-vadc-common.c b/drivers/iio/adc/qcom-vadc-common.c index 2bb78d1c4daa..ffa578ce76db 100644 --- a/drivers/iio/adc/qcom-vadc-common.c +++ b/drivers/iio/adc/qcom-vadc-common.c @@ -89,6 +89,18 @@ static const struct vadc_map_pt adcmap_100k_104ef_104fb_1875_vref[] = { { 46, 125000 }, }; +static const struct vadc_prescale_ratio adc5_prescale_ratios[] = { + {.num = 1, .den = 1}, + {.num = 1, .den = 3}, + {.num = 1, .den = 4}, + {.num = 1, .den = 6}, + {.num = 1, .den = 20}, + {.num = 1, .den = 8}, + {.num = 10, .den = 81}, + {.num = 1, .den = 10}, + {.num = 1, .den = 16} +}; + static int qcom_vadc_scale_hw_calib_volt( const struct vadc_prescale_ratio *prescale, const struct adc5_data *data, @@ -385,10 +397,12 @@ int qcom_vadc_scale(enum vadc_scale_fn_type scaletype, EXPORT_SYMBOL(qcom_vadc_scale); int qcom_adc5_hw_scale(enum vadc_scale_fn_type scaletype, - const struct vadc_prescale_ratio *prescale, + unsigned int prescale_ratio, const struct adc5_data *data, u16 adc_code, int *result) { + const struct vadc_prescale_ratio *prescale = &adc5_prescale_ratios[prescale_ratio]; + if (!(scaletype >= SCALE_HW_CALIB_DEFAULT && scaletype < SCALE_HW_CALIB_INVALID)) { pr_err("Invalid scale type %d\n", scaletype); @@ -400,6 +414,59 @@ int qcom_adc5_hw_scale(enum vadc_scale_fn_type scaletype, } EXPORT_SYMBOL(qcom_adc5_hw_scale); +int qcom_adc5_prescaling_from_dt(u32 num, u32 den) +{ + unsigned int pre; + + for (pre = 0; pre < ARRAY_SIZE(adc5_prescale_ratios); pre++) + if (adc5_prescale_ratios[pre].num == num && + adc5_prescale_ratios[pre].den == den) + break; + + if (pre == ARRAY_SIZE(adc5_prescale_ratios)) + return -EINVAL; + + return pre; +} +EXPORT_SYMBOL(qcom_adc5_prescaling_from_dt); + +int qcom_adc5_hw_settle_time_from_dt(u32 value, + const unsigned int *hw_settle) +{ + unsigned int i; + + for (i = 0; i < VADC_HW_SETTLE_SAMPLES_MAX; i++) { + if (value == hw_settle[i]) + return i; + } + + return -EINVAL; +} +EXPORT_SYMBOL(qcom_adc5_hw_settle_time_from_dt); + +int qcom_adc5_avg_samples_from_dt(u32 value) +{ + if (!is_power_of_2(value) || value > ADC5_AVG_SAMPLES_MAX) + return -EINVAL; + + return __ffs(value); +} +EXPORT_SYMBOL(qcom_adc5_avg_samples_from_dt); + +int qcom_adc5_decimation_from_dt(u32 value, + const unsigned int *decimation) +{ + unsigned int i; + + for (i = 0; i < ADC5_DECIMATION_SAMPLES_MAX; i++) { + if (value == decimation[i]) + return i; + } + + return -EINVAL; +} +EXPORT_SYMBOL(qcom_adc5_decimation_from_dt); + int qcom_vadc_decimation_from_dt(u32 value) { if (!is_power_of_2(value) || value < VADC_DECIMATION_MIN || diff --git a/drivers/iio/adc/qcom-vadc-common.h b/drivers/iio/adc/qcom-vadc-common.h index e074902a24cc..2c65ddc98696 100644 --- a/drivers/iio/adc/qcom-vadc-common.h +++ b/drivers/iio/adc/qcom-vadc-common.h @@ -153,10 +153,20 @@ struct qcom_adc5_scale_type { }; int qcom_adc5_hw_scale(enum vadc_scale_fn_type scaletype, - const struct vadc_prescale_ratio *prescale, + unsigned int prescale_ratio, const struct adc5_data *data, u16 adc_code, int *result_mdec); +int qcom_adc5_prescaling_from_dt(u32 num, u32 den); + +int qcom_adc5_hw_settle_time_from_dt(u32 value, + const unsigned int *hw_settle); + +int qcom_adc5_avg_samples_from_dt(u32 value); + +int qcom_adc5_decimation_from_dt(u32 value, + const unsigned int *decimation); + int qcom_vadc_decimation_from_dt(u32 value); #endif /* QCOM_VADC_COMMON_H */ From patchwork Sun Jun 21 19:35:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 198734 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72C72C433E2 for ; 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Sun, 21 Jun 2020 12:35:58 -0700 (PDT) Received: from eriador.lan ([188.162.65.109]) by smtp.gmail.com with ESMTPSA id r13sm2917854lfp.80.2020.06.21.12.35.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Jun 2020 12:35:57 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Zhang Rui , Daniel Lezcano , Amit Kucheria , Jonathan Cameron , Hartmut Knaack , Lars-Peter Clausen , Peter Meerwald-Stadler Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Vinod Koul , linux-iio@vger.kernel.org Subject: [PATCH 3/5] thermal: qcom: add support for adc-tm5 PMIC thermal monitor Date: Sun, 21 Jun 2020 22:35:47 +0300 Message-Id: <20200621193549.2070434-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200621193549.2070434-1-dmitry.baryshkov@linaro.org> References: <20200621193549.2070434-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support for Thermal Monitoring part of PMIC5. This part is closely coupled with ADC, using it's channels directly. ADC-TM support generating interrupts on ADC value crossing low or high voltage bounds, which is used to support thermal trip points. Signed-off-by: Dmitry Baryshkov --- drivers/iio/adc/qcom-vadc-common.c | 67 +++ drivers/iio/adc/qcom-vadc-common.h | 3 + drivers/thermal/qcom/Kconfig | 11 + drivers/thermal/qcom/Makefile | 1 + drivers/thermal/qcom/qcom-spmi-adc-tm5.c | 617 +++++++++++++++++++++++ 5 files changed, 699 insertions(+) create mode 100644 drivers/thermal/qcom/qcom-spmi-adc-tm5.c diff --git a/drivers/iio/adc/qcom-vadc-common.c b/drivers/iio/adc/qcom-vadc-common.c index ffa578ce76db..e470beb8c6f9 100644 --- a/drivers/iio/adc/qcom-vadc-common.c +++ b/drivers/iio/adc/qcom-vadc-common.c @@ -176,6 +176,47 @@ static int qcom_vadc_map_voltage_temp(const struct vadc_map_pt *pts, return 0; } +static s32 qcom_vadc_map_temp_voltage(const struct vadc_map_pt *pts, + u32 tablesize, int input) +{ + bool descending = 1; + u32 i = 0; + + /* Check if table is descending or ascending */ + if (tablesize > 1) { + if (pts[0].y < pts[1].y) + descending = 0; + } + + while (i < tablesize) { + if ((descending) && (pts[i].y < input)) { + /* table entry is less than measured*/ + /* value and table is descending, stop */ + break; + } else if ((!descending) && + (pts[i].y > input)) { + /* table entry is greater than measured*/ + /*value and table is ascending, stop */ + break; + } + i++; + } + + if (i == 0) + return pts[0].x; + if (i == tablesize) + return pts[tablesize - 1].x; + + /* result is between search_index and search_index-1 */ + /* interpolate linearly */ + return (((s32)((pts[i].x - pts[i - 1].x) * + (input - pts[i - 1].y)) / + (pts[i].y - pts[i - 1].y)) + + pts[i - 1].x); + + return 0; +} + static void qcom_vadc_scale_calib(const struct vadc_linear_graph *calib_graph, u16 adc_code, bool absolute, @@ -273,6 +314,19 @@ static int qcom_vadc_scale_chg_temp(const struct vadc_linear_graph *calib_graph, return 0; } +static u16 qcom_vadc_scale_voltage_code(int voltage, + const struct vadc_prescale_ratio *prescale, + const u32 full_scale_code_volt, + unsigned int factor) +{ + s64 volt = voltage, adc_vdd_ref_mv = 1875; + + volt *= prescale->num * factor * full_scale_code_volt; + volt = div64_s64(volt, (s64)prescale->den * adc_vdd_ref_mv * 1000); + + return volt; +} + static int qcom_vadc_scale_code_voltage_factor(u16 adc_code, const struct vadc_prescale_ratio *prescale, const struct adc5_data *data, @@ -396,6 +450,19 @@ int qcom_vadc_scale(enum vadc_scale_fn_type scaletype, } EXPORT_SYMBOL(qcom_vadc_scale); +u16 qcom_adc_tm5_temp_volt_scale(unsigned int prescale_ratio, + u32 full_scale_code_volt, int temp) +{ + const struct vadc_prescale_ratio *prescale = &adc5_prescale_ratios[prescale_ratio]; + s32 voltage; + + voltage = qcom_vadc_map_temp_voltage(adcmap_100k_104ef_104fb_1875_vref, + ARRAY_SIZE(adcmap_100k_104ef_104fb_1875_vref), + temp); + return qcom_vadc_scale_voltage_code(voltage, prescale, full_scale_code_volt, 1000); +} +EXPORT_SYMBOL(qcom_adc_tm5_temp_volt_scale); + int qcom_adc5_hw_scale(enum vadc_scale_fn_type scaletype, unsigned int prescale_ratio, const struct adc5_data *data, diff --git a/drivers/iio/adc/qcom-vadc-common.h b/drivers/iio/adc/qcom-vadc-common.h index 2c65ddc98696..978820443d8a 100644 --- a/drivers/iio/adc/qcom-vadc-common.h +++ b/drivers/iio/adc/qcom-vadc-common.h @@ -157,6 +157,9 @@ int qcom_adc5_hw_scale(enum vadc_scale_fn_type scaletype, const struct adc5_data *data, u16 adc_code, int *result_mdec); +u16 qcom_adc_tm5_temp_volt_scale(unsigned int prescale_ratio, + u32 full_scale_code_volt, int temp); + int qcom_adc5_prescaling_from_dt(u32 num, u32 den); int qcom_adc5_hw_settle_time_from_dt(u32 value, diff --git a/drivers/thermal/qcom/Kconfig b/drivers/thermal/qcom/Kconfig index aa9c1d80fae4..c61df55760e9 100644 --- a/drivers/thermal/qcom/Kconfig +++ b/drivers/thermal/qcom/Kconfig @@ -20,3 +20,14 @@ config QCOM_SPMI_TEMP_ALARM trip points. The temperature reported by the thermal sensor reflects the real time die temperature if an ADC is present or an estimate of the temperature based upon the over temperature stage value. + +config QCOM_SPMI_ADC_TM5 + tristate "Qualcomm SPMI PMIC Thermal Monitor ADC5" + depends on OF && SPMI && IIO + select REGMAP_SPMI + select QCOM_VADC_COMMON + help + This enables the thermal driver for the ADC thermal monitoring + device. It shows up as a thermal zone with multiple trip points. + Thermal client sets threshold temperature for both warm and cool and + gets updated when a threshold is reached. diff --git a/drivers/thermal/qcom/Makefile b/drivers/thermal/qcom/Makefile index ec86eef7f6a6..5b9445a3fd26 100644 --- a/drivers/thermal/qcom/Makefile +++ b/drivers/thermal/qcom/Makefile @@ -4,3 +4,4 @@ obj-$(CONFIG_QCOM_TSENS) += qcom_tsens.o qcom_tsens-y += tsens.o tsens-v2.o tsens-v1.o tsens-v0_1.o \ tsens-8960.o obj-$(CONFIG_QCOM_SPMI_TEMP_ALARM) += qcom-spmi-temp-alarm.o +obj-$(CONFIG_QCOM_SPMI_ADC_TM5) += qcom-spmi-adc-tm5.o diff --git a/drivers/thermal/qcom/qcom-spmi-adc-tm5.c b/drivers/thermal/qcom/qcom-spmi-adc-tm5.c new file mode 100644 index 000000000000..ebfe0c9fbf96 --- /dev/null +++ b/drivers/thermal/qcom/qcom-spmi-adc-tm5.c @@ -0,0 +1,617 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2020 Linaro Limited + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../../iio/adc/qcom-vadc-common.h" + +#define ADC5_MAX_CHANNEL 0xc0 +#define ADC_TM5_NUM_CHANNELS 8 +#define ADC_TM5_TIMER1 3 /* 3.9ms */ +#define ADC_TM5_TIMER2 10 /* 1 second */ +#define ADC_TM5_TIMER3 4 /* 4 second */ + +#define ADC_TM5_STATUS_LOW 0x0a + +#define ADC_TM5_STATUS_HIGH 0x0b + +#define ADC_TM5_NUM_BTM 0x0f + +#define ADC_TM5_ADC_DIG_PARAM 0x42 + +#define ADC_TM5_FAST_AVG_CTL 0x43 +#define ADC_TM5_FAST_AVG_EN BIT(7) + +#define ADC_TM5_MEAS_INTERVAL_CTL 0x44 + +#define ADC_TM5_MEAS_INTERVAL_CTL2 0x45 +#define ADC_TM5_MEAS_INTERVAL_CTL2_SHIFT 0x4 +#define ADC_TM5_MEAS_INTERVAL_CTL2_MASK 0xf0 +#define ADC_TM5_MEAS_INTERVAL_CTL3_MASK 0xf + +#define ADC_TM5_Mn_EN(n) ((n * 8) + 0x67) +#define ADC_TM5_Mn_MEAS_EN BIT(7) +#define ADC_TM5_Mn_HIGH_THR_INT_EN BIT(1) +#define ADC_TM5_Mn_LOW_THR_INT_EN BIT(0) + +#define ADC_TM5_Mn_ADC_CH_SEL_CTL(n) ((n * 8) + 0x60) +#define ADC_TM5_Mn_LOW_THR0(n) ((n * 8) + 0x61) +#define ADC_TM5_Mn_LOW_THR1(n) ((n * 8) + 0x62) +#define ADC_TM5_Mn_HIGH_THR0(n) ((n * 8) + 0x63) +#define ADC_TM5_Mn_HIGH_THR1(n) ((n * 8) + 0x64) +#define ADC_TM5_Mn_MEAS_INTERVAL_CTL(n) ((n * 8) + 0x65) +#define ADC_TM5_Mn_CTL(n) ((n * 8) + 0x66) +#define ADC_TM5_CTL_HW_SETTLE_DELAY_MASK 0xf +#define ADC_TM5_CTL_CAL_SEL 0x30 +#define ADC_TM5_CTL_CAL_SEL_MASK_SHIFT 4 +#define ADC_TM5_CTL_CAL_VAL 0x40 + +enum adc5_timer_select { + ADC5_TIMER_SEL_1 = 0, + ADC5_TIMER_SEL_2, + ADC5_TIMER_SEL_3, + ADC5_TIMER_SEL_NONE, +}; + +struct adc_tm5_data { + const u32 full_scale_code_volt; + unsigned int *decimation; + unsigned int *hw_settle; +}; + +enum adc_tm5_cal_method { + ADC_TM5_NO_CAL = 0, + ADC_TM5_RATIOMETRIC_CAL, + ADC_TM5_ABSOLUTE_CAL +}; + +struct adc_tm5_chip; + +struct adc_tm5_channel { + unsigned int channel; + unsigned int adc_channel; + enum adc_tm5_cal_method cal_method; + unsigned int prescale; + unsigned int hw_settle_time; + struct iio_channel *iio; + struct adc_tm5_chip *chip; + struct thermal_zone_device *tzd; +}; + +struct adc_tm5_chip { + struct regmap *regmap; + struct device *dev; + struct adc_tm5_channel *channels; + const struct adc_tm5_data *data; + spinlock_t reg_lock; + unsigned int decimation; + unsigned int avg_samples; + unsigned int timer1; + unsigned int timer2; + unsigned int timer3; + unsigned int nchannels; + u16 base; +}; + +static const struct adc_tm5_data adc_tm5_data_pmic = { + .full_scale_code_volt = 0x70e4, + .decimation = (unsigned int []) {250, 420, 840}, + .hw_settle = (unsigned int []) {15, 100, 200, 300, 400, 500, 600, 700, + 1, 2, 4, 8, 16, 32, 64, 128}, +}; + +static const struct of_device_id adc_tm5_match_table[] = { + { + .compatible = "qcom,spmi-adc-tm5", + .data = &adc_tm5_data_pmic, + }, + { } +}; +MODULE_DEVICE_TABLE(of, adc_tm5_match_table); + +static int adc_tm5_read(struct adc_tm5_chip *adc_tm, u16 offset, u8 *data, int len) +{ + return regmap_bulk_read(adc_tm->regmap, adc_tm->base + offset, data, len); +} + +static int adc_tm5_write(struct adc_tm5_chip *adc_tm, u16 offset, u8 *data, int len) +{ + return regmap_bulk_write(adc_tm->regmap, adc_tm->base + offset, data, len); +} + +static int adc_tm5_reg_update(struct adc_tm5_chip *adc_tm, u16 offset, u8 mask, u8 val) +{ + return regmap_write_bits(adc_tm->regmap, adc_tm->base + offset, mask, val); +} + +static irqreturn_t adc_tm5_isr(int irq, void *data) +{ + struct adc_tm5_chip *chip = data; + u8 status_low, status_high, ctl; + int ret = 0, i = 0; + unsigned long flags; + + ret = adc_tm5_read(chip, ADC_TM5_STATUS_LOW, &status_low, 1); + if (ret < 0) { + dev_err(chip->dev, "read status low failed with %d\n", ret); + return IRQ_HANDLED; + } + + ret = adc_tm5_read(chip, ADC_TM5_STATUS_HIGH, &status_high, 1); + if (ret < 0) { + dev_err(chip->dev, "read status high failed with %d\n", ret); + return IRQ_HANDLED; + } + + for (i = 0; i < chip->nchannels; i++) { + bool upper_set = false, lower_set = false; + unsigned int ch = chip->channels[i].channel; + + if (!chip->channels[i].tzd) { + dev_err(chip->dev, "thermal device not found\n"); + continue; + } + + spin_lock_irqsave(&chip->reg_lock, flags); + ret = adc_tm5_read(chip, ADC_TM5_Mn_EN(ch), &ctl, 1); + spin_unlock_irqrestore(&chip->reg_lock, flags); + + if (ret) { + dev_err(chip->dev, "ctl read failed with %d\n", ret); + goto fail; + } + + if ((status_low & BIT(ch)) && (ctl & ADC_TM5_Mn_MEAS_EN) + && (ctl & ADC_TM5_Mn_LOW_THR_INT_EN)) + lower_set = true; + + if ((status_high & BIT(ch)) && (ctl & ADC_TM5_Mn_MEAS_EN) && + (ctl & ADC_TM5_Mn_HIGH_THR_INT_EN)) + upper_set = true; +fail: + + if (upper_set || lower_set) + thermal_zone_device_update(chip->channels[i].tzd, + THERMAL_EVENT_UNSPECIFIED); + } + + return IRQ_HANDLED; +} + +static int adc_tm5_get_temp(void *data, int *temp) +{ + struct adc_tm5_channel *channel = data; + int ret, milli_celsius; + + if (!channel || !channel->iio) + return -EINVAL; + + ret = iio_read_channel_processed(channel->iio, &milli_celsius); + if (ret < 0) + return ret; + + *temp = milli_celsius; + + return 0; +} + +static int adc_tm5_disable_channel(struct adc_tm5_channel *channel) +{ + struct adc_tm5_chip *chip = channel->chip; + unsigned int reg = ADC_TM5_Mn_EN(channel->channel); + + return adc_tm5_reg_update(chip, reg, + ADC_TM5_Mn_MEAS_EN | ADC_TM5_Mn_HIGH_THR_INT_EN | ADC_TM5_Mn_LOW_THR_INT_EN, + 0); +} + +static int adc_tm5_configure(struct adc_tm5_channel *channel, u8 *low_thr, u8 *high_thr) +{ + struct adc_tm5_chip *chip = channel->chip; + u8 buf[8], cal_method; + u16 reg = ADC_TM5_Mn_ADC_CH_SEL_CTL(channel->channel); + int ret = 0; + + ret = adc_tm5_read(chip, reg, buf, 8); + if (ret < 0) { + dev_err(chip->dev, "block read failed with %d\n", ret); + return ret; + } + + /* Update ADC channel select */ + buf[0] = channel->adc_channel; + + if (low_thr) { + buf[1] = low_thr[0]; + buf[2] = low_thr[1]; + buf[7] |= ADC_TM5_Mn_LOW_THR_INT_EN; + } + + if (high_thr) { + buf[3] = high_thr[0]; + buf[4] = high_thr[1]; + buf[7] |= ADC_TM5_Mn_HIGH_THR_INT_EN; + } + + /* Update timer select */ + buf[5] = ADC5_TIMER_SEL_2; + + /* Set calibration select, hw_settle delay */ + cal_method = (u8) (channel->cal_method << ADC_TM5_CTL_CAL_SEL_MASK_SHIFT); + buf[6] &= (u8) ~ADC_TM5_CTL_HW_SETTLE_DELAY_MASK; + buf[6] |= (u8) channel->hw_settle_time; + buf[6] &= (u8) ~ADC_TM5_CTL_CAL_SEL; + buf[6] |= (u8) cal_method; + + buf[7] |= ADC_TM5_Mn_MEAS_EN; + + ret = adc_tm5_write(chip, reg, buf, 8); + if (ret < 0) { + dev_err(chip->dev, "buf write failed\n"); + return ret; + } + + return 0; +} + +static int adc_tm5_set_trip_temp(void *data, + int low_temp, int high_temp) +{ + struct adc_tm5_channel *channel = data; + struct adc_tm5_chip *chip; + u8 trip_high_thr[2], trip_low_thr[2]; + u8 *trip_high_ptr = NULL, *trip_low_ptr = NULL; + int ret; + unsigned long flags; + + if (!channel) + return -EINVAL; + + dev_info(channel->chip->dev, "%d:low_temp(mdegC):%d, high_temp(mdegC):%d\n", + channel->channel, low_temp, high_temp); + chip = channel->chip; + + /* Warm temperature corresponds to low voltage threshold */ + if (high_temp != INT_MAX) { + u16 adc_code = qcom_adc_tm5_temp_volt_scale(channel->prescale, + chip->data->full_scale_code_volt, high_temp); + + trip_low_thr[0] = adc_code & 0xff; + trip_low_thr[1] = adc_code >> 8; + trip_low_ptr = trip_low_thr; + } + + /* Cool temperature corresponds to high voltage threshold */ + if (low_temp != -INT_MAX) { + u16 adc_code = qcom_adc_tm5_temp_volt_scale(channel->prescale, + chip->data->full_scale_code_volt, low_temp); + + trip_high_thr[0] = adc_code & 0xff; + trip_high_thr[1] = adc_code >> 8; + trip_high_ptr = trip_high_thr; + } + + spin_lock_irqsave(&chip->reg_lock, flags); + if (high_temp == INT_MAX && low_temp == INT_MIN) + ret = adc_tm5_disable_channel(channel); + else + ret = adc_tm5_configure(channel, trip_low_ptr, trip_high_ptr); + + spin_unlock_irqrestore(&chip->reg_lock, flags); + + return ret; +} + + +static struct thermal_zone_of_device_ops adc_tm5_ops = { + .get_temp = adc_tm5_get_temp, + .set_trips = adc_tm5_set_trip_temp, +}; + +static int adc_tm5_register_tzd(struct adc_tm5_chip *adc_tm) +{ + unsigned int i; + struct thermal_zone_device *tzd; + + for (i = 0; i < adc_tm->nchannels; i++) { + adc_tm->channels[i].chip = adc_tm; + + tzd = devm_thermal_zone_of_sensor_register( + adc_tm->dev, adc_tm->channels[i].channel, + &adc_tm->channels[i], &adc_tm5_ops); + if (IS_ERR(tzd)) { + dev_err(adc_tm->dev, "Error registering TZ zone:%ld for channel:%d\n", + PTR_ERR(tzd), adc_tm->channels[i].channel); + continue; + } + adc_tm->channels[i].tzd = tzd; + } + + return 0; +} + +static int adc_tm5_init(struct adc_tm5_chip *chip) +{ + u8 buf[4], channels_available, meas_int_timer_2_3 = 0; + int ret; + unsigned int i; + + ret = adc_tm5_read(chip, ADC_TM5_NUM_BTM, &channels_available, 1); + if (ret < 0) { + dev_err(chip->dev, "read failed for BTM channels\n"); + return ret; + } + + ret = adc_tm5_read(chip, ADC_TM5_ADC_DIG_PARAM, buf, 4); + if (ret < 0) { + dev_err(chip->dev, "block read failed with %d\n", ret); + return ret; + } + + /* Select decimation */ + buf[0] = chip->decimation; + + /* Select number of samples in fast average mode */ + buf[1] = chip->avg_samples | ADC_TM5_FAST_AVG_EN; + + /* Select timer1 */ + buf[2] = chip->timer1; + + /* Select timer2 and timer3 */ + meas_int_timer_2_3 |= chip->timer2 << + ADC_TM5_MEAS_INTERVAL_CTL2_SHIFT; + meas_int_timer_2_3 |= chip->timer3; + buf[3] = meas_int_timer_2_3; + + ret = adc_tm5_write(chip, + ADC_TM5_ADC_DIG_PARAM, buf, 4); + if (ret < 0) + dev_err(chip->dev, "block write failed with %d\n", ret); + + for (i = 0; i < chip->nchannels; i++) { + if (chip->channels[i].channel >= channels_available) { + dev_err(chip->dev, "Invalid channel %d\n", chip->channels[i].channel); + return -EINVAL; + } + } + + return ret; +} + +static int adc_tm5_get_dt_channel_data(struct adc_tm5_chip *adc_tm, + struct adc_tm5_channel *prop, + struct device_node *node, + const struct adc_tm5_data *data) +{ + const char *name = node->name; + u32 chan, value, varr[2]; + int ret; + struct device *dev = adc_tm->dev; + + ret = of_property_read_u32(node, "reg", &chan); + if (ret) { + dev_err(dev, "invalid channel number %s\n", name); + return ret; + } + + if (chan >= ADC_TM5_NUM_CHANNELS) { + dev_err(dev, "%s invalid channel number %d\n", name, chan); + return -EINVAL; + } + + /* the channel has DT description */ + prop->channel = chan; + + ret = of_property_read_u32(node, "qcom,adc-channel", &chan); + if (ret) { + dev_err(dev, "invalid channel number %s\n", name); + return ret; + } + if (chan >= ADC5_MAX_CHANNEL) { + dev_err(dev, "%s invalid ADC channel number %d\n", name, chan); + return ret; + } + prop->adc_channel = chan; + + prop->iio = devm_iio_channel_get(adc_tm->dev, name); + if (IS_ERR(prop->iio)) { + ret = PTR_ERR(prop->iio); + prop->iio = NULL; + dev_err(dev, "error getting channel %s: %d\n", name, ret); + return ret; + } + + ret = of_property_read_u32_array(node, "qcom,pre-scaling", varr, 2); + if (!ret) { + ret = qcom_adc5_prescaling_from_dt(varr[0], varr[1]); + if (ret < 0) { + dev_err(dev, "%02x invalid pre-scaling <%d %d>\n", + chan, varr[0], varr[1]); + return ret; + } + prop->prescale = ret; + } else { + prop->prescale = 0; /*1:1 is index 0 */ + } + + ret = of_property_read_u32(node, "qcom,hw-settle-time", &value); + if (!ret) { + ret = qcom_adc5_hw_settle_time_from_dt(value, + data->hw_settle); + if (ret < 0) { + dev_err(dev, "%02x invalid hw-settle-time %d us\n", + chan, value); + return ret; + } + prop->hw_settle_time = ret; + } else { + prop->hw_settle_time = VADC_DEF_HW_SETTLE_TIME; + } + + if (of_property_read_bool(node, "qcom,ratiometric")) + prop->cal_method = ADC_TM5_RATIOMETRIC_CAL; + else + prop->cal_method = ADC_TM5_ABSOLUTE_CAL; + + dev_dbg(dev, "%02x name %s\n", chan, name); + + return 0; +} + +static int adc_tm5_get_dt_data(struct adc_tm5_chip *adc_tm, struct device_node *node) +{ + struct adc_tm5_channel *channels; + struct device_node *child; + unsigned int index = 0; + const struct of_device_id *id; + const struct adc_tm5_data *data; + u32 value; + int ret; + struct device *dev = adc_tm->dev; + + adc_tm->nchannels = of_get_available_child_count(node); + if (!adc_tm->nchannels) + return -EINVAL; + + adc_tm->channels = devm_kcalloc(adc_tm->dev, adc_tm->nchannels, + sizeof(*adc_tm->channels), GFP_KERNEL); + if (!adc_tm->channels) + return -ENOMEM; + + channels = adc_tm->channels; + + id = of_match_node(adc_tm5_match_table, node); + if (id) + data = id->data; + else + data = &adc_tm5_data_pmic; + adc_tm->data = data; + + ret = of_property_read_u32(node, "qcom,decimation", &value); + if (!ret) { + ret = qcom_adc5_decimation_from_dt(value, data->decimation); + if (ret < 0) { + dev_err(dev, "invalid decimation %d\n", + value); + return ret; + } + adc_tm->decimation = ret; + } else { + adc_tm->decimation = ADC5_DECIMATION_DEFAULT; + } + + ret = of_property_read_u32(node, "qcom,avg-samples", &value); + if (!ret) { + ret = qcom_adc5_avg_samples_from_dt(value); + if (ret < 0) { + dev_err(dev, "invalid avg-samples %d\n", + value); + return ret; + } + adc_tm->avg_samples = ret; + } else { + adc_tm->avg_samples = VADC_DEF_AVG_SAMPLES; + } + + adc_tm->timer1 = ADC_TM5_TIMER1; + adc_tm->timer2 = ADC_TM5_TIMER2; + adc_tm->timer3 = ADC_TM5_TIMER3; + + for_each_available_child_of_node(node, child) { + ret = adc_tm5_get_dt_channel_data(adc_tm, channels, child, data); + if (ret) { + of_node_put(child); + return ret; + } + + channels++; + index++; + } + + return 0; +} + +static int adc_tm5_probe(struct platform_device *pdev) +{ + struct device_node *node = pdev->dev.of_node; + struct device *dev = &pdev->dev; + struct adc_tm5_chip *adc_tm; + struct regmap *regmap; + int ret, irq; + u32 reg; + + regmap = dev_get_regmap(dev->parent, NULL); + if (!regmap) + return -ENODEV; + + ret = of_property_read_u32(node, "reg", ®); + if (ret < 0) + return ret; + + adc_tm = devm_kzalloc(&pdev->dev, sizeof(*adc_tm), GFP_KERNEL); + if (!adc_tm) + return -ENOMEM; + + adc_tm->regmap = regmap; + adc_tm->dev = dev; + adc_tm->base = reg; + spin_lock_init(&adc_tm->reg_lock); + + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + dev_err(dev, "get_irq failed: %d\n", irq); + return irq; + } + + ret = adc_tm5_get_dt_data(adc_tm, node); + if (ret) { + dev_err(dev, "get dt data failed: %d\n", ret); + return ret; + } + + ret = adc_tm5_init(adc_tm); + if (ret) { + dev_err(dev, "adc-tm init failed\n"); + return ret; + } + + ret = adc_tm5_register_tzd(adc_tm); + + ret = devm_request_irq(dev, irq, adc_tm5_isr, 0, + "pm-adc-tm5", adc_tm); + if (ret) + return ret; + + platform_set_drvdata(pdev, adc_tm); + + return 0; +} + +static int adc_tm5_remove(struct platform_device *pdev) +{ + return 0; +} + +static struct platform_driver adc_tm5_driver = { + .driver = { + .name = "spmi-adc-tm5", + .of_match_table = adc_tm5_match_table, + }, + .probe = adc_tm5_probe, + .remove = adc_tm5_remove, +}; +module_platform_driver(adc_tm5_driver); + +MODULE_ALIAS("platform:spmi-adc-tm5"); +MODULE_DESCRIPTION("SPMI PMIC Thermal Monitor ADC driver"); +MODULE_LICENSE("GPL v2"); From patchwork Sun Jun 21 19:35:49 2020 Content-Type: text/plain; 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[23.128.96.18]) by mx.google.com with ESMTP id g20si3105175edq.447.2020.06.21.12.36.05; Sun, 21 Jun 2020 12:36:05 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FxDenOYF; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730535AbgFUTgE (ORCPT + 6 others); Sun, 21 Jun 2020 15:36:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51936 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730510AbgFUTgD (ORCPT ); Sun, 21 Jun 2020 15:36:03 -0400 Received: from mail-lf1-x141.google.com (mail-lf1-x141.google.com [IPv6:2a00:1450:4864:20::141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 149BFC061795 for ; Sun, 21 Jun 2020 12:36:03 -0700 (PDT) Received: by mail-lf1-x141.google.com with SMTP id k15so1379800lfc.4 for ; Sun, 21 Jun 2020 12:36:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1ErXkZf7BLCpg6GnDRfFbSB9VliQZ1SaYRDHnOq2XmQ=; b=FxDenOYF/A25j1VglXtu1i1YXkjt6BN1uw/1Pl65aRzdJTSHJot639NR/ARSNVJ+F6 xNRewo7x5sOg0i0gK1tOpUELDEI7C5+GzmFYMk5uzfLJjkLNGTYH17XazC6i2t+IE2s9 RjHP5Acy/RY/JUnqyX6CcrvKUZoteZ/917pdCH9Yfc0tfYvTuCe0/madFMzUBJwHieKB 4/OKykeF4H9qhdGcSPpGjuhzBpRDFQoPsA2hZ6MxmYBnctHwrURyAJD0l1cDWv6377HY 0cQs5sjr9/M25+lNQ9jUFGBTutwEDU6L4Xipu/Clqz6X0vCh/s+dppWmDHLsz+zr50Ke LoTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1ErXkZf7BLCpg6GnDRfFbSB9VliQZ1SaYRDHnOq2XmQ=; b=ECUqkSp+ojzR2abxGTKBV2Xt0gRaCAXmsgAK+rP+Smvq3sR8oSEJWKv4d6gaU3iZg6 OK0zYcVNfST2zDvGl71q2Zezlc8EIX9XVBC0P2Exz7BuWLlC2GpWeOMtgrwlyhsmM8tj nFu7H1xQ8QUIlwfnD9p9CDODblSJwwDNYwbR+k7kRuS+W9uVcyFyJxq3Eq7Jwtg3x1WJ iTppBHHo66bBx1P6nnNQjkZLOxI31gGJv/SzDkLeiXVLZwazmLpDLraTEd9x9UmN0MY+ PoFtqQqd46V8QY3wa5O35jJh7LjlDFPjbJz2Bdr8/MCHhHz12wBiuhFyLGcbdxHkw9P5 Ce3g== X-Gm-Message-State: AOAM531oPcvu+a5DXkxbQfDlXW/gxdHEyznpAhyLv+qjXey4eUM5AAnq RKrIu+pi89OzEUBEnLKgueY1lw== X-Received: by 2002:ac2:5e6c:: with SMTP id a12mr7842921lfr.35.1592768161337; Sun, 21 Jun 2020 12:36:01 -0700 (PDT) Received: from eriador.lan ([188.162.65.109]) by smtp.gmail.com with ESMTPSA id r13sm2917854lfp.80.2020.06.21.12.35.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Jun 2020 12:36:00 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Zhang Rui , Daniel Lezcano , Amit Kucheria , Jonathan Cameron , Hartmut Knaack , Lars-Peter Clausen , Peter Meerwald-Stadler Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Vinod Koul , linux-iio@vger.kernel.org Subject: [PATCH 5/5] arm64: dts: sm8250-dts: add thermal zones using pmic's adc-tm5 Date: Sun, 21 Jun 2020 22:35:49 +0300 Message-Id: <20200621193549.2070434-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200621193549.2070434-1-dmitry.baryshkov@linaro.org> References: <20200621193549.2070434-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Port thermal zones definitions from msm-4.19 tree. Enable and add channel configuration to PMIC's ADC-TM definitions. Declare thermal zones and respective trip points. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8250-mtp.dts | 237 ++++++++++++++++++++++++ 1 file changed, 237 insertions(+) -- 2.27.0 diff --git a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts index aa37eb112d85..78f0cf582a9a 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts @@ -24,6 +24,104 @@ chosen { stdout-path = "serial0:115200n8"; }; + thermal-zones { + xo-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8150_adc_tm 0>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + skin-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8150_adc_tm 1>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + mmw-pa1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8150_adc_tm 2>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + conn-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8150b_adc_tm 0>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + camera-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8150l_adc_tm 0>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + skin-msm-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8150l_adc_tm 1>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + mmw-pa2 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8150l_adc_tm 2>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; @@ -355,6 +453,145 @@ vreg_l7f_1p8: ldo7 { }; }; +&pm8150_adc { + xo-therm@4c { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + skin_therm@4d { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa_therm1@4e { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm8150_adc { + xo-therm@4c { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + skin-therm@4d { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa-therm1@4e { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm8150b_adc { + conn-therm@4f { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm8150l_adc { + camera_flash_therm@4d { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + skin_msm_therm@4e { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa_therm2@4f { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm8150_adc_tm { + status = "okay"; + io-channels = <&pm8150_adc ADC5_XO_THERM_100K_PU>, + <&pm8150_adc ADC5_AMUX_THM1_100K_PU>, + <&pm8150_adc ADC5_AMUX_THM2_100K_PU>; + io-channel-names = "xo-therm", "skin-therm", "pa-therm1"; + + xo-therm@0 { + reg = <0>; + qcom,adc-channel = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + skin-therm@1 { + reg = <1>; + qcom,adc-channel = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa-therm1@2 { + reg = <2>; + qcom,adc-channel = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm8150b_adc_tm { + status = "okay"; + io-channels = <&pm8150b_adc ADC5_AMUX_THM3_100K_PU>; + io-channel-names = "conn-therm"; + + conn-therm@0 { + reg = <0>; + qcom,adc-channel = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm8150l_adc_tm { + status = "okay"; + io-channels = <&pm8150l_adc ADC5_AMUX_THM1_100K_PU>, + <&pm8150l_adc ADC5_AMUX_THM2_100K_PU>, + <&pm8150l_adc ADC5_AMUX_THM3_100K_PU>; + io-channel-names = "camera-flash-therm", "skin-msm-therm", "pa-therm2"; + + camera-flash-therm@0 { + reg = <0>; + qcom,adc-channel = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + skin-msm-therm@1 { + reg = <1>; + qcom,adc-channel = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa-therm2@2 { + reg = <2>; + qcom,adc-channel = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + &qupv3_id_1 { status = "okay"; };