From patchwork Thu Jun 18 22:26:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tanmay Shah X-Patchwork-Id: 194685 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0D2C7C433E1 for ; Thu, 18 Jun 2020 22:27:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D6BB1207D8 for ; Thu, 18 Jun 2020 22:27:27 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="iC8+YRhX" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732260AbgFRW1X (ORCPT ); Thu, 18 Jun 2020 18:27:23 -0400 Received: from mail29.static.mailgun.info ([104.130.122.29]:45771 "EHLO mail29.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728743AbgFRW1U (ORCPT ); Thu, 18 Jun 2020 18:27:20 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1592519239; h=Content-Transfer-Encoding: MIME-Version: References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=74KPYBul0WN79oQ7Kc0yFX4h5YzlQ/ueHWSiolnC5mY=; b=iC8+YRhX5DoS0hs78Gvx8540Qar/mr4ppUbnodCo+VGa4/0muCD8UYPcLqTZmmgrAzX3eV77 yAjPtCbDednevxIKFuHksK7rtb20snAqUbW7zGw6JeI8QpdJT/YgHc/b1PeKqlstXUmbVllO FQwxLsgUoze2qgL5q8mgpoOMqmM= X-Mailgun-Sending-Ip: 104.130.122.29 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n06.prod.us-east-1.postgun.com with SMTP id 5eebea378fe116ddd9277da2 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Thu, 18 Jun 2020 22:27:03 GMT Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 61D11C433CA; Thu, 18 Jun 2020 22:27:02 +0000 (UTC) Received: from linuxdisplay-lab-04.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: tanmay) by smtp.codeaurora.org (Postfix) with ESMTPSA id 5F231C433C8; Thu, 18 Jun 2020 22:26:59 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 5F231C433C8 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=tanmay@codeaurora.org From: Tanmay Shah To: robh+dt@kernel.org, swboyd@chromium.org, sam@ravnborg.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, seanpaul@chromium.org, robdclark@gmail.com, daniel@ffwll.ch, airlied@linux.ie, aravindh@codeaurora.org, abhinavk@codeaurora.org, chandanu@codeaurora.org, varar@codeaurora.org, Tanmay Shah Subject: [PATCH v7 1/6] dt-bindings: msm/dp: add bindings of DP/DP-PLL driver for Snapdragon Date: Thu, 18 Jun 2020 15:26:09 -0700 Message-Id: <20200618222614.14061-2-tanmay@codeaurora.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200618222614.14061-1-tanmay@codeaurora.org> References: <20200618222614.14061-1-tanmay@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Chandan Uddaraju Add bindings for Snapdragon DisplayPort controller driver. Changes in V2: Provide details about sel-gpio Changes in V4: Provide details about max dp lanes Change the commit text Changes in V5: moved dp.txt to yaml file Changes in v6: - Squash all AUX LUT properties into one pattern Property - Make aux-cfg[0-9]-settings properties optional - Remove PLL/PHY bindings from DP controller dts - Add DP clocks description - Remove _clk suffix from clock names - Rename pixel clock to stream_pixel - Remove redundant bindings (GPIO, PHY, HDCP clock, etc..) - Fix indentation - Add Display Port as interface of DPU in DPU bindings and add port mapping accordingly. Chages in v7: - Add dp-controller.yaml file common between multiple SOC - Rename dp-sc7180.yaml to dp-controller-sc7180.yaml - change compatible string and add SOC name to it. - Remove Root clock generator for pixel clock - Add assigned-clocks and assigned-clock-parents bindings - Remove redundant properties, descriptions and blank lines - Add DP port in DPU bindings - Update depends-on tag in commit message and rebase change accordingly This change depends-on: - https://patchwork.freedesktop.org/patch/366159/ Signed-off-by: Chandan Uddaraju Signed-off-by: Vara Reddy Signed-off-by: Tanmay Shah --- .../display/msm/dp-controller-sc7180.yaml | 147 ++++++++++++++++++ .../bindings/display/msm/dp-controller.yaml | 59 +++++++ .../bindings/display/msm/dpu-sc7180.yaml | 11 ++ 3 files changed, 217 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/msm/dp-controller-sc7180.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/dp-controller.yaml diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller-sc7180.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller-sc7180.yaml new file mode 100644 index 000000000000..8dd56816dbbd --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/dp-controller-sc7180.yaml @@ -0,0 +1,147 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dp-controller-sc7180.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MSM SC7180 Display Port Controller. + +maintainers: + - Chandan Uddaraju + - Vara Reddy + - Tanmay Shah + +description: | + Device tree bindings for DP host controller for MSM SC7180 target + that are compatible with VESA Display Port interface specification. + +allOf: + - $ref: dp-controller.yaml# + +properties: + compatible: + items: + - enum: + - qcom,sc7180-dp + + reg: + maxItems: 1 + reg-names: + const: dp_controller + + interrupts: + maxItems: 1 + + clocks: + maxItems: 4 + items: + - description: Display Port AUX clock + - description: Display Port Link clock + - description: Link interface clock between DP and PHY + - description: Display Port Pixel clock + + clock-names: + items: + - const: core_aux + - const: ctrl_link + - const: ctrl_link_iface + - const: stream_pixel + + "#clock-cells": + const: 1 + + assigned-clocks: + maxItems: 1 + assigned-clock-parents: + maxItems: 1 + + data-lanes: + $ref: "/schemas/types.yaml#/definitions/uint32-array" + minItems: 1 + maxItems: 4 + + vdda-1p2-supply: + description: phandle to vdda 1.2V regulator node. + + vdda-0p9-supply: + description: phandle to vdda 0.9V regulator node. + + ports: + type: object + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + port@0: + type: object + port@1: + type: object + +required: + - compatible + - reg + - reg-names + - interrupts + - clocks + - clock-names + - assigned-clocks + - assigned-clock-parents + - vdda-1p2-supply + - vdda-0p9-supply + - data-lanes + - ports + +additionalProperties: false + +examples: + - | + #include + #include + #include + msm_dp: displayport-controller@ae90000{ + compatible = "qcom,sc7180-dp"; + reg = <0 0xae90000 0 0x1400>; + reg-names = "dp_controller"; + + interrupt-parent = <&mdss>; + interrupts = <12 0>; + + clocks = <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; + clock-names = "core_aux", + "ctrl_link", + "ctrl_link_iface", "stream_pixel"; + #clock-cells = <1>; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; + assigned-clock-parents = <&dp_phy 1>; + + vdda-1p2-supply = <&vreg_l3c_1p2>; + vdda-0p9-supply = <&vreg_l4a_0p8>; + + data-lanes = <0 1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dp_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + dp_out: endpoint { + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml new file mode 100644 index 000000000000..7f3bc0878d8c --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dp-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display Port Controller. + +maintainers: + - Chandan Uddaraju + - Vara Reddy + - Tanmay Shah + +description: | + Device tree bindings for MSM Display Port which supports DP host controllers + that are compatible with VESA Display Port interface specification. + +properties: + compatible: + items: + - enum: + - qcom,sc7180-dp + + reg: + maxItems: 1 + reg-names: + const: dp_controller + + interrupts: + maxItems: 1 + + clocks: + maxItems: 4 + items: + - description: Display Port AUX clock + - description: Display Port Link clock + - description: Link interface clock between DP and PHY + - description: Display Port Pixel clock + + clock-names: + items: + - const: core_aux + - const: ctrl_link + - const: ctrl_link_iface + - const: stream_pixel + + assigned-clocks: + maxItems: 1 + assigned-clock-parents: + maxItems: 1 + + data-lanes: + $ref: "/schemas/types.yaml#/definitions/uint32-array" + minItems: 1 + maxItems: 4 + + ports: + type: object +... diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml index b5607f9429d5..9be71558c517 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml +++ b/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml @@ -141,6 +141,9 @@ patternProperties: port@1: type: object description: DPU_INTF2 (DSI2) + port@2: + type: object + description: DPU_INTF0 (DP) assigned-clocks: description: | @@ -237,6 +240,14 @@ examples: remote-endpoint = <&dsi0_in>; }; }; + + port@2 { + reg = <2>; + dpu_intf0_out: endpoint { + remote-endpoint = <&dp_in>; + }; + }; + }; }; }; From patchwork Thu Jun 18 22:26:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tanmay Shah X-Patchwork-Id: 194684 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E7EA7C433DF for ; Thu, 18 Jun 2020 22:27:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B97F02083B for ; Thu, 18 Jun 2020 22:27:50 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Thu, 18 Jun 2020 22:27:34 GMT Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 18C5FC4344E; Thu, 18 Jun 2020 22:27:33 +0000 (UTC) Received: from linuxdisplay-lab-04.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: tanmay) by smtp.codeaurora.org (Postfix) with ESMTPSA id B93E5C43387; Thu, 18 Jun 2020 22:27:26 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org B93E5C43387 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=tanmay@codeaurora.org From: Tanmay Shah To: robh+dt@kernel.org, swboyd@chromium.org, sam@ravnborg.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, seanpaul@chromium.org, robdclark@gmail.com, daniel@ffwll.ch, airlied@linux.ie, aravindh@codeaurora.org, abhinavk@codeaurora.org, chandanu@codeaurora.org, varar@codeaurora.org, Tanmay Shah Subject: [PATCH v7 6/6] drm/msm/dp: Add Display Port HPD feature Date: Thu, 18 Jun 2020 15:26:14 -0700 Message-Id: <20200618222614.14061-7-tanmay@codeaurora.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200618222614.14061-1-tanmay@codeaurora.org> References: <20200618222614.14061-1-tanmay@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Configure HPD registers in DP controller and enable HPD interrupt. Add interrupt to handle HPD connect and disconnect events. Signed-off-by: Tanmay Shah --- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 18 ++++ drivers/gpu/drm/msm/dp/dp_catalog.c | 67 +++++++++------ drivers/gpu/drm/msm/dp/dp_catalog.h | 5 +- drivers/gpu/drm/msm/dp/dp_ctrl.c | 1 - drivers/gpu/drm/msm/dp/dp_display.c | 110 ++++++++++++++++++++++-- drivers/gpu/drm/msm/dp/dp_reg.h | 12 +++ drivers/gpu/drm/msm/msm_drv.h | 6 ++ 7 files changed, 183 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 1295221d7341..ef17c64dd6e3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -765,6 +765,23 @@ static void dpu_irq_preinstall(struct msm_kms *kms) dpu_core_irq_preinstall(dpu_kms); } +static int dpu_irq_postinstall(struct msm_kms *kms) +{ + struct msm_drm_private *priv; + struct dpu_kms *dpu_kms = to_dpu_kms(kms); + + if (!dpu_kms || !dpu_kms->dev) + return -EINVAL; + + priv = dpu_kms->dev->dev_private; + if (!priv) + return -EINVAL; + + msm_dp_irq_postinstall(priv->dp); + + return 0; +} + static void dpu_irq_uninstall(struct msm_kms *kms) { struct dpu_kms *dpu_kms = to_dpu_kms(kms); @@ -775,6 +792,7 @@ static void dpu_irq_uninstall(struct msm_kms *kms) static const struct msm_kms_funcs kms_funcs = { .hw_init = dpu_kms_hw_init, .irq_preinstall = dpu_irq_preinstall, + .irq_postinstall = dpu_irq_postinstall, .irq_uninstall = dpu_irq_uninstall, .irq = dpu_irq, .enable_commit = dpu_kms_enable_commit, diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/dp_catalog.c index 84e7a57f41d0..1b197eebdc5d 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -17,7 +17,6 @@ #define POLLING_SLEEP_US 1000 #define POLLING_TIMEOUT_US 10000 -#define REFTIMER_DEFAULT_VALUE 0x20000 #define SCRAMBLER_RESET_COUNT_VALUE 0xFC #define DP_INTERRUPT_STATUS_ACK_SHIFT 1 @@ -766,35 +765,51 @@ void dp_catalog_ctrl_enable_irq(struct dp_catalog *dp_catalog, } } -void dp_catalog_ctrl_hpd_config(struct dp_catalog *dp_catalog, bool en) +void dp_catalog_hpd_config_intr(struct dp_catalog *dp_catalog, + u32 intr_mask, bool en) { struct dp_catalog_private *catalog = container_of(dp_catalog, struct dp_catalog_private, dp_catalog); - if (en) { - u32 reftimer = dp_read_aux(catalog, REG_DP_DP_HPD_REFTIMER); - - dp_write_aux(catalog, REG_DP_DP_HPD_INT_ACK, - DP_DP_HPD_PLUG_INT_ACK | - DP_DP_IRQ_HPD_INT_ACK | - DP_DP_HPD_REPLUG_INT_ACK | - DP_DP_HPD_UNPLUG_INT_ACK); - dp_write_aux(catalog, REG_DP_DP_HPD_INT_MASK, - DP_DP_HPD_PLUG_INT_MASK | - DP_DP_IRQ_HPD_INT_MASK | - DP_DP_HPD_REPLUG_INT_MASK | - DP_DP_HPD_UNPLUG_INT_MASK); - - /* Configure REFTIMER */ - reftimer |= REFTIMER_DEFAULT_VALUE; - dp_write_aux(catalog, REG_DP_DP_HPD_REFTIMER, reftimer); - /* Enable HPD */ - dp_write_aux(catalog, REG_DP_DP_HPD_CTRL, - DP_DP_HPD_CTRL_HPD_EN); - } else { - /* Disable HPD */ - dp_write_aux(catalog, REG_DP_DP_HPD_CTRL, 0x0); - } + u32 config = dp_read_aux(catalog, REG_DP_DP_HPD_INT_MASK); + + config = (en ? config | intr_mask : config & ~intr_mask); + + dp_write_aux(catalog, REG_DP_DP_HPD_INT_MASK, + config & DP_DP_HPD_INT_MASK); +} + +void dp_catalog_ctrl_hpd_config(struct dp_catalog *dp_catalog) +{ + struct dp_catalog_private *catalog = container_of(dp_catalog, + struct dp_catalog_private, dp_catalog); + + u32 reftimer = dp_read_aux(catalog, REG_DP_DP_HPD_REFTIMER); + + /* enable HPD interrupts */ + dp_catalog_hpd_config_intr(dp_catalog, + DP_DP_HPD_PLUG_INT_MASK | DP_DP_IRQ_HPD_INT_MASK + | DP_DP_HPD_UNPLUG_INT_MASK, true); + + /* Configure REFTIMER and enable it */ + reftimer |= DP_DP_HPD_REFTIMER_ENABLE; + dp_write_aux(catalog, REG_DP_DP_HPD_REFTIMER, reftimer); + + /* Enable HPD */ + dp_write_aux(catalog, REG_DP_DP_HPD_CTRL, DP_DP_HPD_CTRL_HPD_EN); +} + +u32 dp_catalog_hpd_get_intr_status(struct dp_catalog *dp_catalog) +{ + struct dp_catalog_private *catalog = container_of(dp_catalog, + struct dp_catalog_private, dp_catalog); + int isr = 0; + + isr = dp_read_aux(catalog, REG_DP_DP_HPD_INT_STATUS); + dp_write_aux(catalog, REG_DP_DP_HPD_INT_ACK, + (isr & DP_DP_HPD_INT_MASK)); + + return isr; } int dp_catalog_ctrl_get_interrupt(struct dp_catalog *dp_catalog) diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/dp_catalog.h index 86b82d4fcb42..23d1cec7a517 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.h +++ b/drivers/gpu/drm/msm/dp/dp_catalog.h @@ -60,7 +60,10 @@ void dp_catalog_ctrl_reset(struct dp_catalog *dp_catalog); void dp_catalog_ctrl_usb_reset(struct dp_catalog *dp_catalog, bool flip); bool dp_catalog_ctrl_mainlink_ready(struct dp_catalog *dp_catalog); void dp_catalog_ctrl_enable_irq(struct dp_catalog *dp_catalog, bool enable); -void dp_catalog_ctrl_hpd_config(struct dp_catalog *dp_catalog, bool enable); +void dp_catalog_hpd_config_intr(struct dp_catalog *dp_catalog, + u32 intr_mask, bool en); +void dp_catalog_ctrl_hpd_config(struct dp_catalog *dp_catalog); +u32 dp_catalog_hpd_get_intr_status(struct dp_catalog *dp_catalog); void dp_catalog_ctrl_phy_reset(struct dp_catalog *dp_catalog); void dp_catalog_ctrl_phy_lane_cfg(struct dp_catalog *dp_catalog, bool flipped, u8 lane_cnt); diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index ef08e8bbd476..98407e1d09e4 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -1569,7 +1569,6 @@ int dp_ctrl_on(struct dp_ctrl *dp_ctrl) rate = ctrl->panel->link_info.rate; dp_power_clk_enable(ctrl->power, DP_CORE_PM, true); - dp_catalog_ctrl_hpd_config(ctrl->catalog, true); if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) { DRM_DEBUG_DP("using phy test link parameters\n"); diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index cc9b5294762d..192d2a405253 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -17,6 +17,7 @@ #include "dp_power.h" #include "dp_catalog.h" #include "dp_aux.h" +#include "dp_reg.h" #include "dp_link.h" #include "dp_panel.h" #include "dp_ctrl.h" @@ -36,6 +37,7 @@ struct dp_display_private { bool power_on; bool hpd_irq_on; bool audio_supported; + atomic_t hpd_isr_status; struct platform_device *pdev; struct dentry *root; @@ -54,6 +56,8 @@ struct dp_display_private { struct dp_usbpd_cb usbpd_cb; struct dp_display_mode dp_mode; struct msm_dp dp_display; + + struct delayed_work config_hpd_work; }; static const struct of_device_id dp_dt_match[] = { @@ -64,6 +68,20 @@ static const struct of_device_id dp_dt_match[] = { static irqreturn_t dp_display_irq(int irq, void *dev_id) { struct dp_display_private *dp = dev_id; + irqreturn_t ret = IRQ_HANDLED; + u32 hpd_isr_status; + + if (!dp) { + DRM_ERROR("invalid data\n"); + return IRQ_NONE; + } + + hpd_isr_status = dp_catalog_hpd_get_intr_status(dp->catalog); + + if (hpd_isr_status & DP_DP_HPD_INT_MASK) { + atomic_set(&dp->hpd_isr_status, hpd_isr_status); + ret = IRQ_WAKE_THREAD; + } /* DP controller isr */ dp_ctrl_isr(dp->ctrl); @@ -71,6 +89,54 @@ static irqreturn_t dp_display_irq(int irq, void *dev_id) /* DP aux isr */ dp_aux_isr(dp->aux); + return ret; +} + +static irqreturn_t dp_display_hpd_isr_work(int irq, void *data) +{ + struct dp_display_private *dp; + struct dp_usbpd *hpd; + u32 isr = 0; + + dp = (struct dp_display_private *)data; + if (!dp) + return IRQ_NONE; + + isr = atomic_read(&dp->hpd_isr_status); + + /* reset to default */ + atomic_set(&dp->hpd_isr_status, 0); + + hpd = dp->usbpd; + if (!hpd) + return IRQ_NONE; + + if (isr & DP_DP_HPD_PLUG_INT_MASK && + isr & DP_DP_HPD_STATE_STATUS_CONNECTED) { + hpd->hpd_high = 1; + dp->usbpd_cb.configure(&dp->pdev->dev); + } else if (isr & DP_DP_HPD_UNPLUG_INT_MASK && + (isr & DP_DP_HPD_STATE_STATUS_MASK) == + DP_DP_HPD_STATE_STATUS_DISCONNECTED) { + + /* disable HPD plug interrupt until disconnect is done + */ + dp_catalog_hpd_config_intr(dp->catalog, + DP_DP_HPD_PLUG_INT_MASK | DP_DP_IRQ_HPD_INT_MASK, + false); + + hpd->hpd_high = 0; + + /* We don't need separate work for disconnect as + * connect/attention interrupts are disabled + */ + dp->usbpd_cb.disconnect(&dp->pdev->dev); + + dp_catalog_hpd_config_intr(dp->catalog, + DP_DP_HPD_PLUG_INT_MASK | DP_DP_IRQ_HPD_INT_MASK, + true); + } + return IRQ_HANDLED; } @@ -203,8 +269,6 @@ static int dp_display_process_hpd_high(struct dp_display_private *dp) int rc = 0; struct edid *edid; - dp_aux_init(dp->aux, dp->parser->aux_cfg); - if (dp->link->psm_enabled) goto notify; @@ -250,7 +314,7 @@ static void dp_display_host_init(struct dp_display_private *dp) dp_power_init(dp->power, flip); dp_ctrl_host_init(dp->ctrl, flip); - enable_irq(dp->irq); + dp_aux_init(dp->aux, dp->parser->aux_cfg); dp->core_initialized = true; } @@ -261,10 +325,6 @@ static void dp_display_host_deinit(struct dp_display_private *dp) return; } - dp_ctrl_host_deinit(dp->ctrl); - dp_aux_deinit(dp->aux); - dp_power_deinit(dp->power); - disable_irq(dp->irq); dp->core_initialized = false; } @@ -620,7 +680,8 @@ int dp_display_request_irq(struct msm_dp *dp_display) return rc; } - rc = devm_request_irq(&dp->pdev->dev, dp->irq, dp_display_irq, + rc = devm_request_threaded_irq(&dp->pdev->dev, dp->irq, + dp_display_irq, dp_display_hpd_isr_work, IRQF_TRIGGER_HIGH, "dp_display_isr", dp); if (rc < 0) { DRM_ERROR("failed to request IRQ%u: %d\n", @@ -789,6 +850,39 @@ void __exit msm_dp_unregister(void) platform_driver_unregister(&dp_display_driver); } +static void dp_display_config_hpd_work(struct work_struct *work) +{ + struct dp_display_private *dp; + struct delayed_work *dw = to_delayed_work(work); + + dp = container_of(dw, struct dp_display_private, config_hpd_work); + + dp_display_host_init(dp); + dp_catalog_ctrl_hpd_config(dp->catalog); + + /* set default to 0 */ + atomic_set(&dp->hpd_isr_status, 0); + + /* Enable interrupt first time + * we are leaving dp clocks on during disconnect + * and never disable interrupt + */ + enable_irq(dp->irq); +} + +void msm_dp_irq_postinstall(struct msm_dp *dp_display) +{ + struct dp_display_private *dp; + + if (!dp_display) + return; + + dp = container_of(dp_display, struct dp_display_private, dp_display); + + INIT_DELAYED_WORK(&dp->config_hpd_work, dp_display_config_hpd_work); + queue_delayed_work(system_wq, &dp->config_hpd_work, HZ * 10); +} + int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev, struct drm_encoder *encoder) { diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_reg.h index ad6f1760f893..6b3e297e4e04 100644 --- a/drivers/gpu/drm/msm/dp/dp_reg.h +++ b/drivers/gpu/drm/msm/dp/dp_reg.h @@ -54,10 +54,22 @@ #define DP_DP_IRQ_HPD_INT_MASK (0x00000002) #define DP_DP_HPD_REPLUG_INT_MASK (0x00000004) #define DP_DP_HPD_UNPLUG_INT_MASK (0x00000008) +#define DP_DP_HPD_INT_MASK (DP_DP_HPD_PLUG_INT_MASK | \ + DP_DP_IRQ_HPD_INT_MASK | \ + DP_DP_HPD_REPLUG_INT_MASK | \ + DP_DP_HPD_UNPLUG_INT_MASK) +#define DP_DP_HPD_STATE_STATUS_CONNECTED (0x40000000) +#define DP_DP_HPD_STATE_STATUS_PENDING (0x20000000) +#define DP_DP_HPD_STATE_STATUS_DISCONNECTED (0x00000000) +#define DP_DP_HPD_STATE_STATUS_MASK (0xE0000000) #define REG_DP_DP_HPD_REFTIMER (0x00000018) +#define DP_DP_HPD_REFTIMER_ENABLE (1 << 16) + #define REG_DP_DP_HPD_EVENT_TIME_0 (0x0000001C) #define REG_DP_DP_HPD_EVENT_TIME_1 (0x00000020) +#define DP_DP_HPD_EVENT_TIME_0_VAL (0x3E800FA) +#define DP_DP_HPD_EVENT_TIME_1_VAL (0x1F407D0) #define REG_DP_AUX_CTRL (0x00000030) #define DP_AUX_CTRL_ENABLE (0x00000001) diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index 5e3219be65a1..58e5fe5f35f3 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -390,6 +390,7 @@ int msm_dp_display_disable(struct msm_dp *dp, struct drm_encoder *encoder); void msm_dp_display_mode_set(struct msm_dp *dp, struct drm_encoder *encoder, struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode); +void msm_dp_irq_postinstall(struct msm_dp *dp_display); #else static inline int __init msm_dp_register(void) @@ -421,6 +422,11 @@ static inline void msm_dp_display_mode_set(struct msm_dp *dp, struct drm_display_mode *adjusted_mode) { } + +static inline void msm_dp_irq_postinstall(struct msm_dp *dp_display) +{ +} + #endif void __init msm_mdp_register(void);