From patchwork Tue Jun 30 08:45:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 198345 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2102C433DF for ; Tue, 30 Jun 2020 08:46:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 88E1F207F5 for ; Tue, 30 Jun 2020 08:46:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="MxuFojDd" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731701AbgF3Ip7 (ORCPT ); Tue, 30 Jun 2020 04:45:59 -0400 Received: from m43-7.mailgun.net ([69.72.43.7]:38813 "EHLO m43-7.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731685AbgF3Ip5 (ORCPT ); Tue, 30 Jun 2020 04:45:57 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1593506755; h=References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=LEvEvodDhoXLHKbubKsxIozC6pAZZT8N/HoNx4Mmacg=; b=MxuFojDdbfSFvRGDiLj+fZoZ7Z8QkI87UB3tdPPBU4P22D8zCnqbRa56RgPRTBmMnkQ2lGHy lFM4BEMMMW2t2yOrCbRTEIgOx+yvXzOmmxWQbhNd+mU1M0CCN+7GT19idOMq1DhYadES6+Rp nJ1mW06T+ZLjMnmkN95CLgMVwng= X-Mailgun-Sending-Ip: 69.72.43.7 X-Mailgun-Sid: WyI1YmJiNiIsICJkZXZpY2V0cmVlQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n08.prod.us-east-1.postgun.com with SMTP id 5efafbb286de6ccd44db7598 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Tue, 30 Jun 2020 08:45:38 GMT Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 76C23C433CB; Tue, 30 Jun 2020 08:45:37 +0000 (UTC) Received: from blr-ubuntu-173.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: rnayak) by smtp.codeaurora.org (Postfix) with ESMTPSA id C6699C433C8; Tue, 30 Jun 2020 08:45:34 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org C6699C433C8 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=rnayak@codeaurora.org From: Rajendra Nayak To: agross@kernel.org, bjorn.andersson@linaro.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mka@chromium.org, Rajendra Nayak Subject: [PATCH 2/4] arm64: dts: sc7180: Add OPP table for all qup devices Date: Tue, 30 Jun 2020 14:15:10 +0530 Message-Id: <1593506712-24557-3-git-send-email-rnayak@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1593506712-24557-1-git-send-email-rnayak@codeaurora.org> References: <1593506712-24557-1-git-send-email-rnayak@codeaurora.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org qup has a requirement to vote on the performance state of the CX domain in sc7180 devices. Add OPP tables for these and also add power-domains property for all qup instances for uart and spi. i2c does not support scaling and uses a fixed clock. Signed-off-by: Rajendra Nayak --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 59 ++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index ad57df2..78fef54 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -537,6 +537,25 @@ status = "disabled"; }; + qup_opp_table: qup-opp-table { + compatible = "operating-points-v2"; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-128000000 { + opp-hz = /bits/ 64 <128000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + qupv3_id_0: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; reg = <0 0x008c0000 0 0x6000>; @@ -579,6 +598,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SC7180_CX>; + operating-points-v2 = <&qup_opp_table>; interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>; interconnect-names = "qup-core", "qup-config"; @@ -593,6 +614,8 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart0_default>; interrupts = ; + power-domains = <&rpmhpd SC7180_CX>; + operating-points-v2 = <&qup_opp_table>; interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>; interconnect-names = "qup-core", "qup-config"; @@ -627,6 +650,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SC7180_CX>; + operating-points-v2 = <&qup_opp_table>; interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>; interconnect-names = "qup-core", "qup-config"; @@ -641,6 +666,8 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart1_default>; interrupts = ; + power-domains = <&rpmhpd SC7180_CX>; + operating-points-v2 = <&qup_opp_table>; interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>; interconnect-names = "qup-core", "qup-config"; @@ -673,6 +700,8 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart2_default>; interrupts = ; + power-domains = <&rpmhpd SC7180_CX>; + operating-points-v2 = <&qup_opp_table>; interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>; interconnect-names = "qup-core", "qup-config"; @@ -707,6 +736,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SC7180_CX>; + operating-points-v2 = <&qup_opp_table>; interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>; interconnect-names = "qup-core", "qup-config"; @@ -721,6 +752,8 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart3_default>; interrupts = ; + power-domains = <&rpmhpd SC7180_CX>; + operating-points-v2 = <&qup_opp_table>; interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>; interconnect-names = "qup-core", "qup-config"; @@ -753,6 +786,8 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart4_default>; interrupts = ; + power-domains = <&rpmhpd SC7180_CX>; + operating-points-v2 = <&qup_opp_table>; interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>; interconnect-names = "qup-core", "qup-config"; @@ -787,6 +822,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SC7180_CX>; + operating-points-v2 = <&qup_opp_table>; interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>; interconnect-names = "qup-core", "qup-config"; @@ -801,6 +838,8 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart5_default>; interrupts = ; + power-domains = <&rpmhpd SC7180_CX>; + operating-points-v2 = <&qup_opp_table>; interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>; interconnect-names = "qup-core", "qup-config"; @@ -850,6 +889,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SC7180_CX>; + operating-points-v2 = <&qup_opp_table>; interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>; interconnect-names = "qup-core", "qup-config"; @@ -864,6 +905,8 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart6_default>; interrupts = ; + power-domains = <&rpmhpd SC7180_CX>; + operating-points-v2 = <&qup_opp_table>; interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>; interconnect-names = "qup-core", "qup-config"; @@ -896,6 +939,8 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart7_default>; interrupts = ; + power-domains = <&rpmhpd SC7180_CX>; + operating-points-v2 = <&qup_opp_table>; interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>; interconnect-names = "qup-core", "qup-config"; @@ -930,6 +975,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SC7180_CX>; + operating-points-v2 = <&qup_opp_table>; interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>; interconnect-names = "qup-core", "qup-config"; @@ -944,6 +991,8 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart8_default>; interrupts = ; + power-domains = <&rpmhpd SC7180_CX>; + operating-points-v2 = <&qup_opp_table>; interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>; interconnect-names = "qup-core", "qup-config"; @@ -976,6 +1025,8 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart9_default>; interrupts = ; + power-domains = <&rpmhpd SC7180_CX>; + operating-points-v2 = <&qup_opp_table>; interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>; interconnect-names = "qup-core", "qup-config"; @@ -1010,6 +1061,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SC7180_CX>; + operating-points-v2 = <&qup_opp_table>; interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>; interconnect-names = "qup-core", "qup-config"; @@ -1024,6 +1077,8 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart10_default>; interrupts = ; + power-domains = <&rpmhpd SC7180_CX>; + operating-points-v2 = <&qup_opp_table>; interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>; interconnect-names = "qup-core", "qup-config"; @@ -1058,6 +1113,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + power-domains = <&rpmhpd SC7180_CX>; + operating-points-v2 = <&qup_opp_table>; interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>; interconnect-names = "qup-core", "qup-config"; @@ -1072,6 +1129,8 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart11_default>; interrupts = ; + power-domains = <&rpmhpd SC7180_CX>; + operating-points-v2 = <&qup_opp_table>; interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>; interconnect-names = "qup-core", "qup-config"; From patchwork Tue Jun 30 08:45:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 198346 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4D070C433E0 for ; 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Tue, 30 Jun 2020 08:45:40 GMT Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 13600C433CB; Tue, 30 Jun 2020 08:45:40 +0000 (UTC) Received: from blr-ubuntu-173.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: rnayak) by smtp.codeaurora.org (Postfix) with ESMTPSA id 71AA4C433CA; Tue, 30 Jun 2020 08:45:37 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 71AA4C433CA Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=rnayak@codeaurora.org From: Rajendra Nayak To: agross@kernel.org, bjorn.andersson@linaro.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mka@chromium.org, Rajendra Nayak Subject: [PATCH 3/4] arm64: dts: sdm845: Add sdhc opps and power-domains Date: Tue, 30 Jun 2020 14:15:11 +0530 Message-Id: <1593506712-24557-4-git-send-email-rnayak@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1593506712-24557-1-git-send-email-rnayak@codeaurora.org> References: <1593506712-24557-1-git-send-email-rnayak@codeaurora.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the power domain supporting performance state and the corresponding OPP tables for the sdhc device on sdm845. Signed-off-by: Rajendra Nayak --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index db1f82b..67fc87b 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2994,8 +2994,34 @@ <&gcc GCC_SDCC2_APPS_CLK>; clock-names = "iface", "core"; iommus = <&apps_smmu 0xa0 0xf>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&sdhc2_opp_table>; status = "disabled"; + + sdhc2_opp_table: sdhc2-opp-table { + compatible = "operating-points-v2"; + + opp-9600000 { + opp-hz = /bits/ 64 <9600000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-201500000 { + opp-hz = /bits/ 64 <201500000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; }; qspi: spi@88df000 {