From patchwork Sun Jun 21 21:34:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Gupta X-Patchwork-Id: 198729 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34768C433E0 for ; Sun, 21 Jun 2020 21:35:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 110002529D for ; Sun, 21 Jun 2020 21:35:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="R83+V+nL" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730773AbgFUVew (ORCPT ); Sun, 21 Jun 2020 17:34:52 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:8729 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728928AbgFUVev (ORCPT ); Sun, 21 Jun 2020 17:34:51 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Sun, 21 Jun 2020 14:34:38 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Sun, 21 Jun 2020 14:34:51 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Sun, 21 Jun 2020 14:34:51 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sun, 21 Jun 2020 21:34:47 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Sun, 21 Jun 2020 21:34:46 +0000 Received: from sumitg-l4t.nvidia.com (Not Verified[10.24.37.103]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sun, 21 Jun 2020 14:34:46 -0700 From: Sumit Gupta To: , , , , , , , , , , , , CC: , , Subject: [TEGRA194_CPUFREQ Patch v3 1/4] dt-bindings: arm: Add t194 ccplex compatible and bpmp property Date: Mon, 22 Jun 2020 03:04:31 +0530 Message-ID: <1592775274-27513-2-git-send-email-sumitg@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1592775274-27513-1-git-send-email-sumitg@nvidia.com> References: <1592775274-27513-1-git-send-email-sumitg@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1592775278; bh=GFfWIGaXrMvp1DkevXPif529sLhgwm+yOrbKbLziXEQ=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=R83+V+nLFEij8+xT/ZWbBiEktc1LnX/dcasmxo8B0Ww8U9+z2nO3uWqLt/jgDvAU+ B4ueYGfhZdmFqEJp1BTDg3aiAJz591M61cAcpuS+ye7OPfAyrWsUSy7c2newobZ3y1 k5Wo1b8k6cG2ipQS+UXbNGDe5IFqK9c8U6xAkgvJhLJJ6eQvQoszhbfm+vo8a4G5Vd jABIG14QID9C4SfHn6wALN65gQjDkttIfQ8e3sQx8ZwvK+G12ZvqYYzz3Dsyt/EpAS vIYkXCgsgoKfe/Gr2V7wtS5By2cDg/L2CL+D1SZyFFI1+l8PhqCVyj7eIzu6rZuAfm EqAaAFuxi+AHw== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org To do frequency scaling on all CPUs within T194 CPU Complex, we need to query BPMP for data on valid operating points. Document a compatible string under 'cpus' node to represent the CPU Complex for binding drivers like cpufreq which don't have their node or CPU Complex node to bind to. Also, document a property to point to the BPMP device that can be queried for all CPUs. Signed-off-by: Sumit Gupta --- Documentation/devicetree/bindings/arm/cpus.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index a018147..737b55e 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -162,6 +162,7 @@ properties: - nvidia,tegra132-denver - nvidia,tegra186-denver - nvidia,tegra194-carmel + - nvidia,tegra194-ccplex - qcom,krait - qcom,kryo - qcom,kryo260 @@ -255,6 +256,14 @@ properties: where voltage is in V, frequency is in MHz. + nvidia,bpmp: + $ref: '/schemas/types.yaml#/definitions/phandle' + descrption: | + Specifies the bpmp node that needs to be queried to get + operating point data for all CPUs. + + Optional for NVIDIA Tegra194 Carmel CPUs + power-domains: $ref: '/schemas/types.yaml#/definitions/phandle-array' description: From patchwork Sun Jun 21 21:34:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Gupta X-Patchwork-Id: 198728 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02D02C433DF for ; Sun, 21 Jun 2020 21:35:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D56DA252AB for ; Sun, 21 Jun 2020 21:35:07 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="ROO+TbXj" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730806AbgFUVfH (ORCPT ); Sun, 21 Jun 2020 17:35:07 -0400 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:13112 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728928AbgFUVfG (ORCPT ); Sun, 21 Jun 2020 17:35:06 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Sun, 21 Jun 2020 14:33:36 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Sun, 21 Jun 2020 14:35:06 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Sun, 21 Jun 2020 14:35:06 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sun, 21 Jun 2020 21:35:04 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Sun, 21 Jun 2020 21:35:04 +0000 Received: from sumitg-l4t.nvidia.com (Not Verified[10.24.37.103]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sun, 21 Jun 2020 14:35:03 -0700 From: Sumit Gupta To: , , , , , , , , , , , , CC: , , Subject: [TEGRA194_CPUFREQ Patch v3 4/4] arm64: defconfig: Enable CONFIG_ARM_TEGRA194_CPUFREQ Date: Mon, 22 Jun 2020 03:04:34 +0530 Message-ID: <1592775274-27513-5-git-send-email-sumitg@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1592775274-27513-1-git-send-email-sumitg@nvidia.com> References: <1592775274-27513-1-git-send-email-sumitg@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1592775216; bh=lHNVU7VOn42qEJNEwY78N3Q41Uu/bIGWrHx8p5IG6bc=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=ROO+TbXj5NyrxbBYBz04uSud2CCbMrxOFnH+ff6/UnV0wds2XWnFVC/z88XHZwPGx fwjdTMTLcoFwB8WaxjjRhMLGaa9IDw0TibMP68QzqjZ0CP+l2o5Z+4BLbqHgvxsWce fIZJnq2sRLK1GBudQ+LkZUtXJCvnft2nSBN3FKCrSQF+tyUrVgRHrnycKnzue6kJVd mJ+R9VUIzF45LKhBTA4XFqLD9r/pKpUZ2ORwfwm/+rhyvac4reLxRpmNc4t+7h1pY4 6ZvY+zAomPky48squ+UINIV+GMCXsN6NAUosHN3Rd2OzDsIFW5k+D517KXRipHtJYR vDZaeklKc7eug== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Enable Tegra194 CPU frequency scaling support by default. Signed-off-by: Sumit Gupta --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index f9d378d..385bd35 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -91,6 +91,7 @@ CONFIG_ARM_QCOM_CPUFREQ_NVMEM=y CONFIG_ARM_QCOM_CPUFREQ_HW=y CONFIG_ARM_RASPBERRYPI_CPUFREQ=m CONFIG_ARM_TEGRA186_CPUFREQ=y +CONFIG_ARM_TEGRA194_CPUFREQ=y CONFIG_QORIQ_CPUFREQ=y CONFIG_ARM_SCPI_PROTOCOL=y CONFIG_RASPBERRYPI_FIRMWARE=y