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X-Received-From: 2a00:1450:400c:c0c::22f Subject: [Qemu-devel] [RFC PATCH 1/9] tcg/README: listify the TCG types. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Although the other types are aliases lets make it clear what TCG types are available. Signed-off-by: Alex Bennée --- tcg/README | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) -- 2.13.0 Reviewed-by: Richard Henderson diff --git a/tcg/README b/tcg/README index 03bfb6acd4..f116b7b694 100644 --- a/tcg/README +++ b/tcg/README @@ -53,9 +53,12 @@ an "undefined result". TCG instructions operate on variables which are temporaries, local temporaries or globals. TCG instructions and variables are strongly -typed. Two types are supported: 32 bit integers and 64 bit -integers. Pointers are defined as an alias to 32 bit or 64 bit -integers depending on the TCG target word size. +typed. A number of types are supported: + + TCGv_i32 - 32 bit integer + TCGv_i64 - 64 bit integer + TCGv - target pointer (aliased to 32 or 64 bit integer) + TCGv_ptr - host pointer (used for direct access to host structures) Each instruction has a fixed number of output variable operands, input variable operands and always constant operands. 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X-Received-From: 2a00:1450:400c:c0c::235 Subject: [Qemu-devel] [RFC PATCH 2/9] tcg: introduce the concepts of a TCGv_vec register type X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Currently it only makes sense for globals - i.e. registers directly mapped to CPUEnv. --- tcg/README | 1 + tcg/tcg.h | 20 ++++++++++++++++++++ 2 files changed, 21 insertions(+) -- 2.13.0 diff --git a/tcg/README b/tcg/README index f116b7b694..e0868d95b4 100644 --- a/tcg/README +++ b/tcg/README @@ -57,6 +57,7 @@ typed. A number of types are supported: TCGv_i32 - 32 bit integer TCGv_i64 - 64 bit integer + TCGv_vec - an arbitrary sized vector register TCGv - target pointer (aliased to 32 or 64 bit integer) TCGv_ptr - host pointer (used for direct access to host structures) diff --git a/tcg/tcg.h b/tcg/tcg.h index 17b7750ee6..d75636b6ab 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -256,6 +256,7 @@ typedef struct TCGPool { typedef enum TCGType { TCG_TYPE_I32, TCG_TYPE_I64, + TCG_TYPE_VECTOR, TCG_TYPE_COUNT, /* number of different types */ /* An alias for the size of the host register. */ @@ -431,6 +432,7 @@ typedef tcg_target_ulong TCGArg; typedef struct TCGv_i32_d *TCGv_i32; typedef struct TCGv_i64_d *TCGv_i64; typedef struct TCGv_ptr_d *TCGv_ptr; +typedef struct TCGv_vec_d *TCGv_vec; typedef TCGv_ptr TCGv_env; #if TARGET_LONG_BITS == 32 #define TCGv TCGv_i32 @@ -450,6 +452,11 @@ static inline TCGv_i64 QEMU_ARTIFICIAL MAKE_TCGV_I64(intptr_t i) return (TCGv_i64)i; } +static inline TCGv_vec QEMU_ARTIFICIAL MAKE_TCGV_VEC(intptr_t i) +{ + return (TCGv_vec)i; +} + static inline TCGv_ptr QEMU_ARTIFICIAL MAKE_TCGV_PTR(intptr_t i) { return (TCGv_ptr)i; @@ -465,6 +472,11 @@ static inline intptr_t QEMU_ARTIFICIAL GET_TCGV_I64(TCGv_i64 t) return (intptr_t)t; } +static inline intptr_t QEMU_ARTIFICIAL GET_TCGV_VEC(TCGv_vec t) +{ + return (intptr_t)t; +} + static inline intptr_t QEMU_ARTIFICIAL GET_TCGV_PTR(TCGv_ptr t) { return (intptr_t)t; @@ -788,6 +800,7 @@ int tcg_global_mem_new_internal(TCGType, TCGv_ptr, intptr_t, const char *); TCGv_i32 tcg_global_reg_new_i32(TCGReg reg, const char *name); TCGv_i64 tcg_global_reg_new_i64(TCGReg reg, const char *name); +TCGv_vec tcg_global_reg_new_vec(TCGReg reg, const char *name); TCGv_i32 tcg_temp_new_internal_i32(int temp_local); TCGv_i64 tcg_temp_new_internal_i64(int temp_local); @@ -829,6 +842,13 @@ static inline TCGv_i64 tcg_temp_local_new_i64(void) return tcg_temp_new_internal_i64(1); } +static inline TCGv_vec tcg_global_mem_new_vec(TCGv_ptr reg, intptr_t offset, + const char *name) +{ + int idx = tcg_global_mem_new_internal(TCG_TYPE_VECTOR, reg, offset, name); + return MAKE_TCGV_VEC(idx); +} + #if defined(CONFIG_DEBUG_TCG) /* If you call tcg_clear_temp_count() at the start of a section of * code which is not supposed to leak any TCG temporaries, then From patchwork Thu Aug 17 18:03:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 110337 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp2524751qge; Thu, 17 Aug 2017 11:09:46 -0700 (PDT) X-Received: by 10.55.108.3 with SMTP id h3mr8073718qkc.17.1502993386594; Thu, 17 Aug 2017 11:09:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1502993386; cv=none; d=google.com; s=arc-20160816; b=VIc49tVB5Sn9JxCpd2uWzYBT2Za/1mNYP8zAFBeySPz4j1D/IXFw/jP/QkS+J1KNyk 8lEaPdrPOSxstqQlii0YMZzIy5YhjULQGYXVC6fKcen+PQpIJKiU424YSlrrdJlGvQcN 0cOTNAZtlYQeuNvxXP7uttmTB+27o1ADC+X/gx7q1mWe8VcKXsYuw1pcmSzyeblpiy4L nzdOHwtXUYbxArif21k9sYnB5NS62derAt0Aou/if7rFo9r4tFHa7ye/pBdtn6JPkYr8 h4V0RKPmQW6Tf40vITXUIlqvN7bxoYT1x3qx6fgBuYwhRxrXxHA40wLyxItuLTwddSeD xNUw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=MB+PXXB6umsS0QP7qT6V2jBQgssQbx5IiHKDlGxcoXY=; b=wIkbf1z/msSbvqisWjsXqUkpoidTMsDD+aM0hpUVn2L/UQHHvyq0wABOz8fMj9pvrD 0dZfY+2XHgIvXXbexKPx+MY1DeYWem4vhCfhcIS55ldbo6KOlrBV8Z587ZHlVjsZS6jf 0Lrw/51X4zNvnAm6HZ6ThHcPy6S0ZkTIN22UClmsM+qh3MKwsVJFYP50/uITSi3cXGOk sdn+WXOuDKAV/JUz7JpB7sX7rKzwVh5ERQc7UASF+lk9n1sbl4hOgvHJo5MJ+oxXn9kU PO44QRHP5mBdz0P7YA6bSb2v0zrTpqmypOmfeTn2/f8n+9hdSDHvpplMlyQxk7V5L/sD oDww== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=U56+y9+x; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c0c::22e Subject: [Qemu-devel] [RFC PATCH 3/9] tcg: generate ptrs to vector registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" As we operate directly on the vectors in memory we pass around the address for TCG_TYPE_VECTOR. Currently only helpers ever see these values but if we were to generate simd backend instructions they would load directly from the backing store. We also need to ensure when copying from one temp register to the other the right size is used. Signed-off-by: Alex Bennée --- tcg/tcg.c | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) -- 2.13.0 diff --git a/tcg/tcg.c b/tcg/tcg.c index 35598296c5..e16811d68d 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -2034,7 +2034,21 @@ static void temp_load(TCGContext *s, TCGTemp *ts, TCGRegSet desired_regs, break; case TEMP_VAL_MEM: reg = tcg_reg_alloc(s, desired_regs, allocated_regs, ts->indirect_base); - tcg_out_ld(s, ts->type, reg, ts->mem_base->reg, ts->mem_offset); + if (ts->type == TCG_TYPE_VECTOR) { + /* Vector registers are ptr's to the memory representation */ + TCGArg args[TCG_MAX_OP_ARGS]; + int const_args[TCG_MAX_OP_ARGS]; + args[0] = reg; + args[1] = ts->mem_base->reg; + args[2] = ts->mem_offset; + const_args[0] = 0; + const_args[1] = 0; + const_args[2] = 1; + /* FIXME: needs to by host_ptr centric */ + tcg_out_op(s, INDEX_op_add_i64, args, const_args); + } else { + tcg_out_ld(s, ts->type, reg, ts->mem_base->reg, ts->mem_offset); + } ts->mem_coherent = 1; break; case TEMP_VAL_DEAD: @@ -2196,6 +2210,10 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOpDef *def, ots->reg = tcg_reg_alloc(s, tcg_target_available_regs[otype], allocated_regs, ots->indirect_base); } + /* For the purposes of moving stuff about it is a host ptr */ + if (otype == TCG_TYPE_VECTOR) { + otype = TCG_TYPE_PTR; + } tcg_out_mov(s, otype, ots->reg, ts->reg); } ots->val_type = TEMP_VAL_REG; @@ -2440,7 +2458,11 @@ static void tcg_reg_alloc_call(TCGContext *s, int nb_oargs, int nb_iargs, if (ts->val_type == TEMP_VAL_REG) { if (ts->reg != reg) { - tcg_out_mov(s, ts->type, reg, ts->reg); + if (ts->type == TCG_TYPE_VECTOR) { + tcg_out_mov(s, TCG_TYPE_PTR, reg, ts->reg); + } else { + tcg_out_mov(s, ts->type, reg, ts->reg); + } } } else { TCGRegSet arg_set; From patchwork Thu Aug 17 18:03:59 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 110334 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp2521253qge; Thu, 17 Aug 2017 11:06:49 -0700 (PDT) X-Received: by 10.55.33.28 with SMTP id h28mr7874019qkh.281.1502993209427; Thu, 17 Aug 2017 11:06:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1502993209; cv=none; d=google.com; s=arc-20160816; b=NslijasomZNhJDd0v/u3hWyrGD9Dccgl64vLMyoiFPw+qg/pwomkLjNk9Q29kjXqcC Xc8/H9Ix+lbAARcGPde8dZkCpJ6JVy6XfLsof2Umnb5G0hOWAVSToVusYV+5b0ShrH0O lBedfc1ul0lZDMrx8WR1JzToAna4xJSelf4O5BSjOIttVUwAcm8RLIZnHULVpmER2dsP uXvVaeqk0JsfyIzcoeKX2g9gBYmRXC9prdgUldGy/zLO9BHdEYdwLH2ei4GECFEP25/g taiS9DbA7B8hHV7kHCaokah2gfsHD432ys2Z724mHxx5PcmvWESRQ4JSQMeuA0SLs6hO 8YRA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=w838pJBKi9FO1w7BOjy9IbZ2bNjPtkChS6A9ODn8p/8=; b=LKAfKElRYeZE0nA45735epIM4Pxb+EqaRs7DhPQVhcS/+4V0s/ngqgjrKnVQyjZuoD uHtvpM9LYkwdqK/wrUjhzjrj21H69Obe4Uk7y9/e9+XURFK8sDr1TzQZSyM1Yx9Xz/oN srAbfxU+cdIc0suZjG4692I7KdtMQbntUzlDLf4XyRYoSnKd0i1KAedjAbpfQYM1M2uP E3aVBKh8Q4hHSatBkcLkur0mJkxEaLR4I1+pTZnd3Z+0GH42C7snvF+hSDt785pbGQAg of7WDDYxUq7vKp94lX8psYVpwX1vb06NyWv2N1Bmr9UAkI8XYAhVUYTOkOkciWMc0fFQ RMDQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=QXmhNw6j; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c0c::233 Subject: [Qemu-devel] [RFC PATCH 4/9] helper-head: add support for vec type X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , qemu-arm@nongnu.org, =?utf-8?q?Al?= =?utf-8?q?ex_Benn=C3=A9e?= , qemu-devel@nongnu.org, Peter Crosthwaite Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" --- include/exec/helper-head.h | 5 +++++ 1 file changed, 5 insertions(+) -- 2.13.0 diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h index 1cfc43b9ff..3fb4c3fc39 100644 --- a/include/exec/helper-head.h +++ b/include/exec/helper-head.h @@ -23,6 +23,7 @@ #define GET_TCGV_i32 GET_TCGV_I32 #define GET_TCGV_i64 GET_TCGV_I64 #define GET_TCGV_ptr GET_TCGV_PTR +#define GET_TCGV_vec GET_TCGV_VEC /* Some types that make sense in C, but not for TCG. */ #define dh_alias_i32 i32 @@ -33,6 +34,7 @@ #define dh_alias_f32 i32 #define dh_alias_f64 i64 #define dh_alias_ptr ptr +#define dh_alias_vec vec #define dh_alias_void void #define dh_alias_noreturn noreturn #define dh_alias(t) glue(dh_alias_, t) @@ -45,6 +47,7 @@ #define dh_ctype_f32 float32 #define dh_ctype_f64 float64 #define dh_ctype_ptr void * +#define dh_ctype_vec void * #define dh_ctype_void void #define dh_ctype_noreturn void QEMU_NORETURN #define dh_ctype(t) dh_ctype_##t @@ -90,6 +93,7 @@ #define dh_is_64bit_i32 0 #define dh_is_64bit_i64 1 #define dh_is_64bit_ptr (sizeof(void *) == 8) +#define dh_is_64bit_vec (sizeof(void *) == 8) #define dh_is_64bit(t) glue(dh_is_64bit_, dh_alias(t)) #define dh_is_signed_void 0 @@ -106,6 +110,7 @@ extension instructions that may be required, e.g. ia64's addp4. But for now we don't support any 64-bit targets with 32-bit pointers. */ #define dh_is_signed_ptr 0 +#define dh_is_signed_vec dh_is_signed_ptr #define dh_is_signed_env dh_is_signed_ptr #define dh_is_signed(t) dh_is_signed_##t From patchwork Thu Aug 17 18:04:00 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 110335 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp2523018qge; Thu, 17 Aug 2017 11:08:14 -0700 (PDT) X-Received: by 10.55.59.193 with SMTP id i184mr7945199qka.214.1502993294545; Thu, 17 Aug 2017 11:08:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1502993294; cv=none; d=google.com; s=arc-20160816; b=m6HHNQ6Twg/8ISbz4yUl1i1bzeuq168fCkHQqsYAjHZKzmfOgIml3iRyd7MWHL0O9b kURDbVUyehIcpzzrbATmn970H/blVQWeZcnlJZvB5tQBinqcZQ/oPjHpOJlYYczsGGtx jvLz6lKLf/U5PxLmHan71+ZXsKdOKC8H+JojgHwmPIZomBD4ZO1gKMntOKWLuA1elWr6 j72zkMObnumabV9c+oCPzKBJY2782qw5QTVTUcMwJZn8ME10bVbH4wgLBssDA8zH0ArS yEkml93dWlDF9H1X5Jp3rBuqmR8MuJXm9vMYAMXRUbHuye6cukiHOlbjqVvRYhPGGgyl 31IA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=GgVZo7p5mIkOZRxHVwEM7z1GJnFzidDYAWt+rKTnK7Y=; b=p5whLbUFBYvVlUgqK4T2vJ0BSHGReEIeIrfWTH8o6k3j0F6qbjATPfDGnR7fw+NqI1 qIzEFJqUZZmfmMZrVrH38kwIzJa6N/AseEuHlAvSRAuQuTgJfifndgUCPrfZxiPwJcIp CNZA6LQrxz72ufXVx5eoYS9SBgrl12z6bK0Gmq0/t+FzMjIoQIvpihNhyIRdNGyp3QyX uCu6xCH5uMjNHH1krXN0BOfjWjWUZlLyoqcnUOh1bYvnMF2XSP0+bXwiuQ55ifZ2vZtG LNZomaOZAlHRa1TZfYFPrGg0+Q5uY6Ndt7G26D38eVMtz+HILe3Bpp1K/IAbeaffPwaj qMqg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=V/mCCcbo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c0c::230 Subject: [Qemu-devel] [RFC PATCH 5/9] arm/cpu.h: align VFP registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alex Bennée --- target/arm/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.13.0 Reviewed-by: Richard Henderson diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b39d64aa0b..cdd47cb868 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -457,8 +457,8 @@ typedef struct CPUARMState { * the two execution states, and means we do not need to explicitly * map these registers when changing states. */ - float64 regs[64]; - + float64 regs[64] __attribute__((aligned(16))); + /* VFP system registers */ uint32_t xregs[16]; /* We store these fpcsr fields separately for convenience. */ int vec_len; From patchwork Thu Aug 17 18:04:01 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 110340 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp2528622qge; Thu, 17 Aug 2017 11:13:12 -0700 (PDT) X-Received: by 10.55.33.28 with SMTP id h28mr7901255qkh.281.1502993592523; Thu, 17 Aug 2017 11:13:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1502993592; cv=none; d=google.com; s=arc-20160816; b=jwiBt8MlgT/zdptlODw1TjKPch/8bNd9yYchhYgX46OUo/Sj0FgQcCf0GecRCbEV9s G4DOabi60qWcDidmRE/Ftc4nCgXR/8o3jR9N1F1M02bWT2zcvEwc5dpncaK+yFixSeZ4 +4QGZ8TccdHVgFFOo9JuUM1LZbckVM5x3xbHNdW+yaRx1KuEypACkCatG8TfpfHb6ton E6Je0x6a3t8u0D73qiwYGj0Th19oGA8L9ewHjriy2QmGzL4Wb60GRqq3i4M8QhIxcN5J 02Ww85AdNCqGI2J0G/sXSODn+Xy8xznteyIEPFwVNwbnQ5/+K7zMIJ++kJh9wFvM0S07 oRnA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=ieNsD6GEr3OWd7Ih++yjO7tL6HCDLmZ0Skj6lrfUXPw=; b=hzW9KoX98S0kS/q0NWaHbS/98HiS6+TdDeeylqe1oRPeEy3ycvZjhJBg0zo6s9DzE5 FZCj1BcAaNNaIaGNSQWRP6I0Kv5AC14RxLyJxXn7iBQkrqb8EcNeziaYXb/L5r0OjtiQ 3kf89NVm0WVgH4jg8d0wiJunfkJx9LirUrYuEeVt8itlYjrqITAtN0qePdIt+b7t0qYy YmuYOJWG0Ja9c7nuQAQgsOxExcbs6qmwJ/AqEBo4z3+UpKe6Q30uBdP3mDTYaQc7mAxx DAKwpOOlDhf93cB9APLSypka1+aUcP2f7Jp31Ks8PLvQNeNL+aFT3kJ/fQuDyx7utpzk ZoBQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=kdrXeD2W; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id k2si344636qta.131.2017.08.17.11.13.12 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 17 Aug 2017 11:13:12 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=kdrXeD2W; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:38679 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1diPI6-0002hl-9k for patch@linaro.org; Thu, 17 Aug 2017 14:13:10 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37561) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1diP9W-00047u-6F for qemu-devel@nongnu.org; Thu, 17 Aug 2017 14:04:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1diP9R-0005Ja-98 for qemu-devel@nongnu.org; Thu, 17 Aug 2017 14:04:18 -0400 Received: from mail-wr0-x232.google.com ([2a00:1450:400c:c0c::232]:36418) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1diP9R-0005J7-3p for qemu-devel@nongnu.org; Thu, 17 Aug 2017 14:04:13 -0400 Received: by mail-wr0-x232.google.com with SMTP id f8so6194330wrf.3 for ; Thu, 17 Aug 2017 11:04:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ieNsD6GEr3OWd7Ih++yjO7tL6HCDLmZ0Skj6lrfUXPw=; b=kdrXeD2WrZ+Jn95vSs7jaewrO3cd02UwYpETFJ2Mz3YglwTT4sCTAa6hb+fpjojt3R ZpAX2LjglYrZKZ22V8b9t8Y11eIannqgqXMj0lYOxwQOOoX6GhO++TCDFw/UBLDl6Fqh FJ5RMW6mSept+W1/UHBUE7y4idpQAeMzy50Sg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ieNsD6GEr3OWd7Ih++yjO7tL6HCDLmZ0Skj6lrfUXPw=; b=cYk4nXhbS3S9iMHuMvyQ++3q7MQU95uqxQfHFHuBoY6PSmxboEepZF7aqk5zr06MxL hy4pCho8jId6zga0tZV2k4/7tRSjR5/3DQ414c7/HZbKAvT6HX21I7xgZHwmI6wZ1M+o 9YYCD+B0L711bWH4uYE3mA2iweTEIKh8nOsqHxCGXrWVYiR+4YUyefb0jnaDr+Um06uu PbxUSXQ4ox/IiUuguCsbArWZzXrHo6/8rNLufjpISXwDKyYLWRoJja2bj6dDYTRUAf7c wKaC+JlbaIsuV0yL4EVPADEWRts+qguTB1qSkwsEbFDemlwQ9gBbipFYBxkhTUk8icww mkpA== X-Gm-Message-State: AHYfb5jBCOPI8cy0qE6QCuWj+7C9f7aXif1jTygHEeHKK+Us8dX2dkaY fSaEOQ+jbJBtQ7Jtj9gcfw== X-Received: by 10.223.170.2 with SMTP id p2mr4296928wrd.22.1502993052079; Thu, 17 Aug 2017 11:04:12 -0700 (PDT) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id z9sm5090096wrz.0.2017.08.17.11.04.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 17 Aug 2017 11:04:10 -0700 (PDT) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id E70AD3E1337; Thu, 17 Aug 2017 19:04:04 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: rth@twiddle.net, cota@braap.org, batuzovk@ispras.ru Date: Thu, 17 Aug 2017 19:04:01 +0100 Message-Id: <20170817180404.29334-7-alex.bennee@linaro.org> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20170817180404.29334-1-alex.bennee@linaro.org> References: <20170817180404.29334-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::232 Subject: [Qemu-devel] [RFC PATCH 6/9] target/arm/translate-a64: regnames -> x_regnames X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These are the integer registers as will become clear when we start declaring the vector ones. Signed-off-by: Alex Bennée --- target/arm/translate-a64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.13.0 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 2200e25be0..805af51900 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -43,7 +43,7 @@ static TCGv_i64 cpu_pc; static TCGv_i64 cpu_exclusive_high; static TCGv_i64 cpu_reg(DisasContext *s, int reg); -static const char *regnames[] = { +static const char *x_regnames[] = { "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", From patchwork Thu Aug 17 18:04:02 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 110332 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp2518884qge; Thu, 17 Aug 2017 11:04:58 -0700 (PDT) X-Received: by 10.55.67.136 with SMTP id q130mr8157344qka.185.1502993098872; Thu, 17 Aug 2017 11:04:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1502993098; cv=none; d=google.com; s=arc-20160816; b=PmG6ZNIpZ72Ec1+DTrA7KJMI5eNloKaFZCGgodPTDIYUZyFhImJ1kO8yWS7iq3MXuH ZNX63YFe312Vtlp6KxA73VKW656naiFe7p4ANFbdr2arTPG0Un8/V32yL2tuP2V/WGkl rN2UzK+XRWdpx28PEoFWSV2TffrJpkTc5REMyvCz2aiMFxUXDxZj/y8jH/oj6A9DeCYF 0SOtdPm58H+H4eRpnunjA4My4HF1iGez46tF7gPULfrTjnCb5zPOCMr17Ud3efth8/gz mrWn//68A5wcl0yiYCuQuwVl0tX/Rs0bQ1EzILikFYogHh39cMTafTTV5fpG7LsQElro z4rQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=qBqCHRzziGBTUuTJ+hFC9PK4+Y6PwFoHW4T6DhMi7Ss=; b=DNKbCGKghGaJpct52VB6EznKDcT3wR8/QNfAVkqAXF8eyVmq7Pg6KjTvkm6DmHGGgC Rc1lnJJwIke9yR8epB8hzscJDMjbBh/KYmkG9zotYSiM+hdcG06BDJ5WGt09nYeWq53y mEWLPcUvTme7b7fh/ZuSepVbPtXa4AzLluHyLo4sUgNyk02EjDfAf79L25pWc6BWc5Xr FAaTCMvfGbc5wcR76j8Js2bhBSe62uKLVxRyXFgDgQu4B2v7hX5GSh8mrn4+Kemrog9E OzZhZr/zaK0ElChGoIecSIRKjS/hT8RDKPv+aA02SuR25Vlp/eGbz5oN/GP+xgTELoDF dgCw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=iQWKJmPd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c0c::229 Subject: [Qemu-devel] [RFC PATCH 7/9] target/arm/translate-a64: register global vectors X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Register the vector registers with TCG. Signed-off-by: Alex Bennée --- target/arm/translate-a64.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) -- 2.13.0 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 805af51900..b5f48605a7 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -36,8 +36,10 @@ #include "trace-tcg.h" +/* Global registers */ static TCGv_i64 cpu_X[32]; static TCGv_i64 cpu_pc; +static TCGv_vec cpu_V[32]; /* Load/store exclusive handling */ static TCGv_i64 cpu_exclusive_high; @@ -50,6 +52,13 @@ static const char *x_regnames[] = { "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp" }; +static const char *v_regnames[] = { + "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", + "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", + "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", + "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" +}; + enum a64_shift_type { A64_SHIFT_TYPE_LSL = 0, A64_SHIFT_TYPE_LSR = 1, @@ -91,10 +100,18 @@ void a64_translate_init(void) cpu_pc = tcg_global_mem_new_i64(cpu_env, offsetof(CPUARMState, pc), "pc"); - for (i = 0; i < 32; i++) { + + for (i = 0; i < ARRAY_SIZE(cpu_X); i++) { cpu_X[i] = tcg_global_mem_new_i64(cpu_env, offsetof(CPUARMState, xregs[i]), - regnames[i]); + x_regnames[i]); + } + + for (i = 0; i < ARRAY_SIZE(cpu_V); i++) { + cpu_V[i] = tcg_global_mem_new_vec(cpu_env, + offsetof(CPUARMState, + vfp.regs[i * 2]), + v_regnames[i]); } cpu_exclusive_high = tcg_global_mem_new_i64(cpu_env, From patchwork Thu Aug 17 18:04:03 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 110338 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp2527658qge; Thu, 17 Aug 2017 11:12:15 -0700 (PDT) X-Received: by 10.55.115.69 with SMTP id o66mr8868666qkc.110.1502993535746; Thu, 17 Aug 2017 11:12:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1502993535; cv=none; d=google.com; s=arc-20160816; b=fJM0vBGANmYKWYAM0uvFgosNJB3c3bfD1At7i/LaAIy67jmoCZRMSofqtLIW43UaFg Y/q2rNbub7tXwAaJE1psuKhYNJuVlNY1G9fTs9ofuPiF80c7rSC1JWiQVC9SxbZJAgFD 0XFbCQC1DStQWFUxeQILAtrXqWi+X2LBUaSihCvh3M3L6ZOJbo6aIRzzYzCmMoJSYpcN uU88heuOqoNIW4ljCy1kUHXXxe/rG8iwB9kqj665zUvKkbzDQg3KctQ6g6zHglbOl+bW zNV7NbyRTEJ2nEauqs0Xx1hyL3qUSVjrQrjfEkLAe7KOiY6oKxTuOdMLLPInt9mDjA0c U0UA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=1OZ/Z1R6iCyFdgPfKV/7hVu1PAMlL7gRWtPozZg3jDk=; b=f0ZOR8Ob82QKDUS7wE5sIVZbUNUCDtkeO0ij8KjktpAdPz7hL4Xv/t2b372braK61T mlRgaZxFANIuxpQb4vlR2J5LMAsGeac6hRRZYA91Z5Rdm3+779gOvCebBHGG5XJXL+gm HwHJNJc+lm01JpVfn7zQwxUGm4Gm2UoggguVk9XsUpw338l89M046Qhd4HACzySRqO7U T9jUlnCYonzKYIo4GUrYWJfPKkJHMr2Hrluclq2K6T7dwYUPF+oHSv/4+9+TQAopHzqf ogq6lZiROCge9AXOOZb5LrTAEh531s5d4+Y/+v1IteKHI9jM0NnREiYPyxiys/KL6uCf c0rw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=feTPYjQR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c0c::236 Subject: [Qemu-devel] [RFC PATCH 8/9] target/arm/helpers: introduce ADVSIMD flags X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is used to pass constant information to the helper. This includes immediate data and element counts/offsets. Signed-off-by: Alex Bennée --- target/arm/advsimd_helper_flags.h | 50 +++++++++++++++++++++++++++++++++++++++ target/arm/helper-a64.c | 1 + target/arm/translate-a64.c | 2 ++ 3 files changed, 53 insertions(+) create mode 100644 target/arm/advsimd_helper_flags.h -- 2.13.0 diff --git a/target/arm/advsimd_helper_flags.h b/target/arm/advsimd_helper_flags.h new file mode 100644 index 0000000000..47429e6fd1 --- /dev/null +++ b/target/arm/advsimd_helper_flags.h @@ -0,0 +1,50 @@ +/* + * AArch64 Vector Flags + * + * Copyright (c) 2017 Linaro + * Author: Alex Bennée + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +/* AdvSIMD element data + * + * We pack all the additional information for elements into a single + * 32 bit constant passed by register. Hopefully for groups of + * identical operations on different registers this should propergate + * nicely in the TCG. + * + * The following control element iteration: + * ADVSIMD_OPR_ELT - the count of elements affected + * ADVSIMD_ALL_ELT - the total count of elements (e.g. clear all-opr elements) + * ADVSIMD_DOFF_ELT - the offset for the destination register (e.g. foo2 ops) + * + * We encode immediate data in: + * ADVSIMD_DATA + * + * Typically this is things like shift counts and the like. + */ + +#define ADVSIMD_OPR_ELT_BITS 5 +#define ADVSIMD_OPR_ELT_SHIFT 0 +#define ADVSIMD_ALL_ELT_BITS 5 +#define ADVSIMD_ALL_ELT_SHIFT 5 +#define ADVSIMD_DOFF_ELT_BITS 5 +#define ADVSIMD_DOFF_ELT_SHIFT 10 +#define ADVSIMD_DATA_BITS 16 +#define ADVSIMD_DATA_SHIFT 16 + +#define GET_SIMD_DATA(t, d) extract32(d, \ + ADVSIMD_ ## t ## _SHIFT, \ + ADVSIMD_ ## t ## _BITS) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index d9df82cff5..17b1edfb5f 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -30,6 +30,7 @@ #include "exec/exec-all.h" #include "exec/cpu_ldst.h" #include "qemu/int128.h" +#include "advsimd_helper_flags.h" #include "tcg.h" #include /* For crc32 */ diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b5f48605a7..f474c5008b 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -34,6 +34,8 @@ #include "exec/helper-gen.h" #include "exec/log.h" +#include "advsimd_helper_flags.h" + #include "trace-tcg.h" /* Global registers */ From patchwork Thu Aug 17 18:04:04 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 110339 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp2528130qge; Thu, 17 Aug 2017 11:12:44 -0700 (PDT) X-Received: by 10.237.58.106 with SMTP id n97mr8806369qte.284.1502993564541; Thu, 17 Aug 2017 11:12:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1502993564; cv=none; d=google.com; s=arc-20160816; b=LtyUJbzf78nNAYKnpUBbgh9gqXFuNxOcCHTkDmzUcz/1q2L6fpMVVimSn+GXpGNH+N cIYoWY1St2cVyzncBhDE/fCzKO/3Pz6kPMyUCw9rIZ98gT2or4g1E/DmzwWCnYe668mF 0LY1Dt1XWVF+zUmikzLpJTwnlpKFzPX7wPncjsrDHm5mRZ/Z/ZDs75njj5kyN2wI4Yf8 BXSZzNY9zP6P26buOYIZtju1LbjPeND7JytqfLOI5kVx0hWUxMOtj3QgyakbrRcvTHlE +wuVfvfwmCjNvssEcwcBzhsYRE+3FmvZjGlEuWNQ1IMKO2yJ+Nq8kekp0CU1S0OysszM plvQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=UC4iwuAR4yeyWBSDbELSGaxnBCBHWMws/wQFfSoxQ0g=; b=nqDxsmUCeRzHqiaNBoe+JFwYaQmh8gCmBAdv8YmYaFOEyLW/xURrxXMgffZANCIayy 5UUGJncB6UFDIczRLfwnOsXy7aJPd56CzCyRcAJpZiU4xLeaVHGwOd0knKZGNilNwpcu hyqVukMKRnDojQpmECDJn+Ofs1nEvd3zvBQLQX2l8rMqZFo1o143wt6SMPHbcqfA3oIP iLfWmDBrf9fv5K/1Qf/0qI325Gf5kvfd7iVEDK+pynlxHKz4/MqbDXZzHUtQnco4Hg99 B6w2epad26s/vH+TeqSWF7avnDlFQNJ8/l2rry8tmCW7BWXPKLoBIHRAG1x1/u33xZp7 //KA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=FRRxoY1V; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c0c::22e Subject: [Qemu-devel] [RFC PATCH 9/9] target/arm/translate-a64: vectorise smull vD.4s, vN.[48]s, vM.h[] X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These instructions show up in the ffmpeg profile from the ff_simple_idct_put_neon function. WARNING: this is experimental and essentially shortcuts to the vectorised helper for the one instruction that shows up a lot in the ffmpeg trace. Otherwise it falls through to the normal code generation. We also skip where rd == rn to avoid having to explicitly deal with the aliasing in the helper. Signed-off-by: Alex Bennée --- target/arm/helper-a64.c | 17 +++++++++++ target/arm/helper-a64.h | 2 ++ target/arm/translate-a64.c | 72 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 91 insertions(+) -- 2.13.0 diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 17b1edfb5f..ae0f8da5c4 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -538,3 +538,20 @@ uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env, uint64_t addr, return !success; } + +/* Multiply Long (vector, by element) */ +void HELPER(advsimd_smull_idx_s32)(void *d, void *n, uint32_t m, + uint32_t simd_data) +{ + int opr_elt = GET_SIMD_DATA(OPR_ELT, simd_data); + int doff_elt = GET_SIMD_DATA(DOFF_ELT, simd_data); + int32_t *rd = (int32_t *) d; + int16_t *rn = (int16_t *) n; + int16_t rm = (int16_t) m; + int i; + + #pragma GCC ivdep + for (i = 0; i < opr_elt; ++i) { + rd[i] = rn[i + doff_elt] * rm; + } +} diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 6f9eaba533..0bd7942cec 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -44,3 +44,5 @@ DEF_HELPER_FLAGS_3(crc32_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32) DEF_HELPER_FLAGS_3(crc32c_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32) DEF_HELPER_FLAGS_4(paired_cmpxchg64_le, TCG_CALL_NO_WG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(paired_cmpxchg64_be, TCG_CALL_NO_WG, i64, env, i64, i64, i64) + +DEF_HELPER_4(advsimd_smull_idx_s32, void, vec, vec, i32, i32) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index f474c5008b..3a609e571c 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10466,6 +10466,74 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) } } +typedef void AdvSIMDGenTwoPlusOneVectorFn(TCGv_vec, TCGv_vec, TCGv_i32, TCGv_i32); + +/* Handle [U/S]ML[S/A]L instructions + * + * This splits off from bellow only to aid experimentation. + */ +static bool handle_vec_simd_mul_addsub(DisasContext *s, uint32_t insn, int opcode, int size, bool is_q, bool u, int rn, int rm, int rd) +{ + /* fprintf(stderr, "%s: %#04x op:%x sz:%d rn:%d rm:%d rd:%d\n", __func__, */ + /* insn, opcode, size, rn, rm, rd); */ + + if (size == 1) { + AdvSIMDGenTwoPlusOneVectorFn *fn = NULL; + uint32_t simd_info = 0; + + switch (opcode) { + case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ + break; + case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */ + break; + case 0xa: /* SMULL, SMULL2, UMULL, UMULL2 */ + if (!u) + { + /* helper assumes no aliasing */ + if (rd == rn) { + return false; + } + + fn = gen_helper_advsimd_smull_idx_s32; + simd_info = deposit32(simd_info, + ADVSIMD_OPR_ELT_SHIFT, ADVSIMD_OPR_ELT_BITS, 4); + + if (is_q) { + simd_info = deposit32(simd_info, + ADVSIMD_DOFF_ELT_SHIFT, ADVSIMD_DOFF_ELT_BITS, 4); + } + }; + break; + default: + break; + } + + /* assert(fn); */ + + if (fn) { + TCGv_i32 tcg_idx = tcg_temp_new_i32(); + TCGv_i32 tcg_simd_info = tcg_const_i32(simd_info); + int h = extract32(insn, 11, 1); + int lm = extract32(insn, 20, 2); + int index = h << 2 | lm; + + if (!fp_access_check(s)) { + return false; + } + + read_vec_element_i32(s, tcg_idx, rm, index, size); + + fn(cpu_V[rd], cpu_V[rn], tcg_idx, tcg_simd_info); + + tcg_temp_free_i32(tcg_simd_info); + tcg_temp_free_i32(tcg_idx); + return true; + } + } + + return false; +} + /* C3.6.13 AdvSIMD scalar x indexed element * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+ @@ -10518,6 +10586,10 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) unallocated_encoding(s); return; } + /* Shortcut if we have a vectorised helper */ + if (handle_vec_simd_mul_addsub(s, insn, opcode, size, is_q, u, rn, rm, rd)) { + return; + } is_long = true; break; case 0x3: /* SQDMLAL, SQDMLAL2 */