From patchwork Wed Mar 18 06:20:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 203150 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED732C5ACD8 for ; Wed, 18 Mar 2020 06:25:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C33FF20773 for ; Wed, 18 Mar 2020 06:25:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=flygoat.com header.i=jiaxun.yang@flygoat.com header.b="HtxXEXRc" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727291AbgCRGZA (ORCPT ); Wed, 18 Mar 2020 02:25:00 -0400 Received: from sender3-op-o12.zoho.com.cn ([124.251.121.243]:17882 "EHLO sender3-op-o12.zoho.com.cn" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726553AbgCRGZA (ORCPT ); Wed, 18 Mar 2020 02:25:00 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1584512566; s=mail; d=flygoat.com; i=jiaxun.yang@flygoat.com; h=From:To:Cc:Message-ID:Subject:Date:In-Reply-To:References:MIME-Version:Content-Transfer-Encoding:Content-Type; bh=4GS+fzgHRhPzfIm1JsnxfQzRHz6CyvzmhR6kJTWisc4=; b=HtxXEXRcsSeAiNJecHlQufJhtu67In+pVzTVm5+O+7WAkPwje/tYEQVmj1aUwx2/ dORL6mK0TmBwq74S1grMvUrtZDBZRv7k5SvAOihThNakXBl8KxZvD35z5mlbrMdnp8H RuQtSgWuF8FA6KPXnuMGYEzMDV8GvXqgEZwoUI0M= Received: from localhost.localdomain (39.155.141.144 [39.155.141.144]) by mx.zoho.com.cn with SMTPS id 1584512564081798.6091422416087; Wed, 18 Mar 2020 14:22:44 +0800 (CST) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: Jiaxun Yang , Huacai Chen , Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , Mark Rutland , Ralf Baechle , Paul Burton , Greg Kroah-Hartman , Allison Randal , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Message-ID: <20200318062102.8145-2-jiaxun.yang@flygoat.com> Subject: [PATCH v5 01/11] irqchip: Add driver for Loongson I/O Local Interrupt Controller Date: Wed, 18 Mar 2020 14:20:29 +0800 X-Mailer: git-send-email 2.26.0.rc2 In-Reply-To: <20200318062102.8145-1-jiaxun.yang@flygoat.com> References: <20200318062102.8145-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 X-ZohoCNMailClient: External Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This controller appeared on Loongson family of chips as the primary package interrupt source. Co-developed-by: Huacai Chen Signed-off-by: Jiaxun Yang --- v4-v5: Resolve suggestions from maz: - Remove DT validation - Simplify unnucessary functions & variables --- drivers/irqchip/Kconfig | 9 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-loongson-liointc.c | 259 +++++++++++++++++++++++++ 3 files changed, 269 insertions(+) create mode 100644 drivers/irqchip/irq-loongson-liointc.c diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 6d397732138d..c609eaa319d2 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -513,4 +513,13 @@ config EXYNOS_IRQ_COMBINER Say yes here to add support for the IRQ combiner devices embedded in Samsung Exynos chips. +config LOONGSON_LIOINTC + bool "Loongson Local I/O Interrupt Controller" + depends on MACH_LOONGSON64 + default y + select IRQ_DOMAIN + select GENERIC_IRQ_CHIP + help + Support for the Loongson Local I/O Interrupt Controller. + endmenu diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index eae0d78cbf22..5e7678efdfe6 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -105,3 +105,4 @@ obj-$(CONFIG_MADERA_IRQ) += irq-madera.o obj-$(CONFIG_LS1X_IRQ) += irq-ls1x.o obj-$(CONFIG_TI_SCI_INTR_IRQCHIP) += irq-ti-sci-intr.o obj-$(CONFIG_TI_SCI_INTA_IRQCHIP) += irq-ti-sci-inta.o +obj-$(CONFIG_LOONGSON_LIOINTC) += irq-loongson-liointc.o diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c new file mode 100644 index 000000000000..8b6d7b8ddaca --- /dev/null +++ b/drivers/irqchip/irq-loongson-liointc.c @@ -0,0 +1,259 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020, Jiaxun Yang + * Loongson Local IO Interrupt Controller support + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define LIOINTC_CHIP_IRQ 32 +#define LIOINTC_NUM_PARENT 4 + +#define LIOINTC_INTC_CHIP_START 0x20 + +#define LIOINTC_REG_INTC_STATUS (LIOINTC_INTC_CHIP_START + 0x20) +#define LIOINTC_REG_INTC_EN_STATUS (LIOINTC_INTC_CHIP_START + 0x04) +#define LIOINTC_REG_INTC_ENABLE (LIOINTC_INTC_CHIP_START + 0x08) +#define LIOINTC_REG_INTC_DISABLE (LIOINTC_INTC_CHIP_START + 0x0c) +#define LIOINTC_REG_INTC_POL (LIOINTC_INTC_CHIP_START + 0x10) +#define LIOINTC_REG_INTC_EDGE (LIOINTC_INTC_CHIP_START + 0x14) + +#define LIOINTC_SHIFT_INTx 4 + +struct liointc_handler_data { + struct liointc_priv *priv; + u32 parent_int_map; +}; + +struct liointc_priv { + struct irq_chip_generic *gc; + struct liointc_handler_data handler[LIOINTC_NUM_PARENT]; + u8 map_cache[LIOINTC_CHIP_IRQ]; +}; + +static void liointc_chained_handle_irq(struct irq_desc *desc) +{ + struct liointc_handler_data *handler = irq_desc_get_handler_data(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); + struct irq_chip_generic *gc = handler->priv->gc; + u32 pending; + + chained_irq_enter(chip, desc); + + pending = readl(gc->reg_base + LIOINTC_REG_INTC_STATUS); + + if (!pending) + spurious_interrupt(); + + while (pending) { + int bit = __ffs(pending); + + generic_handle_irq(irq_find_mapping(gc->domain, bit)); + pending &= ~BIT(bit); + } + + chained_irq_exit(chip, desc); +} + +static void liointc_set_bit(struct irq_chip_generic *gc, + unsigned int offset, + u32 mask, bool set) +{ + if (set) + writel(readl(gc->reg_base + offset) | mask, + gc->reg_base + offset); + else + writel(readl(gc->reg_base + offset) & ~mask, + gc->reg_base + offset); +} + +static int liointc_set_type(struct irq_data *data, unsigned int type) +{ + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); + u32 mask = data->mask; + unsigned long flags; + + irq_gc_lock_irqsave(gc, flags); + switch (type) { + case IRQ_TYPE_LEVEL_HIGH: + liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false); + liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true); + break; + case IRQ_TYPE_LEVEL_LOW: + liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false); + liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false); + break; + case IRQ_TYPE_EDGE_RISING: + liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true); + liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true); + break; + case IRQ_TYPE_EDGE_FALLING: + liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true); + liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false); + break; + default: + return -EINVAL; + } + irq_gc_unlock_irqrestore(gc, flags); + + irqd_set_trigger_type(data, type); + return 0; +} + +static void liointc_resume(struct irq_chip_generic *gc) +{ + struct liointc_priv *priv = gc->private; + unsigned long flags; + int i; + + irq_gc_lock_irqsave(gc, flags); + /* Disable all at first */ + writel(0xffffffff, gc->reg_base + LIOINTC_REG_INTC_DISABLE); + /* Revert map cache */ + for (i = 0; i < LIOINTC_CHIP_IRQ; i++) + writeb(priv->map_cache[i], gc->reg_base + i); + /* Revert mask cache */ + writel(~gc->mask_cache, gc->reg_base + LIOINTC_REG_INTC_ENABLE); + irq_gc_unlock_irqrestore(gc, flags); +} + +static const char const *parent_names[] = {"int0", "int1", "int2", "int3"}; + +int __init liointc_of_init(struct device_node *node, + struct device_node *parent) +{ + struct irq_chip_generic *gc; + struct irq_domain *domain; + struct irq_chip_type *ct; + struct liointc_priv *priv; + void __iomem *base; + u32 of_parent_int_map[LIOINTC_NUM_PARENT]; + int parent_irq[LIOINTC_NUM_PARENT]; + bool have_parent = FALSE; + int sz, i, err = 0; + + priv = kzalloc(sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + base = of_iomap(node, 0); + if (!base) { + err = -ENODEV; + goto out_free_priv; + } + + for (i = 0; i < LIOINTC_NUM_PARENT; i++) { + parent_irq[i] = of_irq_get_byname(node, parent_names[i]); + if (parent_irq[i] > 0) + have_parent = TRUE; + } + if (!have_parent) { + err = -ENODEV; + goto out_iounmap; + } + + sz = of_property_read_variable_u32_array(node, "loongson,parent_int_map", + &of_parent_int_map[0], LIOINTC_NUM_PARENT, + LIOINTC_NUM_PARENT); + if (sz < 4) { + pr_err("loongson-liointc: No parent_int_map\n"); + err = -ENODEV; + goto out_iounmap; + } + + for (i = 0; i < LIOINTC_NUM_PARENT; i++) + priv->handler[i].parent_int_map = of_parent_int_map[i]; + + /* Setup IRQ domain */ + domain = irq_domain_add_linear(node, 32, + &irq_generic_chip_ops, priv); + if (!domain) { + pr_err("loongson-liointc: cannot add IRQ domain\n"); + err = -EINVAL; + goto out_iounmap; + } + + err = irq_alloc_domain_generic_chips(domain, 32, 1, + node->full_name, handle_level_irq, + IRQ_NOPROBE, 0, 0); + if (err) { + pr_err("loongson-liointc: unable to register IRQ domain\n"); + goto out_free_domain; + } + + + /* Disable all IRQs */ + writel(0xffffffff, base + LIOINTC_REG_INTC_DISABLE); + /* Set to level triggered */ + writel(0x0, base + LIOINTC_REG_INTC_EDGE); + + /* Generate parent INT part of map cache */ + for (i = 0; i < LIOINTC_NUM_PARENT; i++) { + u32 pending = priv->handler[i].parent_int_map; + + while (pending) { + int bit = __ffs(pending); + + priv->map_cache[bit] = BIT(i) << LIOINTC_SHIFT_INTx; + pending &= ~BIT(bit); + } + } + + for (i = 0; i < LIOINTC_CHIP_IRQ; i++) { + /* Generate core part of map cache */ + priv->map_cache[i] |= BIT(loongson_sysconf.boot_cpu_id); + writeb(priv->map_cache[i], base + i); + } + + gc = irq_get_domain_generic_chip(domain, 0); + gc->private = priv; + gc->reg_base = base; + gc->domain = domain; + gc->resume = liointc_resume; + + ct = gc->chip_types; + ct->regs.enable = LIOINTC_REG_INTC_ENABLE; + ct->regs.disable = LIOINTC_REG_INTC_DISABLE; + ct->chip.irq_unmask = irq_gc_unmask_enable_reg; + ct->chip.irq_mask = irq_gc_mask_disable_reg; + ct->chip.irq_mask_ack = irq_gc_mask_disable_reg; + ct->chip.irq_set_type = liointc_set_type; + + gc->mask_cache = 0xffffffff; + priv->gc = gc; + + for (i = 0; i < LIOINTC_NUM_PARENT; i++) { + if (parent_irq[i] <= 0) + continue; + + priv->handler[i].priv = priv; + irq_set_chained_handler_and_data(parent_irq[i], + liointc_chained_handle_irq, &priv->handler[i]); + } + + return 0; + +out_free_domain: + irq_domain_remove(domain); +out_iounmap: + iounmap(base); +out_free_priv: + kfree(priv); + + return err; +} + +IRQCHIP_DECLARE(loongson_liointc_1_0, "loongson,liointc-1.0", liointc_of_init); +IRQCHIP_DECLARE(loongson_liointc_1_0a, "loongson,liointc-1.0a", liointc_of_init); From patchwork Wed Mar 18 06:20:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 203151 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 80D21C5ACD6 for ; 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Wed, 18 Mar 2020 14:23:01 +0800 (CST) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: Jiaxun Yang , Huacai Chen , Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , Mark Rutland , Ralf Baechle , Paul Burton , Allison Randal , Greg Kroah-Hartman , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Message-ID: <20200318062102.8145-3-jiaxun.yang@flygoat.com> Subject: [PATCH v5 02/11] irqchip: loongson-liointc: Workaround LPC IRQ Errata Date: Wed, 18 Mar 2020 14:20:30 +0800 X-Mailer: git-send-email 2.26.0.rc2 In-Reply-To: <20200318062102.8145-1-jiaxun.yang@flygoat.com> References: <20200318062102.8145-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 X-ZohoCNMailClient: External Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The 1.0 version of that controller has a bug that status bit of LPC IRQ sometimes doesn't get set correctly. So we can always blame LPC IRQ when spurious interrupt happens at the parent interrupt line which LPC IRQ supposed to route to. Co-developed-by: Huacai Chen Signed-off-by: Jiaxun Yang --- drivers/irqchip/irq-loongson-liointc.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c index 8b6d7b8ddaca..d5054e90eab8 100644 --- a/drivers/irqchip/irq-loongson-liointc.c +++ b/drivers/irqchip/irq-loongson-liointc.c @@ -32,6 +32,8 @@ #define LIOINTC_SHIFT_INTx 4 +#define LIOINTC_ERRATA_IRQ 10 + struct liointc_handler_data { struct liointc_priv *priv; u32 parent_int_map; @@ -41,6 +43,7 @@ struct liointc_priv { struct irq_chip_generic *gc; struct liointc_handler_data handler[LIOINTC_NUM_PARENT]; u8 map_cache[LIOINTC_CHIP_IRQ]; + bool have_lpc_irq_errata; }; static void liointc_chained_handle_irq(struct irq_desc *desc) @@ -54,8 +57,14 @@ static void liointc_chained_handle_irq(struct irq_desc *desc) pending = readl(gc->reg_base + LIOINTC_REG_INTC_STATUS); - if (!pending) - spurious_interrupt(); + if (!pending) { + /* Always blame LPC IRQ if we have that bug and LPC IRQ is enabled */ + if (handler->priv->have_lpc_irq_errata && + (handler->parent_int_map & ~gc->mask_cache & BIT(LIOINTC_ERRATA_IRQ))) + pending = BIT(LIOINTC_ERRATA_IRQ); + else + spurious_interrupt(); + } while (pending) { int bit = __ffs(pending); @@ -164,6 +173,9 @@ int __init liointc_of_init(struct device_node *node, goto out_iounmap; } + if (of_device_is_compatible(node, "loongson,liointc-1.0")) + priv->have_lpc_irq_errata = true; + sz = of_property_read_variable_u32_array(node, "loongson,parent_int_map", &of_parent_int_map[0], LIOINTC_NUM_PARENT, LIOINTC_NUM_PARENT); From patchwork Wed Mar 18 06:20:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 203149 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F2DFC10DCE for ; Wed, 18 Mar 2020 06:25:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 384BB20752 for ; Wed, 18 Mar 2020 06:25:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=flygoat.com header.i=jiaxun.yang@flygoat.com header.b="ciYYdVSY" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727354AbgCRGZU (ORCPT ); Wed, 18 Mar 2020 02:25:20 -0400 Received: from sender3-op-o12.zoho.com.cn ([124.251.121.243]:17807 "EHLO sender3-op-o12.zoho.com.cn" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726553AbgCRGZU (ORCPT ); Wed, 18 Mar 2020 02:25:20 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1584512654; s=mail; d=flygoat.com; i=jiaxun.yang@flygoat.com; h=From:To:Cc:Message-ID:Subject:Date:In-Reply-To:References:MIME-Version:Content-Transfer-Encoding:Content-Type; bh=/2lzGckd44y7J3i8bIgDra9A9mus3vdjKhhw5nanvI0=; b=ciYYdVSYv6tAjfIljGfljjbd7GQsFMx8YX3U8buZr1Btt+T1Z1AIPRg4AtW2eg5P 2SW8meUntsvbxMOB5sKqnZEA4t7+5DaSGYt3TIV6INf3MsN0m/lv09YA98ZKBo+2cQk ws0vT+a+xOCVLanGYPGdarmRwkQWBxStUHPIr4Jk= Received: from localhost.localdomain (39.155.141.144 [39.155.141.144]) by mx.zoho.com.cn with SMTPS id 1584512653356165.17200962856293; Wed, 18 Mar 2020 14:24:13 +0800 (CST) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: Jiaxun Yang , Huacai Chen , Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , Mark Rutland , Ralf Baechle , Paul Burton , Greg Kroah-Hartman , Allison Randal , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Message-ID: <20200318062102.8145-7-jiaxun.yang@flygoat.com> Subject: [PATCH v5 06/11] irqchip: mips-cpu: Convert to simple domain Date: Wed, 18 Mar 2020 14:20:34 +0800 X-Mailer: git-send-email 2.26.0.rc2 In-Reply-To: <20200318062102.8145-1-jiaxun.yang@flygoat.com> References: <20200318062102.8145-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 X-ZohoCNMailClient: External Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The old code is using legacy domain to setup irq_domain for CPU interrupts which requires irq_desc to be preallocated. However, when MIPS_CPU_IRQ_BASE >= 16, irq_desc for CPU IRQs may end up unallocated and lead to incorrect behavior. Thus we convert the legacy domain to simple domain which can allocate irq_desc during initialization. Co-developed-by: Huacai Chen Signed-off-by: Jiaxun Yang --- drivers/irqchip/irq-mips-cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-mips-cpu.c b/drivers/irqchip/irq-mips-cpu.c index 95d4fd8f7a96..c3cf7fa76424 100644 --- a/drivers/irqchip/irq-mips-cpu.c +++ b/drivers/irqchip/irq-mips-cpu.c @@ -251,7 +251,7 @@ static void __init __mips_cpu_irq_init(struct device_node *of_node) clear_c0_status(ST0_IM); clear_c0_cause(CAUSEF_IP); - irq_domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0, + irq_domain = irq_domain_add_simple(of_node, 8, MIPS_CPU_IRQ_BASE, &mips_cpu_intc_irq_domain_ops, NULL); if (!irq_domain) From patchwork Wed Mar 18 06:20:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 203148 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B750EC10DCE for ; Wed, 18 Mar 2020 06:26:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 833AD20752 for ; Wed, 18 Mar 2020 06:26:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=flygoat.com header.i=jiaxun.yang@flygoat.com header.b="YtqE6eER" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727068AbgCRG0D (ORCPT ); Wed, 18 Mar 2020 02:26:03 -0400 Received: from sender3-op-o12.zoho.com.cn ([124.251.121.243]:17820 "EHLO sender3-op-o12.zoho.com.cn" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727043AbgCRG0D (ORCPT ); Wed, 18 Mar 2020 02:26:03 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1584512708; s=mail; d=flygoat.com; i=jiaxun.yang@flygoat.com; h=From:To:Cc:Message-ID:Subject:Date:In-Reply-To:References:MIME-Version:Content-Transfer-Encoding:Content-Type; bh=BqhPuXbS8FBSBkJ1DaS3p1oUTn1JF6vO5J9lQbBCPec=; b=YtqE6eERhu5wJHq1wxHwQpxyeP4xMPw9/S3G1RLYyAtKO61CJa4n1Hd1axyrQG6M Pm+U3HJJUOgdAkOf1xI3tBiQoJSG5Jl/B/YY9bfvx27qOYuKtSK78+sWCGf/7EvKlVj 7NH08UPgH4uNVacXOOeMAYTanF9MdcbMdUGqM5bk= Received: from localhost.localdomain (39.155.141.144 [39.155.141.144]) by mx.zoho.com.cn with SMTPS id 1584512706755159.37021375092183; Wed, 18 Mar 2020 14:25:06 +0800 (CST) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: Jiaxun Yang , Huacai Chen , Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , Mark Rutland , Ralf Baechle , Paul Burton , Allison Randal , Greg Kroah-Hartman , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Message-ID: <20200318062102.8145-10-jiaxun.yang@flygoat.com> Subject: [PATCH v5 09/11] MIPS: Loongson64: Add generic dts Date: Wed, 18 Mar 2020 14:20:37 +0800 X-Mailer: git-send-email 2.26.0.rc2 In-Reply-To: <20200318062102.8145-1-jiaxun.yang@flygoat.com> References: <20200318062102.8145-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 X-ZohoCNMailClient: External Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add generic device dts for Loongson-3 devices. They are currently almost identical but will be different later. Some PCH devices like PCI Host Bridge is still enabled by platform code for now. Co-developed-by: Huacai Chen Signed-off-by: Jiaxun Yang --- arch/mips/Kconfig | 6 +- arch/mips/boot/dts/Makefile | 1 + arch/mips/boot/dts/loongson/Makefile | 4 ++ .../boot/dts/loongson/loongson3-package.dtsi | 62 +++++++++++++++++++ .../dts/loongson/loongson3_4core_rs780e.dts | 25 ++++++++ .../dts/loongson/loongson3_8core_rs780e.dts | 25 ++++++++ arch/mips/boot/dts/loongson/rs780e-pch.dtsi | 26 ++++++++ 7 files changed, 147 insertions(+), 2 deletions(-) create mode 100644 arch/mips/boot/dts/loongson/Makefile create mode 100644 arch/mips/boot/dts/loongson/loongson3-package.dtsi create mode 100644 arch/mips/boot/dts/loongson/loongson3_4core_rs780e.dts create mode 100644 arch/mips/boot/dts/loongson/loongson3_8core_rs780e.dts create mode 100644 arch/mips/boot/dts/loongson/rs780e-pch.dtsi diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 797d7f1ad5fe..c3aefb49c61a 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -486,9 +486,11 @@ config MACH_LOONGSON64 select SYS_SUPPORTS_HIGHMEM select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_SUPPORTS_ZBOOT - select LOONGSON_MC146818 select ZONE_DMA32 select NUMA + select COMMON_CLK + select USE_OF + select BUILTIN_DTB help This enables the support of Loongson-2/3 family of machines. @@ -3070,7 +3072,7 @@ endchoice choice prompt "Kernel command line type" if !CMDLINE_OVERRIDE default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \ - !MIPS_MALTA && \ + !MACH_LOONGSON64 && !MIPS_MALTA && \ !CAVIUM_OCTEON_SOC default MIPS_CMDLINE_FROM_BOOTLOADER diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile index 1e79cab8e269..d429a69bfe30 100644 --- a/arch/mips/boot/dts/Makefile +++ b/arch/mips/boot/dts/Makefile @@ -4,6 +4,7 @@ subdir-y += cavium-octeon subdir-y += img subdir-y += ingenic subdir-y += lantiq +subdir-y += loongson subdir-y += mscc subdir-y += mti subdir-y += netlogic diff --git a/arch/mips/boot/dts/loongson/Makefile b/arch/mips/boot/dts/loongson/Makefile new file mode 100644 index 000000000000..56d379471262 --- /dev/null +++ b/arch/mips/boot/dts/loongson/Makefile @@ -0,0 +1,4 @@ +# SPDX_License_Identifier: GPL_2.0 +dtb-$(CONFIG_MACH_LOONGSON64) += loongson3_4core_rs780e.dtb loongson3_8core_rs780e.dtb + +obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) diff --git a/arch/mips/boot/dts/loongson/loongson3-package.dtsi b/arch/mips/boot/dts/loongson/loongson3-package.dtsi new file mode 100644 index 000000000000..d09c313603f1 --- /dev/null +++ b/arch/mips/boot/dts/loongson/loongson3-package.dtsi @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +/ { + #address-cells = <2>; + #size-cells = <2>; + + cpuintc: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + compatible = "mti,cpu-interrupt-controller"; + }; + + package0: bus@1fe00000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0x1fe00000 0 0x1fe00000 0x100000 + 0 0x3ff00000 0 0x3ff00000 0x100000 + 0xefd 0xfb000000 0xefd 0xfb000000 0x10000000 /* 3A HT Config Space */ + 0x1efd 0xfb000000 0x1efd 0xfb000000 0x10000000 /* 3B HT Config Space */>; + + liointc: interrupt-controller@3ff01400 { + compatible = "loongson,liointc-1.0"; + reg = <0 0x3ff01400 0x64>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&cpuintc>; + interrupts = <2>, <3>; + interrupt-names = "int0", "int1"; + + loongson,parent_int_map = <0xf0ffffff>, /* int0 */ + <0x0f000000>, /* int1 */ + <0x00000000>, /* int2 */ + <0x00000000>; /* int3 */ + + }; + + cpu_uart0: serial@1fe001e0 { + compatible = "ns16550a"; + reg = <0 0x1fe001e0 0x8>; + clock-frequency = <33000000>; + interrupt-parent = <&liointc>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; + no-loopback-test; + }; + + cpu_uart1: serial@1fe001e8 { + status = "disabled"; + compatible = "ns16550a"; + reg = <0 0x1fe001e8 0x8>; + clock-frequency = <33000000>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&liointc>; + no-loopback-test; + }; + }; +}; diff --git a/arch/mips/boot/dts/loongson/loongson3_4core_rs780e.dts b/arch/mips/boot/dts/loongson/loongson3_4core_rs780e.dts new file mode 100644 index 000000000000..6b5694ca0f95 --- /dev/null +++ b/arch/mips/boot/dts/loongson/loongson3_4core_rs780e.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include "loongson3-package.dtsi" +#include "rs780e-pch.dtsi" + +/ { + compatible = "loongson,loongson3-4core-rs780e"; +}; + +&package0 { + htpic: interrupt-controller@efdfb000080 { + compatible = "loongson,htpic-1.0"; + reg = <0xefd 0xfb000080 0x40>; + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&liointc>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>, + <25 IRQ_TYPE_LEVEL_HIGH>, + <26 IRQ_TYPE_LEVEL_HIGH>, + <27 IRQ_TYPE_LEVEL_HIGH>; + }; +}; diff --git a/arch/mips/boot/dts/loongson/loongson3_8core_rs780e.dts b/arch/mips/boot/dts/loongson/loongson3_8core_rs780e.dts new file mode 100644 index 000000000000..ffefa2f829b0 --- /dev/null +++ b/arch/mips/boot/dts/loongson/loongson3_8core_rs780e.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include "loongson3-package.dtsi" +#include "rs780e-pch.dtsi" + +/ { + compatible = "loongson,loongson3-8core-rs780e"; +}; + +&package0 { + htpic: interrupt-controller@1efdfb000080 { + compatible = "loongson,htpic-1.0"; + reg = <0x1efd 0xfb000080 0x40>; + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&liointc>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>, + <25 IRQ_TYPE_LEVEL_HIGH>, + <26 IRQ_TYPE_LEVEL_HIGH>, + <27 IRQ_TYPE_LEVEL_HIGH>; + }; +}; diff --git a/arch/mips/boot/dts/loongson/rs780e-pch.dtsi b/arch/mips/boot/dts/loongson/rs780e-pch.dtsi new file mode 100644 index 000000000000..45c54d555fa4 --- /dev/null +++ b/arch/mips/boot/dts/loongson/rs780e-pch.dtsi @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + bus@10000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0x10000000 0 0x10000000 0 0x10000000 + 0 0x40000000 0 0x40000000 0 0x40000000 + 0xfd 0xfe000000 0xfd 0xfe000000 0 0x2000000 /* PCI Config Space */>; + + isa { + compatible = "isa"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <1 0 0 0 0x1000>; + + rtc0: rtc@70 { + compatible = "motorola,mc146818"; + reg = <1 0x70 0x8>; + interrupts = <8>; + interrupt-parent = <&htpic>; + }; + }; + }; +}; From patchwork Wed Mar 18 06:20:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 203147 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E2C78C10DCE for ; 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Wed, 18 Mar 2020 14:25:42 +0800 (CST) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: Jiaxun Yang , Huacai Chen , Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , Mark Rutland , Ralf Baechle , Paul Burton , Allison Randal , Greg Kroah-Hartman , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Message-ID: <20200318062102.8145-12-jiaxun.yang@flygoat.com> Subject: [PATCH v5 11/11] MIPS: Loongson64: Move MIPS_CPU_IRQ_BASE Date: Wed, 18 Mar 2020 14:20:39 +0800 X-Mailer: git-send-email 2.26.0.rc2 In-Reply-To: <20200318062102.8145-1-jiaxun.yang@flygoat.com> References: <20200318062102.8145-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 X-ZohoCNMailClient: External Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org To prevent CPU IRQ collide with PCH IRQ, we move down CPU IRQ BASE to 16. Co-developed-by: Huacai Chen Signed-off-by: Jiaxun Yang --- arch/mips/include/asm/mach-loongson64/irq.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/include/asm/mach-loongson64/irq.h b/arch/mips/include/asm/mach-loongson64/irq.h index 12208119aac0..1ce2e0bbe305 100644 --- a/arch/mips/include/asm/mach-loongson64/irq.h +++ b/arch/mips/include/asm/mach-loongson64/irq.h @@ -5,7 +5,7 @@ #include /* cpu core interrupt numbers */ -#define MIPS_CPU_IRQ_BASE 56 +#define MIPS_CPU_IRQ_BASE 16 #include_next #endif /* __ASM_MACH_LOONGSON64_IRQ_H_ */