From patchwork Wed Mar 18 00:15:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Oltean X-Patchwork-Id: 203155 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 99256C1975A for ; Wed, 18 Mar 2020 00:18:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6006320757 for ; Wed, 18 Mar 2020 00:18:02 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Oq350yYd" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727303AbgCRAR6 (ORCPT ); Tue, 17 Mar 2020 20:17:58 -0400 Received: from mail-wm1-f66.google.com ([209.85.128.66]:51302 "EHLO mail-wm1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726965AbgCRARL (ORCPT ); Tue, 17 Mar 2020 20:17:11 -0400 Received: by mail-wm1-f66.google.com with SMTP id c187so18176wme.1; Tue, 17 Mar 2020 17:17:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=pE6LjR29iwQf7D7RlG7d25qJJWFx3m2e6HQhVoX16AY=; b=Oq350yYdRqcZoUIYFTMtYKriySyDk2r83F7XAZna+/BNzTaoUFmeBpLsVWHCK5O7fm 2cwUAa3dCAZbr9rQK8gV7p7WRYwiGP5Osw39oImS3PEr4RL/AXeDf289CQNQ3fFP8CcN cD1N9KGwmhz+1067jVRAw1eHgwNbnZBwzxw0BWeV5/7sZ9CblzkwvkfEiqfyRddfVOmC ADv9QaYagVJyGvwp3pR5BHBlLQUMtK/61BD87Juhk8G9BKH9BTkG3WX5dws9VgXjyMxs tB7Fh6pSGDUBk8YV9/2FXaSb30XlpsvHm6xJTlXJldbBVsZlAiS1tF0lHBp15ScTuL8/ odoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=pE6LjR29iwQf7D7RlG7d25qJJWFx3m2e6HQhVoX16AY=; b=HMYMC2UueQkvQdK6P6xSVitfMm0jYytdI19V8eTu/jWbtUD/8Dc8z8TBs9+FReOhxq Yz9/yOMpwRjywHRcgCjWEAESt2uY4EuKoVlEtckO1d1F3a6I62QUzFAYaCsNrKIzCUsD A7Li+9TLyaDi6t7ciul5Of55ClbApgHYgJH9wxW7hmffJMw0tObfxo2l+ReGo1pwBAch 02QF1+I/8SZ1nKuMmgfkUkChHDgJvn2Pwn/Q/rrXJOebhrGLewNSwOnUurqRBe+MWDk5 TpFPUoq9iYegbCE4vutSYk5alCRQzcgrUU6iiTjpgrEjmLEgE5TMtwm7C2fn7GuAKxlM ssjg== X-Gm-Message-State: ANhLgQ3jKN30Opb5CRZrm5k1aXMoexLFCNCjK2m24s6KzxeGpxJVs97J iiTkTP4tc2yfA3wSZNTqXYA= X-Google-Smtp-Source: ADFU+vtZK5FtJiMPU4xFtis1grhOnhh8z5/n3TB5GJ3/bsDZWnoQsfVvYFUJLe8SFtyTi8q75VqjEg== X-Received: by 2002:a1c:6a08:: with SMTP id f8mr1510919wmc.53.1584490629614; Tue, 17 Mar 2020 17:17:09 -0700 (PDT) Received: from localhost.localdomain ([79.115.60.40]) by smtp.gmail.com with ESMTPSA id i6sm6584600wru.40.2020.03.17.17.17.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Mar 2020 17:17:09 -0700 (PDT) From: Vladimir Oltean To: broonie@kernel.org Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, shawnguo@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, eha@deif.com, angelo@sysam.it, andrew.smirnov@gmail.com, gustavo@embeddedor.com, weic@nvidia.com, mhosny@nvidia.com, michael@walle.cc, peng.ma@nxp.com Subject: [PATCH v5 02/12] spi: spi-fsl-dspi: Fix little endian access to PUSHR CMD and TXDATA Date: Wed, 18 Mar 2020 02:15:53 +0200 Message-Id: <20200318001603.9650-3-olteanv@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200318001603.9650-1-olteanv@gmail.com> References: <20200318001603.9650-1-olteanv@gmail.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Vladimir Oltean In XSPI mode, the 32-bit PUSHR register can be written to separately: the higher 16 bits are for commands and the lower 16 bits are for data. This has nicely been hacked around, by defining a second regmap with a width of 16 bits, and effectively splitting a 32-bit register into 2 16-bit ones, from the perspective of this regmap_pushr. The problem is the assumption about the controller's endianness. If the controller is little endian (such as anything post-LS1046A), then the first 2 bytes, in the order imposed by memory layout, will actually hold the TXDATA, and the last 2 bytes will hold the CMD. So take the controller's endianness into account when performing split writes to PUSHR. The obvious and simple solution would have been to call regmap_get_val_endian(), but that is an internal regmap function and we don't want to change regmap just for this. Therefore, we just re-read the "big-endian" device tree property. Fixes: 58ba07ec79e6 ("spi: spi-fsl-dspi: Add support for XSPI mode registers") Signed-off-by: Vladimir Oltean --- Changes in v5: None. Changes in v4: None. Changes in v3: None. Changes in v2: Parse "big-endian" device tree bindings instead of taking the decision based on compatible SoC. drivers/spi/spi-fsl-dspi.c | 26 ++++++++++++++++++++------ 1 file changed, 20 insertions(+), 6 deletions(-) diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index 6ca35881881b..be717776dd98 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -103,10 +103,6 @@ #define SPI_FRAME_BITS(bits) SPI_CTAR_FMSZ((bits) - 1) #define SPI_FRAME_EBITS(bits) SPI_CTARE_FMSZE(((bits) - 1) >> 4) -/* Register offsets for regmap_pushr */ -#define PUSHR_CMD 0x0 -#define PUSHR_TX 0x2 - #define DMA_COMPLETION_TIMEOUT msecs_to_jiffies(3000) struct chip_data { @@ -240,6 +236,13 @@ struct fsl_dspi { int words_in_flight; + /* + * Offsets for CMD and TXDATA within SPI_PUSHR when accessed + * individually (in XSPI mode) + */ + int pushr_cmd; + int pushr_tx; + void (*host_to_dev)(struct fsl_dspi *dspi, u32 *txdata); void (*dev_to_host)(struct fsl_dspi *dspi, u32 rxdata); }; @@ -673,12 +676,12 @@ static void dspi_pushr_cmd_write(struct fsl_dspi *dspi, u16 cmd) */ if (dspi->len > dspi->oper_word_size) cmd |= SPI_PUSHR_CMD_CONT; - regmap_write(dspi->regmap_pushr, PUSHR_CMD, cmd); + regmap_write(dspi->regmap_pushr, dspi->pushr_cmd, cmd); } static void dspi_pushr_txdata_write(struct fsl_dspi *dspi, u16 txdata) { - regmap_write(dspi->regmap_pushr, PUSHR_TX, txdata); + regmap_write(dspi->regmap_pushr, dspi->pushr_tx, txdata); } static void dspi_xspi_write(struct fsl_dspi *dspi, int cnt, bool eoq) @@ -1259,6 +1262,7 @@ static int dspi_probe(struct platform_device *pdev) struct fsl_dspi *dspi; struct resource *res; void __iomem *base; + bool big_endian; ctlr = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi)); if (!ctlr) @@ -1284,6 +1288,7 @@ static int dspi_probe(struct platform_device *pdev) /* Only Coldfire uses platform data */ dspi->devtype_data = &devtype_data[MCF5441X]; + big_endian = true; } else { ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num); @@ -1305,6 +1310,15 @@ static int dspi_probe(struct platform_device *pdev) ret = -EFAULT; goto out_ctlr_put; } + + big_endian = of_device_is_big_endian(np); + } + if (big_endian) { + dspi->pushr_cmd = 0; + dspi->pushr_tx = 2; + } else { + dspi->pushr_cmd = 2; + dspi->pushr_tx = 0; } if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE) From patchwork Wed Mar 18 00:15:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Oltean X-Patchwork-Id: 203156 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 41E88C5ACD7 for ; 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Tue, 17 Mar 2020 17:17:11 -0700 (PDT) From: Vladimir Oltean To: broonie@kernel.org Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, shawnguo@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, eha@deif.com, angelo@sysam.it, andrew.smirnov@gmail.com, gustavo@embeddedor.com, weic@nvidia.com, mhosny@nvidia.com, michael@walle.cc, peng.ma@nxp.com Subject: [PATCH v5 04/12] spi: spi-fsl-dspi: Avoid reading more data than written in EOQ mode Date: Wed, 18 Mar 2020 02:15:55 +0200 Message-Id: <20200318001603.9650-5-olteanv@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200318001603.9650-1-olteanv@gmail.com> References: <20200318001603.9650-1-olteanv@gmail.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Vladimir Oltean If dspi->words_in_flight is populated with the hardware FIFO size, then in dspi_fifo_read it will attempt to read more data at the end of a buffer that is not a multiple of 16 bytes in length. It will probably time out attempting to do so. So limit the num_fifo_entries variable to the actual number of FIFO entries that is going to be used. Fixes: d59c90a2400f ("spi: spi-fsl-dspi: Convert TCFQ users to XSPI FIFO mode") Signed-off-by: Vladimir Oltean --- Changes in v5: None. Changes in v4: Patch is new. drivers/spi/spi-fsl-dspi.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index 8f2b73cc6ed7..51224b772680 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -739,13 +739,16 @@ static void dspi_eoq_fifo_write(struct fsl_dspi *dspi) int num_fifo_entries = dspi->devtype_data->fifo_size; u16 xfer_cmd = dspi->tx_cmd; + if (num_fifo_entries * dspi->oper_word_size > dspi->len) + num_fifo_entries = dspi->len / dspi->oper_word_size; + dspi->words_in_flight = num_fifo_entries; /* Fill TX FIFO with as many transfers as possible */ - while (dspi->len && num_fifo_entries--) { + while (num_fifo_entries--) { dspi->tx_cmd = xfer_cmd; /* Request EOQF for last transfer in FIFO */ - if (dspi->len == dspi->oper_word_size || num_fifo_entries == 0) + if (num_fifo_entries == 0) dspi->tx_cmd |= SPI_PUSHR_CMD_EOQ; /* Write combined TX FIFO and CMD FIFO entry */ dspi_pushr_write(dspi); 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Tue, 17 Mar 2020 17:17:15 -0700 (PDT) From: Vladimir Oltean To: broonie@kernel.org Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, shawnguo@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, eha@deif.com, angelo@sysam.it, andrew.smirnov@gmail.com, gustavo@embeddedor.com, weic@nvidia.com, mhosny@nvidia.com, michael@walle.cc, peng.ma@nxp.com Subject: [PATCH v5 07/12] spi: spi-fsl-dspi: Avoid NULL pointer in dspi_slave_abort for non-DMA mode Date: Wed, 18 Mar 2020 02:15:58 +0200 Message-Id: <20200318001603.9650-8-olteanv@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200318001603.9650-1-olteanv@gmail.com> References: <20200318001603.9650-1-olteanv@gmail.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Vladimir Oltean The driver does not create the dspi->dma structure unless operating in DSPI_DMA_MODE, so it makes sense to check for that. Fixes: f4b323905d8b ("spi: Introduce dspi_slave_abort() function for NXP's dspi SPI driver") Signed-off-by: Vladimir Oltean --- Changes in v5: None. Changes in v4: Patch is new. drivers/spi/spi-fsl-dspi.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index b65c21d048f9..81e22b6eadc7 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -1192,8 +1192,10 @@ static int dspi_slave_abort(struct spi_master *master) * Terminate all pending DMA transactions for the SPI working * in SLAVE mode. */ - dmaengine_terminate_sync(dspi->dma->chan_rx); - dmaengine_terminate_sync(dspi->dma->chan_tx); + if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) { + dmaengine_terminate_sync(dspi->dma->chan_rx); + dmaengine_terminate_sync(dspi->dma->chan_tx); + } /* Clear the internal DSPI RX and TX FIFO buffers */ regmap_update_bits(dspi->regmap, SPI_MCR, From patchwork Wed Mar 18 00:15:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Oltean X-Patchwork-Id: 203157 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C778AC5ACD7 for ; Wed, 18 Mar 2020 00:17:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9CE6E2076C for ; Wed, 18 Mar 2020 00:17:52 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="KwyMwcTv" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727319AbgCRARU (ORCPT ); Tue, 17 Mar 2020 20:17:20 -0400 Received: from mail-wr1-f68.google.com ([209.85.221.68]:44249 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727313AbgCRART (ORCPT ); Tue, 17 Mar 2020 20:17:19 -0400 Received: by mail-wr1-f68.google.com with SMTP id y2so12610245wrn.11; Tue, 17 Mar 2020 17:17:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=00i66m1wtM2+P1s/tRhqDIGUbMRLcSr0KSarPdUP5w0=; b=KwyMwcTvlZwqq7M8RopS1rcsR9Pl4g3h8aAWTRuCDWS/Y+PAsOCDZV89UouR8StFl8 /sMiQT1OWTZN3nSViZGALrlWN80fh+L1WbdBv/e0lMGWY4U2edaugJnZEuZ6oP7wgHbA 3w8LEef+quCgr8bHoce/njjXXsPenhxo95XM1YqdDJlQ1BZQRQ9rG1pR684o663i+/M7 jfSgPCBfcuwU114PeueZtBc2XnUZblJQT2lHXTfLfVZyceuzLiEeIfV9uOhMtuvcOeUc kf6H9C5IPaJR++D15CbHz+F6GTkRXNNTbpNQcojxqX8DYMx5ltIj0z7urfTU8NMHAO7k CnmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=00i66m1wtM2+P1s/tRhqDIGUbMRLcSr0KSarPdUP5w0=; b=nRHA9c3N9OLxFjMGpj4URTDAaKTnrBlf/7vyUq0Bu0B9DHuVadXYHDPu88imPq6DbA Rd4Do7FzI3k8SHORFj1IJJ9eRbLMu6FBlRik/ePDc37dmAvE/U2NGSMovXy1hC6TLYIj ZftgIZ1tU6zA0cbbQ2B6wojcglK5RlupAd7tZ9nkaM7kPC6bwG31pjQJxkr+0dfDQ1pY A6/k4k7BKOciR8Rfk6VJ2F3yTJ+t/Vby33WN5zeVsniH6wH+IeFGHNMZcSAI1au+Mq4N n61+BIgEOLoN6ccqW+UNHtWRlEY2VVupxqQmBsyTtn21W2R+eZmxOPbzJTVjXMovvNzB +8Sg== X-Gm-Message-State: ANhLgQ33oTR2aBwgsRJSQ2cohdEOY4ezD8nU37dZHK8QarLzxqNp/c12 mhLhNFd5JW4ZMBvrvxhlPVU= X-Google-Smtp-Source: ADFU+vvtlrjqyj2EntsV/CBRdNvwL6+zfzVjVL1dzehHxplW/HnQN2fzjCzAS9/vuC8hEo2yuTH7Hg== X-Received: by 2002:a5d:6150:: with SMTP id y16mr1631350wrt.352.1584490637777; Tue, 17 Mar 2020 17:17:17 -0700 (PDT) Received: from localhost.localdomain ([79.115.60.40]) by smtp.gmail.com with ESMTPSA id i6sm6584600wru.40.2020.03.17.17.17.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Mar 2020 17:17:17 -0700 (PDT) From: Vladimir Oltean To: broonie@kernel.org Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, shawnguo@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, eha@deif.com, angelo@sysam.it, andrew.smirnov@gmail.com, gustavo@embeddedor.com, weic@nvidia.com, mhosny@nvidia.com, michael@walle.cc, peng.ma@nxp.com Subject: [PATCH v5 08/12] spi: spi-fsl-dspi: Fix interrupt-less DMA mode taking an XSPI code path Date: Wed, 18 Mar 2020 02:15:59 +0200 Message-Id: <20200318001603.9650-9-olteanv@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200318001603.9650-1-olteanv@gmail.com> References: <20200318001603.9650-1-olteanv@gmail.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Vladimir Oltean Interrupts are not necessary for DMA functionality, since the completion event is provided by the DMA driver. But if the driver fails to request the IRQ defined in the device tree, it will call dspi_poll which would make the driver hang waiting for data to become available in the RX FIFO. Fixes: c55be3059159 ("spi: spi-fsl-dspi: Use poll mode in case the platform IRQ is missing") Signed-off-by: Vladimir Oltean --- Changes in v5: None. Changes in v4: Patch is new. drivers/spi/spi-fsl-dspi.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index 81e22b6eadc7..fcc6f20b6631 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -965,13 +965,15 @@ static int dspi_transfer_one_message(struct spi_controller *ctlr, goto out; } - if (!dspi->irq) { - do { - status = dspi_poll(dspi); - } while (status == -EINPROGRESS); - } else if (trans_mode != DSPI_DMA_MODE) { - wait_for_completion(&dspi->xfer_done); - reinit_completion(&dspi->xfer_done); + if (trans_mode != DSPI_DMA_MODE) { + if (dspi->irq) { + wait_for_completion(&dspi->xfer_done); + reinit_completion(&dspi->xfer_done); + } else { + do { + status = dspi_poll(dspi); + } while (status == -EINPROGRESS); + } } spi_transfer_delay_exec(transfer); From patchwork Wed Mar 18 00:16:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Oltean X-Patchwork-Id: 203159 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 66295C5ACD7 for ; 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Tue, 17 Mar 2020 17:17:19 -0700 (PDT) From: Vladimir Oltean To: broonie@kernel.org Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, shawnguo@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, eha@deif.com, angelo@sysam.it, andrew.smirnov@gmail.com, gustavo@embeddedor.com, weic@nvidia.com, mhosny@nvidia.com, michael@walle.cc, peng.ma@nxp.com Subject: [PATCH v5 10/12] spi: spi-fsl-dspi: Add support for LS1028A Date: Wed, 18 Mar 2020 02:16:01 +0200 Message-Id: <20200318001603.9650-11-olteanv@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200318001603.9650-1-olteanv@gmail.com> References: <20200318001603.9650-1-olteanv@gmail.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Vladimir Oltean This is similar to the DSPI instantiation on LS1028A, except that: - The A-011218 erratum has been fixed, so DMA works - The endianness is different, which has implications on XSPI mode Some benchmarking with the following command: spidev_test --device /dev/spidev2.0 --bpw 8 --size 256 --cpha --iter 10000000 --speed 20000000 shows that in DMA mode, it can achieve around 2400 kbps, and in XSPI mode, the same command goes up to 4700 kbps. This is somewhat to be expected, since the DMA buffer size is extremely small at 8 bytes, the winner becomes whomever can prepare the buffers for transmission quicker, and DMA mode has higher overhead there. So XSPI FIFO mode has been chosen as the operating mode for this chip. Signed-off-by: Vladimir Oltean --- Changes in v5: None. Changes in v4: None. Changes in v3: Removed the dma_bufsize variable (obsoleted by 03/12). Changes in v2: Switch to DSPI_XSPI_MODE. drivers/spi/spi-fsl-dspi.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index 5873752a091e..50e41f66a2d7 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -124,6 +124,7 @@ struct fsl_dspi_devtype_data { enum { LS1021A, LS1012A, + LS1028A, LS1043A, LS1046A, LS2080A, @@ -151,6 +152,11 @@ static const struct fsl_dspi_devtype_data devtype_data[] = { .max_clock_factor = 8, .fifo_size = 16, }, + [LS1028A] = { + .trans_mode = DSPI_XSPI_MODE, + .max_clock_factor = 8, + .fifo_size = 4, + }, [LS1043A] = { /* Has A-011218 DMA erratum */ .trans_mode = DSPI_XSPI_MODE, @@ -1050,6 +1056,9 @@ static const struct of_device_id fsl_dspi_dt_ids[] = { }, { .compatible = "fsl,ls1012a-dspi", .data = &devtype_data[LS1012A], + }, { + .compatible = "fsl,ls1028a-dspi", + .data = &devtype_data[LS1028A], }, { .compatible = "fsl,ls1043a-dspi", .data = &devtype_data[LS1043A], From patchwork Wed Mar 18 00:16:03 2020 Content-Type: text/plain; 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Tue, 17 Mar 2020 20:17:25 -0400 Received: from mail-wm1-f67.google.com ([209.85.128.67]:32894 "EHLO mail-wm1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727354AbgCRARZ (ORCPT ); Tue, 17 Mar 2020 20:17:25 -0400 Received: by mail-wm1-f67.google.com with SMTP id r7so1068369wmg.0; Tue, 17 Mar 2020 17:17:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=KAXWu0UANDOVatXihProEuzz/73Lcoq083Tlz6zFj1c=; b=YYUwe03PUuNG50h89cb3aEGYaLRC8phyef/6VGQ9Nh1CTR05B+SJ3fswY+FiI5ccia fQYToImXXpkKNToZD30gpK8F357fG9i9sF91tYjq6qeIPK8iXNbfgvfRJTSXqT29HbGo oZu+VVnsOcwnK7nFxmGOhKXLTZkYXyc0wYZUKVxOBpRe72djfsvbs+5KfHWekD8EzK5K b4I0Lpo3oeg9QG1LxsVRKEGLbMrIZIVaZbfL/rSKB1YkOfbpRU6Bl2tyzdQzffa3UtFQ JA3zLOcGpR7T8/SUvned7VSNFtmV8sUmEkMwmu/ClI+Bd3tSPHWpI2qrrrEms5qMx7XG 2log== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; 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On the reference design board, these are exported to either the mikroBUS1 or mikroBUS2 connector (according to the CPLD register BRDCFG3[SPI3]). Signed-off-by: Vladimir Oltean --- Changes in v5: None. Changes in v4: None. Changes in v3: None. Changes in v2: Change compatible string for spidev node. arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts index 6d05b76c2c7a..0d27b5667b8c 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts @@ -83,6 +83,20 @@ }; }; +&dspi2 { + bus-num = <2>; + status = "okay"; + + /* mikroBUS1 */ + spidev@0 { + compatible = "rohm,dh2228fv"; + spi-max-frequency = <20000000>; + fsl,spi-cs-sck-delay = <100>; + fsl,spi-sck-cs-delay = <100>; + reg = <0>; + }; +}; + &esdhc { sd-uhs-sdr104; sd-uhs-sdr50;