From patchwork Mon Aug 21 23:48:11 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 110604 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp1931649qge; Mon, 21 Aug 2017 16:49:46 -0700 (PDT) X-Received: by 10.99.111.204 with SMTP id k195mr18772819pgc.20.1503359386508; Mon, 21 Aug 2017 16:49:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1503359386; cv=none; d=google.com; s=arc-20160816; b=m53YFPfi+Ir62B8qwrEGH5Mn7VyG3yKCg77qxGFcYhmEZe7+rHIAQZaQpl4vwDDPbz d5wUpiQjeIMmN8HAiVb7wMgHTAWH+OIq7y1Z5btZ0n1IwO7l+WT25wkJs8qB8wf9RgP4 NhzbPXcV7bYIucf35xzgvbHN+BThGetG4Z7K9Z+dv6WObIOV7v+GYbsXnFpAEKI4Nwqk lNicFgywldY26hgpEviTxCTvGgZuwgSskZ3ijS7pkuoraQEFyGxNKaPlTSXoBJIQUFcP DcRW7qj5IhamCiq8jnCfPviN6O+dDuSapHQy/BioDk1jDG4XwAuMiTwQXPUWJQcjgznq +7mA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=DnUPfnEFMhyP6q35KJR3nDjxPKI5EqXgIRxjPE7MJJw=; b=GaZ1O+PYO1hgPknz71uOIFjNZQNdXp+SCxDm+Tz7vH/EtHVVFfa7LQIlRuvEogY8AY MSwBafHXKsNUyJKxNCvKVPbGcJqICv29w7NivXvQY35I3SjakaQwwyOzEhoUHgRzG0lS 1tvIreJ7TmJTgRDsFqVzSM44mtU6VrMpjOf9LEUGGh++4r8eIr0Y3xWmNDjcI+DF2XfA vH8c+4Ar04ic3dNFabr0HlLuNqU0A1tYPzKHEEek/P7yfvHqJoAILiQf1jR1uph+xwCk aC6f6iU2tqpLHBorBQx0NsxLq6pjvJCkTyPYw9gYFijK6tI/MXeiSMAkZVeZdKIxVpmp votA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=jKk6+G2O; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b1si8624655pld.664.2017.08.21.16.49.46; Mon, 21 Aug 2017 16:49:46 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=jKk6+G2O; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754328AbdHUXtp (ORCPT + 3 others); Mon, 21 Aug 2017 19:49:45 -0400 Received: from fllnx209.ext.ti.com ([198.47.19.16]:54711 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754271AbdHUXto (ORCPT ); Mon, 21 Aug 2017 19:49:44 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id v7LNmPbb013497; Mon, 21 Aug 2017 18:48:25 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1503359305; bh=0qDzSDVXgs6AVfWVCQAF5wQjn6FSrzZOWUrnB2uIlTg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=jKk6+G2O7BvVyGI6cUxqUHwtP3eUEbvM9vQJDEI6QoWN/FojQorNn96TKIfoiQsJJ ktf4retpEuDSPomZjd4r3QPSOAWGgKaT5eBHNwxQdRWB/+3SnO9i/Ii+dKLOjjPRji VecSeMv33pA91s0P8cDoclff+rtLYtum/C/mCJw4= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7LNmKGo002265; Mon, 21 Aug 2017 18:48:20 -0500 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Mon, 21 Aug 2017 18:48:20 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Mon, 21 Aug 2017 18:48:20 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7LNmKPP031288; Mon, 21 Aug 2017 18:48:20 -0500 Received: from localhost (irmo.dhcp.ti.com [128.247.58.153]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id v7LNmK307078; Mon, 21 Aug 2017 18:48:20 -0500 (CDT) From: Suman Anna To: Tony Lindgren CC: Paul Walmsley , , , Tero Kristo , Suman Anna Subject: [PATCH 1/8] ARM: DRA7: hwmod data: Add MMU data for IPUs Date: Mon, 21 Aug 2017 18:48:11 -0500 Message-ID: <20170821234818.4755-2-s-anna@ti.com> X-Mailer: git-send-email 2.13.1 In-Reply-To: <20170821234818.4755-1-s-anna@ti.com> References: <20170821234818.4755-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org A new MMU hwmod class and data structures are added for representing the MMUs within the IPU1 and IPU2 processor subsystems present on DRA7xx/AM57xx SoCs. Note that the clock integration is slightly different between IPU1 and IPU2. IPU2 functional clock is sourced directly from dpll_core_h22x2_ck, while IPU1 has a mux clock for which one of the inputs is dpll_core_h22x2_ck. This mux clock is configured to be sourced from the dpll_core_h22x2_ck in turn, so that both IPU1 and IPU2 run at the same clock frequency. This is already addressed in commit 39879c7d963e ("ARM: dts: dra7xx-clocks: Source IPU1 functional clock from CORE DPLL"). Signed-off-by: Suman Anna --- arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 81 +++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) -- 2.13.1 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c index f040244c57e7..bf55802448ac 100644 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c @@ -1800,6 +1800,69 @@ static struct omap_hwmod dra7xx_mmc4_hwmod = { }; /* + * 'mmu' class + * The memory management unit performs virtual to physical address translation + * for its requestors. + */ + +static struct omap_hwmod_class_sysconfig dra7xx_mmu_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | + SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class dra7xx_mmu_hwmod_class = { + .name = "mmu", + .sysc = &dra7xx_mmu_sysc, +}; + +/* IPU MMUs */ +static struct omap_hwmod_rst_info dra7xx_mmu_ipu_resets[] = { + { .name = "mmu_cache", .rst_shift = 2 }, +}; + +/* mmu ipu1 */ +static struct omap_hwmod dra7xx_mmu_ipu1_hwmod = { + .name = "mmu_ipu1", + .class = &dra7xx_mmu_hwmod_class, + .clkdm_name = "ipu1_clkdm", + .rst_lines = dra7xx_mmu_ipu_resets, + .rst_lines_cnt = ARRAY_SIZE(dra7xx_mmu_ipu_resets), + .main_clk = "ipu1_gfclk_mux", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_IPU1_IPU1_CLKCTRL_OFFSET, + .rstctrl_offs = DRA7XX_RM_IPU1_RSTCTRL_OFFSET, + .context_offs = DRA7XX_RM_IPU1_IPU1_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, +}; + +/* mmu ipu2 */ +static struct omap_hwmod dra7xx_mmu_ipu2_hwmod = { + .name = "mmu_ipu2", + .class = &dra7xx_mmu_hwmod_class, + .clkdm_name = "ipu2_clkdm", + .rst_lines = dra7xx_mmu_ipu_resets, + .rst_lines_cnt = ARRAY_SIZE(dra7xx_mmu_ipu_resets), + .main_clk = "dpll_core_h22x2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_IPU2_IPU2_CLKCTRL_OFFSET, + .rstctrl_offs = DRA7XX_RM_IPU2_RSTCTRL_OFFSET, + .context_offs = DRA7XX_RM_IPU2_IPU2_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, +}; + +/* * 'mpu' class * */ @@ -2901,6 +2964,22 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l3_main_1 -> mmu_ipu1 */ +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mmu_ipu1 = { + .master = &dra7xx_l3_main_1_hwmod, + .slave = &dra7xx_mmu_ipu1_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_1 -> mmu_ipu2 */ +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mmu_ipu2 = { + .master = &dra7xx_l3_main_1_hwmod, + .slave = &dra7xx_mmu_ipu2_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* l3_main_1 -> l4_per1 */ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = { .master = &dra7xx_l3_main_1_hwmod, @@ -4010,6 +4089,8 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { &dra7xx_l4_per1__mmc2, &dra7xx_l4_per1__mmc3, &dra7xx_l4_per1__mmc4, + &dra7xx_l3_main_1__mmu_ipu1, + &dra7xx_l3_main_1__mmu_ipu2, &dra7xx_l4_cfg__mpu, &dra7xx_l4_cfg__ocp2scp1, &dra7xx_l4_cfg__ocp2scp3, From patchwork Mon Aug 21 23:48:12 2017 Content-Type: text/plain; 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[209.132.180.67]) by mx.google.com with ESMTP id b1si8624655pld.664.2017.08.21.16.48.54; Mon, 21 Aug 2017 16:48:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=AgROb4TD; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754168AbdHUXsw (ORCPT + 3 others); Mon, 21 Aug 2017 19:48:52 -0400 Received: from lelnx193.ext.ti.com ([198.47.27.77]:45841 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754015AbdHUXsu (ORCPT ); Mon, 21 Aug 2017 19:48:50 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v7LNmKZ5028079; Mon, 21 Aug 2017 18:48:20 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1503359301; bh=U99UCTDwiXrTUv+WZDAmfNqlj38dWgCw1fQCsEdw37k=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=AgROb4TD99/tf7QApNfnmeVDJHsz4XaOfirII3d5Bpqe2BzhU0KQLslnGJMPMUCsS 4NgfW8ijpEy/addvEhX0OBjxePXw/J88Q8kHFysNF/JOaKqoIqgRHMJ5mY7bvZuoKi fbQvhu3/ZCgEEjLs7D0jTHfCO9dsFgDwNRz6brcs= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7LNmKxF005764; Mon, 21 Aug 2017 18:48:20 -0500 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Mon, 21 Aug 2017 18:48:20 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Mon, 21 Aug 2017 18:48:20 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7LNmKfk025298; Mon, 21 Aug 2017 18:48:20 -0500 Received: from localhost (irmo.dhcp.ti.com [128.247.58.153]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id v7LNmK307082; Mon, 21 Aug 2017 18:48:20 -0500 (CDT) From: Suman Anna To: Tony Lindgren CC: Paul Walmsley , , , Tero Kristo , Suman Anna Subject: [PATCH 2/8] ARM: DRA7: hwmod data: Add MMU data for DSPs Date: Mon, 21 Aug 2017 18:48:12 -0500 Message-ID: <20170821234818.4755-3-s-anna@ti.com> X-Mailer: git-send-email 2.13.1 In-Reply-To: <20170821234818.4755-1-s-anna@ti.com> References: <20170821234818.4755-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add the data structures for representing the MMUs within the DSP processor subsystems present in DRA7xx/AM57xx SoCs. The DRA7xx family of SoCs usually have one or two DSPs. The DRA74x/DRA76x family has two DSPs, while DRA72x/DRA71x has only a single DSP. Each DSP subsystem has two MMUs, one for the processor core and the other for the internal EDMA block. The hwmod data for the second DSP is only added for DRA74x/DRA76x family of SoCs. Both these MMUs share a common reset line, the MMU on the EDMA port is expected to be mirror-programmed alongside the primary MMU. The reset data is added to both the MMUs to allow the omap_hwmod layer to skip the enabling and idling of these devices, as that would require the reset be released, which is outside the scope of the hwmod core code. The other PRCM data fields are also skipped for both the second MMUs, this will be handled as part of the primary MMU enabling sequence. The pdata quirks will also not be added for the second MMU as the OMAP IOMMU driver releases the reset once and is expected to program both the MMUs together. Signed-off-by: Suman Anna --- arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 109 ++++++++++++++++++++++++++++++ 1 file changed, 109 insertions(+) -- 2.13.1 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c index bf55802448ac..63ad0d3217dc 100644 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c @@ -1821,6 +1821,77 @@ static struct omap_hwmod_class dra7xx_mmu_hwmod_class = { .sysc = &dra7xx_mmu_sysc, }; +/* DSP MMUs */ +static struct omap_hwmod_rst_info dra7xx_mmu_dsp_resets[] = { + { .name = "mmu_cache", .rst_shift = 1 }, +}; + +/* mmu0 - dsp1 */ +static struct omap_hwmod dra7xx_mmu0_dsp1_hwmod = { + .name = "mmu0_dsp1", + .class = &dra7xx_mmu_hwmod_class, + .clkdm_name = "dsp1_clkdm", + .rst_lines = dra7xx_mmu_dsp_resets, + .rst_lines_cnt = ARRAY_SIZE(dra7xx_mmu_dsp_resets), + .main_clk = "dpll_dsp_m2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_DSP1_DSP1_CLKCTRL_OFFSET, + .rstctrl_offs = DRA7XX_RM_DSP1_RSTCTRL_OFFSET, + .context_offs = DRA7XX_RM_DSP1_DSP1_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, +}; + +/* mmu1 - dsp1 */ +static struct omap_hwmod dra7xx_mmu1_dsp1_hwmod = { + .name = "mmu1_dsp1", + .class = &dra7xx_mmu_hwmod_class, + .clkdm_name = "dsp1_clkdm", + .rst_lines = dra7xx_mmu_dsp_resets, + .rst_lines_cnt = ARRAY_SIZE(dra7xx_mmu_dsp_resets), + .main_clk = "dpll_dsp_m2_ck", + .prcm = { + .omap4 = { + .rstctrl_offs = DRA7XX_RM_DSP1_RSTCTRL_OFFSET, + }, + }, +}; + +/* mmu0 - dsp2 */ +static struct omap_hwmod dra7xx_mmu0_dsp2_hwmod = { + .name = "mmu0_dsp2", + .class = &dra7xx_mmu_hwmod_class, + .clkdm_name = "dsp2_clkdm", + .rst_lines = dra7xx_mmu_dsp_resets, + .rst_lines_cnt = ARRAY_SIZE(dra7xx_mmu_dsp_resets), + .main_clk = "dpll_dsp_m2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_DSP2_DSP2_CLKCTRL_OFFSET, + .rstctrl_offs = DRA7XX_RM_DSP2_RSTCTRL_OFFSET, + .context_offs = DRA7XX_RM_DSP2_DSP2_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, +}; + +/* mmu1 - dsp2 */ +static struct omap_hwmod dra7xx_mmu1_dsp2_hwmod = { + .name = "mmu1_dsp2", + .class = &dra7xx_mmu_hwmod_class, + .clkdm_name = "dsp2_clkdm", + .rst_lines = dra7xx_mmu_dsp_resets, + .rst_lines_cnt = ARRAY_SIZE(dra7xx_mmu_dsp_resets), + .main_clk = "dpll_dsp_m2_ck", + .prcm = { + .omap4 = { + .rstctrl_offs = DRA7XX_RM_DSP2_RSTCTRL_OFFSET, + }, + }, +}; + /* IPU MMUs */ static struct omap_hwmod_rst_info dra7xx_mmu_ipu_resets[] = { { .name = "mmu_cache", .rst_shift = 2 }, @@ -2964,6 +3035,38 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l3_main_1 -> mmu0_dsp1 */ +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mmu0_dsp1 = { + .master = &dra7xx_l3_main_1_hwmod, + .slave = &dra7xx_mmu0_dsp1_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_1 -> mmu1_dsp1 */ +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mmu1_dsp1 = { + .master = &dra7xx_l3_main_1_hwmod, + .slave = &dra7xx_mmu1_dsp1_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_1 -> mmu0_dsp2 */ +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mmu0_dsp2 = { + .master = &dra7xx_l3_main_1_hwmod, + .slave = &dra7xx_mmu0_dsp2_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_1 -> mmu1_dsp2 */ +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mmu1_dsp2 = { + .master = &dra7xx_l3_main_1_hwmod, + .slave = &dra7xx_mmu1_dsp2_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* l3_main_1 -> mmu_ipu1 */ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mmu_ipu1 = { .master = &dra7xx_l3_main_1_hwmod, @@ -4089,6 +4192,8 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { &dra7xx_l4_per1__mmc2, &dra7xx_l4_per1__mmc3, &dra7xx_l4_per1__mmc4, + &dra7xx_l3_main_1__mmu0_dsp1, + &dra7xx_l3_main_1__mmu1_dsp1, &dra7xx_l3_main_1__mmu_ipu1, &dra7xx_l3_main_1__mmu_ipu2, &dra7xx_l4_cfg__mpu, @@ -4153,11 +4258,15 @@ static struct omap_hwmod_ocp_if *dra7xx_gp_hwmod_ocp_ifs[] __initdata = { /* SoC variant specific hwmod links */ static struct omap_hwmod_ocp_if *dra76x_hwmod_ocp_ifs[] __initdata = { &dra7xx_l4_per3__usb_otg_ss4, + &dra7xx_l3_main_1__mmu0_dsp2, + &dra7xx_l3_main_1__mmu1_dsp2, NULL, }; static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = { &dra7xx_l4_per3__usb_otg_ss4, + &dra7xx_l3_main_1__mmu0_dsp2, + &dra7xx_l3_main_1__mmu1_dsp2, NULL, }; From patchwork Mon Aug 21 23:48:13 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 110601 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp1931084qge; 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[209.132.180.67]) by mx.google.com with ESMTP id b1si8624655pld.664.2017.08.21.16.48.56; Mon, 21 Aug 2017 16:48:56 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=AuN9DyZE; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754229AbdHUXsz (ORCPT + 3 others); Mon, 21 Aug 2017 19:48:55 -0400 Received: from fllnx210.ext.ti.com ([198.47.19.17]:14378 "EHLO fllnx210.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753979AbdHUXsw (ORCPT ); Mon, 21 Aug 2017 19:48:52 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id v7LNmL8m026862; Mon, 21 Aug 2017 18:48:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1503359301; bh=5Z0homQZYw7bcRpVZegnSWg/q5qsJU5MuzyxW+66OrI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=AuN9DyZE9ZNLs6QsM/OwI0iezjuS7iVKrjUWuFniR8pXRg3RVBZ3o+i+lMW8UiIqQ wbn1zPlyr8shZNjFVAzP4L8auFabgGyhvV4hmxBfJ9x+heLzeBL++NGEd0kInJ/A2g xkiJG7pRFllACU+SGaA4nB6RfsLJyn3JCEVnmFoI= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7LNmLQc002294; Mon, 21 Aug 2017 18:48:21 -0500 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Mon, 21 Aug 2017 18:48:20 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Mon, 21 Aug 2017 18:48:20 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7LNmKmg003473; Mon, 21 Aug 2017 18:48:20 -0500 Received: from localhost (irmo.dhcp.ti.com [128.247.58.153]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id v7LNmK307086; Mon, 21 Aug 2017 18:48:20 -0500 (CDT) From: Suman Anna To: Tony Lindgren CC: Paul Walmsley , , , Tero Kristo , Suman Anna Subject: [PATCH 3/8] ARM: OMAP2+: Extend iommu pdata-quirks to DRA7 IPUs Date: Mon, 21 Aug 2017 18:48:13 -0500 Message-ID: <20170821234818.4755-4-s-anna@ti.com> X-Mailer: git-send-email 2.13.1 In-Reply-To: <20170821234818.4755-1-s-anna@ti.com> References: <20170821234818.4755-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org The IOMMUs within the IPU processor subsystems in DRA7xx SoCs are very similar to those in OMAP4/OMAP5, so extend the OMAP4 iommu pdata quirks for these MMUs as well. Signed-off-by: Suman Anna --- arch/arm/mach-omap2/pdata-quirks.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) -- 2.13.1 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c index 6b433fce65a5..253315393a29 100644 --- a/arch/arm/mach-omap2/pdata-quirks.c +++ b/arch/arm/mach-omap2/pdata-quirks.c @@ -412,7 +412,8 @@ static void __init omap3_pandora_legacy_init(void) } #endif /* CONFIG_ARCH_OMAP3 */ -#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) +#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ + defined(CONFIG_SOC_DRA7XX) static struct iommu_platform_data omap4_iommu_pdata = { .reset_name = "mmu_cache", .assert_reset = omap_device_assert_hardreset, @@ -588,6 +589,10 @@ static struct of_dev_auxdata omap_auxdata_lookup[] __initdata = { &dra7_hsmmc_data_mmc2), OF_DEV_AUXDATA("ti,dra7-hsmmc", 0x480ad000, "480ad000.mmc", &dra7_hsmmc_data_mmc3), + OF_DEV_AUXDATA("ti,dra7-iommu", 0x55082000, "55082000.mmu", + &omap4_iommu_pdata), + OF_DEV_AUXDATA("ti,dra7-iommu", 0x58882000, "58882000.mmu", + &omap4_iommu_pdata), #endif /* Common auxdata */ OF_DEV_AUXDATA("pinctrl-single", 0, NULL, &pcs_pdata), From patchwork Mon Aug 21 23:48:14 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 110597 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp1931032qge; Mon, 21 Aug 2017 16:48:51 -0700 (PDT) X-Received: by 10.84.194.165 with SMTP id h34mr20742032pld.373.1503359331677; Mon, 21 Aug 2017 16:48:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1503359331; cv=none; d=google.com; s=arc-20160816; b=DS4nG7meUXMGhlerlNcYRtJzdFO9DjAt89nuXC+umk+R8aB4I+5lHiseiuA3dk+AYY 8K7jbx4WAUYkifa539fuFZ8mntC6LxTh09AnGvYzdGn5eOpjFIf+iCCE0lJjOOLeAelU tRJLlX6vE1tkd1uZvNptCs3ecNkH9RsLXQdobrlkGrL2YLPt//J/lzH/NfdnVoIPw/5e mv2lxCJBRL8S5xiBtTxwifc7tjUychppdMIgNmbZVmchp8dCvxZ0dDQtDRawtn7O4OVw 7MmtjeNAaAAdXsJjZN3FOl/yCoXw5rL7YiqCT499KoACKGuocfhY9HUL9ynfOaU7dbi7 T4xw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=6hySdF5yGiWwXnq8Xc/crFX0oADJogrclO7I0YmvGoY=; b=vgdIsEJWG5iZs0ioIfhlCl8N2638T7A4sXpqVUfbkVii6MbHOH+XWS+j41A0M5pZ8r ueoEe75w/HsyktN05Gyps4QwW2hTzwBlw9FAF+BtmqiMq+29ghv9grV32urkhCviOFXE hXFYCjC4eC2jCO+LO2XBMK7YPygL13P9QeAVX48idEjOb12GnoFxp1rCGcWMG6m4hLY6 LEsTmzRb/OlUYPOmGiDrG0KMBXGcmN7EtVpOLdIZBaQIcpemoK1GvPEfWwBQp2eHR4O0 VOVC3/lajZWLSrv+/U/a04AcIA2h5K1ZLwOfdHUlT9BQOWLhHyTUers0Rng5F/h1uFfj 5l8Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=flJ1Rv02; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b1si8624655pld.664.2017.08.21.16.48.51; Mon, 21 Aug 2017 16:48:51 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=flJ1Rv02; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753548AbdHUXst (ORCPT + 3 others); Mon, 21 Aug 2017 19:48:49 -0400 Received: from lelnx193.ext.ti.com ([198.47.27.77]:45836 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753979AbdHUXss (ORCPT ); Mon, 21 Aug 2017 19:48:48 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v7LNmLPa028083; Mon, 21 Aug 2017 18:48:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1503359301; bh=Fi5CiceZPtsesNcGp/0yXziImRc2GPvnyEOfM7qeK94=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=flJ1Rv02VMUXlF+zoSFH1bs1AN0jzNeU5dG0e4JtA1Zlcz08q0K46jGZtrW6+91WL Z1bh9IUsP700eqkQftK5dNTIOmdTq3NNiwxSg/MbU0BsY/pT7t2VdVDQMz9EgetIsy HGTDqiT6nQfhGvT+ONxT3u0mgs1ex0Su/1/MAaq8= Received: from DFLE101.ent.ti.com (dfle101.ent.ti.com [10.64.6.22]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7LNmLlv002306; Mon, 21 Aug 2017 18:48:21 -0500 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Mon, 21 Aug 2017 18:48:21 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Mon, 21 Aug 2017 18:48:21 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7LNmLG3003481; Mon, 21 Aug 2017 18:48:21 -0500 Received: from localhost (irmo.dhcp.ti.com [128.247.58.153]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id v7LNmK307092; Mon, 21 Aug 2017 18:48:20 -0500 (CDT) From: Suman Anna To: Tony Lindgren CC: Paul Walmsley , , , Tero Kristo , Suman Anna Subject: [PATCH 4/8] ARM: OMAP2+: Extend iommu pdata-quirks to DRA7 DSPs Date: Mon, 21 Aug 2017 18:48:14 -0500 Message-ID: <20170821234818.4755-5-s-anna@ti.com> X-Mailer: git-send-email 2.13.1 In-Reply-To: <20170821234818.4755-1-s-anna@ti.com> References: <20170821234818.4755-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org The DSP processor subsystem in DRA7xx SoCs has two MMUs, one for the processor port and another for an EDMA port. Both these MMUs share a common reset line, the MMU on the EDMA port will always be mirror-programmed alongside the primary MMU, with the reset handled once. The reset handling is the same as on equivalent DSP subsystems on OMAP4/OMAP5 SoCs, so extend the OMAP4 iommu pdata quirks for reset for the MMU associated with the processor port only. Add these pdata quirks for both the DSP1 and DSP2 processor subsystems. Note that DSP2 subsystem is present only on the DRA74x/DRA76x SoC variants and not on DRA72x/DRA71x SoCs. Signed-off-by: Suman Anna --- arch/arm/mach-omap2/pdata-quirks.c | 4 ++++ 1 file changed, 4 insertions(+) -- 2.13.1 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c index 253315393a29..65e566f0c5ea 100644 --- a/arch/arm/mach-omap2/pdata-quirks.c +++ b/arch/arm/mach-omap2/pdata-quirks.c @@ -589,6 +589,10 @@ static struct of_dev_auxdata omap_auxdata_lookup[] __initdata = { &dra7_hsmmc_data_mmc2), OF_DEV_AUXDATA("ti,dra7-hsmmc", 0x480ad000, "480ad000.mmc", &dra7_hsmmc_data_mmc3), + OF_DEV_AUXDATA("ti,dra7-dsp-iommu", 0x40d01000, "40d01000.mmu", + &omap4_iommu_pdata), + OF_DEV_AUXDATA("ti,dra7-dsp-iommu", 0x41501000, "41501000.mmu", + &omap4_iommu_pdata), OF_DEV_AUXDATA("ti,dra7-iommu", 0x55082000, "55082000.mmu", &omap4_iommu_pdata), OF_DEV_AUXDATA("ti,dra7-iommu", 0x58882000, "58882000.mmu", From patchwork Mon Aug 21 23:48:15 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 110596 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp1931024qge; Mon, 21 Aug 2017 16:48:51 -0700 (PDT) X-Received: by 10.98.71.142 with SMTP id p14mr18206114pfi.96.1503359331090; Mon, 21 Aug 2017 16:48:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1503359331; cv=none; d=google.com; s=arc-20160816; b=Uc4MRG485jr+A3LK/WO51IEB6CaTGnBlH6PsUkkVluvcYObJPfstsHkE0kDgZW4fhi MtsFZI6BWTirYh6L7Ce7c5RcgVP49IzkmEeq7BGDDjwuatiNxxScDUtPNDvlzgN4oDp4 gn1UzanMP/zfK+IlBivWUUpocLnYpzxQyFvWj2xTgCtLT+BJlB0nHbmFx48/ipq1cDw5 08pBYgLWLoJPul+rchuBdRKB0IkEpIIAKnrzhf8ot+Quw2xcUC6x82IGNjGKp5c4t0Lw LGT5qn29DXIaunp9P0mY3xuiCgD6YxKEWOIyf8mJGbFqnvyN+8LdOmE0lU/5WrbGX1H3 IFMg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=vyRCKAZ064tN6CzqxJVYzEuccpv4YfQy/VzLJ2D3w+I=; b=mgEWRLirEv/kOC8fBYwx7jgfdq+ZDO9WepiNhKMTUYSAndNjUuInTXw4i5wuuzhL0D tkMHiGVDSSdfIeVohAIGWRUvf6tdaSsGWb3BVIlTl9PN4gxvX0QsE6mjwA0lZCBbbuaV iKeyy6l4IQRbvV3EesCXZn2vk+kdhn0l31M7JzpkFg2rAiWJUxb5Z+Ox1aVnkK76uopf HKPhsSbTw/IWiawpBY/5pQLoDL+dGhUS+dPFWvVciNKXyCTfrVeaHLfW/CDZz1uyijdf m1LRSfld2fA/JuFVwbg4sA5sLf0BLjBQXDjdhIWfe9Njdchv6nIO6nsqS6P5a0mZRrlH u1Mw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=JJWFSBfT; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b1si8624655pld.664.2017.08.21.16.48.50; Mon, 21 Aug 2017 16:48:51 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=JJWFSBfT; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754071AbdHUXst (ORCPT + 3 others); Mon, 21 Aug 2017 19:48:49 -0400 Received: from lelnx193.ext.ti.com ([198.47.27.77]:45835 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753548AbdHUXss (ORCPT ); Mon, 21 Aug 2017 19:48:48 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v7LNmLUU028087; Mon, 21 Aug 2017 18:48:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1503359301; bh=tXp2X2zj9YbMjp9JcdHQP0KpHK6pfel1R/xnn5bWonI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=JJWFSBfTAN4ZzmtIhpGwo74JrC+VFGtu+WdPjYicIULs69SeNJ3Aocqv+Ngls1RiL KQoDH8ZzPiRi/Pc/U8lkihmdWlZZAUAsYlWdZeiUN+AgkP3ErNRT60ycStuw+VK6M7 2A/zQpsLOGKtlTJdbnaBjm821j8mnyXqamvE+iFU= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7LNmLP1002312; Mon, 21 Aug 2017 18:48:21 -0500 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Mon, 21 Aug 2017 18:48:21 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Mon, 21 Aug 2017 18:48:21 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7LNmLOK025309; Mon, 21 Aug 2017 18:48:21 -0500 Received: from localhost (irmo.dhcp.ti.com [128.247.58.153]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id v7LNmL307097; Mon, 21 Aug 2017 18:48:21 -0500 (CDT) From: Suman Anna To: Tony Lindgren CC: Paul Walmsley , , , Tero Kristo , Suman Anna Subject: [PATCH 5/8] ARM: OMAP4: hwmod_data: Remove modulemode from IPU/DSP hwmods Date: Mon, 21 Aug 2017 18:48:15 -0500 Message-ID: <20170821234818.4755-6-s-anna@ti.com> X-Mailer: git-send-email 2.13.1 In-Reply-To: <20170821234818.4755-1-s-anna@ti.com> References: <20170821234818.4755-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org The .modulemode field is removed from both the IPU and DSP processor hwmods. This fixes a potential kernel crash during the shutdown sequence of any of these remoteproc devices, either during a normal teardown or during a recovery. The DSP and IPU processor subsystems are represented by multiple hwmods, one for each of the MMUs present within the subsystem and one for the processor cores. The processor subsystem is clocked from a single clock source with separate reset lines for each of the processors and the MMUs. This clock and reset information is represented in separate hwmods to allow the management of these entities in different drivers operating on the corresponding platform devices. This doesn't fit quite well into the current omap_hwmod layer due to these inter-dependencies. A remoteproc startup sequence involves enabling and programming of the MMUs, loading of the firmware into RAM mapped by the MMUs, and releasing the processors from reset. A shutdown sequence follows a reverse pattern with the processors put into reset first followed by the unmapping and disabling of the MMUs. Both the processors and the MMUs are present within a single clock domain and requires the domain be clocked and enabled until the last entity. The kernel crash can happen during the unmapping phase of the MMUs, as the hwmod layer disables the module during the omap_device_idle processing of the processor hwmod. This issue is fixed by not defining a modulemode for the IPU/DSP processors, which results in keeping the module in an activated state. The module is disabled properly during the omap_device_idle processing of the MMU hwmod while disabling the MMU. Signed-off-by: Suman Anna --- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 2 -- 1 file changed, 2 deletions(-) -- 2.13.1 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 3e2d792fd9df..d183ffdf37e6 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -550,7 +550,6 @@ static struct omap_hwmod omap44xx_dsp_hwmod = { .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET, .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET, .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, }, }, }; @@ -1561,7 +1560,6 @@ static struct omap_hwmod omap44xx_ipu_hwmod = { .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET, .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET, .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, }, }, }; From patchwork Mon Aug 21 23:48:16 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 110600 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp1931063qge; Mon, 21 Aug 2017 16:48:55 -0700 (PDT) X-Received: by 10.99.4.143 with SMTP id 137mr4890885pge.62.1503359334939; Mon, 21 Aug 2017 16:48:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1503359334; cv=none; d=google.com; s=arc-20160816; b=BSLkgO+P6ty7VMjJnloljygvF//8zrk1BKZDc1c+U3wxdkvTqXglAWdzo8XSJK8Ic7 EgA3v17tFX25eoyOtzR5W+De74b+6I/0SqDCkCV26ntPXfohjZ9BZqeTUbdKBxQbl9yI qd+r1OzbdmOIfe4xnyDpzE6HVoDGqI4q32MtmNc58q8SehZBhK7tBhBUc2qzh+cnR6Xn WVD0wV/LGLNrio8ieTad1rwWEby0axPw7nx8kNJk8aAP2ULA35ALqwZIbqeE5DB0MLdI fdx2SXcNdAmN0+e4TIgWyuu9/9zEGlTDl+vMEaknY+lSc4xAA9jenOg0g5en1T1YQcrC HUAw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=ImK03a/glFpsLq53FIqpMW5J3QI6VyY3eRsnLx+pv7o=; b=OvLMrRvJaxiQYOds7IBq4VdvG6wLcOlFlE9vBCzGkiteTnc8Y3Oy42065oZoZx7XJi 7roYhWOUHx/9NvjeXVoFzTjVOe3jvqeXZfp/fTzInAOs19vaTLGtnhmdGuYvqtfyf6m9 M3njwvbnbFp1+hSIUWU9LqZujL1iXD4iCA2GMEANkB8fcxfqWeVuoPMdY479E1WPja0h 7suq4BA3Ve3eNFmEV1g+vXPz68NySMj8ofp8xgrQVlmR9plQUMVnpGTFdqDax4w0bjKq cl98tLbnNtqLCwkw5/VMr+Gs7z0H2hCJogdw4IQ86UoZcRncsvKlntydfE+sOLHN2NVX O5mg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=FPca4BYS; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b1si8624655pld.664.2017.08.21.16.48.54; Mon, 21 Aug 2017 16:48:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=FPca4BYS; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754015AbdHUXsw (ORCPT + 3 others); Mon, 21 Aug 2017 19:48:52 -0400 Received: from lelnx193.ext.ti.com ([198.47.27.77]:45843 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754077AbdHUXsu (ORCPT ); Mon, 21 Aug 2017 19:48:50 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v7LNmL9H028091; Mon, 21 Aug 2017 18:48:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1503359301; bh=MYQgIAKyPSl2Amo3tRNJ0N9j5w+6+9gagJkxq/Ra64k=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=FPca4BYSLk86tNK/CBUiSIrUoGhyVdEFsf9wbDmH4pLbng30QaH+xOKMx0gtsR1Nm VWXzFwEwMCEDs3GNl5I6R0sZrlXrT0XfjQsOtdLMr+1qz47WXTNtkbUV9e3oHU2FZ3 zjjhhFm68C1c4UNf9rY7N0O0RF+CKFZKlRhKFx4s= Received: from DFLE101.ent.ti.com (dfle101.ent.ti.com [10.64.6.22]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7LNmL0f002318; Mon, 21 Aug 2017 18:48:21 -0500 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Mon, 21 Aug 2017 18:48:21 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Mon, 21 Aug 2017 18:48:21 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7LNmLU2032424; Mon, 21 Aug 2017 18:48:21 -0500 Received: from localhost (irmo.dhcp.ti.com [128.247.58.153]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id v7LNmL307101; Mon, 21 Aug 2017 18:48:21 -0500 (CDT) From: Suman Anna To: Tony Lindgren CC: Paul Walmsley , , , Tero Kristo , Suman Anna Subject: [PATCH 6/8] ARM: OMAP5: hwmod_data: Add data for IPU & DSP processors Date: Mon, 21 Aug 2017 18:48:16 -0500 Message-ID: <20170821234818.4755-7-s-anna@ti.com> X-Mailer: git-send-email 2.13.1 In-Reply-To: <20170821234818.4755-1-s-anna@ti.com> References: <20170821234818.4755-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org OMAP5, like OMAP4, also has an IPU and a DSP processor subsystems. The relevant hwmod classes and data structures are added for these devices. Do note that these hwmod data strucutures do not have a .modulemode field as the devices are managed together with their corresponding MMUs. Each of the processor subsystem and its MMU are present within the same clock domain and requires the domain be clocked and enabled until the last entity is disabled. The module is disabled properly during the omap_device_idle processing of the MMU hwmod while disabling the MMU. Signed-off-by: Suman Anna --- arch/arm/mach-omap2/omap_hwmod_54xx_data.c | 79 ++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) -- 2.13.1 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c index 9a67f013ebad..15f217b5e462 100644 --- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c @@ -335,6 +335,36 @@ static struct omap_hwmod omap54xx_dmic_hwmod = { }; /* + * 'dsp' class + * dsp sub-system + */ + +static struct omap_hwmod_class omap54xx_dsp_hwmod_class = { + .name = "dsp", +}; + +static struct omap_hwmod_rst_info omap54xx_dsp_resets[] = { + { .name = "dsp", .rst_shift = 0 }, +}; + +/* dsp */ +static struct omap_hwmod omap54xx_dsp_hwmod = { + .name = "dsp", + .class = &omap54xx_dsp_hwmod_class, + .clkdm_name = "dsp_clkdm", + .rst_lines = omap54xx_dsp_resets, + .rst_lines_cnt = ARRAY_SIZE(omap54xx_dsp_resets), + .main_clk = "dpll_iva_h11x2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_DSP_DSP_CLKCTRL_OFFSET, + .rstctrl_offs = OMAP54XX_RM_DSP_RSTCTRL_OFFSET, + .context_offs = OMAP54XX_RM_DSP_DSP_CONTEXT_OFFSET, + }, + }, +}; + +/* * 'dss' class * display sub-system */ @@ -940,6 +970,37 @@ static struct omap_hwmod omap54xx_i2c5_hwmod = { }; /* + * 'ipu' class + * image processor unit + */ + +static struct omap_hwmod_class omap54xx_ipu_hwmod_class = { + .name = "ipu", +}; + +static struct omap_hwmod_rst_info omap54xx_ipu_resets[] = { + { .name = "cpu0", .rst_shift = 0 }, + { .name = "cpu1", .rst_shift = 1 }, +}; + +/* ipu */ +static struct omap_hwmod omap54xx_ipu_hwmod = { + .name = "ipu", + .class = &omap54xx_ipu_hwmod_class, + .clkdm_name = "ipu_clkdm", + .rst_lines = omap54xx_ipu_resets, + .rst_lines_cnt = ARRAY_SIZE(omap54xx_ipu_resets), + .main_clk = "dpll_core_h22x2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_IPU_IPU_CLKCTRL_OFFSET, + .rstctrl_offs = OMAP54XX_RM_IPU_RSTCTRL_OFFSET, + .context_offs = OMAP54XX_RM_IPU_IPU_CONTEXT_OFFSET, + }, + }, +}; + +/* * 'kbd' class * keyboard controller */ @@ -2135,6 +2196,14 @@ static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_1 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* dsp -> l3_main_1 */ +static struct omap_hwmod_ocp_if omap54xx_dsp__l3_main_1 = { + .master = &omap54xx_dsp_hwmod, + .slave = &omap54xx_l3_main_1_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* l4_cfg -> mmu_dsp */ static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mmu_dsp = { .master = &omap54xx_l4_cfg_hwmod, @@ -2167,6 +2236,14 @@ static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_2 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l3_main_2 -> ipu */ +static struct omap_hwmod_ocp_if omap54xx_l3_main_2__ipu = { + .master = &omap54xx_l3_main_2_hwmod, + .slave = &omap54xx_ipu_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* l3_main_2 -> mmu_ipu */ static struct omap_hwmod_ocp_if omap54xx_l3_main_2__mmu_ipu = { .master = &omap54xx_l3_main_2_hwmod, @@ -2766,7 +2843,9 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = { &omap54xx_l3_main_3__l3_instr, &omap54xx_l3_main_2__l3_main_1, &omap54xx_l4_cfg__l3_main_1, + &omap54xx_dsp__l3_main_1, &omap54xx_mpu__l3_main_1, + &omap54xx_l3_main_2__ipu, &omap54xx_l3_main_1__l3_main_2, &omap54xx_l4_cfg__l3_main_2, &omap54xx_l3_main_1__l3_main_3, From patchwork Mon Aug 21 23:48:17 2017 Content-Type: text/plain; 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[209.132.180.67]) by mx.google.com with ESMTP id b1si8624655pld.664.2017.08.21.16.48.57; Mon, 21 Aug 2017 16:48:58 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=xChZD8kg; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753979AbdHUXsz (ORCPT + 3 others); Mon, 21 Aug 2017 19:48:55 -0400 Received: from fllnx210.ext.ti.com ([198.47.19.17]:14381 "EHLO fllnx210.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754077AbdHUXsy (ORCPT ); Mon, 21 Aug 2017 19:48:54 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id v7LNmMnU026870; Mon, 21 Aug 2017 18:48:22 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1503359302; bh=pu1IUM4oa/0Ygm0xhHlk+2UrlMrUW4j4oVIBAfAHorU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=xChZD8kgVi5l+tx2V/lC5J2lAJSn5KBeRQkm6QRo6/KNagxUSyfJJMilJSV7tkEda eWoxGLLNlknCqC9+ZrlLxpIIsYFulHkZcTYRxXjOGF57+8PrBGCXAF7YlmXkUacAXL xsT2CNP5Ag3wmkMry7bemj39P7pvVwHuklsHBo8g= Received: from DLEE101.ent.ti.com (dlee101.ent.ti.com [157.170.170.31]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7LNmM4l002324; Mon, 21 Aug 2017 18:48:22 -0500 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Mon, 21 Aug 2017 18:48:21 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Mon, 21 Aug 2017 18:48:21 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7LNmLP9031307; Mon, 21 Aug 2017 18:48:21 -0500 Received: from localhost (irmo.dhcp.ti.com [128.247.58.153]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id v7LNmL307105; Mon, 21 Aug 2017 18:48:21 -0500 (CDT) From: Suman Anna To: Tony Lindgren CC: Paul Walmsley , , , Tero Kristo , Suman Anna Subject: [PATCH 7/8] ARM: DRA7: hwmod_data: Add data for IPUs Date: Mon, 21 Aug 2017 18:48:17 -0500 Message-ID: <20170821234818.4755-8-s-anna@ti.com> X-Mailer: git-send-email 2.13.1 In-Reply-To: <20170821234818.4755-1-s-anna@ti.com> References: <20170821234818.4755-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org The DRA7xx family of SoCs usually have two IPU remote processor subsystems. These subsystems are very similar to the respective processor subsystems on OMAP4/OMAP5 in terms of clock and reset integration. The relevant hwmod classes and data structures are added for IPU1 and IPU2 remoteproc devices that's present on almost all DRA7xx/AM57xx SoCs. Do note that these hwmod data structures do not have a .modulemode field as the devices are managed together with their corresponding MMUs. Each of the processor subsystem and its MMU are present within the same clock domain and requires the domain be clocked and enabled until the last entity is disabled. The module is disabled properly during the omap_device_idle processing of the MMU hwmod while disabling the MMU. Signed-off-by: Suman Anna --- arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 66 +++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) -- 2.13.1 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c index 63ad0d3217dc..e65a02855633 100644 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c @@ -1201,6 +1201,54 @@ static struct omap_hwmod dra7xx_i2c5_hwmod = { }; /* + * 'ipu' class + * image processor unit + */ + +static struct omap_hwmod_class dra7xx_ipu_hwmod_class = { + .name = "ipu", +}; + +static struct omap_hwmod_rst_info dra7xx_ipu_resets[] = { + { .name = "cpu0", .rst_shift = 0 }, + { .name = "cpu1", .rst_shift = 1 }, +}; + +/* ipu1 processor */ +static struct omap_hwmod dra7xx_ipu1_hwmod = { + .name = "ipu1", + .class = &dra7xx_ipu_hwmod_class, + .clkdm_name = "ipu1_clkdm", + .rst_lines = dra7xx_ipu_resets, + .rst_lines_cnt = ARRAY_SIZE(dra7xx_ipu_resets), + .main_clk = "ipu1_gfclk_mux", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_IPU1_IPU1_CLKCTRL_OFFSET, + .rstctrl_offs = DRA7XX_RM_IPU1_RSTCTRL_OFFSET, + .context_offs = DRA7XX_RM_IPU1_IPU1_CONTEXT_OFFSET, + }, + }, +}; + +/* ipu2 processor */ +static struct omap_hwmod dra7xx_ipu2_hwmod = { + .name = "ipu2", + .class = &dra7xx_ipu_hwmod_class, + .clkdm_name = "ipu2_clkdm", + .rst_lines = dra7xx_ipu_resets, + .rst_lines_cnt = ARRAY_SIZE(dra7xx_ipu_resets), + .main_clk = "dpll_core_h22x2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_IPU2_IPU2_CLKCTRL_OFFSET, + .rstctrl_offs = DRA7XX_RM_IPU2_RSTCTRL_OFFSET, + .context_offs = DRA7XX_RM_IPU2_IPU2_CONTEXT_OFFSET, + }, + }, +}; + +/* * 'mailbox' class * */ @@ -3492,6 +3540,22 @@ static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* ipu1 -> l3_main_1 */ +static struct omap_hwmod_ocp_if dra7xx_ipu1__l3_main_1 = { + .master = &dra7xx_ipu1_hwmod, + .slave = &dra7xx_l3_main_1_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* ipu2 -> l3_main_1 */ +static struct omap_hwmod_ocp_if dra7xx_ipu2__l3_main_1 = { + .master = &dra7xx_ipu2_hwmod, + .slave = &dra7xx_l3_main_1_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* l4_cfg -> mailbox1 */ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = { .master = &dra7xx_l4_cfg_hwmod, @@ -4171,6 +4235,8 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { &dra7xx_l4_per1__i2c3, &dra7xx_l4_per1__i2c4, &dra7xx_l4_per1__i2c5, + &dra7xx_ipu1__l3_main_1, + &dra7xx_ipu2__l3_main_1, &dra7xx_l4_cfg__mailbox1, &dra7xx_l4_per3__mailbox2, &dra7xx_l4_per3__mailbox3, From patchwork Mon Aug 21 23:48:18 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 110598 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp1931044qge; Mon, 21 Aug 2017 16:48:53 -0700 (PDT) X-Received: by 10.84.232.77 with SMTP id f13mr13389644pln.173.1503359333481; Mon, 21 Aug 2017 16:48:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1503359333; cv=none; d=google.com; s=arc-20160816; b=I/WEZIcRwQLoEIVDfY6Wolb8jFg7qs2Sg/pIzO5kHUyVVnH5njTbExFxVlK6FX/+DD qSvnaCKptwOzQ+OdF/VhkYV6fjNGHuDmpcNO0wxw/pXFW6dY4m2JhStr8mgt8G0nnwA+ Ss0T1aIX3BXQkKnLyKGq8Pxn9SeUx0s4cS+yjxyoB9fpC3Pgs/4T1EKX+PUY1zk6bw82 azoZYU4bIOiyROiB+U4wLjjM1ttOcmjZDq76yjXc2KRIH37LnJ89VXgdzkcEwKxr+dMI /xsHU9v4AtvGXixWAFL5WQjMlg0ahquPoB/tbwwgxyy6c4chx2/UW2caGLxZOQnuVkf7 6dTQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=JmE3UTur+ojrUGwPzcwmgZoKu6jpuaP+fdVMDjiKF8w=; b=i3EnKo8S01dyl7rpkNFrZsdEDOD9jv/waFJqFI3GRQpVgcpG7U+poyfW+Tp2cV8xdL Swjt+oaBp6D29FxdoDchguTPTB3wAFO3Ydj2TMMz7oDK2ncsbUbjFmxpVygPjRAIKnCq fRyxTM7buVEosIChNyu4d0dhhpeBFGGMGfRCCaWi8fAG7eEQQBroLRamMsYPz62KXHDc FX5wrHrFIx1UY9t7wRTq1DNh76QqVPv56wkNcWhjRymVaCpERcfx0RabvRKWHPP07j5l Kw65JFV4xOcjkGoS0Z2NKtof2RRh+vAeLbPfa4BDcWiHWJHKW//RsEtdegl5ZbtXgr8B NsFg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=G7Citpr2; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b1si8624655pld.664.2017.08.21.16.48.53; Mon, 21 Aug 2017 16:48:53 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=G7Citpr2; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754158AbdHUXsv (ORCPT + 3 others); Mon, 21 Aug 2017 19:48:51 -0400 Received: from lelnx193.ext.ti.com ([198.47.27.77]:45842 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753979AbdHUXsu (ORCPT ); Mon, 21 Aug 2017 19:48:50 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v7LNmORN028101; Mon, 21 Aug 2017 18:48:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1503359304; bh=inoPa+gdh2gb6/1wYMLQTrf2VvtqyKSXqUVFvLKthDw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=G7Citpr25pErNtMt4Jl1dC+K3xQ3OUZ4+6U/WrVUyWtJsLLb8HqoaeaHJ4Tt4Dk59 OrwVyzXwFGTNwkaL5tuhkWSf6yC2JvEf+cpSD8mpnxVifFpym8NJUbgv9g5aWz/qp3 gIXTpORBbA5jiERIDBBNJEVA9dGdAZjyUGDBMNNo= Received: from DLEE101.ent.ti.com (dlee101.ent.ti.com [157.170.170.31]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7LNmOiX002365; Mon, 21 Aug 2017 18:48:24 -0500 Received: from DLEE109.ent.ti.com (157.170.170.41) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Mon, 21 Aug 2017 18:48:21 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Mon, 21 Aug 2017 18:48:21 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7LNmL5E003493; Mon, 21 Aug 2017 18:48:21 -0500 Received: from localhost (irmo.dhcp.ti.com [128.247.58.153]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id v7LNmL307109; Mon, 21 Aug 2017 18:48:21 -0500 (CDT) From: Suman Anna To: Tony Lindgren CC: Paul Walmsley , , , Tero Kristo , Suman Anna Subject: [PATCH 8/8] ARM: DRA7: hwmod_data: Add data for DSPs Date: Mon, 21 Aug 2017 18:48:18 -0500 Message-ID: <20170821234818.4755-9-s-anna@ti.com> X-Mailer: git-send-email 2.13.1 In-Reply-To: <20170821234818.4755-1-s-anna@ti.com> References: <20170821234818.4755-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org The DRA7xx family of SoCs can have up to two identical DSP processor subsystems, with most of them having a single DSP processor subsystem. The second DSP is present only on DRA74x and DRA76x variants currently. These subsystems are very similar to the respective processor subsystems on OMAP4/OMAP5 in terms of clock and reset integration. The relevant hwmod class and data structures are added for both the DSP remoteproc devices, with the data for DSP2 added only on DRA74x/DRA76x variants. Do note that these hwmod data structures do not have a .modulemode field as the devices are managed together with their corresponding MMUs. Each of the processor subsystem and its MMU are present within the same clock domain and requires the domain be clocked and enabled until the last entity is disabled. The module is disabled properly during the omap_device_idle processing of the MMU hwmod while disabling the MMU. Signed-off-by: Suman Anna --- arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 66 +++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) -- 2.13.1 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c index e65a02855633..2a6341753c70 100644 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c @@ -555,6 +555,53 @@ static struct omap_hwmod dra7xx_tptc1_hwmod = { }; /* + * 'dsp' class + * dsp sub-system + */ + +static struct omap_hwmod_class dra7xx_dsp_hwmod_class = { + .name = "dsp", +}; + +static struct omap_hwmod_rst_info dra7xx_dsp_resets[] = { + { .name = "dsp", .rst_shift = 0 }, +}; + +/* dsp1 processor */ +static struct omap_hwmod dra7xx_dsp1_hwmod = { + .name = "dsp1", + .class = &dra7xx_dsp_hwmod_class, + .clkdm_name = "dsp1_clkdm", + .rst_lines = dra7xx_dsp_resets, + .rst_lines_cnt = ARRAY_SIZE(dra7xx_dsp_resets), + .main_clk = "dpll_dsp_m2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_DSP1_DSP1_CLKCTRL_OFFSET, + .rstctrl_offs = DRA7XX_RM_DSP1_RSTCTRL_OFFSET, + .context_offs = DRA7XX_RM_DSP1_DSP1_CONTEXT_OFFSET, + }, + }, +}; + +/* dsp2 processor */ +static struct omap_hwmod dra7xx_dsp2_hwmod = { + .name = "dsp2", + .class = &dra7xx_dsp_hwmod_class, + .clkdm_name = "dsp2_clkdm", + .rst_lines = dra7xx_dsp_resets, + .rst_lines_cnt = ARRAY_SIZE(dra7xx_dsp_resets), + .main_clk = "dpll_dsp_m2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_DSP2_DSP2_CLKCTRL_OFFSET, + .rstctrl_offs = DRA7XX_RM_DSP2_RSTCTRL_OFFSET, + .context_offs = DRA7XX_RM_DSP2_DSP2_CONTEXT_OFFSET, + }, + }, +}; + +/* * 'dss' class * */ @@ -3266,6 +3313,22 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc1 = { .user = OCP_USER_MPU, }; +/* dsp1 -> l3_main_1 */ +static struct omap_hwmod_ocp_if dra7xx_dsp1__l3_main_1 = { + .master = &dra7xx_dsp1_hwmod, + .slave = &dra7xx_l3_main_1_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dsp2 -> l3_main_1 */ +static struct omap_hwmod_ocp_if dra7xx_dsp2__l3_main_1 = { + .master = &dra7xx_dsp2_hwmod, + .slave = &dra7xx_l3_main_1_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* l3_main_1 -> dss */ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = { .master = &dra7xx_l3_main_1_hwmod, @@ -4215,6 +4278,7 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { &dra7xx_l3_main_1__tptc1, &dra7xx_l3_main_1__dss, &dra7xx_l3_main_1__dispc, + &dra7xx_dsp1__l3_main_1, &dra7xx_l3_main_1__hdmi, &dra7xx_l3_main_1__aes1, &dra7xx_l3_main_1__aes2, @@ -4326,6 +4390,7 @@ static struct omap_hwmod_ocp_if *dra76x_hwmod_ocp_ifs[] __initdata = { &dra7xx_l4_per3__usb_otg_ss4, &dra7xx_l3_main_1__mmu0_dsp2, &dra7xx_l3_main_1__mmu1_dsp2, + &dra7xx_dsp2__l3_main_1, NULL, }; @@ -4333,6 +4398,7 @@ static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = { &dra7xx_l4_per3__usb_otg_ss4, &dra7xx_l3_main_1__mmu0_dsp2, &dra7xx_l3_main_1__mmu1_dsp2, + &dra7xx_dsp2__l3_main_1, NULL, };