From patchwork Mon Mar 2 21:39:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Cercueil X-Patchwork-Id: 203934 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.5 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 507BAC3F2CD for ; Mon, 2 Mar 2020 21:40:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 19A232465E for ; Mon, 2 Mar 2020 21:40:10 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=crapouillou.net header.i=@crapouillou.net header.b="NyD6MKC9" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726720AbgCBVkH (ORCPT ); Mon, 2 Mar 2020 16:40:07 -0500 Received: from outils.crapouillou.net ([89.234.176.41]:39900 "EHLO crapouillou.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726700AbgCBVkG (ORCPT ); Mon, 2 Mar 2020 16:40:06 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=crapouillou.net; s=mail; t=1583185204; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:references; bh=XuegH4/ESXmv9jvimvm+jo54TN7v2f2NupKchkt4G/Q=; b=NyD6MKC9v5RxFbr2uvUpwRJKdmd5O+n+22/rdOlK8byogzRzPlpAs/2lXQQnm+Ene1K/9r ITuck8Bav+oLV49CApnUMYiOkYUi0lJEmUw2se054SXvjmMsnKIAsoCF3UpMj6/TtUTRZx 2vu/rU5E8JSyYJbdB0XhX36kSA4zH98= From: Paul Cercueil To: Alessandro Zummo , Alexandre Belloni , Rob Herring , Mark Rutland Cc: od@zcrc.me, =?utf-8?b?5ZGo55Cw5p2w?= , linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Paul Cercueil Subject: [PATCH 1/3] rtc: jz4740: Add support for JZ4760 SoC Date: Mon, 2 Mar 2020 18:39:51 -0300 Message-Id: <20200302213953.28834-1-paul@crapouillou.net> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The WENR feature (set a magic value to enable RTC registers read-write) first appeared on the JZ4760; the JZ4780 came much later. Since it would be dangerous to specify a newer SoC's compatible string as the fallback of an older SoC's compatible string, we add support for the "ingenic,jz4760-rtc" compatible string in the driver. This will permit to support the JZ4770 by having: compatible = "ingenic,jz4770-rtc", "ingenic,jz4760-rtc"; Instead of doing: compatible = "ingenic,jz4770-rtc", "ingenic,jz4780-rtc"; Signed-off-by: Paul Cercueil --- drivers/rtc/rtc-jz4740.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/rtc/rtc-jz4740.c b/drivers/rtc/rtc-jz4740.c index 18023e472cbc..d764cd525c9a 100644 --- a/drivers/rtc/rtc-jz4740.c +++ b/drivers/rtc/rtc-jz4740.c @@ -46,6 +46,7 @@ enum jz4740_rtc_type { ID_JZ4740, + ID_JZ4760, ID_JZ4780, }; @@ -106,7 +107,7 @@ static inline int jz4740_rtc_reg_write(struct jz4740_rtc *rtc, size_t reg, { int ret = 0; - if (rtc->type >= ID_JZ4780) + if (rtc->type >= ID_JZ4760) ret = jz4780_rtc_enable_write(rtc); if (ret == 0) ret = jz4740_rtc_wait_write_ready(rtc); @@ -298,6 +299,7 @@ static void jz4740_rtc_power_off(void) static const struct of_device_id jz4740_rtc_of_match[] = { { .compatible = "ingenic,jz4740-rtc", .data = (void *)ID_JZ4740 }, + { .compatible = "ingenic,jz4760-rtc", .data = (void *)ID_JZ4760 }, { .compatible = "ingenic,jz4780-rtc", .data = (void *)ID_JZ4780 }, {}, }; From patchwork Mon Mar 2 21:39:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Cercueil X-Patchwork-Id: 203933 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.5 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AB5F7C3F2D1 for ; Mon, 2 Mar 2020 21:40:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7C86B22B48 for ; Mon, 2 Mar 2020 21:40:20 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=crapouillou.net header.i=@crapouillou.net header.b="tl1O4K9Y" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726783AbgCBVkU (ORCPT ); Mon, 2 Mar 2020 16:40:20 -0500 Received: from outils.crapouillou.net ([89.234.176.41]:40292 "EHLO crapouillou.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726700AbgCBVkT (ORCPT ); Mon, 2 Mar 2020 16:40:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=crapouillou.net; s=mail; t=1583185211; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=BGwq+fhag28ClFaNMhFdV25yYzPJLioisKoVSy4cwhc=; b=tl1O4K9YHPqpP/GsqLu9svrpCSz0veCI95ciwXCA+E+ILkxuYAI4uKIGaE5Q8BK4tlumUF k1Ks6FAwqPsfzLDBMPufgMm1FyQt4fffJkX/AFULozEojZNKdLTNbmuCHmbmfMPiUcpK3i ksKEkoxDwsYYX54TlSfRvTjNdgEigJM= From: Paul Cercueil To: Alessandro Zummo , Alexandre Belloni , Rob Herring , Mark Rutland Cc: od@zcrc.me, =?utf-8?b?5ZGo55Cw5p2w?= , linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Paul Cercueil Subject: [PATCH 3/3] dt-bindings: rtc: Convert and update jz4740-rtc doc to YAML Date: Mon, 2 Mar 2020 18:39:53 -0300 Message-Id: <20200302213953.28834-3-paul@crapouillou.net> In-Reply-To: <20200302213953.28834-1-paul@crapouillou.net> References: <20200302213953.28834-1-paul@crapouillou.net> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the jz4740-rtc doc to YAML, and update it to reflect the new changes in the driver: - More compatible strings are specified, with fallbacks if needed, - The vendor-specific properties are now properly prefixed with the 'ingenic,' prefix. Signed-off-by: Paul Cercueil --- .../bindings/rtc/ingenic,jz4740-rtc.txt | 37 -------- .../devicetree/bindings/rtc/ingenic,rtc.yaml | 87 +++++++++++++++++++ 2 files changed, 87 insertions(+), 37 deletions(-) delete mode 100644 Documentation/devicetree/bindings/rtc/ingenic,jz4740-rtc.txt create mode 100644 Documentation/devicetree/bindings/rtc/ingenic,rtc.yaml diff --git a/Documentation/devicetree/bindings/rtc/ingenic,jz4740-rtc.txt b/Documentation/devicetree/bindings/rtc/ingenic,jz4740-rtc.txt deleted file mode 100644 index 41c7ae18fd7b..000000000000 --- a/Documentation/devicetree/bindings/rtc/ingenic,jz4740-rtc.txt +++ /dev/null @@ -1,37 +0,0 @@ -JZ4740 and similar SoCs real-time clock driver - -Required properties: - -- compatible: One of: - - "ingenic,jz4740-rtc" - for use with the JZ4740 SoC - - "ingenic,jz4780-rtc" - for use with the JZ4780 SoC -- reg: Address range of rtc register set -- interrupts: IRQ number for the alarm interrupt -- clocks: phandle to the "rtc" clock -- clock-names: must be "rtc" - -Optional properties: -- system-power-controller: To use this component as the - system power controller -- reset-pin-assert-time-ms: Reset pin low-level assertion - time after wakeup (default 60ms; range 0-125ms if RTC clock - at 32 kHz) -- min-wakeup-pin-assert-time-ms: Minimum wakeup pin assertion - time (default 100ms; range 0-2s if RTC clock at 32 kHz) - -Example: - -rtc@10003000 { - compatible = "ingenic,jz4740-rtc"; - reg = <0x10003000 0x40>; - - interrupt-parent = <&intc>; - interrupts = <32>; - - clocks = <&rtc_clock>; - clock-names = "rtc"; - - system-power-controller; - reset-pin-assert-time-ms = <60>; - min-wakeup-pin-assert-time-ms = <100>; -}; diff --git a/Documentation/devicetree/bindings/rtc/ingenic,rtc.yaml b/Documentation/devicetree/bindings/rtc/ingenic,rtc.yaml new file mode 100644 index 000000000000..c18ed8ac263f --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/ingenic,rtc.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/ingenic,rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ingenic SoCs Real-Time Clock DT bindings + +maintainers: + - Paul Cercueil + +allOf: + - $ref: rtc.yaml# + +properties: + compatible: + oneOf: + - enum: + - ingenic,jz4740-rtc + - ingenic,jz4760-rtc + - items: + - const: ingenic,jz4725b-rtc + - const: ingenic,jz4740-rtc + - items: + - enum: + - ingenic,jz4770-rtc + - ingenic,jz4780-rtc + - const: ingenic,jz4760-rtc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: rtc + + system-power-controller: + description: | + Indicates that the RTC is responsible for powering OFF + the system. + type: boolean + + ingenic,reset-pin-assert-time-ms: + description: | + Reset pin low-level assertion time after wakeup + (assuming RTC clock at 32 kHz) + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - minimum: 0 + - maximum: 125 + - default: 60 + + ingenic,min-wakeup-pin-assert-time-ms: + description: | + Minimum wakeup pin assertion time + (assuming RTC clock at 32 kHz) + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - minimum: 0 + - maximum: 2000 + - default: 100 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +examples: + - | + #include + rtc_dev: rtc@10003000 { + compatible = "ingenic,jz4740-rtc"; + reg = <0x10003000 0x40>; + + interrupt-parent = <&intc>; + interrupts = <15>; + + clocks = <&cgu JZ4740_CLK_RTC>; + clock-names = "rtc"; + };