From patchwork Thu Feb 20 16:24:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 204545 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EE7E3C11D12 for ; Thu, 20 Feb 2020 16:26:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D23EA206F4 for ; Thu, 20 Feb 2020 16:26:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728759AbgBTQ0D (ORCPT ); Thu, 20 Feb 2020 11:26:03 -0500 Received: from out28-195.mail.aliyun.com ([115.124.28.195]:57095 "EHLO out28-195.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728217AbgBTQ0C (ORCPT ); Thu, 20 Feb 2020 11:26:02 -0500 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07466222|-1; CH=green; DM=CONTINUE|CONTINUE|true|0.452662-0.00849394-0.538844; DS=CONTINUE|ham_alarm|0.00316388-0.000108622-0.996728; FP=0|0|0|0|0|-1|-1|-1; HT=e02c03279; MF=zhouyanjie@wanyeetech.com; NM=1; PH=DS; RN=23; RT=23; SR=0; TI=SMTPD_---.GqC0FCl_1582215911; Received: from localhost.localdomain(mailfrom:zhouyanjie@wanyeetech.com fp:SMTPD_---.GqC0FCl_1582215911) by smtp.aliyun-inc.com(10.147.40.2); Fri, 21 Feb 2020 00:25:22 +0800 From: =?utf-8?b?5ZGo55Cw5p2wIChaaG91IFlhbmppZSk=?= To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, tglx@linutronix.de, ralf@linux-mips.org, paulburton@kernel.org, jiaxun.yang@flygoat.com, chenhc@lemote.com, sboyd@kernel.org, mturquette@baylibre.com, mark.rutland@arm.com, robh+dt@kernel.org, daniel.lezcano@linaro.org, paul@crapouillou.net, geert+renesas@glider.be, krzk@kernel.org, ebiederm@xmission.com, miquel.raynal@bootlin.com, keescook@chromium.org, sernia.zhou@foxmail.com, zhenwenjin@gmail.com, dongsheng.qiu@ingenic.com Subject: [PATCH v6 1/7] clk: JZ4780: Add function for enable the second core. Date: Fri, 21 Feb 2020 00:24:43 +0800 Message-Id: <1582215889-113034-3-git-send-email-zhouyanjie@wanyeetech.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1582215889-113034-1-git-send-email-zhouyanjie@wanyeetech.com> References: <1582215889-113034-1-git-send-email-zhouyanjie@wanyeetech.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add "jz4780_core1_enable()" for enable the second core of JZ4780, prepare for later commits. Tested-by: H. Nikolaus Schaller Tested-by: Paul Boddie Signed-off-by: 周琰杰 (Zhou Yanjie) Reviewed-by: Jiaxun Yang --- Notes: v5: New patch, split from [1/6] in v4. v5->v6: simplify code with "readl_poll_timeout()". drivers/clk/ingenic/jz4780-cgu.c | 55 ++++++++++++++++++++++++++++++++++++---- 1 file changed, 50 insertions(+), 5 deletions(-) diff --git a/drivers/clk/ingenic/jz4780-cgu.c b/drivers/clk/ingenic/jz4780-cgu.c index d07fff1..92102d8 100644 --- a/drivers/clk/ingenic/jz4780-cgu.c +++ b/drivers/clk/ingenic/jz4780-cgu.c @@ -9,14 +9,16 @@ #include #include #include +#include #include + #include #include "cgu.h" #include "pm.h" /* CGU register offsets */ #define CGU_REG_CLOCKCONTROL 0x00 -#define CGU_REG_PLLCONTROL 0x0c +#define CGU_REG_LCR 0x04 #define CGU_REG_APLL 0x10 #define CGU_REG_MPLL 0x14 #define CGU_REG_EPLL 0x18 @@ -46,8 +48,8 @@ #define CGU_REG_CLOCKSTATUS 0xd4 /* bits within the OPCR register */ -#define OPCR_SPENDN0 (1 << 7) -#define OPCR_SPENDN1 (1 << 6) +#define OPCR_SPENDN0 BIT(7) +#define OPCR_SPENDN1 BIT(6) /* bits within the USBPCR register */ #define USBPCR_USB_MODE BIT(31) @@ -88,6 +90,13 @@ #define USBVBFIL_IDDIGFIL_MASK (0xffff << USBVBFIL_IDDIGFIL_SHIFT) #define USBVBFIL_USBVBFIL_MASK (0xffff) +/* bits within the LCR register */ +#define LCR_PD_SCPU BIT(31) +#define LCR_SCPUS BIT(27) + +/* bits within the CLKGR1 register */ +#define CLKGR1_CORE1 BIT(15) + static struct ingenic_cgu *cgu; static u8 jz4780_otg_phy_get_parent(struct clk_hw *hw) @@ -205,6 +214,42 @@ static const struct clk_ops jz4780_otg_phy_ops = { .set_rate = jz4780_otg_phy_set_rate, }; +static int jz4780_core1_enable(struct clk_hw *hw) +{ + struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw); + struct ingenic_cgu *cgu = ingenic_clk->cgu; + const unsigned int timeout = 5000; + unsigned long flags; + int retval; + u32 lcr, clkgr1; + + spin_lock_irqsave(&cgu->lock, flags); + + lcr = readl(cgu->base + CGU_REG_LCR); + lcr &= ~LCR_PD_SCPU; + writel(lcr, cgu->base + CGU_REG_LCR); + + clkgr1 = readl(cgu->base + CGU_REG_CLKGR1); + clkgr1 &= ~CLKGR1_CORE1; + writel(clkgr1, cgu->base + CGU_REG_CLKGR1); + + spin_unlock_irqrestore(&cgu->lock, flags); + + /* wait for the CPU to be powered up */ + retval = readl_poll_timeout(cgu->base + CGU_REG_LCR, lcr, + !(lcr & LCR_SCPUS), 10, timeout); + if (retval == -ETIMEDOUT) { + pr_err("%s: Wait for power up core1 timeout\n", __func__); + return retval; + } + + return 0; +} + +static const struct clk_ops jz4780_core1_ops = { + .enable = jz4780_core1_enable, +}; + static const s8 pll_od_encoding[16] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, @@ -701,9 +746,9 @@ static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = { }, [JZ4780_CLK_CORE1] = { - "core1", CGU_CLK_GATE, + "core1", CGU_CLK_CUSTOM, .parents = { JZ4780_CLK_CPU, -1, -1, -1 }, - .gate = { CGU_REG_CLKGR1, 15 }, + .custom = { &jz4780_core1_ops }, }, }; From patchwork Thu Feb 20 16:24:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 204546 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 35C1DC11D11 for ; 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Fri, 21 Feb 2020 00:25:25 +0800 From: =?utf-8?b?5ZGo55Cw5p2wIChaaG91IFlhbmppZSk=?= To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, tglx@linutronix.de, ralf@linux-mips.org, paulburton@kernel.org, jiaxun.yang@flygoat.com, chenhc@lemote.com, sboyd@kernel.org, mturquette@baylibre.com, mark.rutland@arm.com, robh+dt@kernel.org, daniel.lezcano@linaro.org, paul@crapouillou.net, geert+renesas@glider.be, krzk@kernel.org, ebiederm@xmission.com, miquel.raynal@bootlin.com, keescook@chromium.org, sernia.zhou@foxmail.com, zhenwenjin@gmail.com, dongsheng.qiu@ingenic.com Subject: [PATCH v6 3/7] MIPS: CI20: Modify DTS to support high resolution timer for SMP. Date: Fri, 21 Feb 2020 00:24:45 +0800 Message-Id: <1582215889-113034-5-git-send-email-zhouyanjie@wanyeetech.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1582215889-113034-1-git-send-email-zhouyanjie@wanyeetech.com> References: <1582215889-113034-1-git-send-email-zhouyanjie@wanyeetech.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Modify DTS, change tcu channel from 2 to 3, channel #0 and #1 for per core local timer, #2 for clocksource. Tested-by: H. Nikolaus Schaller Tested-by: Paul Boddie Signed-off-by: 周琰杰 (Zhou Yanjie) --- Notes: v1->v2: No change. v2->v3: No change. v3->v4: Rebase on top of kernel 5.6-rc1. v4->v5: Move [5/6] in v4 to this patch, to ensure that we can git-bisect without ending up with a broken kernel. v5->v6: No change. arch/mips/boot/dts/ingenic/ci20.dts | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts index 37b9316..29437aa 100644 --- a/arch/mips/boot/dts/ingenic/ci20.dts +++ b/arch/mips/boot/dts/ingenic/ci20.dts @@ -455,7 +455,14 @@ }; &tcu { - /* 3 MHz for the system timer and clocksource */ - assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>; - assigned-clock-rates = <3000000>, <3000000>; + /* 3 MHz for the system timers, 750kHz for the clocksource */ + assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>, + <&tcu TCU_CLK_TIMER2>; + assigned-clock-rates = <3000000>, <3000000>, <750000>; + + /* + * Use channel #0 and #1 for the per core system timer, + * and use channel #2 for the clocksource. + */ + ingenic,pwm-channels-mask = <0xF8>; }; From patchwork Thu Feb 20 16:24:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 204547 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B3E7DC11D10 for ; Thu, 20 Feb 2020 16:25:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8DDE8206F4 for ; Thu, 20 Feb 2020 16:25:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728419AbgBTQZi (ORCPT ); Thu, 20 Feb 2020 11:25:38 -0500 Received: from out28-217.mail.aliyun.com ([115.124.28.217]:43757 "EHLO out28-217.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726871AbgBTQZh (ORCPT ); Thu, 20 Feb 2020 11:25:37 -0500 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436282|-1; CH=green; DM=CONTINUE|CONTINUE|true|0.120704-0.00787874-0.871418; DS=CONTINUE|ham_alarm|0.00702318-0.0015398-0.991437; FP=0|0|0|0|0|-1|-1|-1; HT=e02c03310; MF=zhouyanjie@wanyeetech.com; NM=1; PH=DS; RN=23; RT=23; SR=0; TI=SMTPD_---.GqC0FCl_1582215911; Received: from localhost.localdomain(mailfrom:zhouyanjie@wanyeetech.com fp:SMTPD_---.GqC0FCl_1582215911) by smtp.aliyun-inc.com(10.147.40.2); Fri, 21 Feb 2020 00:25:27 +0800 From: =?utf-8?b?5ZGo55Cw5p2wIChaaG91IFlhbmppZSk=?= To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, tglx@linutronix.de, ralf@linux-mips.org, paulburton@kernel.org, jiaxun.yang@flygoat.com, chenhc@lemote.com, sboyd@kernel.org, mturquette@baylibre.com, mark.rutland@arm.com, robh+dt@kernel.org, daniel.lezcano@linaro.org, paul@crapouillou.net, geert+renesas@glider.be, krzk@kernel.org, ebiederm@xmission.com, miquel.raynal@bootlin.com, keescook@chromium.org, sernia.zhou@foxmail.com, zhenwenjin@gmail.com, dongsheng.qiu@ingenic.com Subject: [PATCH v6 4/7] clocksource: Ingenic: Add high resolution timer support for SMP. Date: Fri, 21 Feb 2020 00:24:46 +0800 Message-Id: <1582215889-113034-6-git-send-email-zhouyanjie@wanyeetech.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1582215889-113034-1-git-send-email-zhouyanjie@wanyeetech.com> References: <1582215889-113034-1-git-send-email-zhouyanjie@wanyeetech.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Enable clock event handling on per CPU core basis. Make sure that interrupts raised on the first core execute event handlers on the correct CPU core. Tested-by: H. Nikolaus Schaller Tested-by: Paul Boddie Signed-off-by: 周琰杰 (Zhou Yanjie) --- Notes: v1->v2: 1.Adjust function naming to make it more reasonable. 2.Replace function smp_call_function_single() with smp_call_function_single_async() in order to resolve the warning below: [ 0.350942] smp: Brought up 1 node, 2 CPUs [ 0.365497] ------------[ cut here ]------------ [ 0.365522] WARNING: CPU: 0 PID: 1 at kernel/smp.c:300 smp_call_function_single+0x110/0x200 [ 0.365533] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 5.5.0-rc1+ #5 [ 0.365537] Stack : 00000000 59c73bcd 00000037 80074e80 80000000 80670000 805a0000 80620590 [ 0.365557] 8065ce38 8fc0dc8c 806d0000 00000000 80670000 00000001 8fc0dc20 59c73bcd [ 0.365574] 00000000 00000000 806f0000 80670000 00000000 806dab00 00000000 2d302e35 [ 0.365591] 203a6d6d 806e0000 806e0000 70617773 80670000 00000000 00000000 00000009 [ 0.365610] 00000000 8fc94e20 8fc0de30 80690000 00000018 803592dc 00000000 806d0000 [ 0.365627] ... [ 0.365634] Call Trace: [ 0.365647] [<8001b9a0>] show_stack+0x6c/0x12c [ 0.365663] [<804aed20>] dump_stack+0x98/0xc8 [ 0.365673] [<8003044c>] __warn+0xc4/0xe8 [ 0.365682] [<800304f4>] warn_slowpath_fmt+0x84/0xb8 [ 0.365690] [<800a886c>] smp_call_function_single+0x110/0x200 [ 0.365703] ---[ end trace 5785856ca39c79d5 ]--- [ 0.365557] 8065ce38 8fc0dc8c 806d0000 00000000 80670000 00000001 8fc0dc20 59c73bcd [ 0.365574] 00000000 00000000 806f0000 80670000 00000000 806dab00 00000000 2d302e35 [ 0.365591] 203a6d6d 806e0000 806e0000 70617773 80670000 00000000 00000000 00000009 [ 0.365610] 00000000 8fc94e20 8fc0de30 80690000 00000018 803592dc 00000000 806d0000 [ 0.365627] ... [ 0.365634] Call Trace: [ 0.365647] [<8001b9a0>] show_stack+0x6c/0x12c [ 0.365663] [<804aed20>] dump_stack+0x98/0xc8 [ 0.365673] [<8003044c>] __warn+0xc4/0xe8 [ 0.365682] [<800304f4>] warn_slowpath_fmt+0x84/0xb8 [ 0.365690] [<800a886c>] smp_call_function_single+0x110/0x200 [ 0.365703] ---[ end trace 5785856ca39c79d5 ]--- v2->v3: No Change. v3->v4: Rebase on top of kernel 5.6-rc1. v4->v5: Move the check for (evt->event_handler) from "ingenic_per_cpu_event_handler" to "ingenic_tcu_cevt_cb". v5->v6: No change. drivers/clocksource/ingenic-timer.c | 113 +++++++++++++++++++++++++++++------- 1 file changed, 91 insertions(+), 22 deletions(-) diff --git a/drivers/clocksource/ingenic-timer.c b/drivers/clocksource/ingenic-timer.c index 4bbdb3d..e396326 100644 --- a/drivers/clocksource/ingenic-timer.c +++ b/drivers/clocksource/ingenic-timer.c @@ -1,7 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 /* - * JZ47xx SoCs TCU IRQ driver + * XBurst SoCs TCU IRQ driver * Copyright (C) 2019 Paul Cercueil + * Copyright (C) 2020 周琰杰 (Zhou Yanjie) */ #include @@ -21,18 +22,23 @@ #include +static DEFINE_PER_CPU(call_single_data_t, ingenic_cevt_csd); + struct ingenic_soc_info { unsigned int num_channels; }; struct ingenic_tcu { struct regmap *map; + struct device_node *np; struct clk *timer_clk, *cs_clk; + unsigned int timer_local[NR_CPUS]; unsigned int timer_channel, cs_channel; struct clock_event_device cevt; struct clocksource cs; - char name[4]; + char name[8]; unsigned long pwm_channels_mask; + int cpu; }; static struct ingenic_tcu *ingenic_tcu; @@ -81,6 +87,24 @@ static int ingenic_tcu_cevt_set_next(unsigned long next, return 0; } +static void ingenic_per_cpu_event_handler(void *info) +{ + struct clock_event_device *cevt = (struct clock_event_device *) info; + + cevt->event_handler(cevt); +} + +static void ingenic_tcu_per_cpu_cb(struct clock_event_device *evt) +{ + struct ingenic_tcu *tcu = to_ingenic_tcu(evt); + call_single_data_t *csd; + + csd = &per_cpu(ingenic_cevt_csd, tcu->cpu); + csd->info = (void *) evt; + csd->func = ingenic_per_cpu_event_handler; + smp_call_function_single_async(tcu->cpu, csd); +} + static irqreturn_t ingenic_tcu_cevt_cb(int irq, void *dev_id) { struct clock_event_device *evt = dev_id; @@ -89,7 +113,7 @@ static irqreturn_t ingenic_tcu_cevt_cb(int irq, void *dev_id) regmap_write(tcu->map, TCU_REG_TECR, BIT(tcu->timer_channel)); if (evt->event_handler) - evt->event_handler(evt); + ingenic_tcu_per_cpu_cb(evt); return IRQ_HANDLED; } @@ -105,14 +129,21 @@ static struct clk * __init ingenic_tcu_get_clock(struct device_node *np, int id) return of_clk_get_from_provider(&args); } -static int __init ingenic_tcu_timer_init(struct device_node *np, - struct ingenic_tcu *tcu) +static int ingenic_tcu_setup_per_cpu_cevt(struct device_node *np, + unsigned int channel) { - unsigned int timer_virq, channel = tcu->timer_channel; + unsigned int timer_virq; struct irq_domain *domain; + struct ingenic_tcu *tcu; unsigned long rate; int err; + tcu = kzalloc(sizeof(*tcu), GFP_KERNEL); + if (!tcu) + return -ENOMEM; + + tcu->map = ingenic_tcu->map; + tcu->timer_clk = ingenic_tcu_get_clock(np, channel); if (IS_ERR(tcu->timer_clk)) return PTR_ERR(tcu->timer_clk); @@ -139,13 +170,15 @@ static int __init ingenic_tcu_timer_init(struct device_node *np, goto err_clk_disable; } - snprintf(tcu->name, sizeof(tcu->name), "TCU"); + snprintf(tcu->name, sizeof(tcu->name), "TCU%u", channel); err = request_irq(timer_virq, ingenic_tcu_cevt_cb, IRQF_TIMER, tcu->name, &tcu->cevt); if (err) goto err_irq_dispose_mapping; + tcu->cpu = smp_processor_id(); + tcu->timer_channel = channel; tcu->cevt.cpumask = cpumask_of(smp_processor_id()); tcu->cevt.features = CLOCK_EVT_FEAT_ONESHOT; tcu->cevt.name = tcu->name; @@ -166,6 +199,25 @@ static int __init ingenic_tcu_timer_init(struct device_node *np, return err; } +static int ingenic_tcu_setup_cevt(unsigned int cpu) +{ + int ret; + + ret = ingenic_tcu_setup_per_cpu_cevt(ingenic_tcu->np, + ingenic_tcu->timer_local[cpu]); + if (ret) + goto err_tcu_clocksource_cleanup; + + return 0; + +err_tcu_clocksource_cleanup: + clocksource_unregister(&ingenic_tcu->cs); + clk_disable_unprepare(ingenic_tcu->cs_clk); + clk_put(ingenic_tcu->cs_clk); + kfree(ingenic_tcu); + return ret; +} + static int __init ingenic_tcu_clocksource_init(struct device_node *np, struct ingenic_tcu *tcu) { @@ -239,6 +291,7 @@ static int __init ingenic_tcu_init(struct device_node *np) const struct ingenic_soc_info *soc_info = id->data; struct ingenic_tcu *tcu; struct regmap *map; + unsigned cpu = 0; long rate; int ret; @@ -252,13 +305,18 @@ static int __init ingenic_tcu_init(struct device_node *np) if (!tcu) return -ENOMEM; - /* Enable all TCU channels for PWM use by default except channels 0/1 */ - tcu->pwm_channels_mask = GENMASK(soc_info->num_channels - 1, 2); + /* + * Enable all TCU channels for PWM use by default except channels 0/1, + * and channel 2 if target CPU is JZ4780 and SMP is selected. + */ + tcu->pwm_channels_mask = GENMASK(soc_info->num_channels - 1, + NR_CPUS + 1); of_property_read_u32(np, "ingenic,pwm-channels-mask", (u32 *)&tcu->pwm_channels_mask); - /* Verify that we have at least two free channels */ - if (hweight8(tcu->pwm_channels_mask) > soc_info->num_channels - 2) { + /* Verify that we have at least NR_CPUS + 1 free channels */ + if (hweight8(tcu->pwm_channels_mask) > + soc_info->num_channels - NR_CPUS + 1) { pr_crit("%s: Invalid PWM channel mask: 0x%02lx\n", __func__, tcu->pwm_channels_mask); ret = -EINVAL; @@ -266,13 +324,27 @@ static int __init ingenic_tcu_init(struct device_node *np) } tcu->map = map; + tcu->np = np; ingenic_tcu = tcu; - tcu->timer_channel = find_first_zero_bit(&tcu->pwm_channels_mask, + tcu->timer_local[cpu] = find_first_zero_bit(&tcu->pwm_channels_mask, soc_info->num_channels); - tcu->cs_channel = find_next_zero_bit(&tcu->pwm_channels_mask, - soc_info->num_channels, - tcu->timer_channel + 1); + + if (NR_CPUS > 1) { + for (cpu = 1; cpu < NR_CPUS; cpu++) + tcu->timer_local[cpu] = find_next_zero_bit( + &tcu->pwm_channels_mask, + soc_info->num_channels, + tcu->timer_local[cpu - 1] + 1); + + tcu->cs_channel = find_next_zero_bit(&tcu->pwm_channels_mask, + soc_info->num_channels, + tcu->timer_local[cpu-1] + 1); + } else { + tcu->cs_channel = find_next_zero_bit(&tcu->pwm_channels_mask, + soc_info->num_channels, + tcu->timer_local[cpu] + 1); + } ret = ingenic_tcu_clocksource_init(np, tcu); if (ret) { @@ -280,9 +352,10 @@ static int __init ingenic_tcu_init(struct device_node *np) goto err_free_ingenic_tcu; } - ret = ingenic_tcu_timer_init(np, tcu); - if (ret) - goto err_tcu_clocksource_cleanup; + /* Setup clock events on each CPU core */ + ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "Ingenic XBurst: online", + ingenic_tcu_setup_cevt, NULL); + WARN_ON(ret < 0); /* Register the sched_clock at the end as there's no way to undo it */ rate = clk_get_rate(tcu->cs_clk); @@ -290,10 +363,6 @@ static int __init ingenic_tcu_init(struct device_node *np) return 0; -err_tcu_clocksource_cleanup: - clocksource_unregister(&tcu->cs); - clk_disable_unprepare(tcu->cs_clk); - clk_put(tcu->cs_clk); err_free_ingenic_tcu: kfree(tcu); return ret;