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[209.132.180.67]) by mx.google.com with ESMTP id l20si1459265pgc.817.2017.09.08.05.45.11; Fri, 08 Sep 2017 05:45:11 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=dt7SGoqk; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755668AbdIHMpJ (ORCPT + 6 others); Fri, 8 Sep 2017 08:45:09 -0400 Received: from mail-lf0-f47.google.com ([209.85.215.47]:37632 "EHLO mail-lf0-f47.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755036AbdIHMpI (ORCPT ); Fri, 8 Sep 2017 08:45:08 -0400 Received: by mail-lf0-f47.google.com with SMTP id 80so5409273lfy.4 for ; Fri, 08 Sep 2017 05:45:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=aK5c7kPpdCYpH7K6rkOUIFXOzYt8+dz+7wZCOQu7EYk=; b=dt7SGoqk2pj3ytblwPwPx9c62G0Rj764BXDluqgu4wTfOQrrB1YegDYQUfK9gTlZ+4 lMavuNHpULEpwwWZKyaqIsbN4NvySNHsD5T/oMQ6ssYmGX+QZmnoi4vNVgXa+xRqJjbc 5GInevvtBG2LDBNyTCeDaEPGA+fVxDdhUouMU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=aK5c7kPpdCYpH7K6rkOUIFXOzYt8+dz+7wZCOQu7EYk=; b=Zq2oDn1GlAkBryi0HT4l2XtZ24bSz/beNvxih3JfS6jlvlis4qgZsCT1nqVJwQMDju EmxqZ5KweSETpvI0hC6VX2L4VsRsY/o5q1buTMT6bzF2AoAn7+wfPHLtI0hAuICbb+z8 KLflnFe06uRFdBrNRUSKfJka4HDiX0h7QeHKVnv/LPCEGO+7anRGKVWuYcAn6RNfo8nx dUkc7iz20EsdCabxuTJ/vHkUKFTQarpdo1qgTj5ovS1Jil19t7zh7n0e/m61ZPOGnVEa s43m8QkNrDeeqOoADfhEOV/vGzouZfXoP9enutEa+p8qJzf0xOrsw1aX09QevhW+GkGB 3YIg== X-Gm-Message-State: AHPjjUiOCme8o4Phc6tqfG1wGD5lsDydjTc6RdXg6smFMoSfSMatOxqb S8DS8Z1yKayueEql X-Google-Smtp-Source: AOwi7QB8L09MHryJ/wwdfI9KNxPyzLy4VQSTdfxlt99g9nM4gXwHvKJv8+LJ9OijYqf0+1mQxN/xkQ== X-Received: by 10.46.9.67 with SMTP id 64mr1015996ljj.134.1504874706824; Fri, 08 Sep 2017 05:45:06 -0700 (PDT) Received: from genomnajs.ideon.se ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id n74sm304029lfn.19.2017.09.08.05.45.05 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 08 Sep 2017 05:45:05 -0700 (PDT) From: Linus Walleij To: Bjorn Helgaas , Lorenzo Pieralisi , Arnd Bergmann Cc: linux-pci@vger.kernel.org, Linus Walleij , devicetree@vger.kernel.org, Marc Gonzalez Subject: [PATCH 1/2 v4] PCI: v3: Update the device tree bindings Date: Fri, 8 Sep 2017 14:45:02 +0200 Message-Id: <20170908124503.4491-1-linus.walleij@linaro.org> X-Mailer: git-send-email 2.13.5 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The bindings for the V3 Semiconductor PCI bridge are a tad bit outdated and predates the more formal format we have adopted for the bindings. Update them a bit so it is easier to read, and add the Integrator AP- specific compatible so we can detect that we are running on that specific platform. Add a second register bank for the configuration memory area. The device tree specs does specify a memory range for configuration space but it is not applicable to custom accessors like this. Instead follow the pattern from the Versatile PCI adapter and simply add a second register bank for this memory. Cc: devicetree@vger.kernel.org Cc: Marc Gonzalez Acked-by: Rob Herring Signed-off-by: Linus Walleij --- ChangeLog v3->v4: - Add bus-range to the example and the required properties. ChangeLog v2->v3: - Add a second register bank for the config space. - Mention that nonpre and pre memory must be 256MB and adjacent - Make the prefetched and non-prefetched memory mapped 1:1 to the PCI address space so that local bus 0x40000000 and 0x50000000 maps to the *same* local (CPU) bus addresses. - Add reference to dma-ranges and that this is required. - Add an example from the ARM Integrator/AP - Rob ACKed an earlier version, he might want to have a glance at this before merging. ChangeLog v1->v2: - Added Rob's ACK. Bjorn: please merge this when you feel confident with it. --- .../devicetree/bindings/pci/v3-v360epc-pci.txt | 75 ++++++++++++++++++++-- 1 file changed, 68 insertions(+), 7 deletions(-) -- 2.13.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/pci/v3-v360epc-pci.txt b/Documentation/devicetree/bindings/pci/v3-v360epc-pci.txt index 30b364e504ba..11063293f761 100644 --- a/Documentation/devicetree/bindings/pci/v3-v360epc-pci.txt +++ b/Documentation/devicetree/bindings/pci/v3-v360epc-pci.txt @@ -2,14 +2,75 @@ V3 Semiconductor V360 EPC PCI bridge This bridge is found in the ARM Integrator/AP (Application Platform) -Integrator-specific notes: +Required properties: +- compatible: should be one of: + "v3,v360epc-pci" + "arm,integrator-ap-pci", "v3,v360epc-pci" +- reg: should contain two register areas: + first the base address of the V3 host bridge controller, 64KB + second the configuration area register space, 16MB +- interrupts: should contain a reference to the V3 error interrupt + as routed on the system. +- bus-range: see pci.txt +- ranges: this follows the standard PCI bindings in the IEEE Std + 1275-1994 (see pci.txt) with the following restriction: + - The non-prefetchable and prefetchable memory windows must + each be exactly 256MB (0x10000000) in size. + - The prefetchable memory window must be immediately adjacent + to the non-prefetcable memory window +- dma-ranges: three ranges for the inbound memory region. The ranges must + be aligned to a 1MB boundary, and may be 1MB, 2MB, 4MB, 8MB, 16MB, 32MB, + 64MB, 128MB, 256MB, 512MB, 1GB or 2GB in size. The memory should be marked + as pre-fetchable. Two ranges are supported by the hardware. -- syscon: should contain a link to the syscon device node (since +Integrator-specific required properties: +- syscon: should contain a link to the syscon device node, since on the Integrator, some registers in the syscon are required to - operate the V3). + operate the V3 host bridge. -V360 EPC specific notes: +Example: -- reg: should contain the base address of the V3 adapter. -- interrupts: should contain a reference to the V3 error interrupt - as routed on the system. +pci: pciv3@62000000 { + compatible = "arm,integrator-ap-pci", "v3,v360epc-pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0x62000000 0x10000>, <0x61000000 0x01000000>; + interrupt-parent = <&pic>; + interrupts = <17>; /* Bus error IRQ */ + clocks = <&pciclk>; + bus-range = <0x00 0xff>; + ranges = 0x01000000 0 0x00000000 /* I/O space @00000000 */ + 0x60000000 0 0x01000000 /* 16 MiB @ LB 60000000 */ + 0x02000000 0 0x40000000 /* non-prefectable memory @40000000 */ + 0x40000000 0 0x10000000 /* 256 MiB @ LB 40000000 1:1 */ + 0x42000000 0 0x50000000 /* prefetchable memory @50000000 */ + 0x50000000 0 0x10000000>; /* 256 MiB @ LB 50000000 1:1 */ + dma-ranges = <0x02000000 0 0x20000000 /* EBI memory space */ + 0x20000000 0 0x20000000 /* 512 MB @ LB 20000000 1:1 */ + 0x02000000 0 0x80000000 /* Core module alias memory */ + 0x80000000 0 0x40000000>; /* 1GB @ LB 80000000 */ + interrupt-map-mask = <0xf800 0 0 0x7>; + interrupt-map = < + /* IDSEL 9 */ + 0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */ + 0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */ + 0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */ + 0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */ + /* IDSEL 10 */ + 0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */ + 0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */ + 0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */ + 0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */ + /* IDSEL 11 */ + 0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */ + 0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */ + 0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */ + 0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */ + /* IDSEL 12 */ + 0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */ + 0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */ + 0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */ + 0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */ + >; +};