From patchwork Mon Feb 17 13:30:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akash Asthana X-Patchwork-Id: 214290 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A343C34021 for ; Mon, 17 Feb 2020 13:30:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3338E208C4 for ; Mon, 17 Feb 2020 13:30:47 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="jPdF7j9A" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728688AbgBQNaq (ORCPT ); Mon, 17 Feb 2020 08:30:46 -0500 Received: from mail27.static.mailgun.info ([104.130.122.27]:58801 "EHLO mail27.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728692AbgBQNaq (ORCPT ); Mon, 17 Feb 2020 08:30:46 -0500 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1581946246; h=References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=+WGApTuKqfOHM6DOZbs0hjT7LC6Y7rCmZikPNioYhqE=; b=jPdF7j9AgPBC65nPK3drV6ydUOVfQTdUCTXd5sZlfi8/BZGIjvXcTx54xeQid6d7/YuEuQAw zaMGO7SkgcuAbtGzHlO7enjoPeu++eY2ClkGJR7Yzq5dZVLn8Es41h5G4mrebS9prFabYWsE Ofpu97tga55VnwYs3mB6RQO6CRs= X-Mailgun-Sending-Ip: 104.130.122.27 X-Mailgun-Sid: WyIzZmY0MiIsICJsaW51eC1zZXJpYWxAdmdlci5rZXJuZWwub3JnIiwgImJlOWU0YSJd Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by mxa.mailgun.org with ESMTP id 5e4a9585.7f138d7c14c8-smtp-out-n03; Mon, 17 Feb 2020 13:30:45 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id AA409C4479C; Mon, 17 Feb 2020 13:30:43 +0000 (UTC) Received: from akashast-linux.qualcomm.com (blr-c-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: akashast) by smtp.codeaurora.org (Postfix) with ESMTPSA id E8FF0C43383; Mon, 17 Feb 2020 13:30:37 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org E8FF0C43383 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=akashast@codeaurora.org From: Akash Asthana To: gregkh@linuxfoundation.org, agross@kernel.org, bjorn.andersson@linaro.org, wsa@the-dreams.de, broonie@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org Cc: linux-i2c@vger.kernel.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, swboyd@chromium.org, mgautam@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-serial@vger.kernel.org, mka@chromium.org, dianders@chromium.org, Akash Asthana Subject: [PATCH 1/6] soc: qcom: geni: Support for ICC voting Date: Mon, 17 Feb 2020 19:00:00 +0530 Message-Id: <1581946205-27189-2-git-send-email-akashast@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1581946205-27189-1-git-send-email-akashast@codeaurora.org> References: <1581946205-27189-1-git-send-email-akashast@codeaurora.org> Sender: linux-serial-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Add necessary enums, macros and structure variables to support ICC BW voting from individual SE drivers. Signed-off-by: Akash Asthana --- include/linux/qcom-geni-se.h | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/include/linux/qcom-geni-se.h b/include/linux/qcom-geni-se.h index dd46494..b0adbfb 100644 --- a/include/linux/qcom-geni-se.h +++ b/include/linux/qcom-geni-se.h @@ -6,6 +6,8 @@ #ifndef _LINUX_QCOM_GENI_SE #define _LINUX_QCOM_GENI_SE +#include + /* Transfer mode supported by GENI Serial Engines */ enum geni_se_xfer_mode { GENI_SE_INVALID, @@ -22,6 +24,13 @@ enum geni_se_protocol_type { GENI_SE_I3C, }; +/* Interconnect paths for GENI */ +enum geni_se_icc_path { + GENI_TO_CORE, + CPU_TO_GENI, + GENI_TO_DDR +}; + struct geni_wrapper; struct clk; @@ -33,6 +42,13 @@ struct clk; * @clk: Handle to the core serial engine clock * @num_clk_levels: Number of valid clock levels in clk_perf_tbl * @clk_perf_tbl: Table of clock frequency input to serial engine clock + * @icc_path: Array of interconnect path handles + * @avg_bw_core: Average bus bandwidth value for QUP core 2x clock + * @peak_bw_core: Peak bus bandwidth value for QUP core 2x clock + * @avg_bw_cpu: Average bus bandwidth value for CPU + * @peak_bw_cpu: Peak bus bandwidth value for CPU + * @avg_bw_ddr: Average bus bandwidth value for DDR + * @peak_bw_ddr: Peak bus bandwidth value for DDR */ struct geni_se { void __iomem *base; @@ -41,6 +57,13 @@ struct geni_se { struct clk *clk; unsigned int num_clk_levels; unsigned long *clk_perf_tbl; + struct icc_path *icc_path[3]; + unsigned int avg_bw_core; + unsigned int peak_bw_core; + unsigned int avg_bw_cpu; + unsigned int peak_bw_cpu; + unsigned int avg_bw_ddr; + unsigned int peak_bw_ddr; }; /* Common SE registers */ @@ -229,6 +252,14 @@ struct geni_se { #define GENI_SE_VERSION_MINOR(ver) ((ver & HW_VER_MINOR_MASK) >> HW_VER_MINOR_SHFT) #define GENI_SE_VERSION_STEP(ver) (ver & HW_VER_STEP_MASK) +/* Core 2X clock frequency to BCM threshold mapping */ +#define CORE_2X_19_2_MHZ 960 +#define CORE_2X_50_MHZ 2500 +#define CORE_2X_100_MHZ 5000 +#define CORE_2X_150_MHZ 7500 +#define CORE_2X_200_MHZ 10000 +#define CORE_2X_236_MHZ 16383 + #if IS_ENABLED(CONFIG_QCOM_GENI_SE) u32 geni_se_get_qup_hw_version(struct geni_se *se); From patchwork Mon Feb 17 13:30:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akash Asthana X-Patchwork-Id: 214289 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DED69C33FA0 for ; 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Mon, 17 Feb 2020 13:30:54 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 43FE6C447A9; Mon, 17 Feb 2020 13:30:52 +0000 (UTC) Received: from akashast-linux.qualcomm.com (blr-c-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: akashast) by smtp.codeaurora.org (Postfix) with ESMTPSA id 39A56C43383; Mon, 17 Feb 2020 13:30:44 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 39A56C43383 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=akashast@codeaurora.org From: Akash Asthana To: gregkh@linuxfoundation.org, agross@kernel.org, bjorn.andersson@linaro.org, wsa@the-dreams.de, broonie@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org Cc: linux-i2c@vger.kernel.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, swboyd@chromium.org, mgautam@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-serial@vger.kernel.org, mka@chromium.org, dianders@chromium.org, Akash Asthana Subject: [PATCH 2/6] tty: serial: qcom_geni_serial: Add interconnect support Date: Mon, 17 Feb 2020 19:00:01 +0530 Message-Id: <1581946205-27189-3-git-send-email-akashast@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1581946205-27189-1-git-send-email-akashast@codeaurora.org> References: <1581946205-27189-1-git-send-email-akashast@codeaurora.org> Sender: linux-serial-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Get the interconnect paths for Uart based Serial Engine device and vote according to the baud rate requirement of the driver. Signed-off-by: Akash Asthana --- drivers/tty/serial/qcom_geni_serial.c | 84 ++++++++++++++++++++++++++++++----- 1 file changed, 74 insertions(+), 10 deletions(-) diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c index 191abb1..a8fb2b7 100644 --- a/drivers/tty/serial/qcom_geni_serial.c +++ b/drivers/tty/serial/qcom_geni_serial.c @@ -174,6 +174,35 @@ static struct qcom_geni_serial_port qcom_geni_console_port = { }, }; +static int geni_serial_icc_get(struct geni_se *se) +{ + if (!se) + return -EINVAL; + + se->icc_path[GENI_TO_CORE] = of_icc_get(se->dev, "qup-core"); + if (IS_ERR(se->icc_path[GENI_TO_CORE])) + return PTR_ERR(se->icc_path[GENI_TO_CORE]); + + se->icc_path[CPU_TO_GENI] = of_icc_get(se->dev, "qup-config"); + if (IS_ERR(se->icc_path[CPU_TO_GENI])) { + icc_put(se->icc_path[GENI_TO_CORE]); + se->icc_path[GENI_TO_CORE] = NULL; + return PTR_ERR(se->icc_path[CPU_TO_GENI]); + } + + return 0; +} + +void geni_serial_icc_put(struct geni_se *se) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(se->icc_path); i++) { + icc_put(se->icc_path[i]); + se->icc_path[i] = NULL; + } +} + static int qcom_geni_serial_request_port(struct uart_port *uport) { struct platform_device *pdev = to_platform_device(uport->dev); @@ -949,6 +978,12 @@ static void qcom_geni_serial_set_termios(struct uart_port *uport, ser_clk_cfg = SER_CLK_EN; ser_clk_cfg |= clk_div << CLK_DIV_SHFT; + /* Put BW vote only on CPU path as driver supports FIFO mode only */ + port->se.avg_bw_cpu = Bps_to_icc(baud); + port->se.peak_bw_cpu = Bps_to_icc(2 * baud); + icc_set_bw(port->se.icc_path[CPU_TO_GENI], port->se.avg_bw_cpu, + port->se.peak_bw_cpu); + /* parity */ tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG); tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG); @@ -1179,11 +1214,20 @@ static void qcom_geni_serial_pm(struct uart_port *uport, if (old_state == UART_PM_STATE_UNDEFINED) old_state = UART_PM_STATE_OFF; - if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) + if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) { + /* Put BW vote for core clocks and CPU */ + icc_set_bw(port->se.icc_path[GENI_TO_CORE], + port->se.avg_bw_core, port->se.peak_bw_core); + icc_set_bw(port->se.icc_path[CPU_TO_GENI], port->se.avg_bw_cpu, + port->se.peak_bw_cpu); geni_se_resources_on(&port->se); - else if (new_state == UART_PM_STATE_OFF && - old_state == UART_PM_STATE_ON) + } else if (new_state == UART_PM_STATE_OFF && + old_state == UART_PM_STATE_ON) { geni_se_resources_off(&port->se); + /* Remove BW vote from core clocks and CPU */ + icc_set_bw(port->se.icc_path[GENI_TO_CORE], 0, 0); + icc_set_bw(port->se.icc_path[CPU_TO_GENI], 0, 0); + } } static const struct uart_ops qcom_geni_console_pops = { @@ -1274,15 +1318,30 @@ static int qcom_geni_serial_probe(struct platform_device *pdev) port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS; port->tx_fifo_width = DEF_FIFO_WIDTH_BITS; + ret = geni_serial_icc_get(&port->se); + if (ret) + return ret; + /* Set the bus quota to a reasonable value */ + port->se.avg_bw_core = console ? Bps_to_icc(1000) : + Bps_to_icc(CORE_2X_50_MHZ); + port->se.peak_bw_core = console ? Bps_to_icc(1000) : + Bps_to_icc(CORE_2X_100_MHZ); + port->se.avg_bw_cpu = Bps_to_icc(1000); + port->se.avg_bw_cpu = Bps_to_icc(1000); + port->name = devm_kasprintf(uport->dev, GFP_KERNEL, "qcom_geni_serial_%s%d", uart_console(uport) ? "console" : "uart", uport->line); - if (!port->name) - return -ENOMEM; + if (!port->name) { + ret = -ENOMEM; + goto geni_serial_put_icc; + } irq = platform_get_irq(pdev, 0); - if (irq < 0) - return irq; + if (irq < 0) { + ret = irq; + goto geni_serial_put_icc; + } uport->irq = irq; uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE); @@ -1295,7 +1354,7 @@ static int qcom_geni_serial_probe(struct platform_device *pdev) ret = uart_add_one_port(drv, uport); if (ret) - return ret; + goto geni_serial_put_icc; irq_set_status_flags(uport->irq, IRQ_NOAUTOEN); ret = devm_request_irq(uport->dev, uport->irq, qcom_geni_serial_isr, @@ -1303,7 +1362,7 @@ static int qcom_geni_serial_probe(struct platform_device *pdev) if (ret) { dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret); uart_remove_one_port(drv, uport); - return ret; + goto geni_serial_put_icc; } /* @@ -1320,11 +1379,15 @@ static int qcom_geni_serial_probe(struct platform_device *pdev) if (ret) { device_init_wakeup(&pdev->dev, false); uart_remove_one_port(drv, uport); - return ret; + goto geni_serial_put_icc; } } return 0; + +geni_serial_put_icc: + geni_serial_icc_put(&port->se); + return ret; } static int qcom_geni_serial_remove(struct platform_device *pdev) @@ -1335,6 +1398,7 @@ static int qcom_geni_serial_remove(struct platform_device *pdev) dev_pm_clear_wake_irq(&pdev->dev); device_init_wakeup(&pdev->dev, false); uart_remove_one_port(drv, &port->uport); + geni_serial_icc_put(&port->se); return 0; } From patchwork Mon Feb 17 13:30:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akash Asthana X-Patchwork-Id: 214288 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 172F6C33FE0 for ; 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Mon, 17 Feb 2020 13:31:00 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 97FB0C447A9; Mon, 17 Feb 2020 13:30:59 +0000 (UTC) Received: from akashast-linux.qualcomm.com (blr-c-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: akashast) by smtp.codeaurora.org (Postfix) with ESMTPSA id 55501C4479F; Mon, 17 Feb 2020 13:30:53 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 55501C4479F Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=akashast@codeaurora.org From: Akash Asthana To: gregkh@linuxfoundation.org, agross@kernel.org, bjorn.andersson@linaro.org, wsa@the-dreams.de, broonie@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org Cc: linux-i2c@vger.kernel.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, swboyd@chromium.org, mgautam@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-serial@vger.kernel.org, mka@chromium.org, dianders@chromium.org, Akash Asthana Subject: [PATCH 3/6] i2c: i2c-qcom-geni: Add interconnect support Date: Mon, 17 Feb 2020 19:00:02 +0530 Message-Id: <1581946205-27189-4-git-send-email-akashast@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1581946205-27189-1-git-send-email-akashast@codeaurora.org> References: <1581946205-27189-1-git-send-email-akashast@codeaurora.org> Sender: linux-serial-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Get the interconnect paths for I2C based Serial Engine device and vote according to the bus speed of the driver. Signed-off-by: Akash Asthana --- drivers/i2c/busses/i2c-qcom-geni.c | 84 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 80 insertions(+), 4 deletions(-) diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c index 17abf60c..5de10a1 100644 --- a/drivers/i2c/busses/i2c-qcom-geni.c +++ b/drivers/i2c/busses/i2c-qcom-geni.c @@ -163,6 +163,44 @@ static void qcom_geni_i2c_conf(struct geni_i2c_dev *gi2c) writel_relaxed(val, gi2c->se.base + SE_I2C_SCL_COUNTERS); } +static int geni_i2c_icc_get(struct geni_se *se) +{ + if (!se) + return -EINVAL; + + se->icc_path[GENI_TO_CORE] = of_icc_get(se->dev, "qup-core"); + if (IS_ERR(se->icc_path[GENI_TO_CORE])) + return PTR_ERR(se->icc_path[GENI_TO_CORE]); + + se->icc_path[CPU_TO_GENI] = of_icc_get(se->dev, "qup-config"); + if (IS_ERR(se->icc_path[CPU_TO_GENI])) { + icc_put(se->icc_path[GENI_TO_CORE]); + se->icc_path[GENI_TO_CORE] = NULL; + return PTR_ERR(se->icc_path[CPU_TO_GENI]); + } + + se->icc_path[GENI_TO_DDR] = of_icc_get(se->dev, "qup-memory"); + if (IS_ERR(se->icc_path[GENI_TO_DDR])) { + icc_put(se->icc_path[GENI_TO_CORE]); + se->icc_path[GENI_TO_CORE] = NULL; + icc_put(se->icc_path[CPU_TO_GENI]); + se->icc_path[CPU_TO_GENI] = NULL; + return PTR_ERR(se->icc_path[GENI_TO_DDR]); + } + + return 0; +} + +void geni_i2c_icc_put(struct geni_se *se) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(se->icc_path); i++) { + icc_put(se->icc_path[i]); + se->icc_path[i] = NULL; + } +} + static void geni_i2c_err_misc(struct geni_i2c_dev *gi2c) { u32 m_cmd = readl_relaxed(gi2c->se.base + SE_GENI_M_CMD0); @@ -563,17 +601,34 @@ static int geni_i2c_probe(struct platform_device *pdev) gi2c->adap.dev.of_node = pdev->dev.of_node; strlcpy(gi2c->adap.name, "Geni-I2C", sizeof(gi2c->adap.name)); + ret = geni_i2c_icc_get(&gi2c->se); + if (ret) + return ret; + /* Set the bus quota to a reasonable value */ + gi2c->se.avg_bw_core = Bps_to_icc(1000); + gi2c->se.peak_bw_core = Bps_to_icc(CORE_2X_100_MHZ); + gi2c->se.avg_bw_cpu = Bps_to_icc(1000); + gi2c->se.peak_bw_cpu = Bps_to_icc(1000); + gi2c->se.avg_bw_ddr = Bps_to_icc(gi2c->clk_freq_out); + gi2c->se.peak_bw_ddr = Bps_to_icc(2 * gi2c->clk_freq_out); + + /* Vote for core clocks and CPU for register access */ + icc_set_bw(gi2c->se.icc_path[GENI_TO_CORE], gi2c->se.avg_bw_core, + gi2c->se.peak_bw_core); + icc_set_bw(gi2c->se.icc_path[CPU_TO_GENI], gi2c->se.avg_bw_cpu, + gi2c->se.peak_bw_cpu); ret = geni_se_resources_on(&gi2c->se); if (ret) { dev_err(&pdev->dev, "Error turning on resources %d\n", ret); - return ret; + goto geni_i2c_put_icc; } proto = geni_se_read_proto(&gi2c->se); tx_depth = geni_se_get_tx_fifo_depth(&gi2c->se); if (proto != GENI_SE_I2C) { dev_err(&pdev->dev, "Invalid proto %d\n", proto); geni_se_resources_off(&gi2c->se); - return -ENXIO; + ret = -ENXIO; + goto geni_i2c_put_icc; } gi2c->tx_wm = tx_depth - 1; geni_se_init(&gi2c->se, gi2c->tx_wm, tx_depth); @@ -582,8 +637,11 @@ static int geni_i2c_probe(struct platform_device *pdev) ret = geni_se_resources_off(&gi2c->se); if (ret) { dev_err(&pdev->dev, "Error turning off resources %d\n", ret); - return ret; + goto geni_i2c_put_icc; } + /* Remove vote from core clocks and CPU */ + icc_set_bw(gi2c->se.icc_path[GENI_TO_CORE], 0, 0); + icc_set_bw(gi2c->se.icc_path[CPU_TO_GENI], 0, 0); dev_dbg(&pdev->dev, "i2c fifo/se-dma mode. fifo depth:%d\n", tx_depth); @@ -597,12 +655,16 @@ static int geni_i2c_probe(struct platform_device *pdev) if (ret) { dev_err(&pdev->dev, "Error adding i2c adapter %d\n", ret); pm_runtime_disable(gi2c->se.dev); - return ret; + goto geni_i2c_put_icc; } dev_dbg(&pdev->dev, "Geni-I2C adaptor successfully added\n"); return 0; + +geni_i2c_put_icc: + geni_i2c_icc_put(&gi2c->se); + return ret; } static int geni_i2c_remove(struct platform_device *pdev) @@ -611,6 +673,7 @@ static int geni_i2c_remove(struct platform_device *pdev) i2c_del_adapter(&gi2c->adap); pm_runtime_disable(gi2c->se.dev); + geni_i2c_icc_put(&gi2c->se); return 0; } @@ -629,6 +692,11 @@ static int __maybe_unused geni_i2c_runtime_suspend(struct device *dev) gi2c->suspended = 1; } + /* Remove BW votes */ + icc_set_bw(gi2c->se.icc_path[GENI_TO_CORE], 0, 0); + icc_set_bw(gi2c->se.icc_path[CPU_TO_GENI], 0, 0); + icc_set_bw(gi2c->se.icc_path[GENI_TO_DDR], 0, 0); + return 0; } @@ -637,6 +705,14 @@ static int __maybe_unused geni_i2c_runtime_resume(struct device *dev) int ret; struct geni_i2c_dev *gi2c = dev_get_drvdata(dev); + /* Vote on Core, DDR and CPU path respectively */ + icc_set_bw(gi2c->se.icc_path[GENI_TO_CORE], gi2c->se.avg_bw_core, + gi2c->se.peak_bw_core); + icc_set_bw(gi2c->se.icc_path[CPU_TO_GENI], gi2c->se.avg_bw_cpu, + gi2c->se.peak_bw_cpu); + icc_set_bw(gi2c->se.icc_path[GENI_TO_DDR], gi2c->se.avg_bw_ddr, + gi2c->se.peak_bw_ddr); + ret = geni_se_resources_on(&gi2c->se); if (ret) return ret; From patchwork Mon Feb 17 13:30:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akash Asthana X-Patchwork-Id: 214287 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BCD03C34020 for ; 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Mon, 17 Feb 2020 13:31:24 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 39E87C4479F; Mon, 17 Feb 2020 13:31:24 +0000 (UTC) Received: from akashast-linux.qualcomm.com (blr-c-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: akashast) by smtp.codeaurora.org (Postfix) with ESMTPSA id 5B1E3C447A5; Mon, 17 Feb 2020 13:31:17 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 5B1E3C447A5 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=akashast@codeaurora.org From: Akash Asthana To: gregkh@linuxfoundation.org, agross@kernel.org, bjorn.andersson@linaro.org, wsa@the-dreams.de, broonie@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org Cc: linux-i2c@vger.kernel.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, swboyd@chromium.org, mgautam@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-serial@vger.kernel.org, mka@chromium.org, dianders@chromium.org, Akash Asthana Subject: [PATCH 6/6] arm64: dts: sc7180: Add interconnect for QUP and QSPI Date: Mon, 17 Feb 2020 19:00:05 +0530 Message-Id: <1581946205-27189-7-git-send-email-akashast@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1581946205-27189-1-git-send-email-akashast@codeaurora.org> References: <1581946205-27189-1-git-send-email-akashast@codeaurora.org> Sender: linux-serial-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Add interconnect ports for GENI QUPs and QSPI to set bus capabilities. Signed-off-by: Akash Asthana --- Note: - This patch depends on series https://patchwork.kernel.org/cover/11313817/ [Add SC7180 interconnect provider driver]. It won't compile without that. arch/arm64/boot/dts/qcom/sc7180.dtsi | 199 +++++++++++++++++++++++++++++++++++ 1 file changed, 199 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index cc5a94f..04569c9 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -352,6 +352,14 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&qup_virt MASTER_QUP_CORE_0 + &qup_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_QUP_0>, + <&aggre1_noc MASTER_QUP_0 + &mc_virt SLAVE_EBI1>; + interconnect-names = "qup-core", "qup-config", + "qup-memory"; status = "disabled"; }; @@ -365,6 +373,11 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&qup_virt MASTER_QUP_CORE_0 + &qup_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_QUP_0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -376,6 +389,11 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart0_default>; interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 + &qup_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_QUP_0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -389,6 +407,14 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&qup_virt MASTER_QUP_CORE_0 + &qup_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_QUP_0>, + <&aggre1_noc MASTER_QUP_0 + &mc_virt SLAVE_EBI1>; + interconnect-names = "qup-core", "qup-config", + "qup-memory"; status = "disabled"; }; @@ -402,6 +428,11 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&qup_virt MASTER_QUP_CORE_0 + &qup_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_QUP_0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -413,6 +444,11 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart1_default>; interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 + &qup_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_QUP_0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -426,6 +462,14 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&qup_virt MASTER_QUP_CORE_0 + &qup_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_QUP_0>, + <&aggre1_noc MASTER_QUP_0 + &mc_virt SLAVE_EBI1>; + interconnect-names = "qup-core", "qup-config", + "qup-memory"; status = "disabled"; }; @@ -437,6 +481,11 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart2_default>; interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 + &qup_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_QUP_0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -450,6 +499,14 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&qup_virt MASTER_QUP_CORE_0 + &qup_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_QUP_0>, + <&aggre1_noc MASTER_QUP_0 + &mc_virt SLAVE_EBI1>; + interconnect-names = "qup-core", "qup-config", + "qup-memory"; status = "disabled"; }; @@ -463,6 +520,11 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&qup_virt MASTER_QUP_CORE_0 + &qup_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_QUP_0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -474,6 +536,11 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart3_default>; interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 + &qup_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_QUP_0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -487,6 +554,14 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&qup_virt MASTER_QUP_CORE_0 + &qup_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_QUP_0>, + <&aggre1_noc MASTER_QUP_0 + &mc_virt SLAVE_EBI1>; + interconnect-names = "qup-core", "qup-config", + "qup-memory"; status = "disabled"; }; @@ -498,6 +573,11 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart4_default>; interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 + &qup_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_QUP_0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -511,6 +591,14 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&qup_virt MASTER_QUP_CORE_0 + &qup_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_QUP_0>, + <&aggre1_noc MASTER_QUP_0 + &mc_virt SLAVE_EBI1>; + interconnect-names = "qup-core", "qup-config", + "qup-memory"; status = "disabled"; }; @@ -524,6 +612,11 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&qup_virt MASTER_QUP_CORE_0 + &qup_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_QUP_0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -535,6 +628,11 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart5_default>; interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_0 + &qup_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_QUP_0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; }; @@ -561,6 +659,14 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&qup_virt MASTER_QUP_CORE_1 + &qup_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_QUP_1>, + <&aggre2_noc MASTER_QUP_1 + &mc_virt SLAVE_EBI1>; + interconnect-names = "qup-core", "qup-config", + "qup-memory"; status = "disabled"; }; @@ -574,6 +680,11 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&qup_virt MASTER_QUP_CORE_1 + &qup_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_QUP_1>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -585,6 +696,11 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart6_default>; interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_1 + &qup_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_QUP_1>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -598,6 +714,14 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&qup_virt MASTER_QUP_CORE_1 + &qup_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_QUP_1>, + <&aggre2_noc MASTER_QUP_1 + &mc_virt SLAVE_EBI1>; + interconnect-names = "qup-core", "qup-config", + "qup-memory"; status = "disabled"; }; @@ -609,6 +733,11 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart7_default>; interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_1 + &qup_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_QUP_1>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -622,6 +751,14 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&qup_virt MASTER_QUP_CORE_1 + &qup_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_QUP_1>, + <&aggre2_noc MASTER_QUP_1 + &mc_virt SLAVE_EBI1>; + interconnect-names = "qup-core", "qup-config", + "qup-memory"; status = "disabled"; }; @@ -635,6 +772,11 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&qup_virt MASTER_QUP_CORE_1 + &qup_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_QUP_1>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -646,6 +788,11 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart8_default>; interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_1 + &qup_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_QUP_1>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -659,6 +806,14 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&qup_virt MASTER_QUP_CORE_1 + &qup_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_QUP_1>, + <&aggre2_noc MASTER_QUP_1 + &mc_virt SLAVE_EBI1>; + interconnect-names = "qup-core", "qup-config", + "qup-memory"; status = "disabled"; }; @@ -670,6 +825,11 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart9_default>; interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_1 + &qup_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_QUP_1>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -683,6 +843,14 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&qup_virt MASTER_QUP_CORE_1 + &qup_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_QUP_1>, + <&aggre2_noc MASTER_QUP_1 + &mc_virt SLAVE_EBI1>; + interconnect-names = "qup-core", "qup-config", + "qup-memory"; status = "disabled"; }; @@ -696,6 +864,11 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&qup_virt MASTER_QUP_CORE_1 + &qup_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_QUP_1>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -707,6 +880,11 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart10_default>; interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_1 + &qup_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_QUP_1>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -720,6 +898,14 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&qup_virt MASTER_QUP_CORE_1 + &qup_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_QUP_1>, + <&aggre2_noc MASTER_QUP_1 + &mc_virt SLAVE_EBI1>; + interconnect-names = "qup-core", "qup-config", + "qup-memory"; status = "disabled"; }; @@ -733,6 +919,11 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&qup_virt MASTER_QUP_CORE_1 + &qup_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_QUP_1>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -744,6 +935,11 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart11_default>; interrupts = ; + interconnects = <&qup_virt MASTER_QUP_CORE_1 + &qup_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_QUP_1>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; }; @@ -1051,6 +1247,9 @@ clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, <&gcc GCC_QSPI_CORE_CLK>; clock-names = "iface", "core"; + interconnects = <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_QSPI_0>; + interconnect-names = "qspi-config"; status = "disabled"; };