From patchwork Mon May 4 13:02:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wan Ahmad Zainie X-Patchwork-Id: 214694 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E2452C47258 for ; Mon, 4 May 2020 13:04:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C5F6D2075A for ; Mon, 4 May 2020 13:04:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726796AbgEDNEg (ORCPT ); Mon, 4 May 2020 09:04:36 -0400 Received: from mga05.intel.com ([192.55.52.43]:6156 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726351AbgEDNEg (ORCPT ); Mon, 4 May 2020 09:04:36 -0400 IronPort-SDR: x08WHTwRg2dAEVK7+R20U8PT2giy7sJ9MBhJRKETdYVMFmBmdW45NIoluv2A+7W6c9GdFzYQUl cEkDX/aMIJzA== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 May 2020 06:03:56 -0700 IronPort-SDR: 4uEX6RVUPKH98FOpWi8oehV2U2DvOAE1QrAA1rsvyRBEnd+MgfnfJYtpCyP21PKo6Wmx0YRiBR psqFAofI2fLQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,352,1583222400"; d="scan'208";a="249169066" Received: from wwanmoha-ilbpg2.png.intel.com ([10.88.227.42]) by fmsmga007.fm.intel.com with ESMTP; 04 May 2020 06:03:53 -0700 From: Wan Ahmad Zainie To: broonie@kernel.org, robh+dt@kernel.org Cc: linux-spi@vger.kernel.org, devicetree@vger.kernel.org, andriy.shevchenko@linux.intel.com, wan.ahmad.zainie.wan.mohamad@intel.com Subject: [PATCH v4 1/7] spi: dw: Fix typo in few registers name Date: Mon, 4 May 2020 21:02:40 +0800 Message-Id: <20200504130246.5135-2-wan.ahmad.zainie.wan.mohamad@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200504130246.5135-1-wan.ahmad.zainie.wan.mohamad@intel.com> References: <20200504130246.5135-1-wan.ahmad.zainie.wan.mohamad@intel.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org This patch will fix typo in the register name used in the source code, to be consistent with the register name used in the databook. Databook: DW_apb_ssi_databook.pdf version 4.01a Signed-off-by: Wan Ahmad Zainie Reviewed-by: Andy Shevchenko --- drivers/spi/spi-dw.c | 18 +++++++++--------- drivers/spi/spi-dw.h | 8 ++++---- 2 files changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c index 31e3f866d11a..fbbafb099571 100644 --- a/drivers/spi/spi-dw.c +++ b/drivers/spi/spi-dw.c @@ -50,9 +50,9 @@ static ssize_t dw_spi_show_regs(struct file *file, char __user *user_buf, len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, "=================================\n"); len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, - "CTRL0: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL0)); + "CTRLR0: \t0x%08x\n", dw_readl(dws, DW_SPI_CTRLR0)); len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, - "CTRL1: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL1)); + "CTRLR1: \t0x%08x\n", dw_readl(dws, DW_SPI_CTRLR1)); len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, "SSIENR: \t0x%08x\n", dw_readl(dws, DW_SPI_SSIENR)); len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, @@ -60,9 +60,9 @@ static ssize_t dw_spi_show_regs(struct file *file, char __user *user_buf, len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, "BAUDR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_BAUDR)); len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, - "TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFLTR)); + "TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFTLR)); len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, - "RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFLTR)); + "RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFTLR)); len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, "TXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_TXFLR)); len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, @@ -340,7 +340,7 @@ static int dw_spi_transfer_one(struct spi_controller *master, cr0 |= (chip->tmode << SPI_TMOD_OFFSET); } - dw_writel(dws, DW_SPI_CTRL0, cr0); + dw_writel(dws, DW_SPI_CTRLR0, cr0); /* Check if current transfer is a DMA transaction */ if (master->can_dma && master->can_dma(master, spi, transfer)) @@ -361,7 +361,7 @@ static int dw_spi_transfer_one(struct spi_controller *master, } } else if (!chip->poll_mode) { txlevel = min_t(u16, dws->fifo_len / 2, dws->len / dws->n_bytes); - dw_writel(dws, DW_SPI_TXFLTR, txlevel); + dw_writel(dws, DW_SPI_TXFTLR, txlevel); /* Set the interrupt mask */ imask |= SPI_INT_TXEI | SPI_INT_TXOI | @@ -452,11 +452,11 @@ static void spi_hw_init(struct device *dev, struct dw_spi *dws) u32 fifo; for (fifo = 1; fifo < 256; fifo++) { - dw_writel(dws, DW_SPI_TXFLTR, fifo); - if (fifo != dw_readl(dws, DW_SPI_TXFLTR)) + dw_writel(dws, DW_SPI_TXFTLR, fifo); + if (fifo != dw_readl(dws, DW_SPI_TXFTLR)) break; } - dw_writel(dws, DW_SPI_TXFLTR, 0); + dw_writel(dws, DW_SPI_TXFTLR, 0); dws->fifo_len = (fifo == 1) ? 0 : fifo; dev_dbg(dev, "Detected FIFO size: %u bytes\n", dws->fifo_len); diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h index 1bf5713e047d..445362c23fde 100644 --- a/drivers/spi/spi-dw.h +++ b/drivers/spi/spi-dw.h @@ -6,14 +6,14 @@ #include /* Register offsets */ -#define DW_SPI_CTRL0 0x00 -#define DW_SPI_CTRL1 0x04 +#define DW_SPI_CTRLR0 0x00 +#define DW_SPI_CTRLR1 0x04 #define DW_SPI_SSIENR 0x08 #define DW_SPI_MWCR 0x0c #define DW_SPI_SER 0x10 #define DW_SPI_BAUDR 0x14 -#define DW_SPI_TXFLTR 0x18 -#define DW_SPI_RXFLTR 0x1c +#define DW_SPI_TXFTLR 0x18 +#define DW_SPI_RXFTLR 0x1c #define DW_SPI_TXFLR 0x20 #define DW_SPI_RXFLR 0x24 #define DW_SPI_SR 0x28 From patchwork Mon May 4 13:02:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wan Ahmad Zainie X-Patchwork-Id: 214693 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0ED8C4725B for ; Mon, 4 May 2020 13:04:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BFE152075A for ; Mon, 4 May 2020 13:04:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726922AbgEDNEh (ORCPT ); Mon, 4 May 2020 09:04:37 -0400 Received: from mga05.intel.com ([192.55.52.43]:6156 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726351AbgEDNEh (ORCPT ); Mon, 4 May 2020 09:04:37 -0400 IronPort-SDR: MoIYkP6QhY5TISmsvN6G0pyF2LdbPHDMq67hmRyV3D+nVRLewQ8ejPL1+FpP8OssXcQuJHu3me 7GK4zyPCwY9Q== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 May 2020 06:03:58 -0700 IronPort-SDR: qF6HrSXklwiqNHJ7VOpJedJGejGfNquucdxyRRf5CIb2J6YsSHTmGdJoVVV8G6BQIy+mb008Pa 8YoRCy4qp+rw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,352,1583222400"; d="scan'208";a="249169100" Received: from wwanmoha-ilbpg2.png.intel.com ([10.88.227.42]) by fmsmga007.fm.intel.com with ESMTP; 04 May 2020 06:03:57 -0700 From: Wan Ahmad Zainie To: broonie@kernel.org, robh+dt@kernel.org Cc: linux-spi@vger.kernel.org, devicetree@vger.kernel.org, andriy.shevchenko@linux.intel.com, wan.ahmad.zainie.wan.mohamad@intel.com Subject: [PATCH v4 3/7] spi: dw: Add support for DesignWare DWC_ssi Date: Mon, 4 May 2020 21:02:42 +0800 Message-Id: <20200504130246.5135-4-wan.ahmad.zainie.wan.mohamad@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200504130246.5135-1-wan.ahmad.zainie.wan.mohamad@intel.com> References: <20200504130246.5135-1-wan.ahmad.zainie.wan.mohamad@intel.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org This patch adds initial support for DesignWare DWC_ssi soft IP. DWC_ssi is the enhanced version of DW_apb_ssi, which is currently supported by this driver. Their registers are same, but the bit fields of register CTRLR0 are different. DWC_ssi has additional features compared to DW_apb_ssi. Major enhancements in DWC_ssi are hyper bus protocol, boot mode support and advanced XIP support. DWC_ssi is an AHB slave device, whilst DW_apb_ssi is an APB slave device. Register offset DW_ssi DW_apb_ssi CTRLR0 0x00 0x00 CTRLR1 0x04 0x04 SSIENR 0x08 0x08 MWCR 0x0c 0x0c SER 0x10 0x10 BAUDR 0x14 0x14 TXFTLR 0x18 0x18 RXFTLR 0x1c 0x1c TXFLR 0x20 0x20 RXFLR 0x24 0x24 SR 0x28 0x28 IMR 0x2c 0x2c ISR 0x30 0x30 RISR 0x34 0x34 TXOICR 0x38 0x38 RXOICR 0x3c 0x3c RXUICR 0x40 0x40 MSTICR 0x44 0x44 ICR 0x48 0x48 DMACR 0x4c 0x4c DMATDLR 0x50 0x50 DMARDLR 0x54 0x54 IDR 0x58 0x58 SSI_VERSION_ID 0x5c 0x5c DRx (0 to 35) 0x60+i*0x4 0x60+i*0x4 RX_SAMPLE_DLY 0xf0 0xf0 SPI_CTRLR0 0xf4 0xf4 TXD_DRIVE_EDGE 0xf8 0xf8 XIP_MODE_BITS 0xfc RSVD Register configuration - CTRLR0 DW_ssi DW_apb_ssi SPI_HYPERBUS_EN bit[24] NONE SPI_FRF bit[23:22] bit[22:21] DFS_32 NONE bit[20:16] CFS bit[19:16] bit[15:12] SSTE bit[14] bit[24] SRL bit[13] bit[11] SLV_OE bit[12] bit[10] TMOD bit[11:10] bit[9:8] SCPOL | SPHA bit[9:8] bit[7:6] FRF bit[7:6] bit[5:4] DFS bit[4:0] bit[3:0] The documents used are [1] DW_apb_ssi_databook.pdf version 4.01a (2016.10a). [2] DWC_ssi_databook.pdf version 1.01a. Signed-off-by: Wan Ahmad Zainie Reviewed-by: Andy Shevchenko --- drivers/spi/spi-dw-mmio.c | 10 ++++++++++ drivers/spi/spi-dw.c | 41 +++++++++++++++++++++++++++++++++++++++ drivers/spi/spi-dw.h | 12 ++++++++++++ 3 files changed, 63 insertions(+) diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c index a52f75e22109..1df6f3deee2c 100644 --- a/drivers/spi/spi-dw-mmio.c +++ b/drivers/spi/spi-dw-mmio.c @@ -146,6 +146,15 @@ static int dw_spi_dw_apb_init(struct platform_device *pdev, return 0; } +static int dw_spi_dwc_ssi_init(struct platform_device *pdev, + struct dw_spi_mmio *dwsmmio) +{ + /* Register hook to configure CTRLR0 */ + dwsmmio->dws.update_cr0 = dw_spi_update_cr0_v1_01a; + + return 0; +} + static int dw_spi_mmio_probe(struct platform_device *pdev) { int (*init_func)(struct platform_device *pdev, @@ -244,6 +253,7 @@ static const struct of_device_id dw_spi_mmio_of_match[] = { { .compatible = "mscc,jaguar2-spi", .data = dw_spi_mscc_jaguar2_init}, { .compatible = "amazon,alpine-dw-apb-ssi", .data = dw_spi_alpine_init}, { .compatible = "renesas,rzn1-spi", .data = dw_spi_dw_apb_init}, + { .compatible = "snps,dwc-ssi-1.01a", .data = dw_spi_dwc_ssi_init}, { /* end of table */} }; MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match); diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c index b475fd32f39a..109894d20194 100644 --- a/drivers/spi/spi-dw.c +++ b/drivers/spi/spi-dw.c @@ -318,6 +318,47 @@ u32 dw_spi_update_cr0(struct spi_controller *master, struct spi_device *spi, } EXPORT_SYMBOL_GPL(dw_spi_update_cr0); +/* Configure CTRLR0 for DWC_ssi */ +u32 dw_spi_update_cr0_v1_01a(struct spi_controller *master, + struct spi_device *spi, + struct spi_transfer *transfer) +{ + struct dw_spi *dws = spi_controller_get_devdata(master); + struct chip_data *chip = spi_get_ctldata(spi); + u32 cr0; + + /* CTRLR0[ 4: 0] Data Frame Size */ + cr0 = (transfer->bits_per_word - 1); + + /* CTRLR0[ 7: 6] Frame Format */ + cr0 |= chip->type << DWC_SSI_CTRLR0_FRF_OFFSET; + + /* + * SPI mode (SCPOL|SCPH) + * CTRLR0[ 8] Serial Clock Phase + * CTRLR0[ 9] Serial Clock Polarity + */ + cr0 |= ((spi->mode & SPI_CPOL) ? 1 : 0) << DWC_SSI_CTRLR0_SCPOL_OFFSET; + cr0 |= ((spi->mode & SPI_CPHA) ? 1 : 0) << DWC_SSI_CTRLR0_SCPH_OFFSET; + + /* CTRLR0[11:10] Transfer Mode */ + cr0 |= chip->tmode << DWC_SSI_CTRLR0_TMOD_OFFSET; + + /* CTRLR0[13] Shift Register Loop */ + cr0 |= ((spi->mode & SPI_LOOP) ? 1 : 0) << DWC_SSI_CTRLR0_SRL_OFFSET; + + /* Adjust Transfer Mode if necessary */ + if (chip->cs_control) { + chip->tmode = dw_spi_update_tmode(dws); + + cr0 &= ~DWC_SSI_CTRLR0_TMOD_MASK; + cr0 |= chip->tmode << DWC_SSI_CTRLR0_TMOD_OFFSET; + } + + return cr0; +} +EXPORT_SYMBOL_GPL(dw_spi_update_cr0_v1_01a); + static int dw_spi_transfer_one(struct spi_controller *master, struct spi_device *spi, struct spi_transfer *transfer) { diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h index d4d3b0b6f5d5..9c237d56f213 100644 --- a/drivers/spi/spi-dw.h +++ b/drivers/spi/spi-dw.h @@ -57,6 +57,15 @@ #define SPI_SRL_OFFSET 11 #define SPI_CFS_OFFSET 12 +/* Bit fields in CTRLR0 based on DWC_ssi_databook.pdf v1.01a */ +#define DWC_SSI_CTRLR0_SRL_OFFSET 13 +#define DWC_SSI_CTRLR0_TMOD_OFFSET 10 +#define DWC_SSI_CTRLR0_TMOD_MASK GENMASK(11, 10) +#define DWC_SSI_CTRLR0_SCPOL_OFFSET 9 +#define DWC_SSI_CTRLR0_SCPH_OFFSET 8 +#define DWC_SSI_CTRLR0_FRF_OFFSET 6 +#define DWC_SSI_CTRLR0_DFS_OFFSET 0 + /* Bit fields in SR, 7 bits */ #define SR_MASK 0x7f /* cover 7 bits */ #define SR_BUSY (1 << 0) @@ -257,6 +266,9 @@ extern int dw_spi_resume_host(struct dw_spi *dws); extern u32 dw_spi_update_cr0(struct spi_controller *master, struct spi_device *spi, struct spi_transfer *transfer); +extern u32 dw_spi_update_cr0_v1_01a(struct spi_controller *master, + struct spi_device *spi, + struct spi_transfer *transfer); /* platform related setup */ extern int dw_spi_mid_init(struct dw_spi *dws); /* Intel MID platforms */ From patchwork Mon May 4 13:02:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wan Ahmad Zainie X-Patchwork-Id: 214692 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8A436C3A5A9 for ; Mon, 4 May 2020 13:04:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5816E2073E for ; Mon, 4 May 2020 13:04:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727783AbgEDNEi (ORCPT ); Mon, 4 May 2020 09:04:38 -0400 Received: from mga05.intel.com ([192.55.52.43]:6156 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726660AbgEDNEh (ORCPT ); Mon, 4 May 2020 09:04:37 -0400 IronPort-SDR: MMDZHUg+UlLhHvR6Y5PMY0sDozXHLXj9x85BLirYhWtWFeMXz9AYW7rsxRdjLVc+vVkZfqdZMV li0oGtiJn9vg== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 May 2020 06:04:00 -0700 IronPort-SDR: VfPxaO3d5Pta7yhcFCav7keMRILjwPMES74yCvUPuw/XU3NFkPd8cimQufimzVd9evQKXzIKfV ayvEVp2zQUgQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,352,1583222400"; d="scan'208";a="249169114" Received: from wwanmoha-ilbpg2.png.intel.com ([10.88.227.42]) by fmsmga007.fm.intel.com with ESMTP; 04 May 2020 06:03:59 -0700 From: Wan Ahmad Zainie To: broonie@kernel.org, robh+dt@kernel.org Cc: linux-spi@vger.kernel.org, devicetree@vger.kernel.org, andriy.shevchenko@linux.intel.com, wan.ahmad.zainie.wan.mohamad@intel.com Subject: [PATCH v4 4/7] dt-bindings: spi: dw-apb-ssi: Add compatible string for DesignWare DWC_ssi Date: Mon, 4 May 2020 21:02:43 +0800 Message-Id: <20200504130246.5135-5-wan.ahmad.zainie.wan.mohamad@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200504130246.5135-1-wan.ahmad.zainie.wan.mohamad@intel.com> References: <20200504130246.5135-1-wan.ahmad.zainie.wan.mohamad@intel.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org This patch adds compatible string "snps,dwc-ssi-1.01a" to the above DT binding document, to provide support for DesignWare DWC_ssi IP [1]. Current driver supports DW_apb_ssi IP [2]. References: [1] https://www.synopsys.com/dw/ipdir.php?c=dwc_ssi [2] https://www.synopsys.com/dw/ipdir.php?c=DW_apb_ssi Signed-off-by: Wan Ahmad Zainie --- Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt index 3ed08ee9feba..2ead46b633ea 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt @@ -2,7 +2,7 @@ Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface. Required properties: - compatible : "snps,dw-apb-ssi" or "mscc,-spi", where soc is "ocelot" or - "jaguar2", or "amazon,alpine-dw-apb-ssi" + "jaguar2", or "amazon,alpine-dw-apb-ssi", or "snps,dwc-ssi-1.01a" - reg : The register base for the controller. For "mscc,-spi", a second register set is required (named ICPU_CFG:SPI_MST) - interrupts : One interrupt, used by the controller. From patchwork Mon May 4 13:02:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wan Ahmad Zainie X-Patchwork-Id: 214691 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD06DC47258 for ; Mon, 4 May 2020 13:04:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C02002073B for ; Mon, 4 May 2020 13:04:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727786AbgEDNEj (ORCPT ); Mon, 4 May 2020 09:04:39 -0400 Received: from mga05.intel.com ([192.55.52.43]:6159 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726660AbgEDNEj (ORCPT ); Mon, 4 May 2020 09:04:39 -0400 IronPort-SDR: 6QGzARkDtTETT1rxyRnOd3iZK5tUBgQr3mAA43T9qRicEavLSWD5jF3AgUuLqMibGJ8AwkF1tV YkKvkNcdYu3Q== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 May 2020 06:04:04 -0700 IronPort-SDR: Jp3+BuxZTFbOqwkr1LxJ9advre9i//UJItPnZzX3Q1xd9vc72gHqCdYMaI/3gyiLcSAAg/POtG 3iOKid0EXJPw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,352,1583222400"; d="scan'208";a="249169148" Received: from wwanmoha-ilbpg2.png.intel.com ([10.88.227.42]) by fmsmga007.fm.intel.com with ESMTP; 04 May 2020 06:04:02 -0700 From: Wan Ahmad Zainie To: broonie@kernel.org, robh+dt@kernel.org Cc: linux-spi@vger.kernel.org, devicetree@vger.kernel.org, andriy.shevchenko@linux.intel.com, wan.ahmad.zainie.wan.mohamad@intel.com Subject: [PATCH v4 6/7] dt-bindings: spi: dw-apb-ssi: Add Intel Keem Bay support Date: Mon, 4 May 2020 21:02:45 +0800 Message-Id: <20200504130246.5135-7-wan.ahmad.zainie.wan.mohamad@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200504130246.5135-1-wan.ahmad.zainie.wan.mohamad@intel.com> References: <20200504130246.5135-1-wan.ahmad.zainie.wan.mohamad@intel.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Document Intel Keem Bay SPI controller DT bindings. Signed-off-by: Wan Ahmad Zainie --- Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt index 2ead46b633ea..7a4702edf896 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt @@ -2,7 +2,8 @@ Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface. Required properties: - compatible : "snps,dw-apb-ssi" or "mscc,-spi", where soc is "ocelot" or - "jaguar2", or "amazon,alpine-dw-apb-ssi", or "snps,dwc-ssi-1.01a" + "jaguar2", or "amazon,alpine-dw-apb-ssi", or "snps,dwc-ssi-1.01a" or + "intel,keembay-ssi" - reg : The register base for the controller. For "mscc,-spi", a second register set is required (named ICPU_CFG:SPI_MST) - interrupts : One interrupt, used by the controller.