From patchwork Tue Sep 12 10:36:16 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 112289 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp4986311qgf; Tue, 12 Sep 2017 03:38:43 -0700 (PDT) X-Google-Smtp-Source: ADKCNb6L2q1hMSr1cZcjoIIlnFimRmuUDzwNCNUVojpN9jCbAbCeeq+3+NOjDSaHhVd6A/YZPwV1 X-Received: by 10.107.186.195 with SMTP id k186mr18212039iof.43.1505212723714; Tue, 12 Sep 2017 03:38:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505212723; cv=none; d=google.com; s=arc-20160816; b=z3PddWx+kRosopW6O+IIPRclnwtk29+E/IWmms/UA53Os4ho2o477ZJqDZjxZgoJiw fTwWZMDEI4JuN49JD50qC8tS4vOI+qYIO9TfrXl/4ZfVdjiN5gPQcO/0jLREjt6YPMPH L5sBhg/KJN9Uy45ALZMAzDHo7i01SU+N6WmGfEemQn0ajgV7ICdkDZ7csK5GBRgKNNmE BRowa4i/GLTovQN2DV45aJriFrAVWN7uDV0inLFGBBSDa8oZcOW6MWJLLSQC2KReWpWx G9dCnXFyn6yEfK2yv/uFQ+UbtWcbAhR0Nin77AvDoF1/kUyJ8HfjAqKxiy5HfVtd63RL t2Gw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=KS6Q9YVa7qmOc5SvqCTmk13b+IrRZVcvj1AMT3IpIW8=; b=gD9ZC91pOnZ9Yuk5qOxbfGWQzBD5rbW+A3k/4GoYJ9SsjyR5H5tEnHSF4s7jXUO+Qs MPNedvYZ/90o6mEYbC74K+/KsHRVbrAiBIoomo/NRBzeammYv/xlRfZ0XTfUSFkMpfNZ CbDYAZzrCOE7hWbcCg1Tm4vjP+8W7AbZsSWNgcKnnGzjz1wj7OS9aCKMe6j4KKpCvDJZ By0gjGjTKpCvIHRXq4IBOl7t7P/YGVOG0jYgN0LCp2LfNEDE3LRiLEF9jTy0EkBH/wn2 714JMNmKc8AdpMGVCuauhBMjXc3/nPJXWy4m+NbYBH6/FOFFCC4C/OeWyxwy1E5iEawo +rcw== ARC-Authentication-Results: i=1; mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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banners=-,-,- X-VirusChecked: Checked Received: (qmail 25125 invoked from network); 12 Sep 2017 10:36:31 -0000 Received: from usa-sjc-mx-foss1.foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-5.tower-206.messagelabs.com with SMTP; 12 Sep 2017 10:36:31 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 74B4615A2; Tue, 12 Sep 2017 03:36:30 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8593B3F578; Tue, 12 Sep 2017 03:36:29 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Tue, 12 Sep 2017 11:36:16 +0100 Message-Id: <20170912103622.18562-2-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170912103622.18562-1-julien.grall@arm.com> References: <20170912103622.18562-1-julien.grall@arm.com> Cc: bhupinder.thakur@linaro.org, Julien Grall , sstabellini@kernel.org Subject: [Xen-devel] [PATCH v2 1/7] xen/arm: traps: Re-order the includes alphabetically X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" Signed-off-by: Julien Grall Acked-by: Bhupinder Thakur Reviewed-by: Stefano Stabellini --- Changes in v2: - Fix alphabetical order - Add Bhupinder's acked-by --- xen/arch/arm/traps.c | 40 +++++++++++++++++++++------------------- 1 file changed, 21 insertions(+), 19 deletions(-) diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 7f6ec15b5e..6b3dfd9bcf 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -16,41 +16,43 @@ * GNU General Public License for more details. */ +#include +#include +#include #include -#include -#include -#include -#include +#include #include #include #include +#include #include -#include -#include -#include -#include #include +#include +#include +#include +#include +#include #include -#include -#include + #include #include -#include -#include -#include + +#include #include -#include -#include +#include #include +#include +#include #include +#include +#include #include +#include +#include +#include #include "decode.h" #include "vtimer.h" -#include -#include -#include -#include /* The base of the stack must always be double-word aligned, which means * that both the kernel half of struct cpu_user_regs (which is pushed in From patchwork Tue Sep 12 10:36:17 2017 Content-Type: text/plain; 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[192.237.175.120]) by mx.google.com with ESMTPS id i140si541459itb.186.2017.09.12.03.38.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Sep 2017 03:38:46 -0700 (PDT) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1driYU-0001O7-Ta; Tue, 12 Sep 2017 10:36:34 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1driYT-0001NV-Jg for xen-devel@lists.xen.org; Tue, 12 Sep 2017 10:36:33 +0000 Received: from [193.109.254.147] by server-1.bemta-6.messagelabs.com id 18/35-03414-0B8B7B95; Tue, 12 Sep 2017 10:36:32 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrILMWRWlGSWpSXmKPExsVysyfVTXfDju2 RBu+2iVgs+biYxYHR4+ju30wBjFGsmXlJ+RUJrBk/D15lKXjFVfHs/GKWBsZJnF2MXBxCApsZ Jfr+bGCDcE4zSqza2cTaxcjJwSagKXHn8ycmEFtEQFri2ufLjCA2s0CcxPtFjSwgtrBAsMTiz qVgcRYBVYmLO3+A1fMKWEpsXr2AHcSWEJCX2NV2EWwmp4CVxKJXC4B6OYCWWUpc2iw5gZF7AS PDKkb14tSistQiXTO9pKLM9IyS3MTMHF1DAzO93NTi4sT01JzEpGK95PzcTYxA7zIAwQ7GeSf 8DzFKcjApifIeWb89UogvKT+lMiOxOCO+qDQntfgQowwHh5IE78ntQDnBotT01Iq0zBxgmMGk JTh4lER4z4GkeYsLEnOLM9MhUqcYdTk6bt79wyTEkpeflyolznsTpEgApCijNA9uBCzkLzHKS gnzMgIdJcRTkFqUm1mCKv+KUZyDUUmY9yrIFJ7MvBK4Ta+AjmACOoLn0haQI0oSEVJSDYxKTS rqRZGR05bWb166NvPmOuUFYR6GjAcC/m1csyCEJ3uFSfKz6Js/7CpaMmeWvBbynOUR87LP8va On4d8T3QdVFXjOVJ0kHOT+oS+DbtmL/68o8stx9ymKOpEj9nPWf1/mPOPC6//Of2g5LI1DQWb Hfn/m1xJsLH7fUDzzYW60nmS+Y+dDPKUWIozEg21mIuKEwG2+KxLdAIAAA== X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-3.tower-27.messagelabs.com!1505212591!116032986!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.4.45; banners=-,-,- X-VirusChecked: Checked Received: (qmail 23115 invoked from network); 12 Sep 2017 10:36:32 -0000 Received: from usa-sjc-mx-foss1.foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-3.tower-27.messagelabs.com with SMTP; 12 Sep 2017 10:36:32 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9E5CE15BF; Tue, 12 Sep 2017 03:36:31 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B04703F578; Tue, 12 Sep 2017 03:36:30 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Tue, 12 Sep 2017 11:36:17 +0100 Message-Id: <20170912103622.18562-3-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170912103622.18562-1-julien.grall@arm.com> References: <20170912103622.18562-1-julien.grall@arm.com> Cc: bhupinder.thakur@linaro.org, Julien Grall , sstabellini@kernel.org Subject: [Xen-devel] [PATCH v2 2/7] xen/arm: Move arch/arm/vtimer.h to include/asm-arm/vtimer.h X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" It will be necessary to include vtimer.h from subdirectory making the inclusion a bit awkward. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- xen/arch/arm/domain.c | 2 +- xen/arch/arm/traps.c | 2 +- xen/{arch/arm => include/asm-arm}/vtimer.h | 0 3 files changed, 2 insertions(+), 2 deletions(-) rename xen/{arch/arm => include/asm-arm}/vtimer.h (100%) diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c index 6512f01463..784ae392cf 100644 --- a/xen/arch/arm/domain.c +++ b/xen/arch/arm/domain.c @@ -33,8 +33,8 @@ #include #include #include +#include -#include "vtimer.h" #include "vuart.h" DEFINE_PER_CPU(struct vcpu *, curr_vcpu); diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 6b3dfd9bcf..6f32f700e5 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -50,9 +50,9 @@ #include #include #include +#include #include "decode.h" -#include "vtimer.h" /* The base of the stack must always be double-word aligned, which means * that both the kernel half of struct cpu_user_regs (which is pushed in diff --git a/xen/arch/arm/vtimer.h b/xen/include/asm-arm/vtimer.h similarity index 100% rename from xen/arch/arm/vtimer.h rename to xen/include/asm-arm/vtimer.h From patchwork Tue Sep 12 10:36:18 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 112292 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp4986358qgf; Tue, 12 Sep 2017 03:38:45 -0700 (PDT) X-Google-Smtp-Source: AOwi7QBadUKLtp5xF0opI5QHNIqZ9gEs6U04/hEGuIJ+iSnnPcoLq9RH2VrTL6BeMQNViDCroTgv X-Received: by 10.36.36.67 with SMTP id f64mr374336ita.10.1505212725868; Tue, 12 Sep 2017 03:38:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505212725; cv=none; d=google.com; s=arc-20160816; b=KJbDnS6ATP4c+Mn/g9zUS9XWX/OgihX3y2JV/xq1teuZlQOJBJ2yVgU4lR/KdGF8h8 DzrRt15K8p8Vkn43pEjzCK040F4tiZXjHmrYVD62lI+WMe2hRo2VwqrwUOhXEVUpkBhN //+hA4MQ5UNpllggfwhHTZNNRJp1/sDv3kAmdWFGaFeTvrZSCWhD8N8LPVOyN/CLclpY exnFtvE3V5/zI+vk3n1EYCgyArrA/FOIsIcp4mbPQ6ak+1MhpW9qgkzOHAdEUiQg1igc OOeXAKiwn6nO0FQtGHG5lZVi6tkpCIY1usDMFDVFLhToieELdEfQWQfZmWH8SiwwvubC AJng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=laPO2nbLoU127BbGlW3P7vygrLiWeCyLRdiN3v1e6H4=; b=EJiU0EDjXv1lmHNLyjgDtNRKuYLxCBkBptqdVuuk5hL+NOI0n0t6K4+6Q3WYzHp3j9 fCEqm3o+D1L994FbA1AxTIOgCwO0JvgbDREXuxMg7VWNI/66Grm/pDAAQ9p+BcPT4xJg S/Bp84/VvPziAE8De//EQLECe7VbctcMvIqfiXmBchl2UZVd4/HiprCYQAsNmpUl/8ir vGj2WTIJ4+3p3dnXh5aHG1iQOUGakh1GW1e3g9i1cb1/5K0atXwX5/vsCcxUMQ/8QkGO Gi+PG02URXSP0MrtCCgWoSTYSlQDTR+8EhUw4vEBuAvW8jYxbqZN1c+NI9c8Tx2W+BBe eh2g== ARC-Authentication-Results: i=1; mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id y11si10564117iod.293.2017.09.12.03.38.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Sep 2017 03:38:45 -0700 (PDT) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1driYX-0001On-Ba; Tue, 12 Sep 2017 10:36:37 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1driYW-0001OO-1d for xen-devel@lists.xen.org; Tue, 12 Sep 2017 10:36:36 +0000 Received: from [193.109.254.147] by server-8.bemta-6.messagelabs.com id 5D/EA-17770-3B8B7B95; Tue, 12 Sep 2017 10:36:35 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrPLMWRWlGSWpSXmKPExsVysyfVTXfjju2 RBp8aDSyWfFzM4sDocXT3b6YAxijWzLyk/IoE1oydt7awFOwxqfi/axpLA+NV9S5GLg4hgc2M Eks3T2SBcE4zSnR/72HtYuTkYBPQlLjz+RMTiC0iIC1x7fNlRhCbWaBa4v/Ck2xdjBwcwgKhE md2h4KYLAKqEtdvqoBU8ApYSuxo+ckOYksIyEvsarsINpFTwEpi0asFLCDlQkA1lzZLTmDkXs DIsIpRvTi1qCy1SNdUL6koMz2jJDcxM0fX0MBMLze1uDgxPTUnMalYLzk/dxMj0LMMQLCDcfp l/0OMkhxMSqK8R9ZvjxTiS8pPqcxILM6ILyrNSS0+xCjDwaEkwSuyHSgnWJSanlqRlpkDDDGY tAQHj5IIbzhImre4IDG3ODMdInWKUZej4+bdP0xCLHn5ealS4ry/tgEVCYAUZZTmwY2AhfslR lkpYV5GoKOEeApSi3IzS1DlXzGKczAqCfOagqziycwrgdv0CugIJqAjeC5tATmiJBEhJdXAeK QmtKXt15QWKVkBXt6m7ZXemc+3PoyuL1D4ofmYMcd43am1FStvSe4ws9n5e8vm/ObAg0oS4TN KbkxVNO7ep1anUeL3uuC9wrXqloWcn1+eeXjkQr386jfc577573p440nRLM2JaWF36x7x6zZt t3CSsdIWeSjlLDc/m7/whLTo5N55ddv9lFiKMxINtZiLihMBBTqGsnICAAA= X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-13.tower-27.messagelabs.com!1505212593!106800360!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.4.45; banners=-,-,- X-VirusChecked: Checked Received: (qmail 11912 invoked from network); 12 Sep 2017 10:36:33 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-13.tower-27.messagelabs.com with SMTP; 12 Sep 2017 10:36:33 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EBDCD1529; Tue, 12 Sep 2017 03:36:32 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id DA0DE3F578; Tue, 12 Sep 2017 03:36:31 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Tue, 12 Sep 2017 11:36:18 +0100 Message-Id: <20170912103622.18562-4-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170912103622.18562-1-julien.grall@arm.com> References: <20170912103622.18562-1-julien.grall@arm.com> Cc: bhupinder.thakur@linaro.org, Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com Subject: [Xen-devel] [PATCH v2 3/7] xen/arm: traps: Export a bunch of helpers to handle emulation X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" A follow-up patch will move some parts of traps.c in separate files. The will require to use helpers that are currently statically defined. Export the following helpers: - inject_undef64_exception - inject_undef_exception - check_conditional_instr - advance_pc - handle_raz_wi - handle_wo_wi - handle_ro_raz Note that asm-arm/arm32/traps.h is empty but it is to keep parity with the arm64 counterpart. Signed-off-by: Julien Grall --- Cc: volodymyr_babchuk@epam.com Changes in v2: - Fixup guards - Add newline for clarity --- xen/arch/arm/traps.c | 43 +++++++++++++++++++-------------------- xen/include/asm-arm/arm32/traps.h | 13 ++++++++++++ xen/include/asm-arm/arm64/traps.h | 15 ++++++++++++++ xen/include/asm-arm/traps.h | 36 ++++++++++++++++++++++++++++++++ 4 files changed, 85 insertions(+), 22 deletions(-) create mode 100644 xen/include/asm-arm/arm32/traps.h create mode 100644 xen/include/asm-arm/arm64/traps.h create mode 100644 xen/include/asm-arm/traps.h diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 6f32f700e5..1c334a7b99 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -49,6 +49,7 @@ #include #include #include +#include #include #include @@ -547,7 +548,7 @@ static vaddr_t exception_handler64(struct cpu_user_regs *regs, vaddr_t offset) } /* Inject an undefined exception into a 64 bit guest */ -static void inject_undef64_exception(struct cpu_user_regs *regs, int instr_len) +void inject_undef64_exception(struct cpu_user_regs *regs, int instr_len) { vaddr_t handler; const union hsr esr = { @@ -620,8 +621,7 @@ static void inject_iabt64_exception(struct cpu_user_regs *regs, #endif -static void inject_undef_exception(struct cpu_user_regs *regs, - const union hsr hsr) +void inject_undef_exception(struct cpu_user_regs *regs, const union hsr hsr) { if ( is_32bit_domain(current->domain) ) inject_undef32_exception(regs); @@ -1714,8 +1714,7 @@ static const unsigned short cc_map[16] = { 0 /* NV */ }; -static int check_conditional_instr(struct cpu_user_regs *regs, - const union hsr hsr) +int check_conditional_instr(struct cpu_user_regs *regs, const union hsr hsr) { unsigned long cpsr, cpsr_cond; int cond; @@ -1777,7 +1776,7 @@ static int check_conditional_instr(struct cpu_user_regs *regs, return 1; } -static void advance_pc(struct cpu_user_regs *regs, const union hsr hsr) +void advance_pc(struct cpu_user_regs *regs, const union hsr hsr) { unsigned long itbits, cond, cpsr = regs->cpsr; @@ -1818,11 +1817,11 @@ static void advance_pc(struct cpu_user_regs *regs, const union hsr hsr) } /* Read as zero and write ignore */ -static void handle_raz_wi(struct cpu_user_regs *regs, - int regidx, - bool read, - const union hsr hsr, - int min_el) +void handle_raz_wi(struct cpu_user_regs *regs, + int regidx, + bool read, + const union hsr hsr, + int min_el) { ASSERT((min_el == 0) || (min_el == 1)); @@ -1836,12 +1835,12 @@ static void handle_raz_wi(struct cpu_user_regs *regs, advance_pc(regs, hsr); } -/* Write only as write ignore */ -static void handle_wo_wi(struct cpu_user_regs *regs, - int regidx, - bool read, - const union hsr hsr, - int min_el) +/* write only as write ignore */ +void handle_wo_wi(struct cpu_user_regs *regs, + int regidx, + bool read, + const union hsr hsr, + int min_el) { ASSERT((min_el == 0) || (min_el == 1)); @@ -1856,11 +1855,11 @@ static void handle_wo_wi(struct cpu_user_regs *regs, } /* Read only as read as zero */ -static void handle_ro_raz(struct cpu_user_regs *regs, - int regidx, - bool read, - const union hsr hsr, - int min_el) +void handle_ro_raz(struct cpu_user_regs *regs, + int regidx, + bool read, + const union hsr hsr, + int min_el) { ASSERT((min_el == 0) || (min_el == 1)); diff --git a/xen/include/asm-arm/arm32/traps.h b/xen/include/asm-arm/arm32/traps.h new file mode 100644 index 0000000000..e3c4a8b473 --- /dev/null +++ b/xen/include/asm-arm/arm32/traps.h @@ -0,0 +1,13 @@ +#ifndef __ASM_ARM32_TRAPS__ +#define __ASM_ARM32_TRAPS__ + +#endif /* __ASM_ARM32_TRAPS__ */ +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ + diff --git a/xen/include/asm-arm/arm64/traps.h b/xen/include/asm-arm/arm64/traps.h new file mode 100644 index 0000000000..e5e5a4a036 --- /dev/null +++ b/xen/include/asm-arm/arm64/traps.h @@ -0,0 +1,15 @@ +#ifndef __ASM_ARM64_TRAPS__ +#define __ASM_ARM64_TRAPS__ + +void inject_undef64_exception(struct cpu_user_regs *regs, int instr_len); + +#endif /* __ASM_ARM64_TRAPS__ */ +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ + diff --git a/xen/include/asm-arm/traps.h b/xen/include/asm-arm/traps.h new file mode 100644 index 0000000000..6d99d228e8 --- /dev/null +++ b/xen/include/asm-arm/traps.h @@ -0,0 +1,36 @@ +#ifndef __ASM_ARM_TRAPS__ +#define __ASM_ARM_TRAPS__ + +#include + +#if defined(CONFIG_ARM_32) +# include +#elif defined(CONFIG_ARM_64) +# include +#endif + +int check_conditional_instr(struct cpu_user_regs *regs, const union hsr hsr); + +void advance_pc(struct cpu_user_regs *regs, const union hsr hsr); + +void inject_undef_exception(struct cpu_user_regs *regs, const union hsr hsr); + +void handle_raz_wi(struct cpu_user_regs *regs, int regidx, bool read, + const union hsr hsr, int min_el); + +void handle_wo_wi(struct cpu_user_regs *regs, int regidx, bool read, + const union hsr hsr, int min_el); + +void handle_ro_raz(struct cpu_user_regs *regs, int regidx, bool read, + const union hsr hsr, int min_el); + +#endif /* __ASM_ARM_TRAPS__ */ +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ + From patchwork Tue Sep 12 10:36:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 112294 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp4986421qgf; Tue, 12 Sep 2017 03:38:48 -0700 (PDT) X-Google-Smtp-Source: AOwi7QBtCx6LpGAYexhDLFosES67G8xp2+AnmDZMRYWd5UCRLqHvGYjg/g//TxKkns4NArsW7Yk8 X-Received: by 10.36.43.208 with SMTP id h199mr337170ita.27.1505212728758; Tue, 12 Sep 2017 03:38:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505212728; cv=none; d=google.com; s=arc-20160816; b=oxNw6Lfl60uv0p85aeItmd3RM0mthC2T7hKX6T+NXQaibRST1yKdxKUWpZ4sOrUSTq Gn0+e3ZE8iuy5507x8UPXO2EcKrhq1NjhGBKxCOi/8VmV5ukFg5DysZNpYAgN6+INVvW 4haJYb+4L5XO5GB6tQ53z8+6A6WDlEpx9ecgqbd0juq1/aPNuw85Z5WcBVP/LIuBZjI3 Yo+AUsvrLUyqmUmslIq1DRD8LS7wSFg1Hgqj7zntQTGwj5xV44S1eRhpuMJTQfLV3PRg y/VZP8XEpP2UtPO7NcrNl5SmBlxJg5OdTa5K5TOmdYvbnLZ11j3T3OtKyT4mgxR+9Xco d5SA== ARC-Message-Signature: i=1; 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[192.237.175.120]) by mx.google.com with ESMTPS id u126si10605681itd.127.2017.09.12.03.38.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Sep 2017 03:38:48 -0700 (PDT) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1driYX-0001Oy-Ig; Tue, 12 Sep 2017 10:36:37 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1driYW-0001OP-I9 for xen-devel@lists.xen.org; Tue, 12 Sep 2017 10:36:36 +0000 Received: from [193.109.254.147] by server-5.bemta-6.messagelabs.com id 8F/D2-03454-3B8B7B95; Tue, 12 Sep 2017 10:36:35 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrBLMWRWlGSWpSXmKPExsVysyfVTXfzju2 RBo/n81ss+biYxYHR4+ju30wBjFGsmXlJ+RUJrBmXH09gKdhSVDG3v5W5gXFTUBcjF4eQwGZG iZe/ZzFBOKcZJX42fmXtYuTkYBPQlLjz+RMTiC0iIC1x7fNlRhCbWSBO4v2iRhYQW1jAU+Lz/ 1NgNouAqsTOFSvZQGxeAUuJ2zPmg9kSAvISu9ougs3kFLCSWPRqAVA9B9AyS4lLmyUnMHIvYG RYxahRnFpUllqka2ihl1SUmZ5RkpuYmaNraGCml5taXJyYnpqTmFSsl5yfu4kR6F8GINjBeHN jwCFGSQ4mJVHeI+u3RwrxJeWnVGYkFmfEF5XmpBYfYpTh4FCS4D25HSgnWJSanlqRlpkDDDSY tAQHj5II7xSQNG9xQWJucWY6ROoUozHHsU2X/zBxdNy8+4dJiCUvPy9VSpy3FKRUAKQ0ozQPb hAsAi4xykoJ8zICnSbEU5BalJtZgir/ilGcg1FJmPcqyBSezLwSuH2vgE5hAjqF59IWkFNKEh FSUg2MwrHdcbIeew9MWPp6o7BxbnxdRCzzf9uY4g1ihyqK3KOdTihnii+RX1dttl3VSNd3RXX 6jzUSa/dW/n7L71wjo/rx179VBaKKVZEZv292eTlmLr+0VezGoQjffJatzgbCXzfv6m6XST0U s6K3y+O29z1hPg/1i/pLyg9yKX725HluMeH0LwMlluKMREMt5qLiRAB6quEsewIAAA== X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-9.tower-27.messagelabs.com!1505212594!116399586!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests=UPPERCASE_25_50 X-StarScan-Received: X-StarScan-Version: 9.4.45; banners=-,-,- X-VirusChecked: Checked Received: (qmail 65369 invoked from network); 12 Sep 2017 10:36:34 -0000 Received: from usa-sjc-mx-foss1.foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-9.tower-27.messagelabs.com with SMTP; 12 Sep 2017 10:36:34 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4480A15A2; Tue, 12 Sep 2017 03:36:34 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 32CC83F578; Tue, 12 Sep 2017 03:36:33 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Tue, 12 Sep 2017 11:36:19 +0100 Message-Id: <20170912103622.18562-5-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170912103622.18562-1-julien.grall@arm.com> References: <20170912103622.18562-1-julien.grall@arm.com> Cc: bhupinder.thakur@linaro.org, Julien Grall , sstabellini@kernel.org Subject: [Xen-devel] [PATCH v2 4/7] xen/arm: Move sysreg emulation outside of traps.c X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" The sysreg emulation is 64-bit specific and surrounded by #ifdef. Move them in a separate file arm/arm64/vsysreg.c to shrink down a bit traps.c No functional change. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- xen/arch/arm/arm64/Makefile | 1 + xen/arch/arm/arm64/vsysreg.c | 229 ++++++++++++++++++++++++++++++++++++++ xen/arch/arm/traps.c | 198 -------------------------------- xen/include/asm-arm/arm64/traps.h | 3 + 4 files changed, 233 insertions(+), 198 deletions(-) create mode 100644 xen/arch/arm/arm64/vsysreg.c diff --git a/xen/arch/arm/arm64/Makefile b/xen/arch/arm/arm64/Makefile index 149b6b3901..718fe44455 100644 --- a/xen/arch/arm/arm64/Makefile +++ b/xen/arch/arm/arm64/Makefile @@ -10,3 +10,4 @@ obj-$(CONFIG_LIVEPATCH) += livepatch.o obj-y += smpboot.o obj-y += traps.o obj-y += vfp.o +obj-y += vsysreg.o diff --git a/xen/arch/arm/arm64/vsysreg.c b/xen/arch/arm/arm64/vsysreg.c new file mode 100644 index 0000000000..c57ac12503 --- /dev/null +++ b/xen/arch/arm/arm64/vsysreg.c @@ -0,0 +1,229 @@ +/* + * xen/arch/arm/arm64/sysreg.c + * + * Emulate system registers trapped. + * + * Copyright (c) 2011 Citrix Systems. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +#include +#include +#include +#include + +void do_sysreg(struct cpu_user_regs *regs, + const union hsr hsr) +{ + int regidx = hsr.sysreg.reg; + struct vcpu *v = current; + + switch ( hsr.bits & HSR_SYSREG_REGS_MASK ) + { + /* + * HCR_EL2.TACR + * + * ARMv8 (DDI 0487A.d): D7.2.1 + */ + case HSR_SYSREG_ACTLR_EL1: + if ( psr_mode_is_user(regs) ) + return inject_undef_exception(regs, hsr); + if ( hsr.sysreg.read ) + set_user_reg(regs, regidx, v->arch.actlr); + break; + + /* + * MDCR_EL2.TDRA + * + * ARMv8 (DDI 0487A.d): D1-1508 Table D1-57 + */ + case HSR_SYSREG_MDRAR_EL1: + return handle_ro_raz(regs, regidx, hsr.sysreg.read, hsr, 1); + + /* + * MDCR_EL2.TDOSA + * + * ARMv8 (DDI 0487A.d): D1-1509 Table D1-58 + * + * Unhandled: + * OSLSR_EL1 + * DBGPRCR_EL1 + */ + case HSR_SYSREG_OSLAR_EL1: + return handle_wo_wi(regs, regidx, hsr.sysreg.read, hsr, 1); + case HSR_SYSREG_OSDLR_EL1: + return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1); + + /* + * MDCR_EL2.TDA + * + * ARMv8 (DDI 0487A.d): D1-1510 Table D1-59 + * + * Unhandled: + * MDCCINT_EL1 + * DBGDTR_EL0 + * DBGDTRRX_EL0 + * DBGDTRTX_EL0 + * OSDTRRX_EL1 + * OSDTRTX_EL1 + * OSECCR_EL1 + * DBGCLAIMSET_EL1 + * DBGCLAIMCLR_EL1 + * DBGAUTHSTATUS_EL1 + */ + case HSR_SYSREG_MDSCR_EL1: + return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1); + case HSR_SYSREG_MDCCSR_EL0: + /* + * Accessible at EL0 only if MDSCR_EL1.TDCC is set to 0. We emulate that + * register as RAZ/WI above. So RO at both EL0 and EL1. + */ + return handle_ro_raz(regs, regidx, hsr.sysreg.read, hsr, 0); + HSR_SYSREG_DBG_CASES(DBGBVR): + HSR_SYSREG_DBG_CASES(DBGBCR): + HSR_SYSREG_DBG_CASES(DBGWVR): + HSR_SYSREG_DBG_CASES(DBGWCR): + return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1); + + /* + * MDCR_EL2.TPM + * + * ARMv8 (DDI 0487A.d): D1-1511 Table D1-61 + * + * Unhandled: + * PMEVCNTR_EL0 + * PMEVTYPER_EL0 + * PMCCFILTR_EL0 + * MDCR_EL2.TPMCR + * + * ARMv7 (DDI 0406C.b): B1.14.17 + * ARMv8 (DDI 0487A.d): D1-1511 Table D1-62 + * + * NB: Both MDCR_EL2.TPM and MDCR_EL2.TPMCR cause trapping of PMCR. + */ + case HSR_SYSREG_PMINTENSET_EL1: + case HSR_SYSREG_PMINTENCLR_EL1: + /* + * Accessible from EL1 only, but if EL0 trap happens handle as + * undef. + */ + return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1); + case HSR_SYSREG_PMUSERENR_EL0: + /* RO at EL0. RAZ/WI at EL1 */ + if ( psr_mode_is_user(regs) ) + return handle_ro_raz(regs, regidx, hsr.sysreg.read, hsr, 0); + else + return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1); + case HSR_SYSREG_PMCR_EL0: + case HSR_SYSREG_PMCNTENSET_EL0: + case HSR_SYSREG_PMCNTENCLR_EL0: + case HSR_SYSREG_PMOVSCLR_EL0: + case HSR_SYSREG_PMSWINC_EL0: + case HSR_SYSREG_PMSELR_EL0: + case HSR_SYSREG_PMCEID0_EL0: + case HSR_SYSREG_PMCEID1_EL0: + case HSR_SYSREG_PMCCNTR_EL0: + case HSR_SYSREG_PMXEVTYPER_EL0: + case HSR_SYSREG_PMXEVCNTR_EL0: + case HSR_SYSREG_PMOVSSET_EL0: + /* + * Accessible at EL0 only if PMUSERENR_EL0.EN is set. We + * emulate that register as 0 above. + */ + return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1); + + /* + * !CNTHCTL_EL2.EL1PCEN + * + * ARMv8 (DDI 0487A.d): D1-1510 Table D1-60 + */ + case HSR_SYSREG_CNTP_CTL_EL0: + case HSR_SYSREG_CNTP_TVAL_EL0: + case HSR_SYSREG_CNTP_CVAL_EL0: + if ( !vtimer_emulate(regs, hsr) ) + return inject_undef_exception(regs, hsr); + break; + + /* + * HCR_EL2.FMO or HCR_EL2.IMO + * + * GIC Architecture Specification (IHI 0069C): Section 4.6.3 + */ + case HSR_SYSREG_ICC_SGI1R_EL1: + case HSR_SYSREG_ICC_ASGI1R_EL1: + case HSR_SYSREG_ICC_SGI0R_EL1: + + if ( !vgic_emulate(regs, hsr) ) + return inject_undef64_exception(regs, hsr.len); + break; + + /* + * ICC_SRE_EL2.Enable = 0 + * + * GIC Architecture Specification (IHI 0069C): Section 8.1.9 + */ + case HSR_SYSREG_ICC_SRE_EL1: + /* + * Trapped when the guest is using GICv2 whilst the platform + * interrupt controller is GICv3. In this case, the register + * should be emulate as RAZ/WI to tell the guest to use the GIC + * memory mapped interface (i.e GICv2 compatibility). + */ + return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1); + + /* + * HCR_EL2.TIDCP + * + * ARMv8 (DDI 0487A.d): D1-1501 Table D1-43 + * + * - Reserved control space for IMPLEMENTATION DEFINED functionality. + * + * CPTR_EL2.TTA + * + * ARMv8 (DDI 0487A.d): D1-1507 Table D1-54 + * + * - All implemented trace registers. + * + * And all other unknown registers. + */ + default: + { + const struct hsr_sysreg sysreg = hsr.sysreg; + + gdprintk(XENLOG_ERR, + "%s %d, %d, c%d, c%d, %d %s x%d @ 0x%"PRIregister"\n", + sysreg.read ? "mrs" : "msr", + sysreg.op0, sysreg.op1, + sysreg.crn, sysreg.crm, + sysreg.op2, + sysreg.read ? "=>" : "<=", + sysreg.reg, regs->pc); + gdprintk(XENLOG_ERR, "unhandled 64-bit sysreg access %#x\n", + hsr.bits & HSR_SYSREG_REGS_MASK); + inject_undef_exception(regs, hsr); + return; + } + } + + regs->pc += 4; +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 1c334a7b99..f00aa48892 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -2295,204 +2295,6 @@ static void do_cp(struct cpu_user_regs *regs, const union hsr hsr) inject_undef_exception(regs, hsr); } -#ifdef CONFIG_ARM_64 -static void do_sysreg(struct cpu_user_regs *regs, - const union hsr hsr) -{ - int regidx = hsr.sysreg.reg; - struct vcpu *v = current; - - switch ( hsr.bits & HSR_SYSREG_REGS_MASK ) - { - /* - * HCR_EL2.TACR - * - * ARMv8 (DDI 0487A.d): D7.2.1 - */ - case HSR_SYSREG_ACTLR_EL1: - if ( psr_mode_is_user(regs) ) - return inject_undef_exception(regs, hsr); - if ( hsr.sysreg.read ) - set_user_reg(regs, regidx, v->arch.actlr); - break; - - /* - * MDCR_EL2.TDRA - * - * ARMv8 (DDI 0487A.d): D1-1508 Table D1-57 - */ - case HSR_SYSREG_MDRAR_EL1: - return handle_ro_raz(regs, regidx, hsr.sysreg.read, hsr, 1); - - /* - * MDCR_EL2.TDOSA - * - * ARMv8 (DDI 0487A.d): D1-1509 Table D1-58 - * - * Unhandled: - * OSLSR_EL1 - * DBGPRCR_EL1 - */ - case HSR_SYSREG_OSLAR_EL1: - return handle_wo_wi(regs, regidx, hsr.sysreg.read, hsr, 1); - case HSR_SYSREG_OSDLR_EL1: - return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1); - - /* - * MDCR_EL2.TDA - * - * ARMv8 (DDI 0487A.d): D1-1510 Table D1-59 - * - * Unhandled: - * MDCCINT_EL1 - * DBGDTR_EL0 - * DBGDTRRX_EL0 - * DBGDTRTX_EL0 - * OSDTRRX_EL1 - * OSDTRTX_EL1 - * OSECCR_EL1 - * DBGCLAIMSET_EL1 - * DBGCLAIMCLR_EL1 - * DBGAUTHSTATUS_EL1 - */ - case HSR_SYSREG_MDSCR_EL1: - return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1); - case HSR_SYSREG_MDCCSR_EL0: - /* - * Accessible at EL0 only if MDSCR_EL1.TDCC is set to 0. We emulate that - * register as RAZ/WI above. So RO at both EL0 and EL1. - */ - return handle_ro_raz(regs, regidx, hsr.sysreg.read, hsr, 0); - HSR_SYSREG_DBG_CASES(DBGBVR): - HSR_SYSREG_DBG_CASES(DBGBCR): - HSR_SYSREG_DBG_CASES(DBGWVR): - HSR_SYSREG_DBG_CASES(DBGWCR): - return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1); - - /* - * MDCR_EL2.TPM - * - * ARMv8 (DDI 0487A.d): D1-1511 Table D1-61 - * - * Unhandled: - * PMEVCNTR_EL0 - * PMEVTYPER_EL0 - * PMCCFILTR_EL0 - * MDCR_EL2.TPMCR - * - * ARMv7 (DDI 0406C.b): B1.14.17 - * ARMv8 (DDI 0487A.d): D1-1511 Table D1-62 - * - * NB: Both MDCR_EL2.TPM and MDCR_EL2.TPMCR cause trapping of PMCR. - */ - case HSR_SYSREG_PMINTENSET_EL1: - case HSR_SYSREG_PMINTENCLR_EL1: - /* - * Accessible from EL1 only, but if EL0 trap happens handle as - * undef. - */ - return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1); - case HSR_SYSREG_PMUSERENR_EL0: - /* RO at EL0. RAZ/WI at EL1 */ - if ( psr_mode_is_user(regs) ) - return handle_ro_raz(regs, regidx, hsr.sysreg.read, hsr, 0); - else - return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1); - case HSR_SYSREG_PMCR_EL0: - case HSR_SYSREG_PMCNTENSET_EL0: - case HSR_SYSREG_PMCNTENCLR_EL0: - case HSR_SYSREG_PMOVSCLR_EL0: - case HSR_SYSREG_PMSWINC_EL0: - case HSR_SYSREG_PMSELR_EL0: - case HSR_SYSREG_PMCEID0_EL0: - case HSR_SYSREG_PMCEID1_EL0: - case HSR_SYSREG_PMCCNTR_EL0: - case HSR_SYSREG_PMXEVTYPER_EL0: - case HSR_SYSREG_PMXEVCNTR_EL0: - case HSR_SYSREG_PMOVSSET_EL0: - /* - * Accessible at EL0 only if PMUSERENR_EL0.EN is set. We - * emulate that register as 0 above. - */ - return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1); - - /* - * !CNTHCTL_EL2.EL1PCEN - * - * ARMv8 (DDI 0487A.d): D1-1510 Table D1-60 - */ - case HSR_SYSREG_CNTP_CTL_EL0: - case HSR_SYSREG_CNTP_TVAL_EL0: - case HSR_SYSREG_CNTP_CVAL_EL0: - if ( !vtimer_emulate(regs, hsr) ) - return inject_undef_exception(regs, hsr); - break; - - /* - * HCR_EL2.FMO or HCR_EL2.IMO - * - * GIC Architecture Specification (IHI 0069C): Section 4.6.3 - */ - case HSR_SYSREG_ICC_SGI1R_EL1: - case HSR_SYSREG_ICC_ASGI1R_EL1: - case HSR_SYSREG_ICC_SGI0R_EL1: - - if ( !vgic_emulate(regs, hsr) ) - return inject_undef64_exception(regs, hsr.len); - break; - - /* - * ICC_SRE_EL2.Enable = 0 - * - * GIC Architecture Specification (IHI 0069C): Section 8.1.9 - */ - case HSR_SYSREG_ICC_SRE_EL1: - /* - * Trapped when the guest is using GICv2 whilst the platform - * interrupt controller is GICv3. In this case, the register - * should be emulate as RAZ/WI to tell the guest to use the GIC - * memory mapped interface (i.e GICv2 compatibility). - */ - return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1); - - /* - * HCR_EL2.TIDCP - * - * ARMv8 (DDI 0487A.d): D1-1501 Table D1-43 - * - * - Reserved control space for IMPLEMENTATION DEFINED functionality. - * - * CPTR_EL2.TTA - * - * ARMv8 (DDI 0487A.d): D1-1507 Table D1-54 - * - * - All implemented trace registers. - * - * And all other unknown registers. - */ - default: - { - const struct hsr_sysreg sysreg = hsr.sysreg; - - gdprintk(XENLOG_ERR, - "%s %d, %d, c%d, c%d, %d %s x%d @ 0x%"PRIregister"\n", - sysreg.read ? "mrs" : "msr", - sysreg.op0, sysreg.op1, - sysreg.crn, sysreg.crm, - sysreg.op2, - sysreg.read ? "=>" : "<=", - sysreg.reg, regs->pc); - gdprintk(XENLOG_ERR, "unhandled 64-bit sysreg access %#x\n", - hsr.bits & HSR_SYSREG_REGS_MASK); - inject_undef_exception(regs, hsr); - return; - } - } - - regs->pc += 4; -} -#endif - void dump_guest_s1_walk(struct domain *d, vaddr_t addr) { register_t ttbcr = READ_SYSREG(TCR_EL1); diff --git a/xen/include/asm-arm/arm64/traps.h b/xen/include/asm-arm/arm64/traps.h index e5e5a4a036..2379b578cb 100644 --- a/xen/include/asm-arm/arm64/traps.h +++ b/xen/include/asm-arm/arm64/traps.h @@ -3,6 +3,9 @@ void inject_undef64_exception(struct cpu_user_regs *regs, int instr_len); +void do_sysreg(struct cpu_user_regs *regs, + const union hsr hsr); + #endif /* __ASM_ARM64_TRAPS__ */ /* * Local variables: From patchwork Tue Sep 12 10:36:20 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 112296 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp4986519qgf; Tue, 12 Sep 2017 03:38:55 -0700 (PDT) X-Google-Smtp-Source: AOwi7QDWwSyR1077E6OXYN6kaVkxFGk0Z98Aj1YSZGkydMwhJlUqunfnTBtK1H/1W8S9uZRs0g6d X-Received: by 10.107.132.84 with SMTP id g81mr22353027iod.47.1505212734999; Tue, 12 Sep 2017 03:38:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505212734; cv=none; d=google.com; s=arc-20160816; b=KTQBJRf+Cfq/0Yg1yZz8z32I0VEKi0w5hqc8nh9OgfSKy1F9SmTrirwJoW1yBk4Ox8 2WqreUjetTFMa/vFcvHrwuzYiJ3x4+NE6AfRtr/mfHCgcdJTYwGaZtQDRUB5ZN0YLn5f Wr01ZOBgAbC2/saNNUAsB96lM0lUx1dvZcw5LtSrlI6kBROBDWwVVLMrSvV1o6r2kUz7 ajmKo7Tha89udHSwjXSjfU/MUDlJFKdVVe+8r/71X4p8GiN7hCaqYzuvRjrBQhnCTXkn GxtII9z5KnvACop+CdhZbMOyyUb3ZoQQy9+QKWJl48oMSPX9AMilxnoJlan4pc8pwsFK +UlA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=QG/FrTtChN2Fp3iB5ALbVLp5MMuHJqFfBeJysuJDlDU=; b=eC4EdorYW1jQNHY2F3l1GItAlsBXfRj55Uv7IOOaZ+CkblHs2/3z36f9xdKUpTxDKX Hoe6mbWlSKW0mQEOGBh+ihK1/JvbHEqfkfsBsWpyKW7cYZZzVu9PT1vu0xVL1bdDbZnn PDSDH7CtKIBmta7BBzqsf4KjbEXkz+0tp1I6BVV2NW79zkVaOhDGvxzg52onxAVvsnaY bbQrUk9JIpMeQwzmkv7Q9o3N4yaaKgeGKu7qwmIGGFkZRnq0MEQExVl6kip6ursvrcXz plB4fakqREguitw4H1Z1qKN3LvfZevXjwKpPqj2PSO/Rfds36BeEb7snw3FcH6J4w28k ZH9Q== ARC-Authentication-Results: i=1; mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id o5si1648404itg.58.2017.09.12.03.38.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Sep 2017 03:38:54 -0700 (PDT) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1driYZ-0001Pt-TP; Tue, 12 Sep 2017 10:36:39 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1driYY-0001PP-CJ for xen-devel@lists.xen.org; Tue, 12 Sep 2017 10:36:38 +0000 Received: from [85.158.143.35] by server-11.bemta-6.messagelabs.com id 10/B7-03616-5B8B7B95; Tue, 12 Sep 2017 10:36:37 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrELMWRWlGSWpSXmKPExsVysyfVTXfLju2 RBpe2alss+biYxYHR4+ju30wBjFGsmXlJ+RUJrBmX+wwKrl1nrOjZfYGtgXHdTMYuRk4OIYHN jBJfW0u7GLmA7NOMErebW9hBEmwCmhJ3Pn9iArFFBKQlrn2+DNbALBAn8X5RIwuILSzgL9H55 ztYPYuAqsT656fB6nkFLCVaHn8FsyUE5CV2tV1kBbE5BawkFr1aANTLAbTMUuLSZskJjNwLGB lWMWoUpxaVpRbpGhnrJRVlpmeU5CZm5ugaGpjp5aYWFyemp+YkJhXrJefnbmIE+pcBCHYw/pk feIhRkoNJSZT3yPrtkUJ8SfkplRmJxRnxRaU5qcWHGGU4OJQkeCduB8oJFqWmp1akZeYAAw0m LcHBoyTCOwUkzVtckJhbnJkOkTrFqMvRcfPuHyYhlrz8vFQpcd5SkCIBkKKM0jy4EbCgv8QoK yXMywh0lBBPQWpRbmYJqvwrRnEORiVh3hiQKTyZeSVwm14BHcEEdATPpS0gR5QkIqSkGhiF/v YY1d/ItrzC9nOdou/ilht5Csct/eeqLhRMEPGtPMyo9+b4gXVZD85Gd5XPSRRo5u801t8jdE3 0TlMF/0QXmxP3uBTvpRnJWrkXXJc/oHlH99yBq3UHnl//WCkw04iF0Wu3kFfJfI2H2k8O1rkp Td60qqXKb4lZluHyXmahJRYXg9czMiixFGckGmoxFxUnAgBbvW8bdQIAAA== X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-12.tower-21.messagelabs.com!1505212595!82402779!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.4.45; banners=-,-,- X-VirusChecked: Checked Received: (qmail 778 invoked from network); 12 Sep 2017 10:36:36 -0000 Received: from usa-sjc-mx-foss1.foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-12.tower-21.messagelabs.com with SMTP; 12 Sep 2017 10:36:36 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9266D1529; Tue, 12 Sep 2017 03:36:35 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 800143F578; Tue, 12 Sep 2017 03:36:34 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Tue, 12 Sep 2017 11:36:20 +0100 Message-Id: <20170912103622.18562-6-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170912103622.18562-1-julien.grall@arm.com> References: <20170912103622.18562-1-julien.grall@arm.com> Cc: bhupinder.thakur@linaro.org, Julien Grall , sstabellini@kernel.org Subject: [Xen-devel] [PATCH v2 5/7] xen/arm: Move co-processor emulation outside of traps.c X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" The co-processor emulation is quite big and pretty much standalone. Move it in a separate file to shrink down the size of traps.c. At the same time remove unused cpregs.h. No functional change. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- xen/arch/arm/Makefile | 1 + xen/arch/arm/traps.c | 421 ----------------------------------------- xen/arch/arm/vcpreg.c | 451 ++++++++++++++++++++++++++++++++++++++++++++ xen/include/asm-arm/traps.h | 8 + 4 files changed, 460 insertions(+), 421 deletions(-) create mode 100644 xen/arch/arm/vcpreg.c diff --git a/xen/arch/arm/Makefile b/xen/arch/arm/Makefile index 282d2c2949..17bff98033 100644 --- a/xen/arch/arm/Makefile +++ b/xen/arch/arm/Makefile @@ -45,6 +45,7 @@ obj-y += smpboot.o obj-y += sysctl.o obj-y += time.o obj-y += traps.o +obj-y += vcpreg.o obj-y += vgic.o obj-y += vgic-v2.o obj-$(CONFIG_HAS_GICV3) += vgic-v3.o diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index f00aa48892..5e6bc3173f 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -38,7 +38,6 @@ #include #include -#include #include #include #include @@ -1875,426 +1874,6 @@ void handle_ro_raz(struct cpu_user_regs *regs, advance_pc(regs, hsr); } -static void do_cp15_32(struct cpu_user_regs *regs, - const union hsr hsr) -{ - const struct hsr_cp32 cp32 = hsr.cp32; - int regidx = cp32.reg; - struct vcpu *v = current; - - if ( !check_conditional_instr(regs, hsr) ) - { - advance_pc(regs, hsr); - return; - } - - switch ( hsr.bits & HSR_CP32_REGS_MASK ) - { - /* - * !CNTHCTL_EL2.EL1PCEN / !CNTHCTL.PL1PCEN - * - * ARMv7 (DDI 0406C.b): B4.1.22 - * ARMv8 (DDI 0487A.d): D1-1510 Table D1-60 - */ - case HSR_CPREG32(CNTP_CTL): - case HSR_CPREG32(CNTP_TVAL): - if ( !vtimer_emulate(regs, hsr) ) - return inject_undef_exception(regs, hsr); - break; - - /* - * HCR_EL2.TACR / HCR.TAC - * - * ARMv7 (DDI 0406C.b): B1.14.6 - * ARMv8 (DDI 0487A.d): G6.2.1 - */ - case HSR_CPREG32(ACTLR): - if ( psr_mode_is_user(regs) ) - return inject_undef_exception(regs, hsr); - if ( cp32.read ) - set_user_reg(regs, regidx, v->arch.actlr); - break; - - /* - * MDCR_EL2.TPM - * - * ARMv7 (DDI 0406C.b): B1.14.17 - * ARMv8 (DDI 0487A.d): D1-1511 Table D1-61 - * - * Unhandled: - * PMEVCNTR - * PMEVTYPER - * PMCCFILTR - * - * MDCR_EL2.TPMCR - * - * ARMv7 (DDI 0406C.b): B1.14.17 - * ARMv8 (DDI 0487A.d): D1-1511 Table D1-62 - * - * NB: Both MDCR_EL2.TPM and MDCR_EL2.TPMCR cause trapping of PMCR. - */ - /* We could trap ID_DFR0 and tell the guest we don't support - * performance monitoring, but Linux doesn't check the ID_DFR0. - * Therefore it will read PMCR. - * - * We tell the guest we have 0 counters. Unfortunately we must - * always support PMCCNTR (the cyle counter): we just RAZ/WI for all - * PM register, which doesn't crash the kernel at least - */ - case HSR_CPREG32(PMUSERENR): - /* RO at EL0. RAZ/WI at EL1 */ - if ( psr_mode_is_user(regs) ) - return handle_ro_raz(regs, regidx, cp32.read, hsr, 0); - else - return handle_raz_wi(regs, regidx, cp32.read, hsr, 1); - case HSR_CPREG32(PMINTENSET): - case HSR_CPREG32(PMINTENCLR): - /* EL1 only, however MDCR_EL2.TPM==1 means EL0 may trap here also. */ - return handle_raz_wi(regs, regidx, cp32.read, hsr, 1); - case HSR_CPREG32(PMCR): - case HSR_CPREG32(PMCNTENSET): - case HSR_CPREG32(PMCNTENCLR): - case HSR_CPREG32(PMOVSR): - case HSR_CPREG32(PMSWINC): - case HSR_CPREG32(PMSELR): - case HSR_CPREG32(PMCEID0): - case HSR_CPREG32(PMCEID1): - case HSR_CPREG32(PMCCNTR): - case HSR_CPREG32(PMXEVTYPER): - case HSR_CPREG32(PMXEVCNTR): - case HSR_CPREG32(PMOVSSET): - /* - * Accessible at EL0 only if PMUSERENR_EL0.EN is set. We - * emulate that register as 0 above. - */ - return handle_raz_wi(regs, regidx, cp32.read, hsr, 1); - - /* - * HCR_EL2.TIDCP - * - * ARMv7 (DDI 0406C.b): B1.14.3 - * ARMv8 (DDI 0487A.d): D1-1501 Table D1-43 - * - * - CRn==c9, opc1=={0-7}, CRm=={c0-c2, c5-c8}, opc2=={0-7} - * (Cache and TCM lockdown registers) - * - CRn==c10, opc1=={0-7}, CRm=={c0, c1, c4, c8}, opc2=={0-7} - * (VMSA CP15 c10 registers) - * - CRn==c11, opc1=={0-7}, CRm=={c0-c8, c15}, opc2=={0-7} - * (VMSA CP15 c11 registers) - * - * CPTR_EL2.T{0..9,12..13} - * - * ARMv7 (DDI 0406C.b): B1.14.12 - * ARMv8 (DDI 0487A.d): N/A - * - * - All accesses to coprocessors 0..9 and 12..13 - * - * HSTR_EL2.T15 - * - * ARMv7 (DDI 0406C.b): B1.14.14 - * ARMv8 (DDI 0487A.d): D1-1507 Table D1-55 - * - * - All accesses to cp15, c15 registers. - * - * And all other unknown registers. - */ - default: - gdprintk(XENLOG_ERR, - "%s p15, %d, r%d, cr%d, cr%d, %d @ 0x%"PRIregister"\n", - cp32.read ? "mrc" : "mcr", - cp32.op1, cp32.reg, cp32.crn, cp32.crm, cp32.op2, regs->pc); - gdprintk(XENLOG_ERR, "unhandled 32-bit CP15 access %#x\n", - hsr.bits & HSR_CP32_REGS_MASK); - inject_undef_exception(regs, hsr); - return; - } - advance_pc(regs, hsr); -} - -static void do_cp15_64(struct cpu_user_regs *regs, - const union hsr hsr) -{ - if ( !check_conditional_instr(regs, hsr) ) - { - advance_pc(regs, hsr); - return; - } - - switch ( hsr.bits & HSR_CP64_REGS_MASK ) - { - /* - * !CNTHCTL_EL2.EL1PCEN / !CNTHCTL.PL1PCEN - * - * ARMv7 (DDI 0406C.b): B4.1.22 - * ARMv8 (DDI 0487A.d): D1-1510 Table D1-60 - */ - case HSR_CPREG64(CNTP_CVAL): - if ( !vtimer_emulate(regs, hsr) ) - return inject_undef_exception(regs, hsr); - break; - - /* - * HCR_EL2.FMO or HCR_EL2.IMO - * - * GIC Architecture Specification (IHI 0069C): Section 4.6.3 - */ - case HSR_CPREG64(ICC_SGI1R): - case HSR_CPREG64(ICC_ASGI1R): - case HSR_CPREG64(ICC_SGI0R): - if ( !vgic_emulate(regs, hsr) ) - return inject_undef_exception(regs, hsr); - break; - - /* - * CPTR_EL2.T{0..9,12..13} - * - * ARMv7 (DDI 0406C.b): B1.14.12 - * ARMv8 (DDI 0487A.d): N/A - * - * - All accesses to coprocessors 0..9 and 12..13 - * - * HSTR_EL2.T15 - * - * ARMv7 (DDI 0406C.b): B1.14.14 - * ARMv8 (DDI 0487A.d): D1-1507 Table D1-55 - * - * - All accesses to cp15, c15 registers. - * - * And all other unknown registers. - */ - default: - { - const struct hsr_cp64 cp64 = hsr.cp64; - - gdprintk(XENLOG_ERR, - "%s p15, %d, r%d, r%d, cr%d @ 0x%"PRIregister"\n", - cp64.read ? "mrrc" : "mcrr", - cp64.op1, cp64.reg1, cp64.reg2, cp64.crm, regs->pc); - gdprintk(XENLOG_ERR, "unhandled 64-bit CP15 access %#x\n", - hsr.bits & HSR_CP64_REGS_MASK); - inject_undef_exception(regs, hsr); - return; - } - } - advance_pc(regs, hsr); -} - -static void do_cp14_32(struct cpu_user_regs *regs, const union hsr hsr) -{ - const struct hsr_cp32 cp32 = hsr.cp32; - int regidx = cp32.reg; - struct domain *d = current->domain; - - if ( !check_conditional_instr(regs, hsr) ) - { - advance_pc(regs, hsr); - return; - } - - switch ( hsr.bits & HSR_CP32_REGS_MASK ) - { - /* - * MDCR_EL2.TDOSA - * - * ARMv7 (DDI 0406C.b): B1.14.15 - * ARMv8 (DDI 0487A.d): D1-1509 Table D1-58 - * - * Unhandled: - * DBGOSLSR - * DBGPRCR - */ - case HSR_CPREG32(DBGOSLAR): - return handle_wo_wi(regs, regidx, cp32.read, hsr, 1); - case HSR_CPREG32(DBGOSDLR): - return handle_raz_wi(regs, regidx, cp32.read, hsr, 1); - - /* - * MDCR_EL2.TDA - * - * ARMv7 (DDI 0406C.b): B1.14.15 - * ARMv8 (DDI 0487A.d): D1-1510 Table D1-59 - * - * Unhandled: - * DBGDCCINT - * DBGDTRRXint - * DBGDTRTXint - * DBGWFAR - * DBGDTRTXext - * DBGDTRRXext, - * DBGBXVR - * DBGCLAIMSET - * DBGCLAIMCLR - * DBGAUTHSTATUS - * DBGDEVID - * DBGDEVID1 - * DBGDEVID2 - * DBGOSECCR - */ - case HSR_CPREG32(DBGDIDR): - { - uint32_t val; - - /* - * Read-only register. Accessible by EL0 if DBGDSCRext.UDCCdis - * is set to 0, which we emulated below. - */ - if ( !cp32.read ) - return inject_undef_exception(regs, hsr); - - /* Implement the minimum requirements: - * - Number of watchpoints: 1 - * - Number of breakpoints: 2 - * - Version: ARMv7 v7.1 - * - Variant and Revision bits match MDIR - */ - val = (1 << 24) | (5 << 16); - val |= ((d->arch.vpidr >> 20) & 0xf) | (d->arch.vpidr & 0xf); - set_user_reg(regs, regidx, val); - - break; - } - - case HSR_CPREG32(DBGDSCRINT): - /* - * Read-only register. Accessible by EL0 if DBGDSCRext.UDCCdis - * is set to 0, which we emulated below. - */ - return handle_ro_raz(regs, regidx, cp32.read, hsr, 1); - - case HSR_CPREG32(DBGDSCREXT): - /* - * Implement debug status and control register as RAZ/WI. - * The OS won't use Hardware debug if MDBGen not set. - */ - return handle_raz_wi(regs, regidx, cp32.read, hsr, 1); - - case HSR_CPREG32(DBGVCR): - case HSR_CPREG32(DBGBVR0): - case HSR_CPREG32(DBGBCR0): - case HSR_CPREG32(DBGWVR0): - case HSR_CPREG32(DBGWCR0): - case HSR_CPREG32(DBGBVR1): - case HSR_CPREG32(DBGBCR1): - return handle_raz_wi(regs, regidx, cp32.read, hsr, 1); - - /* - * CPTR_EL2.TTA - * - * ARMv7 (DDI 0406C.b): B1.14.16 - * ARMv8 (DDI 0487A.d): D1-1507 Table D1-54 - * - * - All implemented trace registers. - * - * MDCR_EL2.TDRA - * - * ARMv7 (DDI 0406C.b): B1.14.15 - * ARMv8 (DDI 0487A.d): D1-1508 Table D1-57 - * - * Unhandled: - * DBGDRAR (32-bit accesses) - * DBGDSAR (32-bit accesses) - * - * And all other unknown registers. - */ - default: - gdprintk(XENLOG_ERR, - "%s p14, %d, r%d, cr%d, cr%d, %d @ 0x%"PRIregister"\n", - cp32.read ? "mrc" : "mcr", - cp32.op1, cp32.reg, cp32.crn, cp32.crm, cp32.op2, regs->pc); - gdprintk(XENLOG_ERR, "unhandled 32-bit cp14 access %#x\n", - hsr.bits & HSR_CP32_REGS_MASK); - inject_undef_exception(regs, hsr); - return; - } - - advance_pc(regs, hsr); -} - -static void do_cp14_64(struct cpu_user_regs *regs, const union hsr hsr) -{ - const struct hsr_cp64 cp64 = hsr.cp64; - - if ( !check_conditional_instr(regs, hsr) ) - { - advance_pc(regs, hsr); - return; - } - - /* - * CPTR_EL2.TTA - * - * ARMv7 (DDI 0406C.b): B1.14.16 - * ARMv8 (DDI 0487A.d): D1-1507 Table D1-54 - * - * - All implemented trace registers. - * - * MDCR_EL2.TDRA - * - * ARMv7 (DDI 0406C.b): B1.14.15 - * ARMv8 (DDI 0487A.d): D1-1508 Table D1-57 - * - * Unhandled: - * DBGDRAR (64-bit accesses) - * DBGDSAR (64-bit accesses) - * - * And all other unknown registers. - */ - gdprintk(XENLOG_ERR, - "%s p14, %d, r%d, r%d, cr%d @ 0x%"PRIregister"\n", - cp64.read ? "mrrc" : "mcrr", - cp64.op1, cp64.reg1, cp64.reg2, cp64.crm, regs->pc); - gdprintk(XENLOG_ERR, "unhandled 64-bit CP14 access %#x\n", - hsr.bits & HSR_CP64_REGS_MASK); - inject_undef_exception(regs, hsr); -} - -static void do_cp14_dbg(struct cpu_user_regs *regs, const union hsr hsr) -{ - struct hsr_cp64 cp64 = hsr.cp64; - - if ( !check_conditional_instr(regs, hsr) ) - { - advance_pc(regs, hsr); - return; - } - - /* - * MDCR_EL2.TDOSA - * - * ARMv7 (DDI 0406C.b): B1.14.15 - * ARMv8 (DDI 0487A.d): D1-1509 Table D1-58 - * - * Unhandled: - * DBGDTRTXint - * DBGDTRRXint - * - * And all other unknown registers. - */ - gdprintk(XENLOG_ERR, - "%s p14, %d, r%d, r%d, cr%d @ 0x%"PRIregister"\n", - cp64.read ? "mrrc" : "mcrr", - cp64.op1, cp64.reg1, cp64.reg2, cp64.crm, regs->pc); - gdprintk(XENLOG_ERR, "unhandled 64-bit CP14 DBG access %#x\n", - hsr.bits & HSR_CP64_REGS_MASK); - - inject_undef_exception(regs, hsr); -} - -static void do_cp(struct cpu_user_regs *regs, const union hsr hsr) -{ - const struct hsr_cp cp = hsr.cp; - - if ( !check_conditional_instr(regs, hsr) ) - { - advance_pc(regs, hsr); - return; - } - - ASSERT(!cp.tas); /* We don't trap SIMD instruction */ - gdprintk(XENLOG_ERR, "unhandled CP%d access\n", cp.coproc); - inject_undef_exception(regs, hsr); -} - void dump_guest_s1_walk(struct domain *d, vaddr_t addr) { register_t ttbcr = READ_SYSREG(TCR_EL1); diff --git a/xen/arch/arm/vcpreg.c b/xen/arch/arm/vcpreg.c new file mode 100644 index 0000000000..f3b08403fb --- /dev/null +++ b/xen/arch/arm/vcpreg.c @@ -0,0 +1,451 @@ +/* + * xen/arch/arm/arm64/vcpreg.c + * + * Emulate co-processor registers trapped. + * + * Copyright (c) 2011 Citrix Systems. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +#include +#include +#include +#include + +void do_cp15_32(struct cpu_user_regs *regs, const union hsr hsr) +{ + const struct hsr_cp32 cp32 = hsr.cp32; + int regidx = cp32.reg; + struct vcpu *v = current; + + if ( !check_conditional_instr(regs, hsr) ) + { + advance_pc(regs, hsr); + return; + } + + switch ( hsr.bits & HSR_CP32_REGS_MASK ) + { + /* + * !CNTHCTL_EL2.EL1PCEN / !CNTHCTL.PL1PCEN + * + * ARMv7 (DDI 0406C.b): B4.1.22 + * ARMv8 (DDI 0487A.d): D1-1510 Table D1-60 + */ + case HSR_CPREG32(CNTP_CTL): + case HSR_CPREG32(CNTP_TVAL): + if ( !vtimer_emulate(regs, hsr) ) + return inject_undef_exception(regs, hsr); + break; + + /* + * HCR_EL2.TACR / HCR.TAC + * + * ARMv7 (DDI 0406C.b): B1.14.6 + * ARMv8 (DDI 0487A.d): G6.2.1 + */ + case HSR_CPREG32(ACTLR): + if ( psr_mode_is_user(regs) ) + return inject_undef_exception(regs, hsr); + if ( cp32.read ) + set_user_reg(regs, regidx, v->arch.actlr); + break; + + /* + * MDCR_EL2.TPM + * + * ARMv7 (DDI 0406C.b): B1.14.17 + * ARMv8 (DDI 0487A.d): D1-1511 Table D1-61 + * + * Unhandled: + * PMEVCNTR + * PMEVTYPER + * PMCCFILTR + * + * MDCR_EL2.TPMCR + * + * ARMv7 (DDI 0406C.b): B1.14.17 + * ARMv8 (DDI 0487A.d): D1-1511 Table D1-62 + * + * NB: Both MDCR_EL2.TPM and MDCR_EL2.TPMCR cause trapping of PMCR. + */ + /* We could trap ID_DFR0 and tell the guest we don't support + * performance monitoring, but Linux doesn't check the ID_DFR0. + * Therefore it will read PMCR. + * + * We tell the guest we have 0 counters. Unfortunately we must + * always support PMCCNTR (the cyle counter): we just RAZ/WI for all + * PM register, which doesn't crash the kernel at least + */ + case HSR_CPREG32(PMUSERENR): + /* RO at EL0. RAZ/WI at EL1 */ + if ( psr_mode_is_user(regs) ) + return handle_ro_raz(regs, regidx, cp32.read, hsr, 0); + else + return handle_raz_wi(regs, regidx, cp32.read, hsr, 1); + case HSR_CPREG32(PMINTENSET): + case HSR_CPREG32(PMINTENCLR): + /* EL1 only, however MDCR_EL2.TPM==1 means EL0 may trap here also. */ + return handle_raz_wi(regs, regidx, cp32.read, hsr, 1); + case HSR_CPREG32(PMCR): + case HSR_CPREG32(PMCNTENSET): + case HSR_CPREG32(PMCNTENCLR): + case HSR_CPREG32(PMOVSR): + case HSR_CPREG32(PMSWINC): + case HSR_CPREG32(PMSELR): + case HSR_CPREG32(PMCEID0): + case HSR_CPREG32(PMCEID1): + case HSR_CPREG32(PMCCNTR): + case HSR_CPREG32(PMXEVTYPER): + case HSR_CPREG32(PMXEVCNTR): + case HSR_CPREG32(PMOVSSET): + /* + * Accessible at EL0 only if PMUSERENR_EL0.EN is set. We + * emulate that register as 0 above. + */ + return handle_raz_wi(regs, regidx, cp32.read, hsr, 1); + + /* + * HCR_EL2.TIDCP + * + * ARMv7 (DDI 0406C.b): B1.14.3 + * ARMv8 (DDI 0487A.d): D1-1501 Table D1-43 + * + * - CRn==c9, opc1=={0-7}, CRm=={c0-c2, c5-c8}, opc2=={0-7} + * (Cache and TCM lockdown registers) + * - CRn==c10, opc1=={0-7}, CRm=={c0, c1, c4, c8}, opc2=={0-7} + * (VMSA CP15 c10 registers) + * - CRn==c11, opc1=={0-7}, CRm=={c0-c8, c15}, opc2=={0-7} + * (VMSA CP15 c11 registers) + * + * CPTR_EL2.T{0..9,12..13} + * + * ARMv7 (DDI 0406C.b): B1.14.12 + * ARMv8 (DDI 0487A.d): N/A + * + * - All accesses to coprocessors 0..9 and 12..13 + * + * HSTR_EL2.T15 + * + * ARMv7 (DDI 0406C.b): B1.14.14 + * ARMv8 (DDI 0487A.d): D1-1507 Table D1-55 + * + * - All accesses to cp15, c15 registers. + * + * And all other unknown registers. + */ + default: + gdprintk(XENLOG_ERR, + "%s p15, %d, r%d, cr%d, cr%d, %d @ 0x%"PRIregister"\n", + cp32.read ? "mrc" : "mcr", + cp32.op1, cp32.reg, cp32.crn, cp32.crm, cp32.op2, regs->pc); + gdprintk(XENLOG_ERR, "unhandled 32-bit CP15 access %#x\n", + hsr.bits & HSR_CP32_REGS_MASK); + inject_undef_exception(regs, hsr); + return; + } + advance_pc(regs, hsr); +} + +void do_cp15_64(struct cpu_user_regs *regs, const union hsr hsr) +{ + if ( !check_conditional_instr(regs, hsr) ) + { + advance_pc(regs, hsr); + return; + } + + switch ( hsr.bits & HSR_CP64_REGS_MASK ) + { + /* + * !CNTHCTL_EL2.EL1PCEN / !CNTHCTL.PL1PCEN + * + * ARMv7 (DDI 0406C.b): B4.1.22 + * ARMv8 (DDI 0487A.d): D1-1510 Table D1-60 + */ + case HSR_CPREG64(CNTP_CVAL): + if ( !vtimer_emulate(regs, hsr) ) + return inject_undef_exception(regs, hsr); + break; + + /* + * HCR_EL2.FMO or HCR_EL2.IMO + * + * GIC Architecture Specification (IHI 0069C): Section 4.6.3 + */ + case HSR_CPREG64(ICC_SGI1R): + case HSR_CPREG64(ICC_ASGI1R): + case HSR_CPREG64(ICC_SGI0R): + if ( !vgic_emulate(regs, hsr) ) + return inject_undef_exception(regs, hsr); + break; + + /* + * CPTR_EL2.T{0..9,12..13} + * + * ARMv7 (DDI 0406C.b): B1.14.12 + * ARMv8 (DDI 0487A.d): N/A + * + * - All accesses to coprocessors 0..9 and 12..13 + * + * HSTR_EL2.T15 + * + * ARMv7 (DDI 0406C.b): B1.14.14 + * ARMv8 (DDI 0487A.d): D1-1507 Table D1-55 + * + * - All accesses to cp15, c15 registers. + * + * And all other unknown registers. + */ + default: + { + const struct hsr_cp64 cp64 = hsr.cp64; + + gdprintk(XENLOG_ERR, + "%s p15, %d, r%d, r%d, cr%d @ 0x%"PRIregister"\n", + cp64.read ? "mrrc" : "mcrr", + cp64.op1, cp64.reg1, cp64.reg2, cp64.crm, regs->pc); + gdprintk(XENLOG_ERR, "unhandled 64-bit CP15 access %#x\n", + hsr.bits & HSR_CP64_REGS_MASK); + inject_undef_exception(regs, hsr); + return; + } + } + advance_pc(regs, hsr); +} + +void do_cp14_32(struct cpu_user_regs *regs, const union hsr hsr) +{ + const struct hsr_cp32 cp32 = hsr.cp32; + int regidx = cp32.reg; + struct domain *d = current->domain; + + if ( !check_conditional_instr(regs, hsr) ) + { + advance_pc(regs, hsr); + return; + } + + switch ( hsr.bits & HSR_CP32_REGS_MASK ) + { + /* + * MDCR_EL2.TDOSA + * + * ARMv7 (DDI 0406C.b): B1.14.15 + * ARMv8 (DDI 0487A.d): D1-1509 Table D1-58 + * + * Unhandled: + * DBGOSLSR + * DBGPRCR + */ + case HSR_CPREG32(DBGOSLAR): + return handle_wo_wi(regs, regidx, cp32.read, hsr, 1); + case HSR_CPREG32(DBGOSDLR): + return handle_raz_wi(regs, regidx, cp32.read, hsr, 1); + + /* + * MDCR_EL2.TDA + * + * ARMv7 (DDI 0406C.b): B1.14.15 + * ARMv8 (DDI 0487A.d): D1-1510 Table D1-59 + * + * Unhandled: + * DBGDCCINT + * DBGDTRRXint + * DBGDTRTXint + * DBGWFAR + * DBGDTRTXext + * DBGDTRRXext, + * DBGBXVR + * DBGCLAIMSET + * DBGCLAIMCLR + * DBGAUTHSTATUS + * DBGDEVID + * DBGDEVID1 + * DBGDEVID2 + * DBGOSECCR + */ + case HSR_CPREG32(DBGDIDR): + { + uint32_t val; + + /* + * Read-only register. Accessible by EL0 if DBGDSCRext.UDCCdis + * is set to 0, which we emulated below. + */ + if ( !cp32.read ) + return inject_undef_exception(regs, hsr); + + /* Implement the minimum requirements: + * - Number of watchpoints: 1 + * - Number of breakpoints: 2 + * - Version: ARMv7 v7.1 + * - Variant and Revision bits match MDIR + */ + val = (1 << 24) | (5 << 16); + val |= ((d->arch.vpidr >> 20) & 0xf) | (d->arch.vpidr & 0xf); + set_user_reg(regs, regidx, val); + + break; + } + + case HSR_CPREG32(DBGDSCRINT): + /* + * Read-only register. Accessible by EL0 if DBGDSCRext.UDCCdis + * is set to 0, which we emulated below. + */ + return handle_ro_raz(regs, regidx, cp32.read, hsr, 1); + + case HSR_CPREG32(DBGDSCREXT): + /* + * Implement debug status and control register as RAZ/WI. + * The OS won't use Hardware debug if MDBGen not set. + */ + return handle_raz_wi(regs, regidx, cp32.read, hsr, 1); + + case HSR_CPREG32(DBGVCR): + case HSR_CPREG32(DBGBVR0): + case HSR_CPREG32(DBGBCR0): + case HSR_CPREG32(DBGWVR0): + case HSR_CPREG32(DBGWCR0): + case HSR_CPREG32(DBGBVR1): + case HSR_CPREG32(DBGBCR1): + return handle_raz_wi(regs, regidx, cp32.read, hsr, 1); + + /* + * CPTR_EL2.TTA + * + * ARMv7 (DDI 0406C.b): B1.14.16 + * ARMv8 (DDI 0487A.d): D1-1507 Table D1-54 + * + * - All implemented trace registers. + * + * MDCR_EL2.TDRA + * + * ARMv7 (DDI 0406C.b): B1.14.15 + * ARMv8 (DDI 0487A.d): D1-1508 Table D1-57 + * + * Unhandled: + * DBGDRAR (32-bit accesses) + * DBGDSAR (32-bit accesses) + * + * And all other unknown registers. + */ + default: + gdprintk(XENLOG_ERR, + "%s p14, %d, r%d, cr%d, cr%d, %d @ 0x%"PRIregister"\n", + cp32.read ? "mrc" : "mcr", + cp32.op1, cp32.reg, cp32.crn, cp32.crm, cp32.op2, regs->pc); + gdprintk(XENLOG_ERR, "unhandled 32-bit cp14 access %#x\n", + hsr.bits & HSR_CP32_REGS_MASK); + inject_undef_exception(regs, hsr); + return; + } + + advance_pc(regs, hsr); +} + +void do_cp14_64(struct cpu_user_regs *regs, const union hsr hsr) +{ + const struct hsr_cp64 cp64 = hsr.cp64; + + if ( !check_conditional_instr(regs, hsr) ) + { + advance_pc(regs, hsr); + return; + } + + /* + * CPTR_EL2.TTA + * + * ARMv7 (DDI 0406C.b): B1.14.16 + * ARMv8 (DDI 0487A.d): D1-1507 Table D1-54 + * + * - All implemented trace registers. + * + * MDCR_EL2.TDRA + * + * ARMv7 (DDI 0406C.b): B1.14.15 + * ARMv8 (DDI 0487A.d): D1-1508 Table D1-57 + * + * Unhandled: + * DBGDRAR (64-bit accesses) + * DBGDSAR (64-bit accesses) + * + * And all other unknown registers. + */ + gdprintk(XENLOG_ERR, + "%s p14, %d, r%d, r%d, cr%d @ 0x%"PRIregister"\n", + cp64.read ? "mrrc" : "mcrr", + cp64.op1, cp64.reg1, cp64.reg2, cp64.crm, regs->pc); + gdprintk(XENLOG_ERR, "unhandled 64-bit CP14 access %#x\n", + hsr.bits & HSR_CP64_REGS_MASK); + inject_undef_exception(regs, hsr); +} + +void do_cp14_dbg(struct cpu_user_regs *regs, const union hsr hsr) +{ + struct hsr_cp64 cp64 = hsr.cp64; + + if ( !check_conditional_instr(regs, hsr) ) + { + advance_pc(regs, hsr); + return; + } + + /* + * MDCR_EL2.TDOSA + * + * ARMv7 (DDI 0406C.b): B1.14.15 + * ARMv8 (DDI 0487A.d): D1-1509 Table D1-58 + * + * Unhandled: + * DBGDTRTXint + * DBGDTRRXint + * + * And all other unknown registers. + */ + gdprintk(XENLOG_ERR, + "%s p14, %d, r%d, r%d, cr%d @ 0x%"PRIregister"\n", + cp64.read ? "mrrc" : "mcrr", + cp64.op1, cp64.reg1, cp64.reg2, cp64.crm, regs->pc); + gdprintk(XENLOG_ERR, "unhandled 64-bit CP14 DBG access %#x\n", + hsr.bits & HSR_CP64_REGS_MASK); + + inject_undef_exception(regs, hsr); +} + +void do_cp(struct cpu_user_regs *regs, const union hsr hsr) +{ + const struct hsr_cp cp = hsr.cp; + + if ( !check_conditional_instr(regs, hsr) ) + { + advance_pc(regs, hsr); + return; + } + + ASSERT(!cp.tas); /* We don't trap SIMD instruction */ + gdprintk(XENLOG_ERR, "unhandled CP%d access\n", cp.coproc); + inject_undef_exception(regs, hsr); +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/include/asm-arm/traps.h b/xen/include/asm-arm/traps.h index 6d99d228e8..53d386d8e5 100644 --- a/xen/include/asm-arm/traps.h +++ b/xen/include/asm-arm/traps.h @@ -24,6 +24,14 @@ void handle_wo_wi(struct cpu_user_regs *regs, int regidx, bool read, void handle_ro_raz(struct cpu_user_regs *regs, int regidx, bool read, const union hsr hsr, int min_el); +/* Co-processor registers emulation (see arch/arm/vcpreg.c). */ +void do_cp15_32(struct cpu_user_regs *regs, const union hsr hsr); +void do_cp15_64(struct cpu_user_regs *regs, const union hsr hsr); +void do_cp14_32(struct cpu_user_regs *regs, const union hsr hsr); +void do_cp14_64(struct cpu_user_regs *regs, const union hsr hsr); +void do_cp14_dbg(struct cpu_user_regs *regs, const union hsr hsr); +void do_cp(struct cpu_user_regs *regs, const union hsr hsr); + #endif /* __ASM_ARM_TRAPS__ */ /* * Local variables: From patchwork Tue Sep 12 10:36:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 112290 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp4986330qgf; Tue, 12 Sep 2017 03:38:44 -0700 (PDT) X-Google-Smtp-Source: AOwi7QCFuS7bZJ2dP97b+7ZnOFCVW55M+WIpEqoX3sbifZIVIj1v622AGqCcxTPbvOET30CHVfxg X-Received: by 10.36.33.78 with SMTP id e75mr384118ita.128.1505212724586; Tue, 12 Sep 2017 03:38:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505212724; cv=none; d=google.com; s=arc-20160816; b=Cu/c+2eS2w0U5KS8wpQMSuByyOlLMGvHB+LzRUr4K5vcibIB+QWdpdoyRW+Q46gQ30 UvfZUx5gLtFc8RZxH0hxd73iphg208a6jqiyLbj2fGQ/Q3Z9F8XMvl9oBmKNN1GNy8SS eZ3Yfk3qeb189THurVtJeHIMhrQwfb0Q76ZsrKIklfpgk4MKnB0HtJf59L/f6JHeBuvl x4/uxAUDfW4zGnPxUkDdgvMzzjZAVOcb246JabVLqE0MCAxYJ1iXjdPr5dJuWVvXk+FJ PSH0puknCWGdjMpwHK8HJiCBdH18IAHYiXEk3weEXV+gaRPH+gaC0c4TWBMYzYVyH+ol Cssw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=pN30eCytd985nM+mIOl+XQCEgsjk2VVuwNln/Xr0hBA=; b=f5auNmPWBhy2qasl+bnpuz7uQro/B3zDjidW5uyu1X2X51IIFEMOil3MNZWYhKEmw6 UPYhCOIbPl2leYIcl8MY+2T9vwrHdg5K97y2cDO6HP+/6EaERir7A7n1qTLx2ne+CRJO r4c+eycXt4cQb9dMrceq3KMqkVmdfKuXZW1pbbCT70IGfPt/CAE2lfkO7TNQeDKyUyMj Fl0NbJQ2FS52jGf/Z6D/hE2AMypF5Jf2nD91fiS14gNtu84MCdLC0OmqHvlitKp6V4MD KHIJxBsRNiLXT77LsZPMX9hYKMgy5V9/PDjxI8qZd2upbXMWint+rE4GD+qTcphE8xox wPtg== ARC-Authentication-Results: i=1; mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id p78si10583888ioi.287.2017.09.12.03.38.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Sep 2017 03:38:44 -0700 (PDT) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1driYb-0001Rj-G9; Tue, 12 Sep 2017 10:36:41 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1driYa-0001OP-4d for xen-devel@lists.xen.org; Tue, 12 Sep 2017 10:36:40 +0000 Received: from [85.158.143.35] by server-5.bemta-6.messagelabs.com id BA/13-03454-7B8B7B95; Tue, 12 Sep 2017 10:36:39 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrALMWRWlGSWpSXmKPExsVysyfVTXfrju2 RBgcuSlss+biYxYHR4+ju30wBjFGsmXlJ+RUJrBk/l05nLVjMX3H8qkMD40LeLkYuDiGBzYwS S/+2sEA4pxklVu24xdTFyMnBJqApcefzJzBbREBa4trny4wgNrNAnMT7RY0sILawgJvExuY3Q DYHB4uAqkTvQV+QMK+ApcTReV+ZQWwJAXmJXW0XWUFsTgEriUWvFoCVCwHVXNosOYGRewEjwy pGjeLUorLUIl1DA72kosz0jJLcxMwcIM9MLze1uDgxPTUnMalYLzk/dxMj0LcMQLCD8fj7uEO MkhxMSqK8R9ZvjxTiS8pPqcxILM6ILyrNSS0+xCjDwaEkwXtyO1BOsCg1PbUiLTMHGGQwaQkO HiUR3nMgad7igsTc4sx0iNQpRl2Ojpt3/zAJseTl56VKifOWghQJgBRllObBjYAF/CVGWSlhX kago4R4ClKLcjNLUOVfMYpzMCoJ814FmcKTmVcCt+kV0BFMQEfwXNoCckRJIkJKqoGxfq2Tio jZdN+CfQGvN56+dXKNFoOVqPrv4uXSs71+iv46rOm2r/3Tv8tPcxvcuObEmyzM2qPK8sXh8qI Eh97izTUxTT1sc03TtU1CczwK04rXX45kO1iaeGruq02vbrH+ETq4+XBTyJNPn5e6bDGJPGHG aPG7h/+DR5OBWtD5swE5deu8+NSUWIozEg21mIuKEwHzaeAjcwIAAA== X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-7.tower-21.messagelabs.com!1505212597!82461341!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.4.45; banners=-,-,- X-VirusChecked: Checked Received: (qmail 34886 invoked from network); 12 Sep 2017 10:36:37 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-7.tower-21.messagelabs.com with SMTP; 12 Sep 2017 10:36:37 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BC27215A2; Tue, 12 Sep 2017 03:36:36 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CE1A33F578; Tue, 12 Sep 2017 03:36:35 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Tue, 12 Sep 2017 11:36:21 +0100 Message-Id: <20170912103622.18562-7-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170912103622.18562-1-julien.grall@arm.com> References: <20170912103622.18562-1-julien.grall@arm.com> Cc: bhupinder.thakur@linaro.org, Julien Grall , sstabellini@kernel.org Subject: [Xen-devel] [PATCH v2 6/7] xen/arm: Move sysregs.h in arm64 sub-directory X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" sysregs.h contains only code protected by #ifdef CONFIG_ARM_64. Move it in arm64 sub-directory to reflect that and remove the #ifdef. At the same time, fixup the guards. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- xen/include/asm-arm/arm64/processor.h | 2 ++ xen/include/asm-arm/{ => arm64}/sysregs.h | 10 +++------- xen/include/asm-arm/processor.h | 1 - 3 files changed, 5 insertions(+), 8 deletions(-) rename xen/include/asm-arm/{ => arm64}/sysregs.h (98%) diff --git a/xen/include/asm-arm/arm64/processor.h b/xen/include/asm-arm/arm64/processor.h index 24f836b023..c18ab7203d 100644 --- a/xen/include/asm-arm/arm64/processor.h +++ b/xen/include/asm-arm/arm64/processor.h @@ -3,6 +3,8 @@ #include +#include + #ifndef __ASSEMBLY__ /* Anonymous union includes both 32- and 64-bit names (e.g., r0/x0). */ diff --git a/xen/include/asm-arm/sysregs.h b/xen/include/asm-arm/arm64/sysregs.h similarity index 98% rename from xen/include/asm-arm/sysregs.h rename to xen/include/asm-arm/arm64/sysregs.h index 887368e248..084d2a1e5d 100644 --- a/xen/include/asm-arm/sysregs.h +++ b/xen/include/asm-arm/arm64/sysregs.h @@ -1,7 +1,5 @@ -#ifndef __ASM_ARM_SYSREGS_H -#define __ASM_ARM_SYSREGS_H - -#ifdef CONFIG_ARM_64 +#ifndef __ASM_ARM_ARM64_SYSREGS_H +#define __ASM_ARM_ARM64_SYSREGS_H #include @@ -168,9 +166,7 @@ #define ICH_AP1R2_EL2 __AP1Rx_EL2(2) #define ICH_AP1R3_EL2 __AP1Rx_EL2(3) -#endif - -#endif +#endif /* _ASM_ARM_ARM64_SYSREGS_H */ /* * Local variables: diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index 9f7a42f86b..d791c12c9c 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -2,7 +2,6 @@ #define __ASM_ARM_PROCESSOR_H #include -#include #ifndef __ASSEMBLY__ #include #endif From patchwork Tue Sep 12 10:36:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 112291 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp4986347qgf; Tue, 12 Sep 2017 03:38:45 -0700 (PDT) X-Google-Smtp-Source: AOwi7QDqTUv3n6a46kWmtaHbshqZl8T+urGDWq8r6CofZvl+dhmCZqfSHveglkdSdqDcKI+ixutB X-Received: by 10.36.81.71 with SMTP id s68mr318919ita.90.1505212725420; Tue, 12 Sep 2017 03:38:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505212725; cv=none; d=google.com; s=arc-20160816; b=vcq0kSQl5vcRhOD7Ng+kdo38swBIb3+/AOTjvzUB4E0xkDwn4rRMOENDksGtW3hFiN iZtRPKnrr8upmHTRTlxw+zAqzM6WUoQKEfYUOMAtsuZJvTyORyqm13oRHy6fKAlmtnA+ 1EcAQcTPNeXrXaPRyZPcgYezg4Oa8+VuK52+vytreJQEM+yGXfiU617EBR/H17+J/4zv okBfouoNBZytp3MgeDJLM0zinOeL7PK9MptB7v+RVvJnfUSiJ4F+F3GlAPHZJYs2fCXq hNB0CBM5MIhZd/cqJrJULj+yztXxinOLGhWzeUfwVYY5UqMbjZaz8EDTC06S/4wlauke TusA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=pJHJ1xiXxeXW9MMVT03lYN7UkZKiZmvCS2/DCaivSdY=; b=Fclt8C9uoe/XtC0HUHTeMwiAPcCtSGHm4lhpkmFfljssvdv4aveWD0tv/CW0fBoKIM /FNflheSi4G38JjkQqcud2zzrdnWSxVkR3h219eEA7syWlsDBVUQ/gjPAJDgGY3tT/Mw leJa05XhCU8nIqXf8m6SteQbcXt04/C9BjjAxPiVLMMKcJUdLUevVStAX8ffqxj3c+39 8oZ+FRP2DAklOc0QcRRip2VsK/5DvYTIsfD60RQCw7iIMfPSjRxH+IFRbVweKwGaqMvI hD8seyyiqB2hOip6TEC+y/6lKsRgEilcSJKHLU/+fhwQDbLvnocyMr/tuEggr+UlMEQE RP8w== ARC-Authentication-Results: i=1; mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id d190si4232926iof.18.2017.09.12.03.38.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Sep 2017 03:38:45 -0700 (PDT) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1driYb-0001RG-8D; Tue, 12 Sep 2017 10:36:41 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1driYZ-0001Ph-WC for xen-devel@lists.xen.org; Tue, 12 Sep 2017 10:36:40 +0000 Received: from [85.158.139.211] by server-10.bemta-5.messagelabs.com id E2/CF-00743-7B8B7B95; Tue, 12 Sep 2017 10:36:39 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrILMWRWlGSWpSXmKPExsVysyfVTXfbju2 RBjt+61gs+biYxYHR4+ju30wBjFGsmXlJ+RUJrBmvL39hKzgnVXGo5ytrA+MTsS5GLg4hgc2M Ei0n77NAOKcZJTbvbWDsYuTkYBPQlLjz+RMTiC0iIC1x7fNlsDizQJzE+0WNLCC2sICNxIaZS 9lBbBYBVYlpXZPZQGxeAUuJGxNOsILYEgLyErvaLoLZnAJWEoteLQDq5QBaZilxabPkBEbuBY wMqxjVi1OLylKLdI31kooy0zNKchMzc3QNDUz1clOLixPTU3MSk4r1kvNzNzECvcsABDsY9/5 zOsQoycGkJMp7ZP32SCG+pPyUyozE4oz4otKc1OJDjDIcHEoSvGzAYBESLEpNT61Iy8wBhhlM WoKDR0mE99x2oDRvcUFibnFmOkTqFKMuR8fNu3+YhFjy8vNSpcR5b4IUCYAUZZTmwY2AhfwlR lkpYV5GoKOEeApSi3IzS1DlXzGKczAqCfMKg1zCk5lXArfpFdARTEBH8FzaAnJESSJCSqqBcc bZhtr1Z7hXlKpU/FBY9L1r5sS+KMFP1xyU5sU33oua+OzInCofp5bNftPK9lRyn9f0fSN0tk5 LKpWFMbrhdcXOK2FXP4ccVL9V94jD7+mXPw/3zzIwehRz5+2BLLe+p87MX76YT9DbFvNFheXN qnT++7GfVR5tOZSYsc46e4PJ9wuJBeopT5VYijMSDbWYi4oTAUJ0uzl0AgAA X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-12.tower-206.messagelabs.com!1505212598!74839376!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.4.45; banners=-,-,- X-VirusChecked: Checked Received: (qmail 13646 invoked from network); 12 Sep 2017 10:36:38 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-12.tower-206.messagelabs.com with SMTP; 12 Sep 2017 10:36:38 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E5B921529; Tue, 12 Sep 2017 03:36:37 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0353A3F578; Tue, 12 Sep 2017 03:36:36 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Tue, 12 Sep 2017 11:36:22 +0100 Message-Id: <20170912103622.18562-8-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170912103622.18562-1-julien.grall@arm.com> References: <20170912103622.18562-1-julien.grall@arm.com> Cc: bhupinder.thakur@linaro.org, Julien Grall , sstabellini@kernel.org Subject: [Xen-devel] [PATCH v2 7/7] xen/arm: Limit the scope of cpregs.h X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" Currently, cpregs.h is included in pretty much every files even for arm64. However, the only use for arm64 is when emulating co-processors. For arm32, all users of processor.h expect cpregs.h to be included in order to access co-processors. So move the inclusion in asm-arm/arm32/processor.h. cpregs.h will also be directly included in the co-processors emulation to accommodate arm64. Signed-off-by: Julien Grall Acked-by: Stefano Stabellini --- Changes in v2: - Update commit message --- xen/arch/arm/smp.c | 1 - xen/arch/arm/vcpreg.c | 1 + xen/arch/arm/vgic-v3.c | 1 + xen/arch/arm/vtimer.c | 2 ++ xen/include/asm-arm/arm32/processor.h | 2 ++ xen/include/asm-arm/percpu.h | 1 - xen/include/asm-arm/processor.h | 1 - 7 files changed, 6 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/smp.c b/xen/arch/arm/smp.c index e7df0874d6..554f4992e6 100644 --- a/xen/arch/arm/smp.c +++ b/xen/arch/arm/smp.c @@ -1,6 +1,5 @@ #include #include -#include #include #include #include diff --git a/xen/arch/arm/vcpreg.c b/xen/arch/arm/vcpreg.c index f3b08403fb..e363183ba8 100644 --- a/xen/arch/arm/vcpreg.c +++ b/xen/arch/arm/vcpreg.c @@ -18,6 +18,7 @@ #include +#include #include #include #include diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index cbeac28b28..a0cf993d13 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -26,6 +26,7 @@ #include #include +#include #include #include #include diff --git a/xen/arch/arm/vtimer.c b/xen/arch/arm/vtimer.c index 9c7e8f441c..0460962f08 100644 --- a/xen/arch/arm/vtimer.c +++ b/xen/arch/arm/vtimer.c @@ -22,6 +22,7 @@ #include #include +#include #include #include #include @@ -29,6 +30,7 @@ #include #include #include +#include /* * Check if regs is allowed access, user_gate is tail end of a diff --git a/xen/include/asm-arm/arm32/processor.h b/xen/include/asm-arm/arm32/processor.h index 68cc82147e..fb330812af 100644 --- a/xen/include/asm-arm/arm32/processor.h +++ b/xen/include/asm-arm/arm32/processor.h @@ -1,6 +1,8 @@ #ifndef __ASM_ARM_ARM32_PROCESSOR_H #define __ASM_ARM_ARM32_PROCESSOR_H +#include + #define ACTLR_CAXX_SMP (1<<6) #ifndef __ASSEMBLY__ diff --git a/xen/include/asm-arm/percpu.h b/xen/include/asm-arm/percpu.h index 7968532462..cdf64e0f77 100644 --- a/xen/include/asm-arm/percpu.h +++ b/xen/include/asm-arm/percpu.h @@ -4,7 +4,6 @@ #ifndef __ASSEMBLY__ #include -#include #if defined(CONFIG_ARM_32) # include #elif defined(CONFIG_ARM_64) diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index d791c12c9c..cd45e5f48f 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -1,7 +1,6 @@ #ifndef __ASM_ARM_PROCESSOR_H #define __ASM_ARM_PROCESSOR_H -#include #ifndef __ASSEMBLY__ #include #endif