From patchwork Tue Sep 12 14:59:46 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Greenhalgh X-Patchwork-Id: 112319 Delivered-To: patch@linaro.org Received: by 10.80.202.13 with SMTP id d13csp36781edi; Tue, 12 Sep 2017 08:00:41 -0700 (PDT) X-Google-Smtp-Source: ADKCNb7RKNLE+PzIP80D8XW2jTOWn48lFyFNkPfKw6ReHSMFn1C+kUMQ+LIkM6uin/MaeVExghaQ X-Received: by 10.99.43.4 with SMTP id r4mr14738903pgr.380.1505228441506; Tue, 12 Sep 2017 08:00:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505228441; cv=none; d=google.com; s=arc-20160816; b=Ji11Oay5g9MeD0LSPV+lgQX2Px/nUFGMfwA31RGd2xshSdQIV/kGCBuEiT8zVnw+7J cqXzyrc1oFNLx6pz+Vqtqwo9K61hH5r6FUusJ5mQRzyOFS/EXgU8yEjmqYDvHPj/Ehcm yDX0xun9ImBIKkdXBlJ4vzoKMwFZTLU+b4CX34mY3pNLmyEIb3lDabeS+qt9oJaVNuJe p2M8CIde6Fuu0/kBOI2b10AEdLUpihQleuxq0fRaHpfHLRa1iurFWE6LivPzBAAbkkB1 hQeX8L0ZCHfWKA9q1rsNFG4cF/r7WKkMd4+hPo46zvNBV8M2CP0TlnM5/QIZfh3PIzso yHJw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=spamdiagnosticmetadata:spamdiagnosticoutput:nodisclaimer :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:delivered-to:sender:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:mailing-list:dkim-signature :domainkey-signature:arc-authentication-results; bh=KPmu87v2owIDR/LwjLOyuIyCBfAr3Q6qiexPZR/lOno=; b=byW3lYN3a7/3bU0/xYJZ1A6jo4dGvZInQLFLLGKXYWksNgDVOmmGNI9m4ihk8Hnlld l99T46aUHXyhnhMH+udOCehAqnfZl52lJbPpILIvzKvA0LWiXVr8tXBoQh0XlxrtnYP5 0WfIe3RGdZjx1BuFaYrMynDSZopBD+MmF3KU81xkxN/4zHEqwA7VVfKW2BEG0b++hdeX 7SK+mu3+N3td4EcDgG3XRPg83poQAbMsOv59iZ0w4Y9m2NVSxcsW5Z2g3PeLUPJDg1yX eyTSGDA/oZLK1IobT8Dbyevb5UnYovFyZ0ob39mdWAHkhOHoaniyxrpx/UtTwA1mxau8 euOA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=X202K3gA; spf=pass (google.com: domain of gcc-patches-return-461941-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-461941-patch=linaro.org@gcc.gnu.org Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id p7si7688237pgd.539.2017.09.12.08.00.41 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Sep 2017 08:00:41 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-461941-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=X202K3gA; spf=pass (google.com: domain of gcc-patches-return-461941-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-461941-patch=linaro.org@gcc.gnu.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; q=dns; s=default; b=B++6m0HiIRJOccKY us3jTpdgtBALY/LELewRXoucazJl5HDXgdqq/8CAqre7+mlBjm39UMUbTQunuPZA 1YazmkN8L950RI5THPEdaCPg3hDVD+oKQ+QrSasRxrFkc0n3hlEBxeFCi7qNmGpu I4ynn7Qfjmsz7jsGJelu6yoyI6g= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; s=default; bh=cOsrPF3shAxIU4SRVQdyuy eY6ww=; b=X202K3gAGpDKYQ2g0kVqX0f8hu/aHpaYAOF5yazULl9LMn+dccF4Pp vBLIMs0kMWpuo7AYE4qJDTb2OYyNKkSMLXfuU4kVVvcx/Ow5ksugq3AqjqTD+Fac d2/VArCx9xwVuCrHSXBjmxxMTbZ7Q9O7pHpQbs0/r9IGv+5TCXpR8= Received: (qmail 8407 invoked by alias); 12 Sep 2017 15:00:26 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 8340 invoked by uid 89); 12 Sep 2017 15:00:23 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-24.6 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_HELO_PASS, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: EUR01-VE1-obe.outbound.protection.outlook.com Received: from mail-ve1eur01on0081.outbound.protection.outlook.com (HELO EUR01-VE1-obe.outbound.protection.outlook.com) (104.47.1.81) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 12 Sep 2017 15:00:16 +0000 Received: from HE1PR0801CA0019.eurprd08.prod.outlook.com (2603:10a6:3:6::29) by AM4PR0801MB1523.eurprd08.prod.outlook.com (2603:10a6:200:3d::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.20.35.12; Tue, 12 Sep 2017 15:00:06 +0000 Received: from VE1EUR03FT044.eop-EUR03.prod.protection.outlook.com (2a01:111:f400:7e09::209) by HE1PR0801CA0019.outlook.office365.com (2603:10a6:3:6::29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.20.56.9 via Frontend Transport; Tue, 12 Sep 2017 15:00:05 +0000 Authentication-Results: spf=pass (sender IP is 217.140.96.140) smtp.mailfrom=arm.com; gcc.gnu.org; dkim=none (message not signed) header.d=none; gcc.gnu.org; dmarc=bestguesspass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 217.140.96.140 as permitted sender) receiver=protection.outlook.com; client-ip=217.140.96.140; helo=nebula.arm.com; Received: from nebula.arm.com (217.140.96.140) by VE1EUR03FT044.mail.protection.outlook.com (10.152.19.106) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA_P384) id 15.20.13.11 via Frontend Transport; Tue, 12 Sep 2017 15:00:05 +0000 Received: from e107456-lin.cambridge.arm.com (10.1.2.79) by mail.arm.com (10.1.106.66) with Microsoft SMTP Server id 14.3.294.0; Tue, 12 Sep 2017 15:59:53 +0100 From: James Greenhalgh To: CC: , , Subject: [Patch AArch64 2/2] Fix memory sizes to load/store patterns Date: Tue, 12 Sep 2017 15:59:46 +0100 Message-ID: <1505228386-33632-1-git-send-email-james.greenhalgh@arm.com> In-Reply-To: <20170727180954.GB8643@arm.com> References: <20170727180954.GB8643@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:217.140.96.140; IPV:CAL; SCL:-1; CTRY:GB; EFV:NLI; SFV:NSPM; SFS:(10009020)(6009001)(39860400002)(2980300002)(438002)(189002)(24454002)(377424004)(199003)(2476003)(36756003)(512874002)(305945005)(4610100001)(50986999)(86362001)(8676002)(568964002)(26826003)(76176999)(478600001)(5660300001)(104016004)(246002)(8936002)(72206003)(356003)(5890100001)(50226002)(189998001)(33646002)(106466001)(54906002)(6666003)(2906002)(4326008)(110136004)(84326002)(6916009)(2950100002)(316002)(2351001)(77096006); DIR:OUT; SFP:1101; SCL:1; SRVR:AM4PR0801MB1523; H:nebula.arm.com; FPR:; SPF:Pass; PTR:fw-tnat.cambridge.arm.com; MX:1; A:1; LANG:en; X-Microsoft-Exchange-Diagnostics: 1; VE1EUR03FT044; 1:EUfKy/JulB8HJ8ot9ssmoz+qarBr9cevBRHUh2uYGTvH0xrfFKl0tR+oATAD5eu/Td45V50SAXbawhhYDGUlkZTJX2Fh7YrUudK7KzYRd8k9GkS9t9osK0Npb8UuqMd4 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 9b6c95ce-1e03-4fb6-ae76-08d4f9eef3f1 X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(300000500095)(300135000095)(300000501095)(300135300095)(22001)(300000502095)(300135100095)(2017030254152)(8251501002)(300000503095)(300135400095)(2017052603199)(49563074)(201703131423075)(201703031133081)(201702281549075)(300000504095)(300135200095)(300000505095)(300135600095)(300000506095)(300135500095); SRVR:AM4PR0801MB1523; X-Microsoft-Exchange-Diagnostics: 1; AM4PR0801MB1523; 3:qOVtx6uKrynaXSLYCJdYYVfKJzfmv/lj4u9rIisUmSy+WxMb8vGFj95jEjkBqr+L2SK4FtQXo+hHSmqROHFBlqRBSBSguSCdl2X4RC9MIyzUo2UHUQ9dqXcZlR0rhnTZUypkMIkfw5hQ2Aj0QUH28dB7moDir595L6u4e4/LraEiPgUU62DlHtFEaxClS4ncl/LKwVysYBtYwDgFd1P1/44uTX5jx9yzVFjks62Bz49i4Hx1qSVI4x5TeL1VhdEzEM21Riy492NWA+9b7EndTdSSg756+7mRCuO05/0rA5NVR34JjMXuBzOBkmktehWhMyoTj77D+QVetRMNpFqUen9cRieJHWYX5xKkwMCwVyg=; 25:UYBoHP9V9j/kmwc8o53kToxKrVYQlCdV7Kv1F1ZIkV/MW9RzYMxlek/1Mm010dIqYPUsLMmmspj/sd3GP7O/waJcAF8hNlwKWlpaT0Uu6LbAhNRP2ZmDSHIkODOQE3SJ5EIRcEQoOrMJCXg6BwkuNP6V9c21/oxX+8ieoT8Mas4qEQPBprZsyaGy4EEJ3p8itQv64fe/dzl24O7OFd2MIHcpTyoAFrdq0PY2JHFRL4XonXJhHBqh2MGcX5KtK23Wj+mgvptsAfTFdparzf6gfEt9zxZjPYIp1WyigRS2EHPgh1JcJI1Aqs2le6RmL0YhzDkTppe3d5S03CPriuB+tw== X-MS-TrafficTypeDiagnostic: AM4PR0801MB1523: X-Microsoft-Exchange-Diagnostics: 1; AM4PR0801MB1523; 31:qkk31ls7J+4p1Nz+pcOUg9rddDomnDMxnOPCRaCjF2m6MBCxnrjgYZZW8BdNmncaUolT0GqOAeQM7gZZYBfuJ3MOAvDr48y9oPHqTm+xQaLM/Q1mazaWr3FBhTKHznBjKwEDhWHDuoewiCfajq9h3PLX58EYDvaaZWEZlzxgo+XopFfdPnpPYxZ/+UhgdRSN/d0/6IbXRnZV4TmsPPM6e05n7tDiNVGKN/fVGGDLG1M=; 20:RV+4G/hBl9LDCOKW3RjDsPVdqC1N0+z8NkUu0Igqj/FhJ9YgvGFRLAHWEYmkaQlH67+0Jza3uSVjH8Pngyf0uioaen+i+ZyEEooba/NOjFUuhKdi0yZJFvpu9KcP2J7EVfRMfAqDwbyzXKZ6T4s7Ol49trTxO4cxEvM+c64bF1XR0RGaU+nujW1c28szy5pJjdpEMIJi/rYqNV5KFh5cdNb0/xGZSLmVRzmyVs4pRvLI9lZT4NisSU5Q9k2n4jRg; 4:/y0eHD6kG7PmTHdnQ2YUZCf3f07sCbBlHuYJCxouw+9KQbQEwBPth22kqr29zx7sblLoLtG0yNFzcBmrmZ0W6hQsgpl6Hrdo1AYvlPie1rWNz1V+r822E1VHsTAN/VTEYC6KopCpr5YP+Mv5SCHidn5eYQs+4rhmHnw25ahegYgzKjxWItAk2kpNTcWthbwBOe6qrjlBZw0QjhCwO+xsHtLflr8UvnQR+rPk7oGrG1ljgcME4ZiAfvMW/rr+oV6nQPxMWvzQBQ9JfymkceyfTPuyAE5rCO15kGBoMxd+2QI= NoDisclaimer: True X-Exchange-Antispam-Report-Test: UriScan:(180628864354917); X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(100000700101)(100105000095)(100000701101)(100105300095)(100000702101)(100105100095)(102415395)(6040450)(2401047)(8121501046)(5005006)(93006095)(93004095)(3002001)(100000703101)(100105400095)(10201501046)(6055026)(6041248)(201703131423075)(201702281528075)(201703061421075)(201703061406153)(20161123562025)(20161123558100)(20161123555025)(20161123560025)(20161123564025)(6072148)(201708071742011)(100000704101)(100105200095)(100000705101)(100105500095); SRVR:AM4PR0801MB1523; BCL:0; PCL:0; RULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(100000804101)(100110200095)(100000805101)(100110500095); SRVR:AM4PR0801MB1523; X-Forefront-PRVS: 042857DBB5 X-Microsoft-Exchange-Diagnostics: 1; AM4PR0801MB1523; 23:X1ZBIHypybqCvQSmwqf5VjGBDNOPaofKQTaxiJ5zMAtjnhvX7GZbU2LDDZrFUtok9vBp14z3HteIF0/2ChcvPX5JBM1OxMrqXVSTFS3Mr80+zmv190hY0eKf2nrjCvgUUNVKV1y9omlCkIWebTnDxK5KXAtLobPJ9OjiddXC67kYZjLS73yOcj8dUIKxI4iarn3sRBdpXm379wMxaFi1MDnCXAXKNeYx1CCLN/k7aBZmQmb5Zeh1czHkcO5116CBQqoqYz7QZ1OsBaWbTIia0hnA8AvQITr+pe0EeaqszabQA26dNIPRwrR2M3Nl9TYa4TzmOYe68mkvVbtktbST6WEIrsICIWQ2mMK09AqhT2+ydMHa1A0G3Kv0uP599pWIpKxhwo5jFpOQiVuT0KR1dMTpSK4HGmG2CFApKM91y7zSXZ5IIjfRjlW0dpOuA8OY5tr26QNJ9AoyLcF+zwZI+laJU0Ym2jknDm54E64spEb68KvyhkOVLE0eysxVkR0GrXI+Prba/fr6R0nVqM8L1JdG5YXF9haNXDqDTVGCIs29p1qWvbrAsvqugS8n9Aiv1QM8XA83PTNV+J8KNUKwm2uh+f2idqaF9ZRspfFWPojoFuTSYYO9SzRIgt0oMsNqcA6+k3u4sG0EFd0tmOBYlGcwB9YBO8vOtywYSXIa0M+S8SwWz9gUWcdzxJk4wGkIOugm86kzElywPaJlorqZ+cHEd8EocKOYBpiDMoLIkRD2kykqk1hnVgbYV8NLy6FLSEtNLZ70I78+iAR0bfmI+f063vnyn3h64it5Zyi9TISnf7qe4vNw5i2qsr7vh6DZyOFQK/fuFJ+gpxlAbqJvwDkQFYmYvhX2H1nQx6mBZ4g69CLVSCSXLVbvOGEGejugDzBUxypdm8Bs9XYk3UoE23iv+uUEKwnw5+M1Bp2JPZdVuLsNsLageHNASeJ1EWYtOIX4yWL3iIgv32vvSZyMSZR4XvfWaybwstMVRmsqPSx0Zjl+otGvAG1gO0FmhxTH9EKc2lcdUJ108BrNc7TQgw== X-Microsoft-Exchange-Diagnostics: 1; AM4PR0801MB1523; 6:g6dOF7q9bxyg1G3dfSj4UqIsDqB2QPYOUnb27a8Ob/SIr2p7EshukYizkF5XDlaXrBuj1znl1De2lKKk8AeWiFkX3vNhnImZvSi6Qa9VGpSG5Wz+cxDI1kKs13teQXLVVKi5PETuONWMFQyGI7V9O4bTmbrg8rbQpbjFXPuzARINfm9MQiwHgfrwfcKt9/witCZcIh1xBjgv/HQWEe8p94AJOFKsD9E9jCnL5evw/Ye+94Eaa62bmxZ395yVk6u+O2spvyyKPYSOTGo2bU85VlypWDPjHhRmHUiIT51Xu2pNjba+fcLmJmgxLAhaX/4rRhJKMCFJOnFo64EWO4lIfw==; 5:uXIRFayazUIBewIJ9xBQPLgY9KfcVFfXU1/l/ncT+nuH8GR3MmJdTPUwGgVprq8uTp5vBGlUdIfVUQE9mIVvyjUQt5HB8hl8gSOm7L3iZEGitARfyOUokz8KUxZuUJZBHfHkMOsYLL6wr5WY+ipllA==; 24:d3856iRnEnHwRBRQxX9msYg0irVKi4gS93Hwc/lfV30K3IAHl5t0iNY/Nl05yxnyXNH7X/Qlaqp515Slb2E9iDzOUJfENkG+LHp+2TsaVSw=; 7:w1uccMeI3+NAK/ixRf55pq0/FVwpaARzG037C8qSL2HJ7esFWNfwGTXS3DOG3X/o8BfMCjPBkGEW1RzSkALR3Jms+EZWT+q86f9AfB6E2RqIcvt8r76IlwI8XrB9lNzmyk4eKxix6XJx1GMbYmDpNgjs0ieQeEgteE2wtc38hltYUQ5nLhkDrgSMFwQf2yTO2UVMMeqXZoppUYXE4G2OzKYCueKhrhEkwzFagzAoIWo= SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Sep 2017 15:00:05.3504 (UTC) X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[217.140.96.140]; Helo=[nebula.arm.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM4PR0801MB1523 X-IsSubscribed: yes On Mon, Jun 12, 2017 at 02:54:00PM +0100, James Greenhalgh wrote: > > Hi, > > There seems to be a partial misconception in the AArch64 backend that > load1/load2 referred to the number of registers to load, rather than the > number of words to load. This patch fixes that using the new "number of > byte" types added in the previous patch. > > That means using the load_16 and store_16 types that were defined in the > previous patch for the first time in the AArch64 backend. To ensure > continuity for scheduling models, I've just split this out from load_8. > Please update your models if this is very wrong! I've updated this patch on trunk, rechecked it, and committed this patch as r252026. Thanks, James --- 2017-09-12 James Greenhalgh * config/aarch64/aarch64.md (movdi_aarch64): Set load/store types correctly. (movti_aarch64): Likewise. (movdf_aarch64): Likewise. (movtf_aarch64): Likewise. (load_pairdi): Likewise. (store_pairdi): Likewise. (load_pairdf): Likewise. (store_pairdf): Likewise. (loadwb_pair_): Likewise. (storewb_pair_): Likewise. (ldr_got_small_): Likewise. (ldr_got_small_28k_): Likewise. (ldr_got_tiny): Likewise. * config/aarch64/iterators.md (ldst_sz): New. (ldpstp_sz): Likewise. * config/aarch64/thunderx.md (thunderx_storepair): Split store_8 to store_16. (thunderx_load): Split load_8 to load_16. * config/aarch64/thunderx2t99.md (thunderx2t99_loadpair): Split load_8 to load_16. (thunderx2t99_storepair_basic): Split store_8 to store_16. * config/arm/xgene1.md (xgene1_load_pair): Split load_8 to load_16. (xgene1_store_pair): Split store_8 to store_16. * config/aarch64/falkor.md (falkor_ld_3_ld): Split load_8 to load_16. (falkor_st_0_st_sd): Split store_8 to store_16. diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 7cbb458..e85376c 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -994,8 +994,8 @@ aarch64_expand_mov_immediate (operands[0], operands[1]); DONE; }" - [(set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,mov_imm,mov_imm,load_4,\ - load_4,store_4,store_4,adr,adr,f_mcr,f_mrc,fmov,neon_move") + [(set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,mov_imm,mov_imm,load_8,\ + load_8,store_8,store_8,adr,adr,f_mcr,f_mrc,fmov,neon_move") (set_attr "fp" "*,*,*,*,*,*,*,yes,*,yes,*,*,yes,yes,yes,*") (set_attr "simd" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,yes")] ) @@ -1039,7 +1039,8 @@ ldr\\t%q0, %1 str\\t%q1, %0" [(set_attr "type" "multiple,f_mcr,f_mrc,neon_logic_q, \ - load_8,store_8,store_8,f_loadd,f_stored") + load_16,store_16,store_16,\ + load_16,store_16") (set_attr "length" "8,8,8,4,4,4,4,4,4") (set_attr "simd" "*,*,*,yes,*,*,*,*,*") (set_attr "fp" "*,*,*,*,*,*,*,yes,yes")] @@ -1142,7 +1143,7 @@ mov\\t%x0, %x1 mov\\t%x0, %1" [(set_attr "type" "neon_move,f_mcr,f_mrc,fmov,fconstd,neon_move,\ - f_loadd,f_stored,load_4,store_4,mov_reg,\ + f_loadd,f_stored,load_8,store_8,mov_reg,\ fconstd") (set_attr "simd" "yes,*,*,*,*,yes,*,*,*,*,*,*")] ) @@ -1187,7 +1188,7 @@ stp\\t%1, %H1, %0 stp\\txzr, xzr, %0" [(set_attr "type" "logic_reg,multiple,f_mcr,f_mrc,neon_move_q,f_mcr,\ - f_loadd,f_stored,load_8,store_8,store_8") + f_loadd,f_stored,load_16,store_16,store_16") (set_attr "length" "4,8,8,8,4,4,4,4,4,4,4") (set_attr "simd" "yes,*,*,*,yes,*,*,*,*,*,*")] ) @@ -1251,7 +1252,7 @@ "@ ldp\\t%x0, %x2, %1 ldp\\t%d0, %d2, %1" - [(set_attr "type" "load_8,neon_load1_2reg") + [(set_attr "type" "load_16,neon_load1_2reg") (set_attr "fp" "*,yes")] ) @@ -1286,7 +1287,7 @@ "@ stp\\t%x1, %x3, %0 stp\\t%d1, %d3, %0" - [(set_attr "type" "store_8,neon_store1_2reg") + [(set_attr "type" "store_16,neon_store1_2reg") (set_attr "fp" "*,yes")] ) @@ -1320,7 +1321,7 @@ "@ ldp\\t%d0, %d2, %1 ldp\\t%x0, %x2, %1" - [(set_attr "type" "neon_load1_2reg,load_8") + [(set_attr "type" "neon_load1_2reg,load_16") (set_attr "fp" "yes,*")] ) @@ -1354,7 +1355,7 @@ "@ stp\\t%d1, %d3, %0 stp\\t%x1, %x3, %0" - [(set_attr "type" "neon_store1_2reg,store_8") + [(set_attr "type" "neon_store1_2reg,store_16") (set_attr "fp" "yes,*")] ) @@ -1372,7 +1373,7 @@ (match_operand:P 5 "const_int_operand" "n"))))])] "INTVAL (operands[5]) == GET_MODE_SIZE (mode)" "ldp\\t%2, %3, [%1], %4" - [(set_attr "type" "load_8")] + [(set_attr "type" "load_")] ) (define_insn "loadwb_pair_" @@ -1405,7 +1406,7 @@ (match_operand:GPI 3 "register_operand" "r"))])] "INTVAL (operands[5]) == INTVAL (operands[4]) + GET_MODE_SIZE (mode)" "stp\\t%2, %3, [%0, %4]!" - [(set_attr "type" "store_8")] + [(set_attr "type" "store_")] ) (define_insn "storewb_pair_" @@ -5355,7 +5356,7 @@ UNSPEC_GOTSMALLPIC))] "" "ldr\\t%0, [%1, #:got_lo12:%a2]" - [(set_attr "type" "load_4")] + [(set_attr "type" "load_")] ) (define_insn "ldr_got_small_sidi" @@ -5378,7 +5379,7 @@ UNSPEC_GOTSMALLPIC28K))] "" "ldr\\t%0, [%1, #::%a2]" - [(set_attr "type" "load_4")] + [(set_attr "type" "load_")] ) (define_insn "ldr_got_small_28k_sidi" @@ -5399,7 +5400,7 @@ UNSPEC_GOTTINYPIC))] "" "ldr\\t%0, %L1" - [(set_attr "type" "load_4")] + [(set_attr "type" "load_8")] ) (define_insn "aarch64_load_tp_hard" diff --git a/gcc/config/aarch64/falkor.md b/gcc/config/aarch64/falkor.md index 66efc8c..83971ce 100644 --- a/gcc/config/aarch64/falkor.md +++ b/gcc/config/aarch64/falkor.md @@ -581,7 +581,7 @@ (define_insn_reservation "falkor_ld_3_ld" 3 (and (eq_attr "tune" "falkor") - (eq_attr "type" "load_4,load_8")) + (eq_attr "type" "load_4,load_8,load_16")) "falkor_ld") ;; Miscellaneous Data-Processing Instructions @@ -663,7 +663,7 @@ (define_insn_reservation "falkor_st_0_st_sd" 0 (and (eq_attr "tune" "falkor") - (eq_attr "type" "store_4,store_8")) + (eq_attr "type" "store_4,store_8,store_16")) "falkor_st+falkor_sd") ;; Muliply bypasses. diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 3e38767..477dc35 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -387,6 +387,11 @@ ;; 32-bit version and "%x0" in the 64-bit version. (define_mode_attr w [(QI "w") (HI "w") (SI "w") (DI "x") (SF "s") (DF "d")]) +;; The size of access, in bytes. +(define_mode_attr ldst_sz [(SI "4") (DI "8")]) +;; Likewise for load/store pair. +(define_mode_attr ldpstp_sz [(SI "8") (DI "16")]) + ;; For inequal width int to float conversion (define_mode_attr w1 [(HF "w") (SF "w") (DF "x")]) (define_mode_attr w2 [(HF "x") (SF "x") (DF "w")]) diff --git a/gcc/config/aarch64/thunderx.md b/gcc/config/aarch64/thunderx.md index c18da2f..84ac6cd 100644 --- a/gcc/config/aarch64/thunderx.md +++ b/gcc/config/aarch64/thunderx.md @@ -100,7 +100,7 @@ ;; Store pair are single issued (define_insn_reservation "thunderx_storepair" 1 (and (eq_attr "tune" "thunderx") - (eq_attr "type" "store_8")) + (eq_attr "type" "store_8,store_16")) "thunderx_pipe0 + thunderx_pipe1") ;; Prefetch are single issued @@ -112,7 +112,7 @@ ;; loads (and load pairs) from L1 take 3 cycles in pipe 0 (define_insn_reservation "thunderx_load" 3 (and (eq_attr "tune" "thunderx") - (eq_attr "type" "load_4, load_8")) + (eq_attr "type" "load_4, load_8, load_16")) "thunderx_pipe0") (define_insn_reservation "thunderx_brj" 1 diff --git a/gcc/config/aarch64/thunderx2t99.md b/gcc/config/aarch64/thunderx2t99.md index 41a45ca..5bcf4ff 100644 --- a/gcc/config/aarch64/thunderx2t99.md +++ b/gcc/config/aarch64/thunderx2t99.md @@ -128,7 +128,7 @@ (define_insn_reservation "thunderx2t99_loadpair" 5 (and (eq_attr "tune" "thunderx2t99") - (eq_attr "type" "load_8")) + (eq_attr "type" "load_8,load_16")) "thunderx2t99_i012,thunderx2t99_ls01") (define_insn_reservation "thunderx2t99_store_basic" 1 @@ -138,7 +138,7 @@ (define_insn_reservation "thunderx2t99_storepair_basic" 1 (and (eq_attr "tune" "thunderx2t99") - (eq_attr "type" "store_8")) + (eq_attr "type" "store_8,store_16")) "thunderx2t99_ls01,thunderx2t99_sd") ;; FP data processing instructions. diff --git a/gcc/config/arm/xgene1.md b/gcc/config/arm/xgene1.md index d0b17ab..c4b3773 100644 --- a/gcc/config/arm/xgene1.md +++ b/gcc/config/arm/xgene1.md @@ -92,12 +92,12 @@ (define_insn_reservation "xgene1_load_pair" 6 (and (eq_attr "tune" "xgene1") - (eq_attr "type" "load_8")) + (eq_attr "type" "load_8, load_16")) "xgene1_decodeIsolated") (define_insn_reservation "xgene1_store_pair" 2 (and (eq_attr "tune" "xgene1") - (eq_attr "type" "store_8")) + (eq_attr "type" "store_8, store_16")) "xgene1_decodeIsolated") (define_insn_reservation "xgene1_fp_load1" 10