From patchwork Fri Sep 15 12:43:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 112731 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp572943qgf; Fri, 15 Sep 2017 05:44:27 -0700 (PDT) X-Google-Smtp-Source: ADKCNb5jmd8FTlptpQaoCxlCp9IuxLgnzjq9GxX+Gw3IYMtQq/yIYRA6MLqrdzP+JzQeYXUKw9+b X-Received: by 10.80.165.23 with SMTP id y23mr13260976edb.155.1505479467873; Fri, 15 Sep 2017 05:44:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505479467; cv=none; d=google.com; s=arc-20160816; b=YESyQDmM/lQqYOHCbLdIJswRQ7cT5PwXJnjmylygTqnPJIdkkQj8HMWe17vw6RmH4/ 7JnlWEOWSsSqqbxSSbDL0gUf+vHNg1GcJ/4zLi9iJkvkQqshKGBaeBMy3lySqtDO6SId RlaMO36TNc0neEKNNxQBcOlApY4y2z9jdrNy+hQuqm1+F4OcUqcqKpHAUjatWCWh0a2B lkFP6yVaJR+Vk14fmfw9GbESY5SEZPdJgnfSZBFb+XWgELeC32HIf8lPPyNeWg3YJfmX pSSEB5f6hsMMvM+KV7N5zD5SWxCeVAQR5LTGPicDQBgVK2exFKfMLokizHOyu2qjkn0o K2gw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:message-id:date:to:from :dkim-signature:dkim-filter:arc-authentication-results; bh=VK92BPU0kO5zStQ9EBgUKtYme1oWb4v0K33WSY0HbFU=; b=fNRDDYPicM/o+CB4jp1FNEMKCqOv5lU91ZopbtHut4CFMQ1WCJwTBd2IX2/Hm12H1+ a5txjHN8X4vopBfPhPy4BtXUnNu7iSSGGgGQG0ZnbUGxkCAixm4bElppcqjKZU2x/Ps3 /dbYGu8zXCeqfggteYNyf0xJvOIbsPUvr1QJtKXSvg14goJn2hheHf9s+P8htFm50Tiz KiUMOWaNTyOKmzXWZKRcQRqInyULaALcwYdMC+CvwAKRW7OUbOXriF7igERBtHXFqGK5 Zp791vIqWQI2aw8FJuDlUv6R3xxr1W5mQxlZSG0azfsylflsoD7OUM6AA22/sz6eUzgS Efnw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=kTghOYMc; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id l63si1191850edl.104.2017.09.15.05.44.27; Fri, 15 Sep 2017 05:44:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=kTghOYMc; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id 5B41EC2200C; Fri, 15 Sep 2017 12:44:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id BB94AC21F73; Fri, 15 Sep 2017 12:44:17 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 8D36EC21FFB; Fri, 15 Sep 2017 12:44:04 +0000 (UTC) Received: from conuserg-11.nifty.com (conuserg-11.nifty.com [210.131.2.78]) by lists.denx.de (Postfix) with ESMTPS id CF907C22009 for ; Fri, 15 Sep 2017 12:43:59 +0000 (UTC) Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-11.nifty.com with ESMTP id v8FChYNu026429; Fri, 15 Sep 2017 21:43:35 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-11.nifty.com v8FChYNu026429 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1505479415; bh=yL45//VAwEq+A1bFOPG3gm96hfy8gxJagfgapCNmx9U=; h=From:To:Cc:Subject:Date:From; b=kTghOYMcUvv5/mFFbVYOth9XVowNb5vaXNc8l91sZMh8V7GJg6ObOC7MzD3bTjiEG rGWWRJIOO4Z9ekr0LHtOl8ut2W5L57tD8frYX2z/g/5USKZzvg6XhBDETgwEJ0THi1 lwxcKK2BXIOsGLMl5Nm54gV+VVPd7NcJzxfpq3WHywrvYVDygNJRCNAr85lbnJJopA cr+MUEpVebfvId93deShhr4RnqoL8LBSbZerOSJB35M0rbMbrfOB1KGqtb5J7nR1fA 7YKiv7x1Tyc7RbBbowSWc0X+kMU8HBEjIr8nXBPCJu2lEH3HwFrEC72flk41UC6eI+ qRTQhAxR78lSw== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Fri, 15 Sep 2017 21:43:19 +0900 Message-Id: <1505479402-17945-1-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 Cc: Scott Wood , Scott Wood Subject: [U-Boot] [PATCH 1/4] mtd: nand: denali: allow to override corrupted revision register X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The Denali IP does not update the revision register properly. Allow to override it with SoC data associated with compatible. Linux had already finished big surgery of this driver, but I need to prepare the NAND core before the full sync of the driver. For now, I am fixing the most fatal problem on UniPhier platform. Signed-off-by: Masahiro Yamada --- drivers/mtd/nand/denali.c | 27 +++++++++++++++------------ drivers/mtd/nand/denali.h | 7 +++++-- drivers/mtd/nand/denali_dt.c | 30 ++++++++++++++++++++++++++++++ 3 files changed, 50 insertions(+), 14 deletions(-) diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index 47cf37d..54718f4 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -10,7 +10,7 @@ #include #include #include -#include +#include #include "denali.h" @@ -433,17 +433,13 @@ static void find_valid_banks(struct denali_nand_info *denali) */ static void detect_max_banks(struct denali_nand_info *denali) { - uint32_t features = readl(denali->flash_reg + FEATURES); - /* - * Read the revision register, so we can calculate the max_banks - * properly: the encoding changed from rev 5.0 to 5.1 - */ - u32 revision = MAKE_COMPARABLE_REVISION( - readl(denali->flash_reg + REVISION)); - if (revision < REVISION_5_1) - denali->max_banks = 2 << (features & FEATURES__N_BANKS); - else - denali->max_banks = 1 << (features & FEATURES__N_BANKS); + uint32_t features = ioread32(denali->flash_reg + FEATURES); + + denali->max_banks = 1 << (features & FEATURES__N_BANKS); + + /* the encoding changed from rev 5.0 to 5.1 */ + if (denali->revision < 0x0501) + denali->max_banks <<= 1; } static void detect_partition_feature(struct denali_nand_info *denali) @@ -1154,6 +1150,13 @@ static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col, static void denali_hw_init(struct denali_nand_info *denali) { /* + * The REVISION register may not be reliable. Platforms are allowed to + * override it. + */ + if (!denali->revision) + denali->revision = swab16(ioread32(denali->flash_reg + REVISION)); + + /* * tell driver how many bit controller will skip before writing * ECC code in OOB. This is normally used for bad block marker */ diff --git a/drivers/mtd/nand/denali.h b/drivers/mtd/nand/denali.h index 694bce5..08db488 100644 --- a/drivers/mtd/nand/denali.h +++ b/drivers/mtd/nand/denali.h @@ -166,8 +166,6 @@ #define REVISION 0x370 #define REVISION__VALUE 0xffff -#define MAKE_COMPARABLE_REVISION(x) swab16((x) & REVISION__VALUE) -#define REVISION_5_1 0x00000501 #define ONFI_DEVICE_FEATURES 0x380 #define ONFI_DEVICE_FEATURES__VALUE 0x003f @@ -462,8 +460,13 @@ struct denali_nand_info { uint32_t blksperchip; uint32_t bbtskipbytes; uint32_t max_banks; + unsigned int revision; + unsigned int caps; }; +#define DENALI_CAP_HW_ECC_FIXUP BIT(0) +#define DENALI_CAP_DMA_64BIT BIT(1) + int denali_init(struct denali_nand_info *denali); #endif /* __DENALI_H__ */ diff --git a/drivers/mtd/nand/denali_dt.c b/drivers/mtd/nand/denali_dt.c index 0a6155c..4afd679 100644 --- a/drivers/mtd/nand/denali_dt.c +++ b/drivers/mtd/nand/denali_dt.c @@ -12,15 +12,38 @@ #include "denali.h" +struct denali_dt_data { + unsigned int revision; + unsigned int caps; +}; + +static const struct denali_dt_data denali_socfpga_data = { + .caps = DENALI_CAP_HW_ECC_FIXUP, +}; + +static const struct denali_dt_data denali_uniphier_v5a_data = { + .caps = DENALI_CAP_HW_ECC_FIXUP | + DENALI_CAP_DMA_64BIT, +}; + +static const struct denali_dt_data denali_uniphier_v5b_data = { + .revision = 0x0501, + .caps = DENALI_CAP_HW_ECC_FIXUP | + DENALI_CAP_DMA_64BIT, +}; + static const struct udevice_id denali_nand_dt_ids[] = { { .compatible = "altr,socfpga-denali-nand", + .data = (unsigned long)&denali_socfpga_data, }, { .compatible = "socionext,uniphier-denali-nand-v5a", + .data = (unsigned long)&denali_uniphier_v5a_data, }, { .compatible = "socionext,uniphier-denali-nand-v5b", + .data = (unsigned long)&denali_uniphier_v5b_data, }, { /* sentinel */ } }; @@ -28,9 +51,16 @@ static const struct udevice_id denali_nand_dt_ids[] = { static int denali_dt_probe(struct udevice *dev) { struct denali_nand_info *denali = dev_get_priv(dev); + const struct denali_dt_data *data; struct resource res; int ret; + data = (void *)dev_get_driver_data(dev); + if (data) { + denali->revision = data->revision; + denali->caps = data->caps; + } + ret = dev_read_resource_byname(dev, "denali_reg", &res); if (ret) return ret; From patchwork Fri Sep 15 12:43:20 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 112730 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp572493qgf; Fri, 15 Sep 2017 05:43:55 -0700 (PDT) X-Google-Smtp-Source: ADKCNb4gUaBxeZ0XVDHZisuA9cxhd8UV6Oe5/0OPTi60u/Ema1ITIuYZHlK+dzcX5XnGGSrUKZTT X-Received: by 10.80.176.38 with SMTP id i35mr20706012edd.100.1505479435693; Fri, 15 Sep 2017 05:43:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505479435; cv=none; d=google.com; s=arc-20160816; b=cs/cyRh4fyxQ0i6eL6dwy/6XhviZlSNcRgx1cZ6fX2uQRWxSI4QwrH1dJayuySM8U4 Yutd23N+fFfdjontKz1bN6JJbi2du4eWAXLlyIuctyLzI3uylvu78HQFjVwkBVWS12bX LlF2rEYyO0jg1mS9VKzPDYAtfFRyJ93zkWHB0qt9kGBw8j7ISX9EpSmbq3uzONmpHIwX JSizApNqD3XpAlf7cnIVYxGeOfOW/BCu5kGHfXh5l6svANApvMI6FElxPfmbRLaqzSBm rXkimX12NlUy/QEX0PIrXYhE0ztKXt7S32my6uJh2i9+p3s04Lg9l8fcXl7SJxnhRYc/ iKoQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:dkim-filter:arc-authentication-results; bh=gAXDJEioWCEJvh+zskd4uIa4KIqfrbADh0UVDUKJv5Q=; b=XUofZCBpRVPndvObHBvKXCG3v2ru7kngvzZmdu9VQEiU5YBvsV2nIqT9sswYUa+cdo M4rc9Xe4gUjRoGrOl/wWZPgG43QMKblw5sdhPsGxifkdFn4+h+juyrMgCQLhgNkfzbYO N1or+B7z67Fju+qVkIGRDzxVGEpiY1g9Bs3TSBK8a3eDAgc6mUHAretySQ1nNOauqSwK REV08unZAKNyK2jf3+grj4FL2/eaPp9FiGrXqr459KDigRjcaOdsDkEubvBg4rp66gz+ S9gq9QadXB62MxsKShE4LjWj8F1CTzaErCgytslugBS6oe0UMcPs5doS+KxFKb8u9pnP dCQQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=vk2sHfcE; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id 2si1174455edy.182.2017.09.15.05.43.55; Fri, 15 Sep 2017 05:43:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=vk2sHfcE; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id 02650C22011; Fri, 15 Sep 2017 12:43:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 139B2C21DF7; Fri, 15 Sep 2017 12:43:51 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id A7591C21DF7; Fri, 15 Sep 2017 12:43:49 +0000 (UTC) Received: from conuserg-11.nifty.com (conuserg-11.nifty.com [210.131.2.78]) by lists.denx.de (Postfix) with ESMTPS id 80C3CC21DC0 for ; Fri, 15 Sep 2017 12:43:48 +0000 (UTC) Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-11.nifty.com with ESMTP id v8FChYNv026429; Fri, 15 Sep 2017 21:43:40 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-11.nifty.com v8FChYNv026429 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1505479420; bh=1Z8Uqlk88rfS7gZZvqiXrqPywQpuF2PgRk83uXIiPVI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=vk2sHfcEDxvuihWbhJuECnfrQhJbA23nTMlVe3UssWFImY8lsdAa0oKKhbjoD3Tcv 0pfJY1s/uQurdzSWEU9vHj+uMeu4ptJ1imLiI90cgslwUxIcVSFf7xbB3kf3poDMFx NJakafmQiXHCK8ipq/tC9dSm1qxkqK4iOKaBg2bmPGpbV8tsXVewu1oBVj8OSXPpft vxOPTRWipL/yo+OB/7T4bcNPiNAzKxzcDELZQB8iCtkoyW8VXYz/jb+8I+m+yJ0uwO oezAGbhFyRc1rYOcP1IBKt6FASVYHEsbiZxNgN4X2d6sI4vLVKXGLvUw1H1hP3zFDb EWCwe8iolknJA== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Fri, 15 Sep 2017 21:43:20 +0900 Message-Id: <1505479402-17945-2-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505479402-17945-1-git-send-email-yamada.masahiro@socionext.com> References: <1505479402-17945-1-git-send-email-yamada.masahiro@socionext.com> Subject: [U-Boot] [PATCH 2/4] ARM: uniphier: merge two defconfig files into uniphier_v7_defconfig X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The main difference between Pro4 and PXs2/LD6b is the Denali NAND IP version. This is now distinguished by DT. Merge the two defconfig files into uniphier_v7_defconfig. Update the README.uniphier too. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/Kconfig | 21 +++++----- configs/uniphier_pro4_defconfig | 49 ---------------------- ...r_pxs2_ld6b_defconfig => uniphier_v7_defconfig} | 4 +- doc/README.uniphier | 33 ++++++++------- 4 files changed, 31 insertions(+), 76 deletions(-) delete mode 100644 configs/uniphier_pro4_defconfig rename configs/{uniphier_pxs2_ld6b_defconfig => uniphier_v7_defconfig} (93%) diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig index ee22112..c8b5ab4 100644 --- a/arch/arm/mach-uniphier/Kconfig +++ b/arch/arm/mach-uniphier/Kconfig @@ -12,18 +12,14 @@ config ARCH_UNIPHIER_32BIT choice prompt "UniPhier SoC select" - default ARCH_UNIPHIER_PRO4 + default ARCH_UNIPHIER_V8_MULTI config ARCH_UNIPHIER_LD4_SLD8 bool "UniPhier LD4/sLD8 SoCs" select ARCH_UNIPHIER_32BIT -config ARCH_UNIPHIER_PRO4 - bool "UniPhier Pro4 SoC" - select ARCH_UNIPHIER_32BIT - -config ARCH_UNIPHIER_PRO5_PXS2_LD6B - bool "UniPhier Pro5/PXs2/LD6b SoCs" +config ARCH_UNIPHIER_V7_MULTI + bool "UniPhier Pro4/Pro5/PXs2/LD6b SoCs" select ARCH_UNIPHIER_32BIT config ARCH_UNIPHIER_V8_MULTI @@ -44,19 +40,24 @@ config ARCH_UNIPHIER_SLD8 depends on ARCH_UNIPHIER_LD4_SLD8 default y +config ARCH_UNIPHIER_PRO4 + bool "Enable UniPhier Pro4 SoC support" + depends on ARCH_UNIPHIER_V7_MULTI + default y + config ARCH_UNIPHIER_PRO5 bool "Enable UniPhier Pro5 SoC support" - depends on ARCH_UNIPHIER_PRO5_PXS2_LD6B + depends on ARCH_UNIPHIER_V7_MULTI default y config ARCH_UNIPHIER_PXS2 bool "Enable UniPhier Pxs2 SoC support" - depends on ARCH_UNIPHIER_PRO5_PXS2_LD6B + depends on ARCH_UNIPHIER_V7_MULTI default y config ARCH_UNIPHIER_LD6B bool "Enable UniPhier LD6b SoC support" - depends on ARCH_UNIPHIER_PRO5_PXS2_LD6B + depends on ARCH_UNIPHIER_V7_MULTI default y config ARCH_UNIPHIER_LD11 diff --git a/configs/uniphier_pro4_defconfig b/configs/uniphier_pro4_defconfig deleted file mode 100644 index 7348675..0000000 --- a/configs/uniphier_pro4_defconfig +++ /dev/null @@ -1,49 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_UNIPHIER=y -CONFIG_SYS_TEXT_BASE=0x84000000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_NAND_SUPPORT=y -CONFIG_MICRO_SUPPORT_CARD=y -CONFIG_DEFAULT_DEVICE_TREE="uniphier-pro4-ref" -# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set -CONFIG_SPL=y -CONFIG_SPL_NOR_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_CONFIG=y -CONFIG_CMD_BOOTZ=y -# CONFIG_CMD_XIMG is not set -# CONFIG_CMD_ENV_EXISTS is not set -# CONFIG_CMD_FPGA is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_TIME=y -# CONFIG_CMD_MISC is not set -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_EFI_PARTITION is not set -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_GPIO_UNIPHIER=y -CONFIG_MISC=y -CONFIG_I2C_EEPROM=y -CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 -CONFIG_MMC_UNIPHIER=y -CONFIG_NAND=y -CONFIG_NAND_DENALI=y -CONFIG_NAND_DENALI_DT=y -CONFIG_SYS_NAND_DENALI_64BIT=y -CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8 -CONFIG_SPL_NAND_DENALI=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_GENERIC=y -CONFIG_USB_STORAGE=y diff --git a/configs/uniphier_pxs2_ld6b_defconfig b/configs/uniphier_v7_defconfig similarity index 93% rename from configs/uniphier_pxs2_ld6b_defconfig rename to configs/uniphier_v7_defconfig index c242776..3c25484 100644 --- a/configs/uniphier_pxs2_ld6b_defconfig +++ b/configs/uniphier_v7_defconfig @@ -5,7 +5,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y -CONFIG_ARCH_UNIPHIER_PRO5_PXS2_LD6B=y +CONFIG_ARCH_UNIPHIER_V7_MULTI=y CONFIG_MICRO_SUPPORT_CARD=y CONFIG_DEFAULT_DEVICE_TREE="uniphier-pxs2-vodka" # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set @@ -45,4 +45,6 @@ CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8 CONFIG_SPL_NAND_DENALI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_STORAGE=y diff --git a/doc/README.uniphier b/doc/README.uniphier index fa1f9bc..e4fd9a3 100644 --- a/doc/README.uniphier +++ b/doc/README.uniphier @@ -27,17 +27,17 @@ The following tables show and for each board. 32bit SoC boards: - Board | | ----------------|------------------------------|------------------------------ -LD4 reference | uniphier_ld4_sld8_defconfig | uniphier-ld4-ref (default) -sld8 reference | uniphier_ld4_sld8_defconfig | uniphier-sld8-def -Pro4 reference | uniphier_pro4_defconfig | uniphier-pro4-ref (default) -Pro4 Ace | uniphier_pro4_defconfig | uniphier-pro4-ace -Pro4 Sanji | uniphier_pro4_defconfig | uniphier-pro4-sanji -Pro5 4KBOX | uniphier_pxs2_ld6b_defconfig | uniphier-pro5-4kbox -PXs2 Gentil | uniphier_pxs2_ld6b_defconfig | uniphier-pxs2-gentil -PXs2 Vodka | uniphier_pxs2_ld6b_defconfig | uniphier-pxs2-vodka (default) -LD6b reference | uniphier_pxs2_ld6b_defconfig | uniphier-ld6b-ref + Board | | +---------------|-----------------------------|------------------------------ +LD4 reference | uniphier_ld4_sld8_defconfig | uniphier-ld4-ref (default) +sld8 reference | uniphier_ld4_sld8_defconfig | uniphier-sld8-def +Pro4 reference | uniphier_v7_defconfig | uniphier-pro4-ref +Pro4 Ace | uniphier_v7_defconfig | uniphier-pro4-ace +Pro4 Sanji | uniphier_v7_defconfig | uniphier-pro4-sanji +Pro5 4KBOX | uniphier_v7_defconfig | uniphier-pro5-4kbox +PXs2 Gentil | uniphier_v7_defconfig | uniphier-pxs2-gentil +PXs2 Vodka | uniphier_v7_defconfig | uniphier-pxs2-vodka (default) +LD6b reference | uniphier_v7_defconfig | uniphier-ld6b-ref 64bit SoC boards: @@ -47,17 +47,18 @@ LD11 reference | uniphier_v8_defconfig | uniphier-ld11-ref LD11 Global | uniphier_v8_defconfig | uniphier-ld11-global LD20 reference | uniphier_v8_defconfig | uniphier-ld20-ref (default) LD20 Global | uniphier_v8_defconfig | uniphier-ld20-global +PXs3 reference | uniphier_v8_defconfig | uniphier-pxs3-ref For example, to compile the source for PXs2 Vodka board, run the following: - $ make uniphier_pxs2_ld6b_defconfig + $ make uniphier_v7_defconfig $ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-pxs2-vodka The device tree marked as (default) can be omitted. `uniphier-pxs2-vodka` is -the default device tree for the configuration `uniphier_pxs2_ld6b_defconfig`, -so the following gives the same result. +the default device tree for the configuration `uniphier_v7_defconfig`, so the +following gives the same result. - $ make uniphier_pxs2_ld6b_defconfig + $ make uniphier_v7_defconfig $ make CROSS_COMPILE=arm-linux-gnueabihf- @@ -178,4 +179,4 @@ newer SoCs. Even if it is, EA[25] is not connected on most of the boards. -- Masahiro Yamada -Jul. 2017 +Sep. 2017 From patchwork Fri Sep 15 12:43:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 112732 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp573819qgf; Fri, 15 Sep 2017 05:45:26 -0700 (PDT) X-Google-Smtp-Source: AOwi7QDy3Nf7wwR3wBz0Pja1E7qS3Wkq8lQAK3ZVGF5fsVRIWZQzErt+kwWfo3wKhV4sWAq9Fkd2 X-Received: by 10.80.181.59 with SMTP id y56mr11365114edd.140.1505479526197; Fri, 15 Sep 2017 05:45:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505479526; cv=none; d=google.com; s=arc-20160816; b=i1Wfx2R4Oa6EhTHqODzgy+OMZPJM7s3dQSf8PS6YF2cP95hEeLPMzjK1sDbI1iO+zG lk2mOgJQtohreWzb4kLhHoSe+rXXn7/yzWPenuTfcj37CwSiUn54u0R7G/HmnCnHApOu jKLa/nOla5icbp16zHCAbkC7Epllf88VTZel3/TYjIrHHp8VmJ/ljBB9oeq1243jFeA7 pWg3hAf8LFJq5qVMoGv14mnI3n1/IkBOmDQHhtpkkgcSli/5YlGtcyEz4VQoN6+5nT22 Swd3/UxrXEmbJTkxLythWwqBu4rSGbSDX75O3kiJiEKzZjR82pOOCgS5O7dlMnouG6H0 aA4g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:dkim-signature:dkim-filter:arc-authentication-results; bh=de1Im0KkUca9VHx350O2rHBimV/NXciRC4mTEFNuCcA=; b=QTNGKKJq3HvMkDEq0nvHSkeSx7WoGOrctyoYWZGuY/8CToKfFKKmOMKP6ok4nXO2K5 XMJXZhFCZ+c9VC11G5EtyTR00dyK2LLt8eCcJ3hIdkNHLk8Ih4cmgEi5+nkdudHDE+oS e2jSHT7nNW6GmGQH7Be5ld4fnp3AuvV9M/rIVfV4gyWlWgez10X5zBlJpB99YYiiTRxN 2Z5mYff9mZp4SgrawvRHqOM5oOink0q/b5zl9GXm+5ZYC0IOBH8nRyE9zhQZEWr4YssN rxTMBSEj+ZhWPJz25MZk+yBCzmA+xPkpN3e7TEfW5sFRLSRGKKg60MsOCzSTQVeA26JJ ovGg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=RGYwcSUk; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id 63si1115997edy.413.2017.09.15.05.45.25; Fri, 15 Sep 2017 05:45:26 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=RGYwcSUk; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id CB24BC21FC6; Fri, 15 Sep 2017 12:44:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id EBD6AC2200D; Fri, 15 Sep 2017 12:44:34 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 373B1C21FBC; Fri, 15 Sep 2017 12:44:18 +0000 (UTC) Received: from conuserg-11.nifty.com (conuserg-11.nifty.com [210.131.2.78]) by lists.denx.de (Postfix) with ESMTPS id 205E6C22010 for ; Fri, 15 Sep 2017 12:44:16 +0000 (UTC) Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-11.nifty.com with ESMTP id v8FChYNw026429; Fri, 15 Sep 2017 21:43:50 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-11.nifty.com v8FChYNw026429 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1505479430; bh=5ndXK3JmBYE08oP9HeehPkMB4lAlvDDMGLbm8ddZoMo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RGYwcSUk0ZI7jwLZN+Puo144dEH/F9ZyYB4mMoWnGjMbuEb+ny1LQ5NMcBrZif6+V be3il/PMzSF8hLNl3YhslzRP5myrFbMdAqXHQ3OcDHLSF/xioDcXifxs/Q2iHMHuP3 OsQJ8yHhAIBzi1KeS9nCZ+X4oNsy9BbKHWw5Qr5fGrSkv+JABYnFaZUqzMw0axEaOp I4gQ7OOomOVT7LQF2TjVuiVoBd5ZafClaxkQBiy5SYgM1psJ/DGa+CYg+gyg9VCeOf SGZuW+guPR8YlN5OKGEDEUpyMwz9vyPwRsjVw66Qcxu7MVSARfTMQT6V5kTCmpyVPt ROblZrOnDd1qA== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Fri, 15 Sep 2017 21:43:21 +0900 Message-Id: <1505479402-17945-3-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505479402-17945-1-git-send-email-yamada.masahiro@socionext.com> References: <1505479402-17945-1-git-send-email-yamada.masahiro@socionext.com> Cc: Marek Vasut Subject: [U-Boot] [PATCH 3/4] ARM: uniphier: remove bit field macros from sc64-regs.h X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Starting from PXs3, the bit fields of RSTCTRL, CLKCTRL registers will change every SoC. There is no more point to define bitfields in the common header file. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/clk/clk-ld11.c | 2 +- arch/arm/mach-uniphier/sc64-regs.h | 18 ------------------ 2 files changed, 1 insertion(+), 19 deletions(-) diff --git a/arch/arm/mach-uniphier/clk/clk-ld11.c b/arch/arm/mach-uniphier/clk/clk-ld11.c index 0266e7e..a4b7419 100644 --- a/arch/arm/mach-uniphier/clk/clk-ld11.c +++ b/arch/arm/mach-uniphier/clk/clk-ld11.c @@ -40,7 +40,7 @@ void uniphier_ld11_clk_init(void) int ch; tmp = readl(SC_CLKCTRL4); - tmp |= SC_CLKCTRL4_MIO | SC_CLKCTRL4_STDMAC; + tmp |= BIT(10) | BIT(8); /* MIO, STDMAC */ writel(tmp, SC_CLKCTRL4); for (ch = 0; ch < 3; ch++) { diff --git a/arch/arm/mach-uniphier/sc64-regs.h b/arch/arm/mach-uniphier/sc64-regs.h index d0a51f2..80efb4e 100644 --- a/arch/arm/mach-uniphier/sc64-regs.h +++ b/arch/arm/mach-uniphier/sc64-regs.h @@ -15,34 +15,16 @@ #define SC_RSTCTRL (SC_BASE_ADDR | 0x2000) #define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008) #define SC_RSTCTRL4 (SC_BASE_ADDR | 0x200c) -#define SC_RSTCTRL4_ETHER (1 << 6) -#define SC_RSTCTRL4_NAND (1 << 0) #define SC_RSTCTRL5 (SC_BASE_ADDR | 0x2010) #define SC_RSTCTRL6 (SC_BASE_ADDR | 0x2014) #define SC_RSTCTRL7 (SC_BASE_ADDR | 0x2018) -#define SC_RSTCTRL7_UMCSB (1 << 16) -#define SC_RSTCTRL7_UMCA2 (1 << 10) -#define SC_RSTCTRL7_UMCA1 (1 << 9) -#define SC_RSTCTRL7_UMCA0 (1 << 8) -#define SC_RSTCTRL7_UMC32 (1 << 2) -#define SC_RSTCTRL7_UMC31 (1 << 1) -#define SC_RSTCTRL7_UMC30 (1 << 0) #define SC_CLKCTRL (SC_BASE_ADDR | 0x2100) #define SC_CLKCTRL3 (SC_BASE_ADDR | 0x2108) #define SC_CLKCTRL4 (SC_BASE_ADDR | 0x210c) -#define SC_CLKCTRL4_MIO (1 << 10) -#define SC_CLKCTRL4_STDMAC (1 << 8) -#define SC_CLKCTRL4_PERI (1 << 7) -#define SC_CLKCTRL4_ETHER (1 << 6) -#define SC_CLKCTRL4_NAND (1 << 0) #define SC_CLKCTRL5 (SC_BASE_ADDR | 0x2110) #define SC_CLKCTRL6 (SC_BASE_ADDR | 0x2114) #define SC_CLKCTRL7 (SC_BASE_ADDR | 0x2118) -#define SC_CLKCTRL7_UMCSB (1 << 16) -#define SC_CLKCTRL7_UMC32 (1 << 2) -#define SC_CLKCTRL7_UMC31 (1 << 1) -#define SC_CLKCTRL7_UMC30 (1 << 0) #define SC_CA72_GEARST (SC_BASE_ADDR | 0x8000) #define SC_CA72_GEARSET (SC_BASE_ADDR | 0x8004) From patchwork Fri Sep 15 12:43:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 112733 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp573979qgf; Fri, 15 Sep 2017 05:45:37 -0700 (PDT) X-Google-Smtp-Source: AOwi7QDRtYMBgAPTfgHfIcqQq4DpRp/tMUGghazQSR3qWRKh/DX0/2Dd8RJBXdiAnCypoBZOhZtD X-Received: by 10.80.146.194 with SMTP id l2mr5145369eda.71.1505479537744; Fri, 15 Sep 2017 05:45:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505479537; cv=none; d=google.com; s=arc-20160816; b=mUqjsfnPLVvDSGbCSc/CkWZSS4WE4cmeKZUxfd4QiuMjhxVKdp2cpasaAoVYURi/O7 ktEa3aYskkrjSd6bgQ6E7BjlP2KPZYnHCXgvYlMDNvlmwlNGtU3SswD+SBKOsIf85wiK L/76+9F6ZqbDrdTyqYP99Pqypd3BpL9RHdO25VJuSpt1r0RmslI/AJYDdTlv9/TwD4lL 2mIZ3swsv2FphUs72mnPfUtZGCKo5CzBfZm+4B9IqCNPPXAauP2cLC+ycwxLdrIdW/Te L5jUe7LsG1h+FjqSXQEC5ajz/tPEDxwYoQVVc4Q/ZxQ7RQgE1LLeA/kXmWmn06dsMF7H X0LQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:dkim-filter:arc-authentication-results; bh=mmwOLqZkFCZB3djKveJaOBNrp3RhUQEWTrLWA/4sp9M=; b=QWEG7e9G8tzhAQBLmzwwRVqer99ZIwx7UOLlOs1Tz6BRCeQktzRlkHIOBrrukm+dPJ hHgfBTFj0gzrPMW/vB71l9HpCLXLcCmcqrTEVFE0OtultuxcNHtJSV0094NQt8pPeGnx 3hwxSQK7EPC3YilgDZLXKFd/COOUlowF3pWLtSHADmPp/pyqgN3KxjimxIH6F9jtg+4s KslXl/kNjBykts/PO0CFd7vhAaPg09M6sNGBhrtZUJiozNE6YfynVhp8+9lGu3qA40vA FYhfinZMgRZZ0l01l5UVDBcncfnm6mJcQpnGr6cn/PNqQl42zk4lrUMDtEpevuXz5Xkr xE4g== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=gsct4I8C; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id u14si1018240edl.539.2017.09.15.05.45.37; Fri, 15 Sep 2017 05:45:37 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=gsct4I8C; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id 511E9C2201F; Fri, 15 Sep 2017 12:44:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 3601AC21FF5; Fri, 15 Sep 2017 12:44:56 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 34573C21F2A; Fri, 15 Sep 2017 12:44:17 +0000 (UTC) Received: from conuserg-11.nifty.com (conuserg-11.nifty.com [210.131.2.78]) by lists.denx.de (Postfix) with ESMTPS id C9332C21FF6 for ; Fri, 15 Sep 2017 12:44:16 +0000 (UTC) Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-11.nifty.com with ESMTP id v8FChYNx026429; Fri, 15 Sep 2017 21:43:54 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-11.nifty.com v8FChYNx026429 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1505479434; bh=7W8mAOOUVMszxzViYVtTIQqf9QEBAlrqlIOKf4OJE4w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=gsct4I8CfNts+mkzITf6m5AXuqoAd73npLTD90KL2osFzmgJjl10LKKElsHUWhW1p EvlUMqbDxdx9I7xQkYoIN20WxQQKtKanYjyXG3aRHckm5FhnK8lqL2mPrRRX2kG+sh n9O49Xnp63D5xxkn2rN56CLzYoec0rRKN9cBHspSIN/U2PGKbUfQgLgUOhpbMwzs/J i0S9mc/YBHOhIa/b5RWseA2+Ii7ZXfRQitmOXDrc4Vi7DuUztnrWYgPtTySYVn2Uhl 4mKKSN0l+ZJvLyo11BfeBOMDkAUCvEtZiojiCpxT4+IPW4j/DoGEDJmXm+eZyqDU55 4/pO5oFoLZCGg== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Fri, 15 Sep 2017 21:43:22 +0900 Message-Id: <1505479402-17945-4-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505479402-17945-1-git-send-email-yamada.masahiro@socionext.com> References: <1505479402-17945-1-git-send-email-yamada.masahiro@socionext.com> Subject: [U-Boot] [PATCH 4/4] ARM: uniphier: add GPU(Mali) reset deassert and clk enable X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The driver for Linux is out of control of Socionext, so set up reset / clock in here. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/clk/clk-ld20.c | 12 ++++++++++++ arch/arm/mach-uniphier/clk/clk-pxs3.c | 12 ++++++++++++ 2 files changed, 24 insertions(+) diff --git a/arch/arm/mach-uniphier/clk/clk-ld20.c b/arch/arm/mach-uniphier/clk/clk-ld20.c index 5bb560c..f79fb38 100644 --- a/arch/arm/mach-uniphier/clk/clk-ld20.c +++ b/arch/arm/mach-uniphier/clk/clk-ld20.c @@ -4,14 +4,26 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include #include #include "../init.h" +#include "../sc64-regs.h" #define SDCTRL_EMMC_HW_RESET 0x59810280 void uniphier_ld20_clk_init(void) { + u32 tmp; + + tmp = readl(SC_RSTCTRL6); + tmp |= BIT(8); /* Mali */ + writel(tmp, SC_RSTCTRL6); + + tmp = readl(SC_CLKCTRL6); + tmp |= BIT(8); /* Mali */ + writel(tmp, SC_CLKCTRL6); + /* TODO: use "mmc-pwrseq-emmc" */ writel(1, SDCTRL_EMMC_HW_RESET); } diff --git a/arch/arm/mach-uniphier/clk/clk-pxs3.c b/arch/arm/mach-uniphier/clk/clk-pxs3.c index 2dee857..3b9cc62 100644 --- a/arch/arm/mach-uniphier/clk/clk-pxs3.c +++ b/arch/arm/mach-uniphier/clk/clk-pxs3.c @@ -4,14 +4,26 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include #include #include "../init.h" +#include "../sc64-regs.h" #define SDCTRL_EMMC_HW_RESET 0x59810280 void uniphier_pxs3_clk_init(void) { + u32 tmp; + + tmp = readl(SC_RSTCTRL6); + tmp |= BIT(8); /* Mali */ + writel(tmp, SC_RSTCTRL6); + + tmp = readl(SC_CLKCTRL6); + tmp |= BIT(8); /* Mali */ + writel(tmp, SC_CLKCTRL6); + /* TODO: use "mmc-pwrseq-emmc" */ writel(1, SDCTRL_EMMC_HW_RESET); }