From patchwork Thu Apr 30 08:04:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 220255 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.5 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5753AC83009 for ; Thu, 30 Apr 2020 08:05:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 35FF82073E for ; Thu, 30 Apr 2020 08:05:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=marvell.com header.i=@marvell.com header.b="tWCk372i" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726672AbgD3IFK (ORCPT ); Thu, 30 Apr 2020 04:05:10 -0400 Received: from mx0a-0016f401.pphosted.com ([67.231.148.174]:54784 "EHLO mx0b-0016f401.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726424AbgD3IFJ (ORCPT ); Thu, 30 Apr 2020 04:05:09 -0400 Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 03U852cA011045; Thu, 30 Apr 2020 01:05:08 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0818; bh=tn9jbC7/ij901B2RkllXfirUysWJSGmhHGBMTo3Hf/g=; b=tWCk372iHq8depn6E5k0hrV67dTlw4Nw8I48QtMVq//golD4s09s3QxhUrbPJTYBXnGk B8yVg3T4OiNlZDWEJUHZh8ppCB7ccFp7F/Utfnz//Cp3s3eKWB/8R0ec2LIXQUpqaenj TifVmaKNR9E8WaxFLnPZsuTOM2HKnWMnyjPFM4Xz2T33lZBWqI6ipwbrfPcW2g2jwZra DRxMaob49ohRqaQ5siB4eWXVWEK7vDdpFGKwIjWuLnfPBEsqcW7mv3Z0JpLvMhAyyzAo ss1fUJq3QLff8jQ8fDAgWNJyj/EMC+v27Hsnzz2GwOT8/OYBi0d17R+heiQzw4wEgdSJ iA== Received: from sc-exch03.marvell.com ([199.233.58.183]) by mx0a-0016f401.pphosted.com with ESMTP id 30mjjqnshh-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 30 Apr 2020 01:05:08 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 30 Apr 2020 01:05:06 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 30 Apr 2020 01:05:07 -0700 Received: from NN-LT0019.marvell.com (unknown [10.193.46.2]) by maili.marvell.com (Postfix) with ESMTP id 39D843F703F; Thu, 30 Apr 2020 01:05:04 -0700 (PDT) From: Igor Russkikh To: CC: "David S . Miller" , Mark Starovoytov , Igor Russkikh Subject: [PATCH v2 net-next 02/17] net: atlantic: add A2 device IDs Date: Thu, 30 Apr 2020 11:04:30 +0300 Message-ID: <20200430080445.1142-3-irusskikh@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200430080445.1142-1-irusskikh@marvell.com> References: <20200430080445.1142-1-irusskikh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.676 definitions=2020-04-30_02:2020-04-30,2020-04-30 signatures=0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Adding device ids for the new generation of atlantic nic. Signed-off-by: Igor Russkikh Signed-off-by: Mark Starovoytov --- drivers/net/ethernet/aquantia/atlantic/aq_common.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_common.h b/drivers/net/ethernet/aquantia/atlantic/aq_common.h index d5beb798bab6..1261e7c7a01e 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_common.h +++ b/drivers/net/ethernet/aquantia/atlantic/aq_common.h @@ -37,6 +37,13 @@ #define AQ_DEVICE_ID_AQC111S 0x91B1 #define AQ_DEVICE_ID_AQC112S 0x92B1 +#define AQ_DEVICE_ID_AQC113DEV 0x00C0 +#define AQ_DEVICE_ID_AQC113CS 0x94C0 +#define AQ_DEVICE_ID_AQC114CS 0x93C0 +#define AQ_DEVICE_ID_AQC113 0x04C0 +#define AQ_DEVICE_ID_AQC113C 0x14C0 +#define AQ_DEVICE_ID_AQC115C 0x12C0 + #define HW_ATL_NIC_NAME "Marvell (aQuantia) AQtion 10Gbit Network Adapter" #define AQ_HWREV_ANY 0 From patchwork Thu Apr 30 08:04:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 220253 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.5 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 48BD4C83009 for ; Thu, 30 Apr 2020 08:05:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 274002073E for ; Thu, 30 Apr 2020 08:05:22 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=marvell.com header.i=@marvell.com header.b="xYOsUoE/" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726683AbgD3IFO (ORCPT ); Thu, 30 Apr 2020 04:05:14 -0400 Received: from mx0a-0016f401.pphosted.com ([67.231.148.174]:28842 "EHLO mx0b-0016f401.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726424AbgD3IFM (ORCPT ); Thu, 30 Apr 2020 04:05:12 -0400 Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 03U85443011213; Thu, 30 Apr 2020 01:05:11 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0818; bh=8+QsHNwsVguzepb0Iynr19dvCx5TFFGx/3z0/+lkxF4=; b=xYOsUoE/h/MXyL0DyTyTh6bHfvvPEkVNr3YsaRkZeoe2glIWwvQ938ZL0olRTdOnfYqu DfSqSQUkNdNJp5+v2eyWeqfkw/wFhR8Jlr447lJ68y3BSSC+SJvEzsi+2Uf5IIofgkr5 08yMJH2M96IxmtpXYcOEKmzA9dICmc6hSoYZjEqMxolexqP80OU4HfLQEebQp874g23O eAoZlz67TQXZ7Md0mtSpMJWSJFiGoBmDK+rPYvJIBs3ZUdqilEmXTV1FAdPUkWMtGlkQ +W8rvmocZEpG3bykldPnTy8PgFggKxcIHdi6I+/wuYwG0IA4WRR7iSFFsspnovT6MER7 wQ== Received: from sc-exch01.marvell.com ([199.233.58.181]) by mx0a-0016f401.pphosted.com with ESMTP id 30mjjqnsj0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 30 Apr 2020 01:05:11 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 30 Apr 2020 01:05:09 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 30 Apr 2020 01:05:09 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 30 Apr 2020 01:05:09 -0700 Received: from NN-LT0019.marvell.com (unknown [10.193.46.2]) by maili.marvell.com (Postfix) with ESMTP id 537EC3F7040; Thu, 30 Apr 2020 01:05:07 -0700 (PDT) From: Igor Russkikh To: CC: "David S . Miller" , Mark Starovoytov , Igor Russkikh Subject: [PATCH v2 net-next 03/17] net: atlantic: add defines for 10M and EEE 100M link mode Date: Thu, 30 Apr 2020 11:04:31 +0300 Message-ID: <20200430080445.1142-4-irusskikh@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200430080445.1142-1-irusskikh@marvell.com> References: <20200430080445.1142-1-irusskikh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.676 definitions=2020-04-30_02:2020-04-30,2020-04-30 signatures=0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This patch adds defines for 10M and EEE 100M link modes, which are supported by A2. 10M support is added in this patch series. EEE is out of scope, but will be added in a follow-up series. Signed-off-by: Igor Russkikh Signed-off-by: Mark Starovoytov --- .../ethernet/aquantia/atlantic/aq_common.h | 22 ++++++++++--------- .../ethernet/aquantia/atlantic/aq_ethtool.c | 3 +++ .../net/ethernet/aquantia/atlantic/aq_nic.c | 12 ++++++++++ 3 files changed, 27 insertions(+), 10 deletions(-) diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_common.h b/drivers/net/ethernet/aquantia/atlantic/aq_common.h index 1261e7c7a01e..53620ba6d7a6 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_common.h +++ b/drivers/net/ethernet/aquantia/atlantic/aq_common.h @@ -50,16 +50,18 @@ #define AQ_HWREV_1 1 #define AQ_HWREV_2 2 -#define AQ_NIC_RATE_10G BIT(0) -#define AQ_NIC_RATE_5G BIT(1) -#define AQ_NIC_RATE_5GSR BIT(2) -#define AQ_NIC_RATE_2GS BIT(3) -#define AQ_NIC_RATE_1G BIT(4) -#define AQ_NIC_RATE_100M BIT(5) +#define AQ_NIC_RATE_10G BIT(0) +#define AQ_NIC_RATE_5G BIT(1) +#define AQ_NIC_RATE_5GSR BIT(2) +#define AQ_NIC_RATE_2GS BIT(3) +#define AQ_NIC_RATE_1G BIT(4) +#define AQ_NIC_RATE_100M BIT(5) +#define AQ_NIC_RATE_10M BIT(6) -#define AQ_NIC_RATE_EEE_10G BIT(6) -#define AQ_NIC_RATE_EEE_5G BIT(7) -#define AQ_NIC_RATE_EEE_2GS BIT(8) -#define AQ_NIC_RATE_EEE_1G BIT(9) +#define AQ_NIC_RATE_EEE_10G BIT(7) +#define AQ_NIC_RATE_EEE_5G BIT(8) +#define AQ_NIC_RATE_EEE_2GS BIT(9) +#define AQ_NIC_RATE_EEE_1G BIT(10) +#define AQ_NIC_RATE_EEE_100M BIT(11) #endif /* AQ_COMMON_H */ diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_ethtool.c b/drivers/net/ethernet/aquantia/atlantic/aq_ethtool.c index 7241cf92b43a..0c9dd8edc062 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_ethtool.c +++ b/drivers/net/ethernet/aquantia/atlantic/aq_ethtool.c @@ -611,6 +611,9 @@ static enum hw_atl_fw2x_rate eee_mask_to_ethtool_mask(u32 speed) if (speed & AQ_NIC_RATE_EEE_1G) rate |= SUPPORTED_1000baseT_Full; + if (speed & AQ_NIC_RATE_EEE_100M) + rate |= SUPPORTED_100baseT_Full; + return rate; } diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_nic.c b/drivers/net/ethernet/aquantia/atlantic/aq_nic.c index a369705a786a..80dd744dcbd1 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_nic.c +++ b/drivers/net/ethernet/aquantia/atlantic/aq_nic.c @@ -885,6 +885,10 @@ void aq_nic_get_link_ksettings(struct aq_nic_s *self, ethtool_link_ksettings_add_link_mode(cmd, supported, 100baseT_Full); + if (self->aq_nic_cfg.aq_hw_caps->link_speed_msk & AQ_NIC_RATE_10M) + ethtool_link_ksettings_add_link_mode(cmd, supported, + 10baseT_Full); + if (self->aq_nic_cfg.aq_hw_caps->flow_control) { ethtool_link_ksettings_add_link_mode(cmd, supported, Pause); @@ -924,6 +928,10 @@ void aq_nic_get_link_ksettings(struct aq_nic_s *self, ethtool_link_ksettings_add_link_mode(cmd, advertising, 100baseT_Full); + if (self->aq_nic_cfg.link_speed_msk & AQ_NIC_RATE_10M) + ethtool_link_ksettings_add_link_mode(cmd, advertising, + 10baseT_Full); + if (self->aq_nic_cfg.fc.cur & AQ_NIC_FC_RX) ethtool_link_ksettings_add_link_mode(cmd, advertising, Pause); @@ -954,6 +962,10 @@ int aq_nic_set_link_ksettings(struct aq_nic_s *self, speed = cmd->base.speed; switch (speed) { + case SPEED_10: + rate = AQ_NIC_RATE_10M; + break; + case SPEED_100: rate = AQ_NIC_RATE_100M; break; From patchwork Thu Apr 30 08:04:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 220254 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.5 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22DDAC83006 for ; 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Thu, 30 Apr 2020 01:05:11 -0700 (PDT) From: Igor Russkikh To: CC: "David S . Miller" , Mark Starovoytov , Nikita Danilov Subject: [PATCH v2 net-next 05/17] net: atlantic: simplify hw_get_fw_version() usage Date: Thu, 30 Apr 2020 11:04:33 +0300 Message-ID: <20200430080445.1142-6-irusskikh@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200430080445.1142-1-irusskikh@marvell.com> References: <20200430080445.1142-1-irusskikh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.676 definitions=2020-04-30_02:2020-04-30,2020-04-30 signatures=0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Nikita Danilov hw_get_fw_version() never fails, so this patch simplifies its usage by utilizing return value instead of output argument. Signed-off-by: Nikita Danilov Signed-off-by: Mark Starovoytov --- drivers/net/ethernet/aquantia/atlantic/aq_hw.h | 2 +- drivers/net/ethernet/aquantia/atlantic/aq_nic.c | 6 +----- .../net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c | 8 +++----- .../net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h | 2 +- 4 files changed, 6 insertions(+), 12 deletions(-) diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_hw.h b/drivers/net/ethernet/aquantia/atlantic/aq_hw.h index 84abce29d590..c0dada1075cf 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_hw.h +++ b/drivers/net/ethernet/aquantia/atlantic/aq_hw.h @@ -259,7 +259,7 @@ struct aq_hw_ops { struct aq_stats_s *(*hw_get_hw_stats)(struct aq_hw_s *self); - int (*hw_get_fw_version)(struct aq_hw_s *self, u32 *fw_version); + u32 (*hw_get_fw_version)(struct aq_hw_s *self); int (*hw_set_offload)(struct aq_hw_s *self, struct aq_nic_cfg_s *aq_nic_cfg); diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_nic.c b/drivers/net/ethernet/aquantia/atlantic/aq_nic.c index 7f4d8abab951..57102f35e9f3 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_nic.c +++ b/drivers/net/ethernet/aquantia/atlantic/aq_nic.c @@ -1032,11 +1032,7 @@ struct aq_nic_cfg_s *aq_nic_get_cfg(struct aq_nic_s *self) u32 aq_nic_get_fw_version(struct aq_nic_s *self) { - u32 fw_version = 0U; - - self->aq_hw_ops->hw_get_fw_version(self->aq_hw, &fw_version); - - return fw_version; + return self->aq_hw_ops->hw_get_fw_version(self->aq_hw); } int aq_nic_set_loopback(struct aq_nic_s *self) diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c index 7259bcb81e9b..bd1712ca9ef2 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c @@ -70,7 +70,7 @@ int hw_atl_utils_initfw(struct aq_hw_s *self, const struct aq_fw_ops **fw_ops) hw_atl_utils_hw_chip_features_init(self, &self->chip_features); - hw_atl_utils_get_fw_version(self, &self->fw_ver_actual); + self->fw_ver_actual = hw_atl_utils_get_fw_version(self); if (hw_atl_utils_ver_match(HW_ATL_FW_VER_1X, self->fw_ver_actual) == 0) { @@ -915,11 +915,9 @@ int hw_atl_utils_hw_get_regs(struct aq_hw_s *self, return 0; } -int hw_atl_utils_get_fw_version(struct aq_hw_s *self, u32 *fw_version) +u32 hw_atl_utils_get_fw_version(struct aq_hw_s *self) { - *fw_version = aq_hw_read_reg(self, 0x18U); - - return 0; + return aq_hw_read_reg(self, HW_ATL_MPI_FW_VERSION); } static int aq_fw1x_set_wake_magic(struct aq_hw_s *self, bool wol_enabled, diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h index b15513914636..086627a96746 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h @@ -622,7 +622,7 @@ int hw_atl_utils_hw_set_power(struct aq_hw_s *self, int hw_atl_utils_hw_deinit(struct aq_hw_s *self); -int hw_atl_utils_get_fw_version(struct aq_hw_s *self, u32 *fw_version); +u32 hw_atl_utils_get_fw_version(struct aq_hw_s *self); int hw_atl_utils_update_stats(struct aq_hw_s *self); From patchwork Thu Apr 30 08:04:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 220251 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.5 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6BD4AC83001 for ; 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Thu, 30 Apr 2020 01:05:16 -0700 (PDT) From: Igor Russkikh To: CC: "David S . Miller" , Mark Starovoytov , Dmitry Bogdanov Subject: [PATCH v2 net-next 08/17] net: atlantic: A2 driver-firmware interface Date: Thu, 30 Apr 2020 11:04:36 +0300 Message-ID: <20200430080445.1142-9-irusskikh@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200430080445.1142-1-irusskikh@marvell.com> References: <20200430080445.1142-1-irusskikh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.676 definitions=2020-04-30_02:2020-04-30,2020-04-30 signatures=0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Dmitry Bogdanov This patch adds the driver<->firmware interface for A2 Signed-off-by: Dmitry Bogdanov Signed-off-by: Mark Starovoytov --- .../aquantia/atlantic/hw_atl2/hw_atl2_utils.h | 593 ++++++++++++++++++ 1 file changed, 593 insertions(+) create mode 100644 drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_utils.h diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_utils.h b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_utils.h new file mode 100644 index 000000000000..7d4ac65440c9 --- /dev/null +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_utils.h @@ -0,0 +1,593 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Atlantic Network Driver + * Copyright (C) 2020 Marvell International Ltd. + */ + +#ifndef HW_ATL2_UTILS_H +#define HW_ATL2_UTILS_H + +/* F W A P I */ + +struct link_options_s { + u8 link_up:1; + u8 link_renegotiate:1; + u8 minimal_link_speed:1; + u8 internal_loopback:1; + u8 external_loopback:1; + u8 rate_10M_hd:1; + u8 rate_100M_hd:1; + u8 rate_1G_hd:1; + + u8 rate_10M:1; + u8 rate_100M:1; + u8 rate_1G:1; + u8 rate_2P5G:1; + u8 rate_N2P5G:1; + u8 rate_5G:1; + u8 rate_N5G:1; + u8 rate_10G:1; + + u8 eee_100M:1; + u8 eee_1G:1; + u8 eee_2P5G:1; + u8 eee_5G:1; + u8 eee_10G:1; + u8 rsvd3:3; + + u8 pause_rx:1; + u8 pause_tx:1; + u8 rsvd4:1; + u8 downshift:1; + u8 downshift_retry:4; +}; + +struct link_control_s { + u8 mode:4; + u8 disable_crc_corruption:1; + u8 discard_short_frames:1; + u8 flow_control_mode:1; + u8 disable_length_check:1; + + u8 discard_errored_frames:1; + u8 control_frame_enable:1; + u8 enable_tx_padding:1; + u8 enable_crc_forwarding:1; + u8 enable_frame_padding_removal_rx: 1; + u8 promiscuous_mode: 1; + u8 rsvd:2; + + u16 rsvd2; +}; + +struct thermal_shutdown_s { + u8 enable:1; + u8 warning_enable:1; + u8 rsvd:6; + + u8 shutdown_temperature; + u8 cold_temperature; + u8 warning_temperature; +}; + +struct mac_address_s { + u8 mac_address[6]; +}; + +struct mac_address_aligned_s { + struct mac_address_s aligned; + u16 rsvd; +}; + +struct sleep_proxy_s { + struct wake_on_lan_s { + u8 wake_on_magic_packet:1; + u8 wake_on_pattern:1; + u8 wake_on_link_up:1; + u8 wake_on_link_down:1; + u8 wake_on_ping:1; + u8 wake_on_timer:1; + u8 rsvd:2; + + u8 rsvd2; + u16 rsvd3; + + u32 link_up_timeout; + u32 link_down_timeout; + u32 timer; + } wake_on_lan; + + struct { + u32 mask[4]; + u32 crc32; + } wake_up_pattern[8]; + + struct __attribute__ ((__packed__)) { + u8 arp_responder:1; + u8 echo_responder:1; + u8 igmp_client:1; + u8 echo_truncate:1; + u8 address_guard:1; + u8 ignore_fragmented:1; + u8 rsvd:2; + + u16 echo_max_len; + u8 rsvd2; + } ipv4_offload; + + u32 ipv4_offload_addr[8]; + u32 reserved[8]; + + struct __attribute__ ((__packed__)) { + u8 ns_responder:1; + u8 echo_responder:1; + u8 mld_client:1; + u8 echo_truncate:1; + u8 address_guard:1; + u8 rsvd:3; + + u16 echo_max_len; + u8 rsvd2; + } ipv6_offload; + + u32 ipv6_offload_addr[16][4]; + + struct { + u16 port[16]; + } tcp_port_offload; + + struct { + u16 port[16]; + } udp_port_offload; + + struct { + u32 retry_count; + u32 retry_interval; + } ka4_offload; + + struct { + u32 timeout; + u16 local_port; + u16 remote_port; + u8 remote_mac_addr[6]; + u16 rsvd; + u32 rsvd2; + u32 rsvd3; + u16 rsvd4; + u16 win_size; + u32 seq_num; + u32 ack_num; + u32 local_ip; + u32 remote_ip; + } ka4_connection[16]; + + struct { + u32 retry_count; + u32 retry_interval; + } ka6_offload; + + struct { + u32 timeout; + u16 local_port; + u16 remote_port; + u8 remote_mac_addr[6]; + u16 rsvd; + u32 rsvd2; + u32 rsvd3; + u16 rsvd4; + u16 win_size; + u32 seq_num; + u32 ack_num; + u32 local_ip[4]; + u32 remote_ip[4]; + } ka6_connection[16]; + + struct { + u32 rr_count; + u32 rr_buf_len; + u32 idx_offset; + u32 rr__offset; + } mdns_offload; +}; + +struct pause_quanta_s { + u16 quanta_10M; + u16 threshold_10M; + u16 quanta_100M; + u16 threshold_100M; + u16 quanta_1G; + u16 threshold_1G; + u16 quanta_2P5G; + u16 threshold_2P5G; + u16 quanta_5G; + u16 threshold_5G; + u16 quanta_10G; + u16 threshold_10G; +}; + +struct data_buffer_status_s { + u32 data_offset; + u32 data_length; +}; + +struct device_caps_s { + u8 finite_flashless:1; + u8 cable_diag:1; + u8 ncsi:1; + u8 avb:1; + u8 rsvd:4; + + u8 rsvd2; + u16 rsvd3; + u32 rsvd4; +}; + +struct version_s { + struct bundle_version_t { + u8 major; + u8 minor; + u16 build; + } bundle; + struct mac_version_t { + u8 major; + u8 minor; + u16 build; + } mac; + struct phy_version_t { + u8 major; + u8 minor; + u16 build; + } phy; + u32 rsvd; +}; + +struct link_status_s { + u8 link_state:4; + u8 link_rate:4; + + u8 pause_tx:1; + u8 pause_rx:1; + u8 eee:1; + u8 duplex:1; + u8 rsvd:4; + + u16 rsvd2; +}; + +struct wol_status_s { + u8 wake_count; + u8 wake_reason; + + u16 wake_up_packet_length :12; + u16 wake_up_pattern_number :3; + u16 rsvd:1; + + u32 wake_up_packet[379]; +}; + +struct mac_health_monitor_s { + u8 mac_ready:1; + u8 mac_fault:1; + u8 mac_flashless_finished:1; + u8 rsvd:5; + + u8 mac_temperature; + u16 mac_heart_beat; + u16 mac_fault_code; + u16 rsvd2; +}; + +struct phy_health_monitor_s { + u8 phy_ready:1; + u8 phy_fault:1; + u8 phy_hot_warning:1; + u8 rsvd:5; + + u8 phy_temperature; + u16 phy_heart_beat; + u16 phy_fault_code; + u16 rsvd2; +}; + +struct device_link_caps_s { + u8 rsvd:3; + u8 internal_loopback:1; + u8 external_loopback:1; + u8 rate_10M_hd:1; + u8 rate_100M_hd:1; + u8 rate_1G_hd:1; + + u8 rate_10M:1; + u8 rate_100M:1; + u8 rate_1G:1; + u8 rate_2P5G:1; + u8 rate_N2P5G:1; + u8 rate_5G:1; + u8 rate_N5G:1; + u8 rate_10G:1; + + u8 rsvd3:1; + u8 eee_100M:1; + u8 eee_1G:1; + u8 eee_2P5G:1; + u8 rsvd4:1; + u8 eee_5G:1; + u8 rsvd5:1; + u8 eee_10G:1; + + u8 pause_rx:1; + u8 pause_tx:1; + u8 pfc:1; + u8 downshift:1; + u8 downshift_retry:4; +}; + +struct sleep_proxy_caps_s { + u8 ipv4_offload:1; + u8 ipv6_offload:1; + u8 tcp_port_offload:1; + u8 udp_port_offload:1; + u8 ka4_offload:1; + u8 ka6_offload:1; + u8 mdns_offload:1; + u8 wake_on_ping:1; + + u8 wake_on_magic_packet:1; + u8 wake_on_pattern:1; + u8 wake_on_timer:1; + u8 wake_on_link:1; + u8 wake_patterns_count:4; + + u8 ipv4_count; + u8 ipv6_count; + + u8 tcp_port_offload_count; + u8 udp_port_offload_count; + + u8 tcp4_ka_count; + u8 tcp6_ka_count; + + u8 igmp_offload:1; + u8 mld_offload:1; + u8 rsvd:6; + + u8 rsvd2; + u16 rsvd3; +}; + +struct lkp_link_caps_s { + u8 rsvd:5; + u8 rate_10M_hd:1; + u8 rate_100M_hd:1; + u8 rate_1G_hd:1; + + u8 rate_10M:1; + u8 rate_100M:1; + u8 rate_1G:1; + u8 rate_2P5G:1; + u8 rate_N2P5G:1; + u8 rate_5G:1; + u8 rate_N5G:1; + u8 rate_10G:1; + + u8 rsvd2:1; + u8 eee_100M:1; + u8 eee_1G:1; + u8 eee_2P5G:1; + u8 rsvd3:1; + u8 eee_5G:1; + u8 rsvd4:1; + u8 eee_10G:1; + + u8 pause_rx:1; + u8 pause_tx:1; + u8 rsvd5:6; +}; + +struct core_dump_s { + u32 reg0; + u32 reg1; + u32 reg2; + + u32 hi; + u32 lo; + + u32 regs[32]; +}; + +struct trace_s { + u32 sync_counter; + u32 mem_buffer[0x1ff]; +}; + +struct cable_diag_control_s { + u8 toggle :1; + u8 rsvd:7; + + u8 wait_timeout_sec; + u16 rsvd2; +}; + +struct cable_diag_lane_data_s { + u8 result_code; + u8 dist; + u8 far_dist; + u8 rsvd; +}; + +struct cable_diag_status_s { + struct cable_diag_lane_data_s lane_data[4]; + u8 transact_id; + u8 status:4; + u8 rsvd:4; + u16 rsvd2; +}; + +struct statistics_s { + struct { + u32 link_up; + u32 link_down; + } link; + + struct { + u64 tx_unicast_octets; + u64 tx_multicast_octets; + u64 tx_broadcast_octets; + u64 rx_unicast_octets; + u64 rx_multicast_octets; + u64 rx_broadcast_octets; + + u32 tx_unicast_frames; + u32 tx_multicast_frames; + u32 tx_broadcast_frames; + u32 tx_errors; + + u32 rx_unicast_frames; + u32 rx_multicast_frames; + u32 rx_broadcast_frames; + u32 rx_dropped_frames; + u32 rx_error_frames; + + u32 tx_good_frames; + u32 rx_good_frames; + u32 reserve_fw_gap; + } msm; + u32 main_loop_cycles; + u32 reserve_fw_gap; +}; + +struct filter_caps_s { + u8 l2_filters_base_index:6; + u8 flexible_filter_mask:2; + u8 l2_filter_count; + u8 ethertype_filter_base_index; + u8 ethertype_filter_count; + + u8 vlan_filter_base_index; + u8 vlan_filter_count; + u8 l3_ip4_filter_base_index:4; + u8 l3_ip4_filter_count:4; + u8 l3_ip6_filter_base_index:4; + u8 l3_ip6_filter_count:4; + + u8 l4_filter_base_index:4; + u8 l4_filter_count:4; + u8 l4_flex_filter_base_index:4; + u8 l4_flex_filter_count:4; + u8 rslv_tbl_base_index; + u8 rslv_tbl_count; +}; + +struct request_policy_s { + struct { + u8 all:1; + u8 mcast:1; + u8 rx_queue_tc_index:5; + u8 queue_or_tc:1; + } promisc; + + struct { + u8 accept:1; + u8 rsvd:1; + u8 rx_queue_tc_index:5; + u8 queue_or_tc:1; + } bcast; + + struct { + u8 accept:1; + u8 rsvd:1; + u8 rx_queue_tc_index:5; + u8 queue_or_tc:1; + } mcast; + + u8 rsvd:8; +}; + +struct fw_interface_in { + u32 mtu; + u32 rsvd1; + struct mac_address_aligned_s mac_address; + struct link_control_s link_control; + u32 rsvd2; + struct link_options_s link_options; + u32 rsvd3; + struct thermal_shutdown_s thermal_shutdown; + u32 rsvd4; + struct sleep_proxy_s sleep_proxy; + u32 rsvd5; + struct pause_quanta_s pause_quanta[8]; + struct cable_diag_control_s cable_diag_control; + u32 rsvd6; + struct data_buffer_status_s data_buffer_status; + u32 rsvd7; + struct request_policy_s request_policy; +}; + +struct transaction_counter_s { + u16 transaction_cnt_a; + u16 transaction_cnt_b; +}; + +struct management_status_s { + struct mac_address_s mac_address; + u16 vlan; + + struct{ + u32 enable : 1; + u32 rsvd:31; + } flags; + + u32 rsvd1; + u32 rsvd2; + u32 rsvd3; + u32 rsvd4; + u32 rsvd5; +}; + +struct fw_interface_out { + struct transaction_counter_s transaction_id; + struct version_s version; + struct link_status_s link_status; + struct wol_status_s wol_status; + u32 rsvd; + u32 rsvd2; + struct mac_health_monitor_s mac_health_monitor; + u32 rsvd3; + u32 rsvd4; + struct phy_health_monitor_s phy_health_monitor; + u32 rsvd5; + u32 rsvd6; + struct cable_diag_status_s cable_diag_status; + u32 rsvd7; + struct device_link_caps_s device_link_caps; + u32 rsvd8; + struct sleep_proxy_caps_s sleep_proxy_caps; + u32 rsvd9; + struct lkp_link_caps_s lkp_link_caps; + u32 rsvd10; + struct core_dump_s core_dump; + u32 rsvd11; + struct statistics_s stats; + u32 rsvd12; + struct filter_caps_s filter_caps; + struct device_caps_s device_caps; + u32 rsvd13; + struct management_status_s management_status; + u32 reserve[21]; + struct trace_s trace; +}; + +#define AQ_A2_FW_LINK_RATE_INVALID 0 +#define AQ_A2_FW_LINK_RATE_10M 1 +#define AQ_A2_FW_LINK_RATE_100M 2 +#define AQ_A2_FW_LINK_RATE_1G 3 +#define AQ_A2_FW_LINK_RATE_2G5 4 +#define AQ_A2_FW_LINK_RATE_5G 5 +#define AQ_A2_FW_LINK_RATE_10G 6 + +#define AQ_HOST_MODE_INVALID 0U +#define AQ_HOST_MODE_ACTIVE 1U +#define AQ_HOST_MODE_SLEEP_PROXY 2U +#define AQ_HOST_MODE_LOW_POWER 3U +#define AQ_HOST_MODE_SHUTDOWN 4U + +#endif /* HW_ATL2_UTILS_H */ From patchwork Thu Apr 30 08:04:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 220252 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.5 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1CD80C83006 for ; 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Thu, 30 Apr 2020 01:05:20 -0700 Received: from NN-LT0019.marvell.com (unknown [10.193.46.2]) by maili.marvell.com (Postfix) with ESMTP id B1F3C3F7041; Thu, 30 Apr 2020 01:05:18 -0700 (PDT) From: Igor Russkikh To: CC: "David S . Miller" , Mark Starovoytov , Dmitry Bogdanov Subject: [PATCH v2 net-next 09/17] net: atlantic: minimal A2 HW bindings required for fw_ops Date: Thu, 30 Apr 2020 11:04:37 +0300 Message-ID: <20200430080445.1142-10-irusskikh@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200430080445.1142-1-irusskikh@marvell.com> References: <20200430080445.1142-1-irusskikh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.676 definitions=2020-04-30_02:2020-04-30,2020-04-30 signatures=0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Dmitry Bogdanov This patch adds the bare minimum of A2 HW bindings required to get fw_ops working. Signed-off-by: Dmitry Bogdanov Signed-off-by: Mark Starovoytov --- .../net/ethernet/aquantia/atlantic/Makefile | 1 + .../net/ethernet/aquantia/atlantic/aq_hw.h | 1 + .../aquantia/atlantic/hw_atl2/hw_atl2_llh.c | 56 +++++++++++++++++++ .../aquantia/atlantic/hw_atl2/hw_atl2_llh.h | 31 ++++++++++ .../atlantic/hw_atl2/hw_atl2_llh_internal.h | 48 ++++++++++++++++ 5 files changed, 137 insertions(+) create mode 100644 drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh.c create mode 100644 drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh.h create mode 100644 drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh_internal.h diff --git a/drivers/net/ethernet/aquantia/atlantic/Makefile b/drivers/net/ethernet/aquantia/atlantic/Makefile index 8b555665a33a..86824f1868ab 100644 --- a/drivers/net/ethernet/aquantia/atlantic/Makefile +++ b/drivers/net/ethernet/aquantia/atlantic/Makefile @@ -25,6 +25,7 @@ atlantic-objs := aq_main.o \ hw_atl/hw_atl_utils.o \ hw_atl/hw_atl_utils_fw2x.o \ hw_atl/hw_atl_llh.o \ + hw_atl2/hw_atl2_llh.o \ macsec/macsec_api.o atlantic-$(CONFIG_MACSEC) += aq_macsec.o diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_hw.h b/drivers/net/ethernet/aquantia/atlantic/aq_hw.h index f420ef40b627..e770d91e0876 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_hw.h +++ b/drivers/net/ethernet/aquantia/atlantic/aq_hw.h @@ -172,6 +172,7 @@ struct aq_hw_s { struct hw_atl_utils_fw_rpc rpc; s64 ptp_clk_offset; u16 phy_id; + void *priv; }; struct aq_ring_s; diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh.c new file mode 100644 index 000000000000..b6164bc5fffd --- /dev/null +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh.c @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Atlantic Network Driver + * Copyright (C) 2020 Marvell International Ltd. + */ + +#include "hw_atl2_llh.h" +#include "hw_atl2_llh_internal.h" +#include "aq_hw_utils.h" + +void hw_atl2_mif_shared_buf_get(struct aq_hw_s *aq_hw, int offset, u32 *data, + int len) +{ + int j = 0; + int i; + + for (i = offset; i < offset + len; i++, j++) + data[j] = aq_hw_read_reg(aq_hw, + HW_ATL2_MIF_SHARED_BUFFER_IN_ADR(i)); +} + +void hw_atl2_mif_shared_buf_write(struct aq_hw_s *aq_hw, int offset, u32 *data, + int len) +{ + int j = 0; + int i; + + for (i = offset; i < offset + len; i++, j++) + aq_hw_write_reg(aq_hw, HW_ATL2_MIF_SHARED_BUFFER_IN_ADR(i), + data[j]); +} + +void hw_atl2_mif_shared_buf_read(struct aq_hw_s *aq_hw, int offset, u32 *data, + int len) +{ + int j = 0; + int i; + + for (i = offset; i < offset + len; i++, j++) + data[j] = aq_hw_read_reg(aq_hw, + HW_ATL2_MIF_SHARED_BUFFER_OUT_ADR(i)); +} + +void hw_atl2_mif_host_finished_write_set(struct aq_hw_s *aq_hw, u32 finish) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL2_MIF_HOST_FINISHED_WRITE_ADR, + HW_ATL2_MIF_HOST_FINISHED_WRITE_MSK, + HW_ATL2_MIF_HOST_FINISHED_WRITE_SHIFT, + finish); +} + +u32 hw_atl2_mif_mcp_finished_read_get(struct aq_hw_s *aq_hw) +{ + return aq_hw_read_reg_bit(aq_hw, HW_ATL2_MIF_MCP_FINISHED_READ_ADR, + HW_ATL2_MIF_MCP_FINISHED_READ_MSK, + HW_ATL2_MIF_MCP_FINISHED_READ_SHIFT); +} diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh.h b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh.h new file mode 100644 index 000000000000..8ef8bd6b2534 --- /dev/null +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Atlantic Network Driver + * Copyright (C) 2020 Marvell International Ltd. + */ + +#ifndef HW_ATL2_LLH_H +#define HW_ATL2_LLH_H + +#include + +struct aq_hw_s; + +/* get data from firmware shared input buffer */ +void hw_atl2_mif_shared_buf_get(struct aq_hw_s *aq_hw, int offset, u32 *data, + int len); + +/* set data into firmware shared input buffer */ +void hw_atl2_mif_shared_buf_write(struct aq_hw_s *aq_hw, int offset, u32 *data, + int len); + +/* get data from firmware shared output buffer */ +void hw_atl2_mif_shared_buf_read(struct aq_hw_s *aq_hw, int offset, u32 *data, + int len); + +/* set host finished write shared buffer indication */ +void hw_atl2_mif_host_finished_write_set(struct aq_hw_s *aq_hw, u32 finish); + +/* get mcp finished read shared buffer indication */ +u32 hw_atl2_mif_mcp_finished_read_get(struct aq_hw_s *aq_hw); + +#endif /* HW_ATL2_LLH_H */ diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh_internal.h b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh_internal.h new file mode 100644 index 000000000000..835deb2d1950 --- /dev/null +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh_internal.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Atlantic Network Driver + * Copyright (C) 2020 Marvell International Ltd. + */ + +#ifndef HW_ATL2_LLH_INTERNAL_H +#define HW_ATL2_LLH_INTERNAL_H + +/* Register address for firmware shared input buffer */ +#define HW_ATL2_MIF_SHARED_BUFFER_IN_ADR(dword) (0x00012000U + (dword) * 0x4U) +/* Register address for firmware shared output buffer */ +#define HW_ATL2_MIF_SHARED_BUFFER_OUT_ADR(dword) (0x00013000U + (dword) * 0x4U) + +/* pif_host_finished_buf_wr_i Bitfield Definitions + * Preprocessor definitions for the bitfield "pif_host_finished_buf_wr_i". + * PORT="pif_host_finished_buf_wr_i" + */ +/* Register address for bitfield rpif_host_finished_buf_wr_i */ +#define HW_ATL2_MIF_HOST_FINISHED_WRITE_ADR 0x00000e00u +/* Bitmask for bitfield pif_host_finished_buf_wr_i */ +#define HW_ATL2_MIF_HOST_FINISHED_WRITE_MSK 0x00000001u +/* Inverted bitmask for bitfield pif_host_finished_buf_wr_i */ +#define HW_ATL2_MIF_HOST_FINISHED_WRITE_MSKN 0xFFFFFFFEu +/* Lower bit position of bitfield pif_host_finished_buf_wr_i */ +#define HW_ATL2_MIF_HOST_FINISHED_WRITE_SHIFT 0 +/* Width of bitfield pif_host_finished_buf_wr_i */ +#define HW_ATL2_MIF_HOST_FINISHED_WRITE_WIDTH 1 +/* Default value of bitfield pif_host_finished_buf_wr_i */ +#define HW_ATL2_MIF_HOST_FINISHED_WRITE_DEFAULT 0x0 + +/* pif_mcp_finished_buf_rd_i Bitfield Definitions + * Preprocessor definitions for the bitfield "pif_mcp_finished_buf_rd_i". + * PORT="pif_mcp_finished_buf_rd_i" + */ +/* Register address for bitfield pif_mcp_finished_buf_rd_i */ +#define HW_ATL2_MIF_MCP_FINISHED_READ_ADR 0x00000e04u +/* Bitmask for bitfield pif_mcp_finished_buf_rd_i */ +#define HW_ATL2_MIF_MCP_FINISHED_READ_MSK 0x00000001u +/* Inverted bitmask for bitfield pif_mcp_finished_buf_rd_i */ +#define HW_ATL2_MIF_MCP_FINISHED_READ_MSKN 0xFFFFFFFEu +/* Lower bit position of bitfield pif_mcp_finished_buf_rd_i */ +#define HW_ATL2_MIF_MCP_FINISHED_READ_SHIFT 0 +/* Width of bitfield pif_mcp_finished_buf_rd_i */ +#define HW_ATL2_MIF_MCP_FINISHED_READ_WIDTH 1 +/* Default value of bitfield pif_mcp_finished_buf_rd_i */ +#define HW_ATL2_MIF_MCP_FINISHED_READ_DEFAULT 0x0 + +#endif /* HW_ATL2_LLH_INTERNAL_H */ From patchwork Thu Apr 30 08:04:41 2020 Content-Type: text/plain; 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Thu, 30 Apr 2020 01:05:30 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 30 Apr 2020 01:05:29 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 30 Apr 2020 01:05:29 -0700 Received: from NN-LT0019.marvell.com (unknown [10.193.46.2]) by maili.marvell.com (Postfix) with ESMTP id 69B1C3F7041; Thu, 30 Apr 2020 01:05:27 -0700 (PDT) From: Igor Russkikh To: CC: "David S . Miller" , Mark Starovoytov , Igor Russkikh , "Dmitry Bogdanov" Subject: [PATCH v2 net-next 13/17] net: atlantic: add A2 RPF hw_ops Date: Thu, 30 Apr 2020 11:04:41 +0300 Message-ID: <20200430080445.1142-14-irusskikh@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200430080445.1142-1-irusskikh@marvell.com> References: <20200430080445.1142-1-irusskikh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.676 definitions=2020-04-30_02:2020-04-30,2020-04-30 signatures=0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This patch adds RPF-related hw_ops, which are needed for basic functionality. Signed-off-by: Igor Russkikh Co-developed-by: Dmitry Bogdanov Signed-off-by: Dmitry Bogdanov Signed-off-by: Mark Starovoytov --- .../aquantia/atlantic/hw_atl/hw_atl_utils.h | 2 + .../aquantia/atlantic/hw_atl2/hw_atl2.c | 208 ++++++++++++++++++ .../atlantic/hw_atl2/hw_atl2_internal.h | 49 +++++ 3 files changed, 259 insertions(+) diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h index 5513254642b3..5db57ea9a5bd 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h @@ -360,6 +360,8 @@ struct aq_rx_filter_vlan { u8 queue; }; +#define HW_ATL_VLAN_MAX_FILTERS 16U + struct aq_rx_filter_l2 { s8 queue; u8 location; diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2.c index 58c74a73b6cf..7dd5f9a1c505 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2.c +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2.c @@ -4,9 +4,17 @@ */ #include "aq_hw.h" +#include "aq_hw_utils.h" +#include "aq_nic.h" +#include "hw_atl/hw_atl_utils.h" +#include "hw_atl/hw_atl_llh.h" #include "hw_atl2_utils.h" +#include "hw_atl2_llh.h" #include "hw_atl2_internal.h" +static int hw_atl2_act_rslvr_table_set(struct aq_hw_s *self, u8 location, + u32 tag, u32 mask, u32 action); + #define DEFAULT_BOARD_BASIC_CAPABILITIES \ .is_64_dma = true, \ .msix_irqs = 8U, \ @@ -55,6 +63,11 @@ const struct aq_hw_caps_s hw_atl2_caps_aqc113 = { AQ_NIC_RATE_10M, }; +static u32 hw_atl2_sem_act_rslvr_get(struct aq_hw_s *self) +{ + return hw_atl_reg_glb_cpu_sem_get(self, HW_ATL2_FW_SM_ACT_RSLVR); +} + static int hw_atl2_hw_reset(struct aq_hw_s *self) { return -EOPNOTSUPP; @@ -78,6 +91,60 @@ static int hw_atl2_hw_offload_set(struct aq_hw_s *self, return -EOPNOTSUPP; } +static void hw_atl2_hw_new_rx_filter_vlan_promisc(struct aq_hw_s *self, + bool promisc) +{ + u16 off_action = (!promisc && + !hw_atl_rpfl2promiscuous_mode_en_get(self)) ? + HW_ATL2_ACTION_DROP : HW_ATL2_ACTION_DISABLE; + struct hw_atl2_priv *priv = (struct hw_atl2_priv *)self->priv; + u8 index; + + index = priv->art_base_index + HW_ATL2_RPF_VLAN_PROMISC_OFF_INDEX; + hw_atl2_act_rslvr_table_set(self, index, 0, + HW_ATL2_RPF_TAG_VLAN_MASK | + HW_ATL2_RPF_TAG_UNTAG_MASK, off_action); +} + +static void hw_atl2_hw_new_rx_filter_promisc(struct aq_hw_s *self, bool promisc) +{ + u16 off_action = promisc ? HW_ATL2_ACTION_DISABLE : HW_ATL2_ACTION_DROP; + struct hw_atl2_priv *priv = (struct hw_atl2_priv *)self->priv; + bool vlan_promisc_enable; + u8 index; + + index = priv->art_base_index + HW_ATL2_RPF_L2_PROMISC_OFF_INDEX; + hw_atl2_act_rslvr_table_set(self, index, 0, + HW_ATL2_RPF_TAG_UC_MASK | + HW_ATL2_RPF_TAG_ALLMC_MASK, + off_action); + + /* turn VLAN promisc mode too */ + vlan_promisc_enable = hw_atl_rpf_vlan_prom_mode_en_get(self); + hw_atl2_hw_new_rx_filter_vlan_promisc(self, promisc | + vlan_promisc_enable); +} + +static int hw_atl2_act_rslvr_table_set(struct aq_hw_s *self, u8 location, + u32 tag, u32 mask, u32 action) +{ + u32 val; + int err; + + err = readx_poll_timeout_atomic(hw_atl2_sem_act_rslvr_get, + self, val, val == 1, + 1, 10000U); + if (err) + return err; + + hw_atl2_rpf_act_rslvr_record_set(self, location, tag, mask, + action); + + hw_atl_reg_glb_cpu_sem_set(self, 1, HW_ATL2_FW_SM_ACT_RSLVR); + + return err; +} + static int hw_atl2_hw_mac_addr_set(struct aq_hw_s *self, u8 *mac_addr) { return -EOPNOTSUPP; @@ -170,6 +237,88 @@ static int hw_atl2_hw_irq_read(struct aq_hw_s *self, u64 *mask) return -EOPNOTSUPP; } +#define IS_FILTER_ENABLED(_F_) ((packet_filter & (_F_)) ? 1U : 0U) + +static int hw_atl2_hw_packet_filter_set(struct aq_hw_s *self, + unsigned int packet_filter) +{ + struct aq_nic_cfg_s *cfg = self->aq_nic_cfg; + u32 vlan_promisc; + u32 l2_promisc; + unsigned int i; + + l2_promisc = IS_FILTER_ENABLED(IFF_PROMISC) || + !!(cfg->priv_flags & BIT(AQ_HW_LOOPBACK_DMA_NET)); + vlan_promisc = l2_promisc || cfg->is_vlan_force_promisc; + + hw_atl_rpfl2promiscuous_mode_en_set(self, l2_promisc); + + hw_atl_rpf_vlan_prom_mode_en_set(self, vlan_promisc); + + hw_atl2_hw_new_rx_filter_promisc(self, IS_FILTER_ENABLED(IFF_PROMISC)); + + hw_atl_rpfl2multicast_flr_en_set(self, + IS_FILTER_ENABLED(IFF_ALLMULTI) && + IS_FILTER_ENABLED(IFF_MULTICAST), 0); + + hw_atl_rpfl2_accept_all_mc_packets_set(self, + IS_FILTER_ENABLED(IFF_ALLMULTI) && + IS_FILTER_ENABLED(IFF_MULTICAST)); + + hw_atl_rpfl2broadcast_en_set(self, IS_FILTER_ENABLED(IFF_BROADCAST)); + + for (i = HW_ATL2_MAC_MIN; i < HW_ATL2_MAC_MAX; ++i) + hw_atl_rpfl2_uc_flr_en_set(self, + (cfg->is_mc_list_enabled && + (i <= cfg->mc_list_count)) ? + 1U : 0U, i); + + return aq_hw_err_from_flags(self); +} + +#undef IS_FILTER_ENABLED + +static int hw_atl2_hw_multicast_list_set(struct aq_hw_s *self, + u8 ar_mac + [AQ_HW_MULTICAST_ADDRESS_MAX] + [ETH_ALEN], + u32 count) +{ + struct aq_nic_cfg_s *cfg = self->aq_nic_cfg; + int err = 0; + + if (count > (HW_ATL2_MAC_MAX - HW_ATL2_MAC_MIN)) { + err = -EBADRQC; + goto err_exit; + } + for (cfg->mc_list_count = 0U; + cfg->mc_list_count < count; + ++cfg->mc_list_count) { + u32 i = cfg->mc_list_count; + u32 h = (ar_mac[i][0] << 8) | (ar_mac[i][1]); + u32 l = (ar_mac[i][2] << 24) | (ar_mac[i][3] << 16) | + (ar_mac[i][4] << 8) | ar_mac[i][5]; + + hw_atl_rpfl2_uc_flr_en_set(self, 0U, HW_ATL2_MAC_MIN + i); + + hw_atl_rpfl2unicast_dest_addresslsw_set(self, l, + HW_ATL2_MAC_MIN + i); + + hw_atl_rpfl2unicast_dest_addressmsw_set(self, h, + HW_ATL2_MAC_MIN + i); + + hw_atl2_rpfl2_uc_flr_tag_set(self, 1, HW_ATL2_MAC_MIN + i); + + hw_atl_rpfl2_uc_flr_en_set(self, (cfg->is_mc_list_enabled), + HW_ATL2_MAC_MIN + i); + } + + err = aq_hw_err_from_flags(self); + +err_exit: + return err; +} + static int hw_atl2_hw_interrupt_moderation_set(struct aq_hw_s *self) { return -EOPNOTSUPP; @@ -195,6 +344,61 @@ static struct aq_stats_s *hw_atl2_utils_get_hw_stats(struct aq_hw_s *self) return &self->curr_stats; } +static int hw_atl2_hw_vlan_set(struct aq_hw_s *self, + struct aq_rx_filter_vlan *aq_vlans) +{ + struct hw_atl2_priv *priv = (struct hw_atl2_priv *)self->priv; + u32 queue; + u8 index; + int i; + + hw_atl_rpf_vlan_prom_mode_en_set(self, 1U); + + for (i = 0; i < HW_ATL_VLAN_MAX_FILTERS; i++) { + queue = HW_ATL2_ACTION_ASSIGN_QUEUE(aq_vlans[i].queue); + + hw_atl_rpf_vlan_flr_en_set(self, 0U, i); + hw_atl_rpf_vlan_rxq_en_flr_set(self, 0U, i); + index = priv->art_base_index + HW_ATL2_RPF_VLAN_USER_INDEX + i; + hw_atl2_act_rslvr_table_set(self, index, 0, 0, + HW_ATL2_ACTION_DISABLE); + if (aq_vlans[i].enable) { + hw_atl_rpf_vlan_id_flr_set(self, + aq_vlans[i].vlan_id, i); + hw_atl_rpf_vlan_flr_act_set(self, 1U, i); + hw_atl_rpf_vlan_flr_en_set(self, 1U, i); + + if (aq_vlans[i].queue != 0xFF) { + hw_atl_rpf_vlan_rxq_flr_set(self, + aq_vlans[i].queue, + i); + hw_atl_rpf_vlan_rxq_en_flr_set(self, 1U, i); + + hw_atl2_rpf_vlan_flr_tag_set(self, i + 2, i); + + index = priv->art_base_index + + HW_ATL2_RPF_VLAN_USER_INDEX + i; + hw_atl2_act_rslvr_table_set(self, index, + (i + 2) << HW_ATL2_RPF_TAG_VLAN_OFFSET, + HW_ATL2_RPF_TAG_VLAN_MASK, queue); + } else { + hw_atl2_rpf_vlan_flr_tag_set(self, 1, i); + } + } + } + + return aq_hw_err_from_flags(self); +} + +static int hw_atl2_hw_vlan_ctrl(struct aq_hw_s *self, bool enable) +{ + /* set promisc in case of disabing the vlan filter */ + hw_atl_rpf_vlan_prom_mode_en_set(self, !enable); + hw_atl2_hw_new_rx_filter_vlan_promisc(self, !enable); + + return aq_hw_err_from_flags(self); +} + const struct aq_hw_ops hw_atl2_ops = { .hw_set_mac_address = hw_atl2_hw_mac_addr_set, .hw_init = hw_atl2_hw_init, @@ -218,6 +422,10 @@ const struct aq_hw_ops hw_atl2_ops = { .hw_ring_rx_init = hw_atl2_hw_ring_rx_init, .hw_ring_tx_init = hw_atl2_hw_ring_tx_init, + .hw_packet_filter_set = hw_atl2_hw_packet_filter_set, + .hw_filter_vlan_set = hw_atl2_hw_vlan_set, + .hw_filter_vlan_ctrl = hw_atl2_hw_vlan_ctrl, + .hw_multicast_list_set = hw_atl2_hw_multicast_list_set, .hw_interrupt_moderation_set = hw_atl2_hw_interrupt_moderation_set, .hw_rss_set = hw_atl2_hw_rss_set, .hw_rss_hash_set = hw_atl2_hw_rss_hash_set, diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_internal.h b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_internal.h index f82058484332..dccc89df2223 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_internal.h +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_internal.h @@ -18,6 +18,10 @@ #define HW_ATL2_TXD_SIZE (16U) #define HW_ATL2_RXD_SIZE (16U) +#define HW_ATL2_MAC_UC 0U +#define HW_ATL2_MAC_MIN 1U +#define HW_ATL2_MAC_MAX 38U + #define HW_ATL2_TC_MAX 1U #define HW_ATL2_RSS_MAX 8U @@ -29,6 +33,51 @@ #define HW_ATL2_MAX_RXD 8184U #define HW_ATL2_MAX_TXD 8184U +#define HW_ATL2_FW_SM_ACT_RSLVR 0x3U + +#define HW_ATL2_RPF_TAG_UC_OFFSET 0x0 +#define HW_ATL2_RPF_TAG_ALLMC_OFFSET 0x6 +#define HW_ATL2_RPF_TAG_ET_OFFSET 0x7 +#define HW_ATL2_RPF_TAG_VLAN_OFFSET 0xA +#define HW_ATL2_RPF_TAG_UNTAG_OFFSET 0xE +#define HW_ATL2_RPF_TAG_L3_V4_OFFSET 0xF +#define HW_ATL2_RPF_TAG_L3_V6_OFFSET 0x12 +#define HW_ATL2_RPF_TAG_L4_OFFSET 0x15 +#define HW_ATL2_RPF_TAG_L4_FLEX_OFFSET 0x18 +#define HW_ATL2_RPF_TAG_FLEX_OFFSET 0x1B +#define HW_ATL2_RPF_TAG_PCP_OFFSET 0x1D + +#define HW_ATL2_RPF_TAG_UC_MASK (0x0000003F << HW_ATL2_RPF_TAG_UC_OFFSET) +#define HW_ATL2_RPF_TAG_ALLMC_MASK (0x00000001 << HW_ATL2_RPF_TAG_ALLMC_OFFSET) +#define HW_ATL2_RPF_TAG_UNTAG_MASK (0x00000001 << HW_ATL2_RPF_TAG_UNTAG_OFFSET) +#define HW_ATL2_RPF_TAG_VLAN_MASK (0x0000000F << HW_ATL2_RPF_TAG_VLAN_OFFSET) +#define HW_ATL2_RPF_TAG_ET_MASK (0x00000007 << HW_ATL2_RPF_TAG_ET_OFFSET) +#define HW_ATL2_RPF_TAG_L3_V4_MASK (0x00000007 << HW_ATL2_RPF_TAG_L3_V4_OFFSET) +#define HW_ATL2_RPF_TAG_L3_V6_MASK (0x00000007 << HW_ATL2_RPF_TAG_L3_V6_OFFSET) +#define HW_ATL2_RPF_TAG_L4_MASK (0x00000007 << HW_ATL2_RPF_TAG_L4_OFFSET) +#define HW_ATL2_RPF_TAG_PCP_MASK (0x00000007 << HW_ATL2_RPF_TAG_PCP_OFFSET) + +enum HW_ATL2_RPF_ART_INDEX { + HW_ATL2_RPF_L2_PROMISC_OFF_INDEX, + HW_ATL2_RPF_VLAN_PROMISC_OFF_INDEX, + HW_ATL2_RPF_L3L4_USER_INDEX = 8, + HW_ATL2_RPF_ET_PCP_USER_INDEX = HW_ATL2_RPF_L3L4_USER_INDEX + 16, + HW_ATL2_RPF_VLAN_USER_INDEX = HW_ATL2_RPF_ET_PCP_USER_INDEX + 16, + HW_ATL2_RPF_PCP_TO_TC_INDEX = HW_ATL2_RPF_VLAN_USER_INDEX + + HW_ATL_VLAN_MAX_FILTERS, +}; + +#define HW_ATL2_ACTION(ACTION, RSS, INDEX, VALID) \ + ((((ACTION) & 0x3U) << 8) | \ + (((RSS) & 0x1U) << 7) | \ + (((INDEX) & 0x3FU) << 2) | \ + (((VALID) & 0x1U) << 0)) + +#define HW_ATL2_ACTION_DROP HW_ATL2_ACTION(0, 0, 0, 1) +#define HW_ATL2_ACTION_DISABLE HW_ATL2_ACTION(0, 0, 0, 0) +#define HW_ATL2_ACTION_ASSIGN_QUEUE(QUEUE) HW_ATL2_ACTION(1, 0, (QUEUE), 1) +#define HW_ATL2_ACTION_ASSIGN_TC(TC) HW_ATL2_ACTION(1, 1, (TC), 1) + struct hw_atl2_priv { struct statistics_s last_stats; unsigned int art_base_index; From patchwork Thu Apr 30 08:04:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 220249 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.5 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19BD2C83001 for ; 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Thu, 30 Apr 2020 01:05:32 -0700 (PDT) From: Igor Russkikh To: CC: "David S . Miller" , Mark Starovoytov , Dmitry Bogdanov , "Igor Russkikh" Subject: [PATCH v2 net-next 15/17] net: atlantic: common functions needed for basic A2 init/deinit hw_ops Date: Thu, 30 Apr 2020 11:04:43 +0300 Message-ID: <20200430080445.1142-16-irusskikh@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200430080445.1142-1-irusskikh@marvell.com> References: <20200430080445.1142-1-irusskikh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.676 definitions=2020-04-30_02:2020-04-30,2020-04-30 signatures=0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Dmitry Bogdanov This patch adds common functions (mostly FW-related), which are needed for basic A2 HW initialization / deinitialization. Signed-off-by: Dmitry Bogdanov Co-developed-by: Igor Russkikh Signed-off-by: Igor Russkikh Signed-off-by: Mark Starovoytov --- .../net/ethernet/aquantia/atlantic/Makefile | 1 + .../aquantia/atlantic/hw_atl/hw_atl_utils.c | 3 +- .../aquantia/atlantic/hw_atl/hw_atl_utils.h | 2 + .../aquantia/atlantic/hw_atl2/hw_atl2_utils.c | 139 ++++++++++++++++++ .../aquantia/atlantic/hw_atl2/hw_atl2_utils.h | 8 + .../atlantic/hw_atl2/hw_atl2_utils_fw.c | 12 ++ 6 files changed, 163 insertions(+), 2 deletions(-) create mode 100644 drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_utils.c diff --git a/drivers/net/ethernet/aquantia/atlantic/Makefile b/drivers/net/ethernet/aquantia/atlantic/Makefile index 23f0e5b5fcdb..130a105d03f3 100644 --- a/drivers/net/ethernet/aquantia/atlantic/Makefile +++ b/drivers/net/ethernet/aquantia/atlantic/Makefile @@ -26,6 +26,7 @@ atlantic-objs := aq_main.o \ hw_atl/hw_atl_utils_fw2x.o \ hw_atl/hw_atl_llh.o \ hw_atl2/hw_atl2.o \ + hw_atl2/hw_atl2_utils.o \ hw_atl2/hw_atl2_utils_fw.o \ hw_atl2/hw_atl2_llh.o \ macsec/macsec_api.o diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c index 20655a2170cc..1100d40a0302 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c @@ -53,7 +53,6 @@ enum mcp_area { MCP_AREA_SETTINGS = 0x20000000, }; -static int hw_atl_utils_ver_match(u32 ver_expected, u32 ver_actual); static int hw_atl_utils_mpi_set_state(struct aq_hw_s *self, enum hal_atl_utils_fw_state_e state); static u32 hw_atl_utils_get_mpi_mbox_tid(struct aq_hw_s *self); @@ -434,7 +433,7 @@ int hw_atl_write_fwsettings_dwords(struct aq_hw_s *self, u32 offset, u32 *p, p, cnt, MCP_AREA_SETTINGS); } -static int hw_atl_utils_ver_match(u32 ver_expected, u32 ver_actual) +int hw_atl_utils_ver_match(u32 ver_expected, u32 ver_actual) { const u32 dw_major_mask = 0xff000000U; const u32 dw_minor_mask = 0x00ffffffU; diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h index 5db57ea9a5bd..99c1b6644ec3 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h @@ -634,6 +634,8 @@ int hw_atl_utils_fw_rpc_call(struct aq_hw_s *self, unsigned int rpc_size); int hw_atl_utils_fw_rpc_wait(struct aq_hw_s *self, struct hw_atl_utils_fw_rpc **rpc); +int hw_atl_utils_ver_match(u32 ver_expected, u32 ver_actual); + extern const struct aq_fw_ops aq_fw_1x_ops; extern const struct aq_fw_ops aq_fw_2x_ops; diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_utils.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_utils.c new file mode 100644 index 000000000000..85ccc9a011a0 --- /dev/null +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_utils.c @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Atlantic Network Driver + * Copyright (C) 2020 Marvell International Ltd. + */ + +#include + +#include "aq_hw_utils.h" +#include "hw_atl/hw_atl_utils.h" +#include "hw_atl2_utils.h" +#include "hw_atl2_llh.h" +#include "hw_atl2_llh_internal.h" + +#define HW_ATL2_FW_VER_1X 0x01000000U + +#define AQ_A2_BOOT_STARTED BIT(0x18) +#define AQ_A2_CRASH_INIT BIT(0x1B) +#define AQ_A2_BOOT_CODE_FAILED BIT(0x1C) +#define AQ_A2_FW_INIT_FAILED BIT(0x1D) +#define AQ_A2_FW_INIT_COMP_SUCCESS BIT(0x1F) + +#define AQ_A2_FW_BOOT_FAILED_MASK (AQ_A2_CRASH_INIT | \ + AQ_A2_BOOT_CODE_FAILED | \ + AQ_A2_FW_INIT_FAILED) +#define AQ_A2_FW_BOOT_COMPLETE_MASK (AQ_A2_FW_BOOT_FAILED_MASK | \ + AQ_A2_FW_INIT_COMP_SUCCESS) + +#define AQ_A2_FW_BOOT_REQ_REBOOT BIT(0x0) +#define AQ_A2_FW_BOOT_REQ_HOST_BOOT BIT(0x8) +#define AQ_A2_FW_BOOT_REQ_MAC_FAST_BOOT BIT(0xA) +#define AQ_A2_FW_BOOT_REQ_PHY_FAST_BOOT BIT(0xB) + +int hw_atl2_utils_initfw(struct aq_hw_s *self, const struct aq_fw_ops **fw_ops) +{ + int err; + + self->fw_ver_actual = hw_atl2_utils_get_fw_version(self); + + if (hw_atl_utils_ver_match(HW_ATL2_FW_VER_1X, + self->fw_ver_actual) == 0) { + *fw_ops = &aq_a2_fw_ops; + } else { + aq_pr_err("Bad FW version detected: %x, but continue\n", + self->fw_ver_actual); + *fw_ops = &aq_a2_fw_ops; + } + aq_pr_trace("Detect ATL2FW %x\n", self->fw_ver_actual); + self->aq_fw_ops = *fw_ops; + err = self->aq_fw_ops->init(self); + + self->chip_features |= ATL_HW_CHIP_ANTIGUA; + + return err; +} + +static bool hw_atl2_mcp_boot_complete(struct aq_hw_s *self) +{ + u32 rbl_status; + + rbl_status = hw_atl2_mif_mcp_boot_reg_get(self); + if (rbl_status & AQ_A2_FW_BOOT_COMPLETE_MASK) + return true; + + /* Host boot requested */ + if (hw_atl2_mif_host_req_int_get(self) & HW_ATL2_MCP_HOST_REQ_INT_READY) + return true; + + return false; +} + +int hw_atl2_utils_soft_reset(struct aq_hw_s *self) +{ + bool rbl_complete = false; + u32 rbl_status = 0; + u32 rbl_request; + int err; + + err = readx_poll_timeout_atomic(hw_atl2_mif_mcp_boot_reg_get, self, + rbl_status, + ((rbl_status & AQ_A2_BOOT_STARTED) && + (rbl_status != 0xFFFFFFFFu)), + 10, 500000); + if (err) + aq_pr_trace("Boot code probably hanged, reboot anyway"); + + hw_atl2_mif_host_req_int_clr(self, 0x01); + rbl_request = AQ_A2_FW_BOOT_REQ_REBOOT; +#ifdef AQ_CFG_FAST_START + rbl_request |= AQ_A2_FW_BOOT_REQ_MAC_FAST_BOOT; +#endif + hw_atl2_mif_mcp_boot_reg_set(self, rbl_request); + + /* Wait for RBL boot */ + err = readx_poll_timeout_atomic(hw_atl2_mif_mcp_boot_reg_get, self, + rbl_status, + ((rbl_status & AQ_A2_BOOT_STARTED) && + (rbl_status != 0xFFFFFFFFu)), + 10, 200000); + if (err) { + aq_pr_err("Boot code hanged"); + goto err_exit; + } + + err = readx_poll_timeout_atomic(hw_atl2_mcp_boot_complete, self, + rbl_complete, + rbl_complete, + 10, 2000000); + + if (err) { + aq_pr_err("FW Restart timed out"); + goto err_exit; + } + + rbl_status = hw_atl2_mif_mcp_boot_reg_get(self); + + if (rbl_status & AQ_A2_FW_BOOT_FAILED_MASK) { + err = -EIO; + aq_pr_err("FW Restart failed"); + goto err_exit; + } + + if (hw_atl2_mif_host_req_int_get(self) & + HW_ATL2_MCP_HOST_REQ_INT_READY) { + err = -EIO; + aq_pr_err("No FW detected. Dynamic FW load not implemented"); + goto err_exit; + } + + if (self->aq_fw_ops) { + err = self->aq_fw_ops->init(self); + if (err) { + aq_pr_err("FW Init failed"); + goto err_exit; + } + } + +err_exit: + return err; +} diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_utils.h b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_utils.h index 5421fbed3db5..2317dd8459d0 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_utils.h +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_utils.h @@ -6,6 +6,8 @@ #ifndef HW_ATL2_UTILS_H #define HW_ATL2_UTILS_H +#include "aq_hw.h" + /* F W A P I */ struct link_options_s { @@ -590,6 +592,12 @@ struct fw_interface_out { #define AQ_HOST_MODE_LOW_POWER 3U #define AQ_HOST_MODE_SHUTDOWN 4U +int hw_atl2_utils_initfw(struct aq_hw_s *self, const struct aq_fw_ops **fw_ops); + +int hw_atl2_utils_soft_reset(struct aq_hw_s *self); + +u32 hw_atl2_utils_get_fw_version(struct aq_hw_s *self); + int hw_atl2_utils_get_action_resolve_table_caps(struct aq_hw_s *self, u8 *base_index, u8 *count); diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_utils_fw.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_utils_fw.c index c3e0e5575810..f5fb4b11f51a 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_utils_fw.c +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_utils_fw.c @@ -301,6 +301,18 @@ static int aq_a2_fw_renegotiate(struct aq_hw_s *self) return err; } +u32 hw_atl2_utils_get_fw_version(struct aq_hw_s *self) +{ + struct version_s version; + + hw_atl2_shared_buffer_read_safe(self, version, &version); + + /* A2 FW version is stored in reverse order */ + return version.mac.major << 24 | + version.mac.minor << 16 | + version.mac.build; +} + int hw_atl2_utils_get_action_resolve_table_caps(struct aq_hw_s *self, u8 *base_index, u8 *count) { From patchwork Thu Apr 30 08:04:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 220248 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.5 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 17A5EC83009 for ; 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Thu, 30 Apr 2020 01:05:39 -0700 Received: from NN-LT0019.marvell.com (unknown [10.193.46.2]) by maili.marvell.com (Postfix) with ESMTP id A349A3F7041; Thu, 30 Apr 2020 01:05:37 -0700 (PDT) From: Igor Russkikh To: CC: "David S . Miller" , Mark Starovoytov , Igor Russkikh Subject: [PATCH v2 net-next 17/17] net: atlantic: A2 ingress / egress hw configuration Date: Thu, 30 Apr 2020 11:04:45 +0300 Message-ID: <20200430080445.1142-18-irusskikh@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200430080445.1142-1-irusskikh@marvell.com> References: <20200430080445.1142-1-irusskikh@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.676 definitions=2020-04-30_02:2020-04-30,2020-04-30 signatures=0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Chip generations are mostly compatible register-wise, but there are still some differences. Therefore we've made some of first generation (A1) code non-static to re-use it where possible. Some pieces are A2 specific, in which case we redefine/extend such APIs. Signed-off-by: Igor Russkikh Signed-off-by: Mark Starovoytov --- .../aquantia/atlantic/hw_atl/hw_atl_b0.c | 54 +++--- .../aquantia/atlantic/hw_atl/hw_atl_b0.h | 23 +++ .../aquantia/atlantic/hw_atl2/hw_atl2.c | 176 ++++++++++-------- .../atlantic/hw_atl2/hw_atl2_internal.h | 3 + .../aquantia/atlantic/hw_atl2/hw_atl2_llh.c | 8 + .../aquantia/atlantic/hw_atl2/hw_atl2_llh.h | 5 + .../atlantic/hw_atl2/hw_atl2_llh_internal.h | 8 + 7 files changed, 172 insertions(+), 105 deletions(-) diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c index c46199f14ec4..cbb7a00d61b4 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c @@ -251,9 +251,10 @@ int hw_atl_b0_hw_rss_set(struct aq_hw_s *self, return err; } -static int hw_atl_b0_hw_offload_set(struct aq_hw_s *self, - struct aq_nic_cfg_s *aq_nic_cfg) +int hw_atl_b0_hw_offload_set(struct aq_hw_s *self, + struct aq_nic_cfg_s *aq_nic_cfg) { + u64 rxcsum = !!(aq_nic_cfg->features & NETIF_F_RXCSUM); unsigned int i; /* TX checksums offloads*/ @@ -261,10 +262,8 @@ static int hw_atl_b0_hw_offload_set(struct aq_hw_s *self, hw_atl_tpo_tcp_udp_crc_offload_en_set(self, 1); /* RX checksums offloads*/ - hw_atl_rpo_ipv4header_crc_offload_en_set(self, !!(aq_nic_cfg->features & - NETIF_F_RXCSUM)); - hw_atl_rpo_tcp_udp_crc_offload_en_set(self, !!(aq_nic_cfg->features & - NETIF_F_RXCSUM)); + hw_atl_rpo_ipv4header_crc_offload_en_set(self, rxcsum); + hw_atl_rpo_tcp_udp_crc_offload_en_set(self, rxcsum); /* LSO offloads*/ hw_atl_tdm_large_send_offload_en_set(self, 0xFFFFFFFFU); @@ -272,7 +271,7 @@ static int hw_atl_b0_hw_offload_set(struct aq_hw_s *self, /* Outer VLAN tag offload */ hw_atl_rpo_outer_vlan_tag_mode_set(self, 1U); -/* LRO offloads */ + /* LRO offloads */ { unsigned int val = (8U < HW_ATL_B0_LRO_RXD_MAX) ? 0x3U : ((4U < HW_ATL_B0_LRO_RXD_MAX) ? 0x2U : @@ -384,7 +383,7 @@ static int hw_atl_b0_hw_init_rx_path(struct aq_hw_s *self) return aq_hw_err_from_flags(self); } -static int hw_atl_b0_hw_mac_addr_set(struct aq_hw_s *self, u8 *mac_addr) +int hw_atl_b0_hw_mac_addr_set(struct aq_hw_s *self, u8 *mac_addr) { unsigned int h = 0U; unsigned int l = 0U; @@ -479,16 +478,14 @@ static int hw_atl_b0_hw_init(struct aq_hw_s *self, u8 *mac_addr) return err; } -static int hw_atl_b0_hw_ring_tx_start(struct aq_hw_s *self, - struct aq_ring_s *ring) +int hw_atl_b0_hw_ring_tx_start(struct aq_hw_s *self, struct aq_ring_s *ring) { hw_atl_tdm_tx_desc_en_set(self, 1, ring->idx); return aq_hw_err_from_flags(self); } -static int hw_atl_b0_hw_ring_rx_start(struct aq_hw_s *self, - struct aq_ring_s *ring) +int hw_atl_b0_hw_ring_rx_start(struct aq_hw_s *self, struct aq_ring_s *ring) { hw_atl_rdm_rx_desc_en_set(self, 1, ring->idx); @@ -511,9 +508,8 @@ static int hw_atl_b0_hw_tx_ring_tail_update(struct aq_hw_s *self, return 0; } -static int hw_atl_b0_hw_ring_tx_xmit(struct aq_hw_s *self, - struct aq_ring_s *ring, - unsigned int frags) +int hw_atl_b0_hw_ring_tx_xmit(struct aq_hw_s *self, struct aq_ring_s *ring, + unsigned int frags) { struct aq_ring_buff_s *buff = NULL; struct hw_atl_txd_s *txd = NULL; @@ -600,9 +596,8 @@ static int hw_atl_b0_hw_ring_tx_xmit(struct aq_hw_s *self, return aq_hw_err_from_flags(self); } -static int hw_atl_b0_hw_ring_rx_init(struct aq_hw_s *self, - struct aq_ring_s *aq_ring, - struct aq_ring_param_s *aq_ring_param) +int hw_atl_b0_hw_ring_rx_init(struct aq_hw_s *self, struct aq_ring_s *aq_ring, + struct aq_ring_param_s *aq_ring_param) { u32 dma_desc_addr_msw = (u32)(((u64)aq_ring->dx_ring_pa) >> 32); u32 vlan_rx_stripping = self->aq_nic_cfg->is_vlan_rx_strip; @@ -643,9 +638,8 @@ static int hw_atl_b0_hw_ring_rx_init(struct aq_hw_s *self, return aq_hw_err_from_flags(self); } -static int hw_atl_b0_hw_ring_tx_init(struct aq_hw_s *self, - struct aq_ring_s *aq_ring, - struct aq_ring_param_s *aq_ring_param) +int hw_atl_b0_hw_ring_tx_init(struct aq_hw_s *self, struct aq_ring_s *aq_ring, + struct aq_ring_param_s *aq_ring_param) { u32 dma_desc_msw_addr = (u32)(((u64)aq_ring->dx_ring_pa) >> 32); u32 dma_desc_lsw_addr = (u32)aq_ring->dx_ring_pa; @@ -673,9 +667,8 @@ static int hw_atl_b0_hw_ring_tx_init(struct aq_hw_s *self, return aq_hw_err_from_flags(self); } -static int hw_atl_b0_hw_ring_rx_fill(struct aq_hw_s *self, - struct aq_ring_s *ring, - unsigned int sw_tail_old) +int hw_atl_b0_hw_ring_rx_fill(struct aq_hw_s *self, struct aq_ring_s *ring, + unsigned int sw_tail_old) { for (; sw_tail_old != ring->sw_tail; sw_tail_old = aq_ring_next_dx(ring, sw_tail_old)) { @@ -734,8 +727,8 @@ static int hw_atl_b0_hw_ring_hwts_rx_receive(struct aq_hw_s *self, return aq_hw_err_from_flags(self); } -static int hw_atl_b0_hw_ring_tx_head_update(struct aq_hw_s *self, - struct aq_ring_s *ring) +int hw_atl_b0_hw_ring_tx_head_update(struct aq_hw_s *self, + struct aq_ring_s *ring) { unsigned int hw_head_; int err = 0; @@ -753,8 +746,7 @@ static int hw_atl_b0_hw_ring_tx_head_update(struct aq_hw_s *self, return err; } -static int hw_atl_b0_hw_ring_rx_receive(struct aq_hw_s *self, - struct aq_ring_s *ring) +int hw_atl_b0_hw_ring_rx_receive(struct aq_hw_s *self, struct aq_ring_s *ring) { for (; ring->hw_head != ring->sw_tail; ring->hw_head = aq_ring_next_dx(ring, ring->hw_head)) { @@ -1071,16 +1063,14 @@ static int hw_atl_b0_hw_stop(struct aq_hw_s *self) return err; } -static int hw_atl_b0_hw_ring_tx_stop(struct aq_hw_s *self, - struct aq_ring_s *ring) +int hw_atl_b0_hw_ring_tx_stop(struct aq_hw_s *self, struct aq_ring_s *ring) { hw_atl_tdm_tx_desc_en_set(self, 0U, ring->idx); return aq_hw_err_from_flags(self); } -static int hw_atl_b0_hw_ring_rx_stop(struct aq_hw_s *self, - struct aq_ring_s *ring) +int hw_atl_b0_hw_ring_rx_stop(struct aq_hw_s *self, struct aq_ring_s *ring) { hw_atl_rdm_rx_desc_en_set(self, 0U, ring->idx); diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.h b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.h index ea7136b06b32..f5091d79ab43 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.h +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.h @@ -37,6 +37,29 @@ int hw_atl_b0_hw_rss_hash_set(struct aq_hw_s *self, struct aq_rss_parameters *rss_params); int hw_atl_b0_hw_rss_set(struct aq_hw_s *self, struct aq_rss_parameters *rss_params); +int hw_atl_b0_hw_offload_set(struct aq_hw_s *self, + struct aq_nic_cfg_s *aq_nic_cfg); + +int hw_atl_b0_hw_ring_tx_start(struct aq_hw_s *self, struct aq_ring_s *ring); +int hw_atl_b0_hw_ring_rx_start(struct aq_hw_s *self, struct aq_ring_s *ring); + +int hw_atl_b0_hw_ring_rx_init(struct aq_hw_s *self, struct aq_ring_s *aq_ring, + struct aq_ring_param_s *aq_ring_param); +int hw_atl_b0_hw_ring_rx_fill(struct aq_hw_s *self, struct aq_ring_s *ring, + unsigned int sw_tail_old); +int hw_atl_b0_hw_ring_rx_receive(struct aq_hw_s *self, struct aq_ring_s *ring); + +int hw_atl_b0_hw_ring_tx_init(struct aq_hw_s *self, struct aq_ring_s *aq_ring, + struct aq_ring_param_s *aq_ring_param); +int hw_atl_b0_hw_ring_tx_xmit(struct aq_hw_s *self, struct aq_ring_s *ring, + unsigned int frags); +int hw_atl_b0_hw_ring_tx_head_update(struct aq_hw_s *self, + struct aq_ring_s *ring); + +int hw_atl_b0_hw_ring_tx_stop(struct aq_hw_s *self, struct aq_ring_s *ring); +int hw_atl_b0_hw_ring_rx_stop(struct aq_hw_s *self, struct aq_ring_s *ring); + +int hw_atl_b0_hw_mac_addr_set(struct aq_hw_s *self, u8 *mac_addr); int hw_atl_b0_hw_start(struct aq_hw_s *self); diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2.c index ad0b22b3c01f..04d194f754fa 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2.c +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2.c @@ -5,6 +5,7 @@ #include "aq_hw.h" #include "aq_hw_utils.h" +#include "aq_ring.h" #include "aq_nic.h" #include "hw_atl/hw_atl_b0.h" #include "hw_atl/hw_atl_utils.h" @@ -174,12 +175,6 @@ static int hw_atl2_hw_rss_set(struct aq_hw_s *self, return hw_atl_b0_hw_rss_set(self, rss_params); } -static int hw_atl2_hw_offload_set(struct aq_hw_s *self, - struct aq_nic_cfg_s *aq_nic_cfg) -{ - return -EOPNOTSUPP; -} - static int hw_atl2_hw_init_tx_path(struct aq_hw_s *self) { /* Tx TC/RSS number config */ @@ -359,11 +354,6 @@ static int hw_atl2_hw_init_rx_path(struct aq_hw_s *self) return aq_hw_err_from_flags(self); } -static int hw_atl2_hw_mac_addr_set(struct aq_hw_s *self, u8 *mac_addr) -{ - return -EOPNOTSUPP; -} - static int hw_atl2_hw_init(struct aq_hw_s *self, u8 *mac_addr) { static u32 aq_hw_atl2_igcr_table_[4][2] = { @@ -390,7 +380,7 @@ static int hw_atl2_hw_init(struct aq_hw_s *self, u8 *mac_addr) hw_atl2_hw_init_tx_path(self); hw_atl2_hw_init_rx_path(self); - hw_atl2_hw_mac_addr_set(self, mac_addr); + hw_atl_b0_hw_mac_addr_set(self, mac_addr); self->aq_fw_ops->set_link_speed(self, aq_nic_cfg->link_speed_msk); self->aq_fw_ops->set_state(self, MPI_INIT); @@ -424,61 +414,24 @@ static int hw_atl2_hw_init(struct aq_hw_s *self, u8 *mac_addr) ((HW_ATL2_ERR_INT << 0x10) | (1U << 0x17)), 0U); - hw_atl2_hw_offload_set(self, aq_nic_cfg); + hw_atl_b0_hw_offload_set(self, aq_nic_cfg); err_exit: return err; } -static int hw_atl2_hw_ring_tx_start(struct aq_hw_s *self, - struct aq_ring_s *ring) -{ - return -EOPNOTSUPP; -} - -static int hw_atl2_hw_ring_rx_start(struct aq_hw_s *self, - struct aq_ring_s *ring) -{ - return -EOPNOTSUPP; -} - -static int hw_atl2_hw_ring_tx_xmit(struct aq_hw_s *self, - struct aq_ring_s *ring, - unsigned int frags) -{ - return -EOPNOTSUPP; -} - static int hw_atl2_hw_ring_rx_init(struct aq_hw_s *self, struct aq_ring_s *aq_ring, struct aq_ring_param_s *aq_ring_param) { - return -EOPNOTSUPP; + return hw_atl_b0_hw_ring_rx_init(self, aq_ring, aq_ring_param); } static int hw_atl2_hw_ring_tx_init(struct aq_hw_s *self, struct aq_ring_s *aq_ring, struct aq_ring_param_s *aq_ring_param) { - return -EOPNOTSUPP; -} - -static int hw_atl2_hw_ring_rx_fill(struct aq_hw_s *self, struct aq_ring_s *ring, - unsigned int sw_tail_old) -{ - return -EOPNOTSUPP; -} - -static int hw_atl2_hw_ring_tx_head_update(struct aq_hw_s *self, - struct aq_ring_s *ring) -{ - return -EOPNOTSUPP; -} - -static int hw_atl2_hw_ring_rx_receive(struct aq_hw_s *self, - struct aq_ring_s *ring) -{ - return -EOPNOTSUPP; + return hw_atl_b0_hw_ring_tx_init(self, aq_ring, aq_ring_param); } #define IS_FILTER_ENABLED(_F_) ((packet_filter & (_F_)) ? 1U : 0U) @@ -536,7 +489,94 @@ static int hw_atl2_hw_multicast_list_set(struct aq_hw_s *self, static int hw_atl2_hw_interrupt_moderation_set(struct aq_hw_s *self) { - return -EOPNOTSUPP; + unsigned int i = 0U; + u32 itr_tx = 2U; + u32 itr_rx = 2U; + + switch (self->aq_nic_cfg->itr) { + case AQ_CFG_INTERRUPT_MODERATION_ON: + case AQ_CFG_INTERRUPT_MODERATION_AUTO: + hw_atl_tdm_tx_desc_wr_wb_irq_en_set(self, 0U); + hw_atl_tdm_tdm_intr_moder_en_set(self, 1U); + hw_atl_rdm_rx_desc_wr_wb_irq_en_set(self, 0U); + hw_atl_rdm_rdm_intr_moder_en_set(self, 1U); + + if (self->aq_nic_cfg->itr == AQ_CFG_INTERRUPT_MODERATION_ON) { + /* HW timers are in 2us units */ + int tx_max_timer = self->aq_nic_cfg->tx_itr / 2; + int tx_min_timer = tx_max_timer / 2; + + int rx_max_timer = self->aq_nic_cfg->rx_itr / 2; + int rx_min_timer = rx_max_timer / 2; + + tx_max_timer = min(HW_ATL2_INTR_MODER_MAX, + tx_max_timer); + tx_min_timer = min(HW_ATL2_INTR_MODER_MIN, + tx_min_timer); + rx_max_timer = min(HW_ATL2_INTR_MODER_MAX, + rx_max_timer); + rx_min_timer = min(HW_ATL2_INTR_MODER_MIN, + rx_min_timer); + + itr_tx |= tx_min_timer << 0x8U; + itr_tx |= tx_max_timer << 0x10U; + itr_rx |= rx_min_timer << 0x8U; + itr_rx |= rx_max_timer << 0x10U; + } else { + static unsigned int hw_atl2_timers_table_tx_[][2] = { + {0xfU, 0xffU}, /* 10Gbit */ + {0xfU, 0x1ffU}, /* 5Gbit */ + {0xfU, 0x1ffU}, /* 5Gbit 5GS */ + {0xfU, 0x1ffU}, /* 2.5Gbit */ + {0xfU, 0x1ffU}, /* 1Gbit */ + {0xfU, 0x1ffU}, /* 100Mbit */ + }; + static unsigned int hw_atl2_timers_table_rx_[][2] = { + {0x6U, 0x38U},/* 10Gbit */ + {0xCU, 0x70U},/* 5Gbit */ + {0xCU, 0x70U},/* 5Gbit 5GS */ + {0x18U, 0xE0U},/* 2.5Gbit */ + {0x30U, 0x80U},/* 1Gbit */ + {0x4U, 0x50U},/* 100Mbit */ + }; + unsigned int mbps = self->aq_link_status.mbps; + unsigned int speed_index; + + speed_index = hw_atl_utils_mbps_2_speed_index(mbps); + + /* Update user visible ITR settings */ + self->aq_nic_cfg->tx_itr = hw_atl2_timers_table_tx_ + [speed_index][1] * 2; + self->aq_nic_cfg->rx_itr = hw_atl2_timers_table_rx_ + [speed_index][1] * 2; + + itr_tx |= hw_atl2_timers_table_tx_ + [speed_index][0] << 0x8U; + itr_tx |= hw_atl2_timers_table_tx_ + [speed_index][1] << 0x10U; + + itr_rx |= hw_atl2_timers_table_rx_ + [speed_index][0] << 0x8U; + itr_rx |= hw_atl2_timers_table_rx_ + [speed_index][1] << 0x10U; + } + break; + case AQ_CFG_INTERRUPT_MODERATION_OFF: + hw_atl_tdm_tx_desc_wr_wb_irq_en_set(self, 1U); + hw_atl_tdm_tdm_intr_moder_en_set(self, 0U); + hw_atl_rdm_rx_desc_wr_wb_irq_en_set(self, 1U); + hw_atl_rdm_rdm_intr_moder_en_set(self, 0U); + itr_tx = 0U; + itr_rx = 0U; + break; + } + + for (i = HW_ATL2_RINGS_MAX; i--;) { + hw_atl2_reg_tx_intr_moder_ctrl_set(self, itr_tx, i); + hw_atl_reg_rx_intr_moder_ctrl_set(self, itr_rx, i); + } + + return aq_hw_err_from_flags(self); } static int hw_atl2_hw_stop(struct aq_hw_s *self) @@ -546,16 +586,6 @@ static int hw_atl2_hw_stop(struct aq_hw_s *self) return 0; } -static int hw_atl2_hw_ring_tx_stop(struct aq_hw_s *self, struct aq_ring_s *ring) -{ - return -EOPNOTSUPP; -} - -static int hw_atl2_hw_ring_rx_stop(struct aq_hw_s *self, struct aq_ring_s *ring) -{ - return -EOPNOTSUPP; -} - static struct aq_stats_s *hw_atl2_utils_get_hw_stats(struct aq_hw_s *self) { return &self->curr_stats; @@ -619,21 +649,21 @@ static int hw_atl2_hw_vlan_ctrl(struct aq_hw_s *self, bool enable) const struct aq_hw_ops hw_atl2_ops = { .hw_soft_reset = hw_atl2_utils_soft_reset, .hw_prepare = hw_atl2_utils_initfw, - .hw_set_mac_address = hw_atl2_hw_mac_addr_set, + .hw_set_mac_address = hw_atl_b0_hw_mac_addr_set, .hw_init = hw_atl2_hw_init, .hw_reset = hw_atl2_hw_reset, .hw_start = hw_atl_b0_hw_start, - .hw_ring_tx_start = hw_atl2_hw_ring_tx_start, - .hw_ring_tx_stop = hw_atl2_hw_ring_tx_stop, - .hw_ring_rx_start = hw_atl2_hw_ring_rx_start, - .hw_ring_rx_stop = hw_atl2_hw_ring_rx_stop, + .hw_ring_tx_start = hw_atl_b0_hw_ring_tx_start, + .hw_ring_tx_stop = hw_atl_b0_hw_ring_tx_stop, + .hw_ring_rx_start = hw_atl_b0_hw_ring_rx_start, + .hw_ring_rx_stop = hw_atl_b0_hw_ring_rx_stop, .hw_stop = hw_atl2_hw_stop, - .hw_ring_tx_xmit = hw_atl2_hw_ring_tx_xmit, - .hw_ring_tx_head_update = hw_atl2_hw_ring_tx_head_update, + .hw_ring_tx_xmit = hw_atl_b0_hw_ring_tx_xmit, + .hw_ring_tx_head_update = hw_atl_b0_hw_ring_tx_head_update, - .hw_ring_rx_receive = hw_atl2_hw_ring_rx_receive, - .hw_ring_rx_fill = hw_atl2_hw_ring_rx_fill, + .hw_ring_rx_receive = hw_atl_b0_hw_ring_rx_receive, + .hw_ring_rx_fill = hw_atl_b0_hw_ring_rx_fill, .hw_irq_enable = hw_atl_b0_hw_irq_enable, .hw_irq_disable = hw_atl_b0_hw_irq_disable, @@ -650,5 +680,5 @@ const struct aq_hw_ops hw_atl2_ops = { .hw_rss_hash_set = hw_atl_b0_hw_rss_hash_set, .hw_get_hw_stats = hw_atl2_utils_get_hw_stats, .hw_get_fw_version = hw_atl2_utils_get_fw_version, - .hw_set_offload = hw_atl2_hw_offload_set, + .hw_set_offload = hw_atl_b0_hw_offload_set, }; diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_internal.h b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_internal.h index eb1243256730..e66b3583bfe9 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_internal.h +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_internal.h @@ -34,6 +34,9 @@ #define HW_ATL2_TC_MAX 1U #define HW_ATL2_RSS_MAX 8U +#define HW_ATL2_INTR_MODER_MAX 0x1FF +#define HW_ATL2_INTR_MODER_MIN 0xFF + #define HW_ATL2_MIN_RXD \ (ALIGN(AQ_CFG_SKB_FRAGS_MAX + 1U, AQ_HW_RXD_MULTIPLE)) #define HW_ATL2_MIN_TXD \ diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh.c index af176e1e5a18..e779d70fde66 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh.c +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh.c @@ -68,6 +68,14 @@ void hw_atl2_tpb_tx_buf_clk_gate_en_set(struct aq_hw_s *aq_hw, u32 clk_gate_en) clk_gate_en); } +void hw_atl2_reg_tx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw, + u32 tx_intr_moderation_ctl, + u32 queue) +{ + aq_hw_write_reg(aq_hw, HW_ATL2_TX_INTR_MODERATION_CTL_ADR(queue), + tx_intr_moderation_ctl); +} + void hw_atl2_tps_tx_pkt_shed_tc_data_max_credit_set(struct aq_hw_s *aq_hw, u32 max_credit, u32 tc) diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh.h b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh.h index 4acbbceb623f..8c6d78a64d42 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh.h +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh.h @@ -10,6 +10,11 @@ struct aq_hw_s; +/* Set TX Interrupt Moderation Control Register */ +void hw_atl2_reg_tx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw, + u32 tx_intr_moderation_ctl, + u32 queue); + /** Set RSS HASH type */ void hw_atl2_rpf_rss_hash_type_set(struct aq_hw_s *aq_hw, u32 rss_hash_type); diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh_internal.h b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh_internal.h index 14b78e090950..cde9e9d2836d 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh_internal.h +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh_internal.h @@ -178,6 +178,14 @@ /* default value of bitfield data_tc{t}_weight[8:0] */ #define HW_ATL2_TPS_DATA_TCTWEIGHT_DEFAULT 0x0 +/* tx interrupt moderation control register definitions + * Preprocessor definitions for TX Interrupt Moderation Control Register + * Base Address: 0x00007c28 + * Parameter: queue {Q} | stride size 0x4 | range [0, 31] + */ + +#define HW_ATL2_TX_INTR_MODERATION_CTL_ADR(queue) (0x00007c28u + (queue) * 0x40) + /* Launch time control register */ #define HW_ATL2_LT_CTRL_ADR 0x00007a1c