From patchwork Tue Sep 19 13:56:09 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 112991 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp4964294qgf; Tue, 19 Sep 2017 07:09:39 -0700 (PDT) X-Received: by 10.200.16.6 with SMTP id z6mr2275044qti.267.1505830179485; Tue, 19 Sep 2017 07:09:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505830179; cv=none; d=google.com; s=arc-20160816; b=M0ahFFBKj6U6QBfcmZfaWDeg09yxOuzk7Mr57sJSD1OKjMBCLEenN5+j1LCrOQgTZF kieQCJ+HSJpAcIRmQB+Kxzaja9qBo1K2BcbxJSvZcZ9TRGQ3l+B267K1zP9hudTTtnWS iXGBJYhj4WsExClwWstG9pljqwmw8sYkiwrqFuCLg8CG/owHLoWY3w4QYVOVs5QsNvZV S0bEGHRzFCpcWImAn1ih0poVUwAPqHQ6fAnqNJ/+WUZbDFZ0gOPNvk3ubXk7FrWm4Ryp u5Pk0ODPArEj5pQX39yqldVlSnyc2LGwDg1fjiBvs7hyClrPKqfdv65iTssOuDpcRhHK FmnQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:delivered-to:arc-authentication-results; bh=HkLNh6Xkfp6RmMFt9eG03mRTqnSgY0Szk6gOYQZJ22Q=; b=bkW0t1ZRH4SKKY5dbfWI/IWh6yj3Txm7U5Xz/pqMu5Q7YD5K0sRnGusq6+3ktkIrFn ZjjAVn+f8PVXdfL6+tDL5+3twwNGao+ZK9B4zKEs/HhHgeIheixlxMpS6isAXc5jvkua Lan3+C+dxtLMVp++JZgJFTgQ6fiuQ9hI2S7hBBkfMhk2tA2JCTFFOcGpQH0BLqlOEcjy MvfVRwc8x9od+1c6z6PJ878AuABlrDG/irhlnegKra8phNHmtGHQsNPPjTss608pGAS3 6O3/z1XJUrI3YZ0vS8ioQdOpSxWur7QKv6f4Hll6ET8Od0PZtSAx3d3Wi3zrS2D4tCXu 82bw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id r46si1392582qtb.243.2017.09.19.07.09.39; Tue, 19 Sep 2017 07:09:39 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id D8A3E62C7E; Tue, 19 Sep 2017 14:09:38 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 2E5A060F34; Tue, 19 Sep 2017 14:09:32 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 8B9F462D05; Tue, 19 Sep 2017 14:05:33 +0000 (UTC) Received: from mail-pf0-f177.google.com (mail-pf0-f177.google.com [209.85.192.177]) by lists.linaro.org (Postfix) with ESMTPS id 7E11462C5C for ; Tue, 19 Sep 2017 14:05:02 +0000 (UTC) Received: by mail-pf0-f177.google.com with SMTP id r68so39066pfj.3 for ; Tue, 19 Sep 2017 07:05:02 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=QX2dgutI+nFskJkoF1cilb/q8OTH+RxDAazfmAHRDfc=; b=InESJm8mAgiZpsx+GWb+mJmlDe1YYEFNNeF1WcIQNoADLItSI50MKYfKPR89S6nNZt i3AIE18qr4xtoiA+DwPNqM78Y4wlbeK9GFyl9fbrY7oiuX/o8NhtX+OIKAX0odqfuxv9 JGIXDfM7U2XFUuMFWhAC8wH36y3x8jqdXEbm2czS+VeJ3FoX9CE3WsLEq7huBqQAvOw3 j/y6vJaykLbEOfk/ohwcokBqCcuffzB9iEPD2TtDPaxlgGrLunonjuatRUsN+JZkHh3o ioNFkYf1f4+Ib1XPgnUTp5i5WXZ5vnr4U6Y/Xu0yXkEXq0s5VEjPMXbKx+OTkQ9QJ6Sx tL9w== X-Gm-Message-State: AHPjjUjRLI/4ZAIkYQWkduGWMCMnugywAktmbIoowvi94yc7cXNR/SSW bO4C4sVjnFEvi3XQ0wQ7+Nsjsmgd X-Google-Smtp-Source: AOwi7QDHCFSbKf3NCTDgWEI03KSJQe/wiMOiAR5C1QnQWWtO6uX755ryAyW6qIz13jEgWtIlWa8+Yg== X-Received: by 10.98.74.217 with SMTP id c86mr1395884pfj.225.1505829901413; Tue, 19 Sep 2017 07:05:01 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id 13sm4390439pfm.138.2017.09.19.07.04.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 19 Sep 2017 07:05:00 -0700 (PDT) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, graeme.gregory@linaro.org Date: Tue, 19 Sep 2017 21:56:09 +0800 Message-Id: <1505829398-52214-4-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1505829398-52214-1-git-send-email-heyi.guo@linaro.org> References: <1505829398-52214-1-git-send-email-heyi.guo@linaro.org> Cc: guoheyi@huawei.com, huangming23@huawei.com, zhangjinsong2@huawei.com, wanghuiqiang@huawei.com Subject: [Linaro-uefi] [linaro-uefi v1 03/32] Hisilicon/PciHostBridgeDxe: Assign BAR resource from PciRegionBase X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: "For discussions about Linaro-related UEFI development. Not a substitute for edk2-devel." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" From: huangming Io BAR should be based IoBase and Mem BAR should be based PciRegionBase. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ming Huang Change-Id: I23f987b24e284fc2e2c3c3270b32acd80052b284 --- .../Drivers/PciHostBridgeDxe/PciHostBridge.c | 29 ++++++++++++++-------- .../Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 15 +++++++++-- 2 files changed, 31 insertions(+), 13 deletions(-) diff --git a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c index a970da6..6ecc1e5 100644 --- a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c +++ b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c @@ -1410,9 +1410,8 @@ SetResource( Ptr->ResType = 1; Ptr->GenFlag = 0; Ptr->SpecificFlag = 0; - /* This is PCIE Device Bus which start address is the low 32bit of mem base*/ - Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) + - (RootBridgeInstance->MemBase & 0xFFFFFFFF); + /* PCIE Device Iobar address should be based on IoBase */ + Ptr->AddrRangeMin = RootBridgeInstance->IoBase; Ptr->AddrRangeMax = 0; Ptr->AddrTranslationOffset = \ (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS; @@ -1429,9 +1428,13 @@ SetResource( Ptr->GenFlag = 0; Ptr->SpecificFlag = 0; Ptr->AddrSpaceGranularity = 32; - /* This is PCIE Device Bus which start address is the low 32bit of mem base*/ + /* PCIE device Bar should be based on PciRegionBase */ + if (RootBridgeInstance->PciRegionBase > 0xFFFFFFFF) { + DEBUG((DEBUG_ERROR, "PCIE Res(TypeMem32) unsupported.\n")); + return EFI_UNSUPPORTED; + } Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) + - (RootBridgeInstance->MemBase & 0xFFFFFFFF); + (RootBridgeInstance->PciRegionBase & 0xFFFFFFFF); Ptr->AddrRangeMax = 0; Ptr->AddrTranslationOffset = \ (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS; @@ -1448,9 +1451,13 @@ SetResource( Ptr->GenFlag = 0; Ptr->SpecificFlag = 6; Ptr->AddrSpaceGranularity = 32; - /* This is PCIE Device Bus which start address is the low 32bit of mem base*/ + /* PCIE device Bar should be based on PciRegionBase */ + if (RootBridgeInstance->PciRegionBase > 0xFFFFFFFF) { + DEBUG((DEBUG_ERROR, "PCIE Res(TypePMem32) unsupported.\n")); + return EFI_UNSUPPORTED; + } Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) + - (RootBridgeInstance->MemBase & 0xFFFFFFFF); + (RootBridgeInstance->PciRegionBase & 0xFFFFFFFF); Ptr->AddrRangeMax = 0; Ptr->AddrTranslationOffset = \ (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS; @@ -1467,9 +1474,9 @@ SetResource( Ptr->GenFlag = 0; Ptr->SpecificFlag = 0; Ptr->AddrSpaceGranularity = 64; - /* This is PCIE Device Bus which start address is the low 32bit of mem base*/ + /* PCIE device Bar should be based on PciRegionBase */ Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) + - (RootBridgeInstance->MemBase & 0xFFFFFFFFFFFFFFFF); + (RootBridgeInstance->PciRegionBase & 0xFFFFFFFFFFFFFFFF); Ptr->AddrRangeMax = 0; Ptr->AddrTranslationOffset = \ (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS; @@ -1486,9 +1493,9 @@ SetResource( Ptr->GenFlag = 0; Ptr->SpecificFlag = 6; Ptr->AddrSpaceGranularity = 64; - /* This is PCIE Device Bus which start address is the low 32bit of mem base*/ + /* PCIE device Bar should be based on PciRegionBase */ Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) + - (RootBridgeInstance->MemBase & 0xFFFFFFFFFFFFFFFF); + (RootBridgeInstance->PciRegionBase & 0xFFFFFFFFFFFFFFFF); Ptr->AddrRangeMax = 0; Ptr->AddrTranslationOffset = \ (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS; diff --git a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c index 03edcf1..8dfb4b9 100644 --- a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c @@ -2301,8 +2301,19 @@ RootBridgeIoConfiguration ( PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This); for (Index = 0; Index < TypeMax; Index++) { if (PrivateData->ResAllocNode[Index].Status == ResAllocated) { - Configuration.SpaceDesp[Index].AddrRangeMin = PrivateData->ResAllocNode[Index].Base; - Configuration.SpaceDesp[Index].AddrRangeMax = PrivateData->ResAllocNode[Index].Base + PrivateData->ResAllocNode[Index].Length - 1; + switch (Index) { + case TypeIo: + Configuration.SpaceDesp[Index].AddrRangeMin = PrivateData->IoBase; + break; + case TypeBus: + Configuration.SpaceDesp[Index].AddrRangeMin = PrivateData->ResAllocNode[Index].Base; + break; + default: + /* PCIE Device bar address should be base on PciRegionBase */ + Configuration.SpaceDesp[Index].AddrRangeMin = (PrivateData->ResAllocNode[Index].Base - PrivateData->MemBase) + + (PrivateData->PciRegionBase & 0xFFFFFFFFFFFFFFFF); + } + Configuration.SpaceDesp[Index].AddrRangeMax = Configuration.SpaceDesp[Index].AddrRangeMin + PrivateData->ResAllocNode[Index].Length - 1; Configuration.SpaceDesp[Index].AddrLen = PrivateData->ResAllocNode[Index].Length; } } From patchwork Tue Sep 19 13:56:10 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 112992 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp4965188qgf; Tue, 19 Sep 2017 07:10:21 -0700 (PDT) X-Received: by 10.200.26.65 with SMTP id q1mr2108454qtk.186.1505830221371; Tue, 19 Sep 2017 07:10:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505830221; cv=none; d=google.com; s=arc-20160816; b=T2snpOOvgjGqEiGMyK+RJQqTD87uTNH4kxOoW7N0KpAV7vODKW7NnhG5qrHba3xSGb RbAzIy+gCRq4WPb3WnjVZLvnU6IDjsf0+F+KezDumxMpZSrwUSZvPsu1hRstRX7dAf0d iDez+wbeK/uTLJBvEPJUo6+pXUfcSMAFaHkhgddbKv6V9UlY5EowcFth2Y1xfHA6qEd5 pDWLsI+c2D3l2PNorBcTQLZjassECTsyTw9kwMp7MMymDosj5a2QQ7uwQsj9FDCQmeDj zfQKguZ0ywoSOryeWuBKgr6Cmq5UB2MLz80dngsdXuE0o64KdzKCm+DDRrs68tdkJQuY DE1g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:delivered-to:arc-authentication-results; bh=QTXiAcEVhGBOiC53w5fPrzsFLM3UvCuQUMILqtxQMxc=; b=NN6sx0TMDoYqeiCEr3wJgmq9kPZOWKmSiv1WZ9KEcdcdWQcNOfUKwxuLMh8B1i8Ow/ vmPZO2YRu/CjjpnhHbkPDDq0mvCh5xYittvw6leqHwWSm94PvnU8rMXlH2iQ+AHRgkc7 srcKzt5KVD6UfR0kiziYsbO5+96Schl4fJ2JVOk07J4LvgM/vFG+hExaKg9w15JgMVbx MB6wXHZx2T8iTifHAU4xaFWWRnuqa4jm71xuRaStyb8JnZt10MbxaB5PkB5wrz49vama qtiDHY8k6ElokH3b6N82pBcaBacT1BC0mJbRVtEltXAgI9W+5RLXJPpezOQcV3538OQq HsMg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id y77si9570866qky.38.2017.09.19.07.10.20; Tue, 19 Sep 2017 07:10:21 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id AB93162DF8; Tue, 19 Sep 2017 14:10:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 52A6362C59; Tue, 19 Sep 2017 14:09:35 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 3856B62B5D; Tue, 19 Sep 2017 14:05:37 +0000 (UTC) Received: from mail-pf0-f174.google.com (mail-pf0-f174.google.com [209.85.192.174]) by lists.linaro.org (Postfix) with ESMTPS id C61BE62C62 for ; Tue, 19 Sep 2017 14:05:04 +0000 (UTC) Received: by mail-pf0-f174.google.com with SMTP id m63so33964pfk.7 for ; Tue, 19 Sep 2017 07:05:04 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Royye+3LqidWPmIUVdq8Hd78szctyusrg+EL/wtwDo0=; b=INdroukzj4Ybh4DtVVafW0HGjYCZnmGB009TCIaW7P833jRKKXNeR5N+/wPY16HoOR mve2gKLSvPr9+tfd2A8D4zZrr8YblIJwjO2sS4SGhKc/j7FOzpl291nIpUUKSQA4QUid CxBz9k7AEeslAb2Sm4z4MBUyghV2NTC/Q2HXOXgO7UA5a9dYFXmvYSisJVcgwtnSpPwR hKIyWBFhCHse5ZN/dxBu4DGbBYUkZcP4z9WUpsMhTzAaZ2oKlrhs3uhEbhSokHU7OKUS ZBjBkUrLtlU79CDoPI1fEMn4R2j7sgBPklYP1ZYuRZtBT2+OsQiU1Se4R3LqevUJbkSs HIKw== X-Gm-Message-State: AHPjjUh2hKFwTtVgk3ZutkVtgVxWotLkRBfBGl9ieg3kGj9OgP0MyeKu REqfpnDdqusZyp/STuhnsS6rxEx+ X-Google-Smtp-Source: AOwi7QDtw3lu4lzYGkOz8Nw0rU7LqpVvJjeQsAQTYikLjz1aanrqFYWqhgj4X2I8w93v/4JvEcYKkg== X-Received: by 10.99.137.72 with SMTP id v69mr1433829pgd.418.1505829903914; Tue, 19 Sep 2017 07:05:03 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id 13sm4390439pfm.138.2017.09.19.07.05.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 19 Sep 2017 07:05:03 -0700 (PDT) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, graeme.gregory@linaro.org Date: Tue, 19 Sep 2017 21:56:10 +0800 Message-Id: <1505829398-52214-5-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1505829398-52214-1-git-send-email-heyi.guo@linaro.org> References: <1505829398-52214-1-git-send-email-heyi.guo@linaro.org> Cc: huangming23@huawei.com, zhangjinsong2@huawei.com, guoheyi@huawei.com, Chenhui Sun , wanghuiqiang@huawei.com Subject: [Linaro-uefi] [linaro-uefi v1 04/32] Hisilicon/d03: support MBIGen v8 driver X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: "For discussions about Linaro-related UEFI development. Not a substitute for edk2-devel." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" From: Chenhui Sun Put interrupt resource both in _CRS and _PRS according to MBIGen v8 driver version. Change-Id: Ibab703354c2bbc64f02d7ff4b125da3f5f0f6c78 Signed-off-by: Chenhui Sun --- .../Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl | 145 +++++++++++++++++++++ 1 file changed, 145 insertions(+) diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl index 46b8db0..775da7d 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl @@ -20,6 +20,7 @@ Scope(_SB) Name(_CID, "MBIGen") Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xa0080000, 0x10000) + Interrupt(ResourceProducer, Edge, ActiveHigh, Exclusive, 0,,) {640, 641} //OHCI: 640, EHCI 641 }) Name(_PRS, ResourceTemplate() { @@ -41,6 +42,41 @@ Scope(_SB) Name(_CID, "MBIGen") Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xa0080000, 0x10000) + Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, ,, ) + { + 64,65,66,67,68, + 69,70,71,72,73, + 74,75,76,77,78, + 79,80,81,82,83, + 84,85,86,87,88, + 89,90,91,92,93, + 94,95,96,97,98, + 99,100,101,102,103, + 104,105,106,107,108, + 109,110,111,112,113, + 114,115,116,117,118, + 119,120,121,122,123, + 124,125,126,127,128, + 129,130,131,132,133, + 134,135,136,137,138, + 139,140,141,142,143, + 144,145,146,147,148, + 149,150,151,152,153, + 154,155,156,157,158, + 159, + } + + Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, ,, ) + { + 576,577,578,579,580, + 581,582,583,584,585, + 586,587,588,589,590, + 591,592,593,594,595, + 596,597,598,599,600, + 601,602,603,604,605, + 606,607, + } + }) Name(_PRS, ResourceTemplate() { @@ -94,6 +130,40 @@ Scope(_SB) Name(_CID, "MBIGen") Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xa0080000, 0x10000) + Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, ,, ) + { + 192,193,194,195,196, + 197,198,199,200,201, + 202,203,204,205,206, + 207,208,209,210,211, + 212,213,214,215,216, + 217,218,219,220,221, + 222,223,224,225,226, + 227,228,229,230,231, + 232,233,234,235,236, + 237,238,239,240,241, + 242,243,244,245,246, + 247,248,249,250,251, + 252,253,254,255,256, + 257,258,259,260,261, + 262,263,264,265,266, + 267,268,269,270,271, + 272,273,274,275,276, + 277,278,279,280,281, + 282,283,284,285,286, + 287, + } + + Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, ,, ) + { + 608,609,610,611, + 612,613,614,615,616, + 617,618,619,620,621, + 622,623,624,625,626, + 627,628,629,630,631, + 632,633,634,635,636, + 637,638,639, + } }) Name(_PRS, ResourceTemplate() { @@ -147,6 +217,41 @@ Scope(_SB) Name(_CID, "MBIGen") Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xc0080000, 0x10000) + Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive,,,) + { + 576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588, + 589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600, + } + Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive,,,) + { + 960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975, + 976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988, 989, 990, 991, + 992, 993, 994, 995, 996, 997, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007, + 1008, 1009, 1010, 1011, 1012, 1013, 1014, 1015, 1016, 1017, 1018, 1019, 1020, 1021, 1022, 1023, + 1024, 1025, 1026, 1027, 1028, 1029, 1030, 1031, 1032, 1033, 1034, 1035, 1036, 1037, 1038, 1039, + 1040, 1041, 1042, 1043, 1044, 1045, 1046, 1047, 1048, 1049, 1050, 1051, 1052, 1053, 1054, 1055, + 1056, 1057, 1058, 1059, 1060, 1061, 1062, 1063, 1064, 1065, 1066, 1067, 1068, 1069, 1070, 1071, + 1072, 1073, 1074, 1075, 1076, 1077, 1078, 1079, 1080, 1081, 1082, 1083, 1084, 1085, 1086, 1087, + 1088, 1089, 1090, 1091, 1092, 1093, 1094, 1095, 1096, 1097, 1098, 1099, 1100, 1101, 1102, 1103, + 1104, 1105, 1106, 1107, 1108, 1109, 1110, 1111, 1112, 1113, 1114, 1115, 1116, 1117, 1118, 1119, + 1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 1134, 1135, + 1136, 1137, 1138, 1139, 1140, 1141, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151, + } + Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive,,,) + { + 1152, 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1162, 1163, 1164, 1165, 1166, 1167, + 1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183, + 1184, 1185, 1186, 1187, 1188, 1189, 1190, 1191, 1192, 1193, 1194, 1195, 1196, 1197, 1198, 1199, + 1200, 1201, 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209, 1210, 1211, 1212, 1213, 1214, 1215, + 1216, 1217, 1218, 1219, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1228, 1229, 1230, 1231, + 1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1244, 1245, 1246, 1247, + 1248, 1249, 1250, 1251, 1252, 1253, 1254, 1255, 1256, 1257, 1258, 1259, 1260, 1261, 1262, 1263, + 1264, 1265, 1266, 1267, 1268, 1269, 1270, 1271, 1272, 1273, 1274, 1275, 1276, 1277, 1278, 1279, + 1280, 1281, 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289, 1290, 1291, 1292, 1293, 1294, 1295, + 1296, 1297, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311, + 1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327, + 1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343, + } }) Name(_PRS, ResourceTemplate() { @@ -231,6 +336,40 @@ Name(_PRS, ResourceTemplate() { Name(_CID, "MBIGen") Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xc0080000, 0x10000) + Interrupt (Resourceproducer, Level, ActiveHigh, Exclusive, ,, ) + { + 64,65,66,67,68, + 69,70,71,72,73, + 74,75,76,77,78, + 79,80,81,82,83, + 84,85,86,87,88, + 89,90,91,92,93, + 94,95,96,97,98, + 99,100,101,102,103, + 104,105,106,107,108, + 109,110,111,112,113, + 114,115,116,117,118, + 119,120,121,122,123, + 124,125,126,127,128, + 129,130,131,132,133, + 134,135,136,137,138, + 139,140,141,142,143, + 144,145,146,147,148, + 149,150,151,152,153, + 154,155,156,157,158, + 159, + } + + Interrupt (Resourceproducer, Edge, ActiveHigh, Exclusive, ,, ) + { + 601,602,603,604, + 605,606,607,608,609, + 610,611,612,613,614, + 615,616,617,618,619, + 620,621,622,623,624, + 625,626,627,628,629, + 630,631,632, + } }) Name(_PRS, ResourceTemplate() { @@ -285,6 +424,12 @@ Name(_PRS, ResourceTemplate() { Name(_CID, "MBIGen") Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xc0080000, 0x10000) + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,) + { + 722, 723, 724, 725, 726, 727, 728, 729, 730, 731, 732, 733, + 734, 735, 736, 737, 738, 739, 740, 741, 742, 743, 744, 745, + 746, 747, 748, 749, 750, 751, 752, 753, 785, 754, + } }) Name (_PRS, ResourceTemplate (){ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,) From patchwork Tue Sep 19 13:56:11 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 112995 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id 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[54.225.227.206]) by mx.google.com with ESMTP id l27si9681768qtl.35.2017.09.19.07.11.57; Tue, 19 Sep 2017 07:11:57 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id E079E64482; Tue, 19 Sep 2017 14:11:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 0614762D05; Tue, 19 Sep 2017 14:09:52 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 62AE862C62; Tue, 19 Sep 2017 14:05:41 +0000 (UTC) Received: from mail-pf0-f178.google.com (mail-pf0-f178.google.com [209.85.192.178]) by lists.linaro.org (Postfix) with ESMTPS id 487C362C60 for ; Tue, 19 Sep 2017 14:05:07 +0000 (UTC) Received: by mail-pf0-f178.google.com with SMTP id u12so36897pfl.4 for ; Tue, 19 Sep 2017 07:05:07 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=g1gFMr+4zw1RO8pwrg+vOHFUF0Ph+Gloq2CjyE+14nY=; b=erUwDjs3Dv9prMwVVf7I/SF7bcTfttuMunqFqymzrJ8bs0n3XXTLrIF0BG7sVxc0nf nNuIHlWgYan4x+ISv3U2EjwTublw1EnsgceImO5E3oROB5K+WHlqCkATXNvAriCDQBiJ pWlkeOKgNGNSkotSUU3JW7PPnCdUw97+S75oJU86YPfbvFWz99fhDNF7aHdqBaXjqp+L 4TzwnwmU4y34CF6wSOMz0eBf4WQP0hJsUOUBjJnKKQIb0AV/LS3M3YKnQ7K/k597G707 Pw8J6a3tnWkQ0Ib/9rhdWQEicWOkwf/yRXsODzUsrSTBU4kCCz39qqAhyxC1GnepW2VJ zORg== X-Gm-Message-State: AHPjjUiXG+XyE/09FYAC8ZybbVKfMRTuLylKe5at+L6EYid7VXCJ696A AIbTHKW8ledGomZWbTdrTmyx5w/I X-Google-Smtp-Source: AOwi7QBa+MPslHdg8H3oFh5IhJhkuWimCEGR6CfbLZFTjcDNAn6RDc9V+UH8W11GJbqT03vVIN+Z1g== X-Received: by 10.98.48.194 with SMTP id w185mr1438701pfw.231.1505829906493; Tue, 19 Sep 2017 07:05:06 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id 13sm4390439pfm.138.2017.09.19.07.05.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 19 Sep 2017 07:05:05 -0700 (PDT) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, graeme.gregory@linaro.org Date: Tue, 19 Sep 2017 21:56:11 +0800 Message-Id: <1505829398-52214-6-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1505829398-52214-1-git-send-email-heyi.guo@linaro.org> References: <1505829398-52214-1-git-send-email-heyi.guo@linaro.org> Cc: huangming23@huawei.com, zhangjinsong2@huawei.com, Anurup M , guoheyi@huawei.com, Chenhui Sun , wanghuiqiang@huawei.com Subject: [Linaro-uefi] [linaro-uefi v1 05/32] Hisilicon/D03: Uncore PMU Add L3 cache, MN PMU devices and properties.eml X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: "For discussions about Linaro-related UEFI development. Not a substitute for edk2-devel." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" From: Chenhui Sun The Hisilicon SoC uncore PMU devices like L3 cache, MN etc are probed by djtag. The djtag will have _HID and L3 cache and MN will use _ADR and _CID to identity the hardware version. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Anurup M --- .../Hi1610/Hi1610AcpiTables/Dsdt/D03UncorePmu.asl | 204 +++++++++++++++++++++ .../Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl | 2 + 2 files changed, 206 insertions(+) create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03UncorePmu.asl diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03UncorePmu.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03UncorePmu.asl new file mode 100644 index 0000000..6d07475 --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03UncorePmu.asl @@ -0,0 +1,204 @@ +/** @file + Differentiated System Description Table Fields (DSDT) + + Copyright (c) 2017, ARM Ltd. All rights reserved.
+ Copyright (c) 2017, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2017, Linaro Limited. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ + +**/ + +Scope(_SB) { + // Djtag for CPU die #1 (scl #1) + Device (DJT0) { + Name (_HID, "HISI0201") // _HID: Hardware ID + Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings + QWordMemory ( // CPU die sysctrl memory region + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + Cacheable, + ReadWrite, + 0x0, // Granularity + 0x40010000, // Min Base Address + 0x4001FFFF, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,scl-id", 0x01} + } + }) + + // L3C Bank 0 for SCL #1 + Device (L3C0) { + Name (_ADR, 0) + Name (_CID, "HISI0211") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x04, 0x02}}, + } + }) + } + + // L3C Bank 1 for SCL #1 + Device (L3C1) { + Name (_ADR, 1) + Name (_CID, "HISI0211") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x04, 0x04}}, + } + }) + } + + // L3C Bank 2 for SCL #1 + Device (L3C2) { + Name (_ADR, 2) + Name (_CID, "HISI0211") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x04, 0x01}}, + } + }) + } + + // L3C Bank 3 for SCL #1 + Device (L3C3) { + Name (_ADR, 3) + Name (_CID, "HISI0211") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x04, 0x08}}, + } + }) + } + + // MN1 for SCL #1 + Device (MN1) { + Name (_ADR, 4) + Name (_CID, "HISI0221") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", 0xb}, + } + }) + } + } + + // Djtag for CPU die #2 (scl #2) + Device (DJT1) { + Name (_HID, "HISI0201") // _HID: Hardware ID + Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings + QWordMemory ( // CPU die sysctrl memory region + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + Cacheable, + ReadWrite, + 0x0, // Granularity + 0x60010000, // Min Base Address + 0x6001FFFF, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,scl-id", 0x02}, + } + }) + + // L3C Bank 0 for SCL #2 + Device (L3C0) { + Name (_ADR, 0) + Name (_CID, "HISI0211") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x04, 0x02}}, + } + }) + } + + // L3C Bank 1 for SCL #2 + Device (L3C1) { + Name (_ADR, 1) + Name (_CID, "HISI0211") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x04, 0x04}}, + } + }) + } + + // L3C Bank 2 for SCL #2 + Device (L3C2) { + Name (_ADR, 2) + Name (_CID, "HISI0211") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x04, 0x01}}, + } + }) + } + + // L3C Bank 3 for SCL #2 + Device (L3C3) { + Name (_ADR, 3) + Name (_CID, "HISI0211") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x04, 0x08}}, + } + }) + } + + // MN1 for SCL #2 + Device (MN1) { + Name (_ADR, 4) + Name (_CID, "HISI0221") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", 0xb}, + } + }) + } + } +} + diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl index 4185f80..af80eb6 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/DsdtHi1610.asl @@ -26,4 +26,6 @@ DefinitionBlock("DsdtTable.aml", "DSDT", 1, "HISI ", "HIP06 ", EFI_ACPI_ARM_O include ("D03Hns.asl") include ("D03Sas.asl") include ("D03Pci.asl") + include ("Apei.asl") + include ("D03UncorePmu.asl") } From patchwork Tue Sep 19 13:56:12 2017 Content-Type: text/plain; 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[54.225.227.206]) by mx.google.com with ESMTP id n55si9736439qta.8.2017.09.19.07.11.22; Tue, 19 Sep 2017 07:11:22 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id E729D6446E; Tue, 19 Sep 2017 14:11:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id C076C62CE2; Tue, 19 Sep 2017 14:09:47 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id EDD3F62C5C; Tue, 19 Sep 2017 14:05:40 +0000 (UTC) Received: from mail-pf0-f175.google.com (mail-pf0-f175.google.com [209.85.192.175]) by lists.linaro.org (Postfix) with ESMTPS id 06BB562C6C for ; Tue, 19 Sep 2017 14:05:10 +0000 (UTC) Received: by mail-pf0-f175.google.com with SMTP id p87so31651pfj.9 for ; Tue, 19 Sep 2017 07:05:09 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hPCbigJ/QdT/KTFXNcgaZbW3s6EwIhX2j0rMWgvYJiI=; b=q7h21NFSWrgy3O6EFTSNi0uvU5Uhx+xy4fdtTXoC5gJHJASByhi8fw1GGISP9M+0Q1 LYEqShAT1Fd4giAxZFcCxxtdHtNfOiQDD5P7OxHweqoFualBUnFU3B0/8xEt8p9bXYVb IJMbSB1u2wfjbCCuj+3/qt8DFpqSuRTWtoArt9ZTdcT9t6PcSSgIgdus4tfZ6JyH3pn9 2YxtPIHinXJ5d/C7g/0cmXt8RgQ29GfrxJ1Bzzb8x4/pM7Vu/2Vun0pB4RpOy2Q52Fcy qxuHqKRuAt0kHdaI3CdBelhvsWI+YyipzmgrjYqN8+WvNnSTKkcL7ivWvlVwWy5B8Jdm JSpw== X-Gm-Message-State: AHPjjUjJwUdOC/d1zYNjA//e5r+8Ogmj3b62lU0iyJpAvvlDz9+jmleC nFmj6cacjEs/T9wk6UNpYI/yKPwS X-Google-Smtp-Source: AOwi7QCPeW44CVoV/Lb+bj1GbdB1Mz9XG1H4Bj+hvj/FmG2WcwViUeZzxuXPN8anMM9AWdjQnM/zIg== X-Received: by 10.98.8.81 with SMTP id c78mr1436758pfd.166.1505829909132; Tue, 19 Sep 2017 07:05:09 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id 13sm4390439pfm.138.2017.09.19.07.05.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 19 Sep 2017 07:05:08 -0700 (PDT) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, graeme.gregory@linaro.org Date: Tue, 19 Sep 2017 21:56:12 +0800 Message-Id: <1505829398-52214-7-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1505829398-52214-1-git-send-email-heyi.guo@linaro.org> References: <1505829398-52214-1-git-send-email-heyi.guo@linaro.org> Cc: huangming23@huawei.com, zhangjinsong2@huawei.com, Anurup M , guoheyi@huawei.com, Chenhui Sun , wanghuiqiang@huawei.com Subject: [Linaro-uefi] [linaro-uefi v1 06/32] Hisilicon D05: Uncore PMU: Add L3 cache, MN PMU devices and properties X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: "For discussions about Linaro-related UEFI development. Not a substitute for edk2-devel." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" From: Chenhui Sun 1) The Hisilicon SoC uncore PMU devices like L3 cache, MN etc are probed by djtag. The djtag will have _HID and L3 cache and MN will use _ADR and _CID to identity the hardware version. 2) Use QWordMemory to support 64-bit address of CPU sysctrl. 3) Include UncorePMU asl in Hi1616 Dsdt. Signed-off-by: Anurup M --- .../Hi1616/D05AcpiTables/Dsdt/D05UncorePmu.asl | 385 +++++++++++++++++++++ .../Hi1616/D05AcpiTables/Dsdt/DsdtHi1616.asl | 1 + 2 files changed, 386 insertions(+) create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05UncorePmu.asl diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05UncorePmu.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05UncorePmu.asl new file mode 100644 index 0000000..d2a1432 --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05UncorePmu.asl @@ -0,0 +1,385 @@ +/** @file + Differentiated System Description Table Fields (DSDT) + + Copyright (c) 2017, ARM Ltd. All rights reserved.
+ Copyright (c) 2017, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2017, Linaro Limited. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ + +**/ + +Scope(_SB) { + // Djtag for CPU die #1 (scl #1) + Device (DJT0) { + Name (_HID, "HISI0202") // _HID: Hardware ID + Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings + QWordMemory ( // CPU die sysctrl memory region + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + Cacheable, + ReadWrite, + 0x0, // Granularity + 0x40010000, // Min Base Address + 0x4001FFFF, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,scl-id", 0x01} + } + }) + + // L3C Bank 0 for SCL #1 + Device (L3C0) { + Name (_ADR, 0) + Name (_CID, "HISI0212") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x01, 0x01}}, + } + }) + } + + // L3C Bank 1 for SCL #1 + Device (L3C1) { + Name (_ADR, 1) + Name (_CID, "HISI0212") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x02, 0x01}}, + } + }) + } + + // L3C Bank 2 for SCL #1 + Device (L3C2) { + Name (_ADR, 2) + Name (_CID, "HISI0212") + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x03, 0x01}}, + } + }) + } + + // L3C Bank 3 for SCL #1 + Device (L3C3) { + Name (_ADR, 3) + Name (_CID, "HISI0212") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x04, 0x01}}, + } + }) + } + + // MN1 for SCL #1 + Device (MN1) { + Name (_ADR, 4) + Name (_CID, "HISI0222") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", 0x21}, + } + }) + } + } + + // Djtag for CPU die #2 (scl #3) + Device (DJT1) { + Name (_HID, "HISI0202") // _HID: Hardware ID + Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings + QWordMemory ( // CPU die sysctrl memory region + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + Cacheable, + ReadWrite, + 0x0, // Granularity + 0x60010000, // Min Base Address + 0x6001FFFF, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,scl-id", 0x03}, + } + }) + + // L3C Bank 0 for SCL #3 + Device (L3C0) { + Name (_ADR, 0) + Name (_CID, "HISI0212") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x01, 0x01}}, + } + }) + } + + // L3C Bank 1 for SCL #3 + Device (L3C1) { + Name (_ADR, 1) + Name (_CID, "HISI0212") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x02, 0x01}}, + } + }) + } + + // L3C Bank 2 for SCL #3 + Device (L3C2) { + Name (_ADR, 2) + Name (_CID, "HISI0212") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x03, 0x01}}, + } + }) + } + + // L3C Bank 3 for SCL #3 + Device (L3C3) { + Name (_ADR, 3) + Name (_CID, "HISI0212") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x04, 0x01}}, + } + }) + } + + // MN1 for SCL #3 + Device (MN1) { + Name (_ADR, 4) + Name (_CID, "HISI0222") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", 0x21}, + } + }) + } + } + + // Djtag for CPU die #3 (scl #5) + Device (DJT2) { + Name (_HID, "HISI0202") // _HID: Hardware ID + Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings + QWordMemory ( // CPU die sysctrl memory region + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + Cacheable, + ReadWrite, + 0x0, // Granularity + 0x40040010000, // Min Base Address + 0x4004001FFFF, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,scl-id", 0x05} + } + }) + + // L3C Bank 0 for SCL #5 + Device (L3C0) { + Name (_ADR, 0) + Name (_CID, "HISI0212") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x01, 0x01}}, + } + }) + } + + // L3C Bank 1 for SCL #5 + Device (L3C1) { + Name (_ADR, 1) + Name (_CID, "HISI0212") + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x02, 0x01}}, + } + }) + } + + // L3C Bank 2 for SCL #5 + Device (L3C2) { + Name (_ADR, 2) + Name (_CID, "HISI0212") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x03, 0x01}}, + } + }) + } + + // L3C Bank 3 for SCL #5 + Device (L3C3) { + Name (_ADR, 3) + Name (_CID, "HISI0212") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x04, 0x01}}, + } + }) + } + + // MN1 for SCL #5 + Device (MN1) { + Name (_ADR, 4) + Name (_CID, "HISI0222") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", 0x21}, + } + }) + } + } + + // Djtag for CPU die #4 (scl #7) + Device (DJT3) { + Name (_HID, "HISI0202") // _HID: Hardware ID + Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings + QWordMemory ( // CPU die sysctrl memory region + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + Cacheable, + ReadWrite, + 0x0, // Granularity + 0x40060010000, // Min Base Address + 0x4006001FFFF, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,scl-id", 0x07} + } + }) + + // L3C Bank 0 for SCL #7 + Device (L3C0) { + Name (_ADR, 0) + Name (_CID, "HISI0212") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x01, 0x01}}, + } + }) + } + + // L3C Bank 1 for SCL #7 + Device (L3C1) { + Name (_ADR, 1) + Name (_CID, "HISI0212") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x02, 0x01}}, + } + }) + } + + // L3C Bank 2 for SCL #7 + Device (L3C2) { + Name (_ADR, 2) + Name (_CID, "HISI0212") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x03, 0x01}}, + } + }) + } + + // L3C Bank 3 for SCL #7 + Device (L3C3) { + Name (_ADR, 3) + Name (_CID, "HISI0212") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x04, 0x01}}, + } + }) + } + + // MN1 for SCL #7 + Device (MN1) { + Name (_ADR, 4) + Name (_CID, "HISI0222") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", 0x21}, + } + }) + } + } +} diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/DsdtHi1616.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/DsdtHi1616.asl index b4fc538..e4928b6 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/DsdtHi1616.asl +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/DsdtHi1616.asl @@ -28,4 +28,5 @@ DefinitionBlock("DsdtTable.aml", "DSDT", 2, "HISI ", "HIP07 ", EFI_ACPI_ARM_O include ("D05Hns.asl") include ("D05Sas.asl") include ("D05Pci.asl") + include ("D05UncorePmu.asl") } From patchwork Tue Sep 19 13:56:13 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 112996 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp4968093qgf; Tue, 19 Sep 2017 07:12:32 -0700 (PDT) X-Received: by 10.13.220.2 with SMTP id f2mr1091507ywe.175.1505830352039; Tue, 19 Sep 2017 07:12:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505830352; cv=none; d=google.com; s=arc-20160816; b=QuP7XYpi7a/JXWRElP+GYbKlrfcLv7iGJ6NXH6idaVOJUvnYt6eLr6468RGCBSHIVa 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[54.225.227.206]) by mx.google.com with ESMTP id g128si1764052qkg.434.2017.09.19.07.12.31; Tue, 19 Sep 2017 07:12:32 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 9992D62D0D; Tue, 19 Sep 2017 14:12:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 309C362D11; Tue, 19 Sep 2017 14:09:54 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 59D7D62C62; Tue, 19 Sep 2017 14:05:43 +0000 (UTC) Received: from mail-pf0-f169.google.com (mail-pf0-f169.google.com [209.85.192.169]) by lists.linaro.org (Postfix) with ESMTPS id B024B62C7E for ; Tue, 19 Sep 2017 14:05:12 +0000 (UTC) Received: by mail-pf0-f169.google.com with SMTP id z84so39865pfi.2 for ; Tue, 19 Sep 2017 07:05:12 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=emmEn9Eq2IaukDQNh6Bryt4Z8rrM5547xXFLnoUNyZI=; b=tTgqk4hjNyv7f+y2bgoPErO5N8xVh/ZV/R53e5V1zzfBQ+2+S1Y+SSr1AiJdEFHGTo gw12pG5fmNByaiRf/SmWquJsW6QnVy0stYWinaixEzEzhyYZc9NGZnJ399W8dT/ZYvvo OraYa//hFq7DzEMcgPBPomchGqSGthklr3yWCN57WM6UIS628NxE5rqvFRrgUfRGJSh+ AuEO2we2flFhaW5K0hxOp1ej3ULOtBiUISh+RC3ot0oSed0R3k/0DpIrszrMiEWzjaD8 yaRclQO+gLG56cpiP6sXvbIcmwb5JbJeOOgXFU3FFee7Reg8oIuxCCFTSUlztxa6Tuc9 bITA== X-Gm-Message-State: AHPjjUgmZ6OCb513AOOJ8P/GfZtuYdfUGlYZ5z+uzsonMPLeT4BaIBaM u7Roj8VEIEwolnJR+1pwgfj/ZeLX X-Google-Smtp-Source: AOwi7QBgpKx+Versg9TxoSGMjV+cJs4tb9od3kVfPjrjeAqAPBvseglUNC9MmqHLHSvJAcIDw4Sktg== X-Received: by 10.84.238.131 with SMTP id v3mr1443589plk.342.1505829911974; Tue, 19 Sep 2017 07:05:11 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id 13sm4390439pfm.138.2017.09.19.07.05.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 19 Sep 2017 07:05:11 -0700 (PDT) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, graeme.gregory@linaro.org Date: Tue, 19 Sep 2017 21:56:13 +0800 Message-Id: <1505829398-52214-8-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1505829398-52214-1-git-send-email-heyi.guo@linaro.org> References: <1505829398-52214-1-git-send-email-heyi.guo@linaro.org> Cc: huangming23@huawei.com, zhangjinsong2@huawei.com, Anurup M , guoheyi@huawei.com, Chenhui Sun , wanghuiqiang@huawei.com Subject: [Linaro-uefi] [linaro-uefi v1 07/32] Hisilicon D03: Uncore PMU: Add DDRC PMU device and properties X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: "For discussions about Linaro-related UEFI development. Not a substitute for edk2-devel." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" From: Chenhui Sun Use _HID of HISI0231 for DDRC uncore PMU in hi1612. Every CPU die support 2 DDRC channels and each DDRC channel will be represented as a device with _HID and _UID. The device will also support _STA method. Signed-off-by: Anurup M --- .../Hi1610/Hi1610AcpiTables/Dsdt/D03UncorePmu.asl | 137 ++++++++++++++++++++- 1 file changed, 136 insertions(+), 1 deletion(-) diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03UncorePmu.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03UncorePmu.asl index 6d07475..96aaaa5 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03UncorePmu.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03UncorePmu.asl @@ -200,5 +200,140 @@ Scope(_SB) { }) } } -} + // DDRC Channel 0 for CPU die #1 (scl #1) + Device (DDR0) { + Name (_HID, "HISI0231") // _HID: Hardware ID + Name (_UID, 0) // _UID: Unique ID + Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings + QWordMemory ( + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x40348000, // Min Base Address + 0x40348FFF, // Max Base Address + 0x0, // Translate + 0x1000 // Length + ) + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,scl-id", 0x01}, + Package () {"hisilicon,ch-id", 0x00}, + } + }) + + Method (_STA, 0x0, NotSerialized) + { + Return (0xf) + } + } + + // DDRC Channel 1 for CPU die #1 (scl #1) + Device (DDR1) { + Name (_HID, "HISI0231") // _HID: Hardware ID + Name (_UID, 1) // _UID: Unique ID + Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings + QWordMemory ( + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x40358000, // Min Base Address + 0x40358FFF, // Max Base Address + 0x0, // Translate + 0x1000 // Length + ) + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,scl-id", 0x01}, + Package () {"hisilicon,ch-id", 0x01}, + } + }) + + Method (_STA, 0x0, NotSerialized) + { + Return (0xf) + } + } + + // DDRC Channel 0 for CPU die #2 (scl #2) + Device (DDR2) { + Name (_HID, "HISI0231") // _HID: Hardware ID + Name (_UID, 2) // _UID: Unique ID + Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings + QWordMemory ( + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x60348000, // Min Base Address + 0x60348FFF, // Max Base Address + 0x0, // Translate + 0x1000 // Length + ) + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,scl-id", 0x02}, + Package () {"hisilicon,ch-id", 0x00}, + } + }) + + Method (_STA, 0x0, NotSerialized) + { + Return (0xf) + } + } + + // DDRC Channel 1 for CPU die #2 (scl #2) + Device (DDR3) { + Name (_HID, "HISI0231") // _HID: Hardware ID + Name (_UID, 3) // _UID: Unique ID + Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings + QWordMemory ( + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x60358000, // Min Base Address + 0x60358FFF, // Max Base Address + 0x0, // Translate + 0x1000 // Length + ) + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,scl-id", 0x02}, + Package () {"hisilicon,ch-id", 0x01}, + } + }) + + Method (_STA, 0x0, NotSerialized) + { + Return (0xf) + } + } +} From patchwork Tue Sep 19 13:56:14 2017 Content-Type: text/plain; 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Not a substitute for edk2-devel." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" From: Chenhui Sun Use _HID of HISI0232 for DDRC uncore PMU in hi1616 Every CPU die support 2 DDRC channels and each DDRC channel will be represented as a device with _HID and _UID. The device will also support _STA method. Signed-off-by: Anurup M --- .../Hi1616/D05AcpiTables/Dsdt/D05UncorePmu.asl | 272 +++++++++++++++++++++ 1 file changed, 272 insertions(+) diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05UncorePmu.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05UncorePmu.asl index d2a1432..dcb287d 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05UncorePmu.asl +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05UncorePmu.asl @@ -382,4 +382,276 @@ Scope(_SB) { }) } } + + // DDRC Channel 0 for CPU die #1 (scl #1) + Device (DDR0) { + Name (_HID, "HISI0232") // _HID: Hardware ID + Name (_UID, 0) // _UID: Unique ID + Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings + QWordMemory ( + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x40348000, // Min Base Address + 0x40348FFF, // Max Base Address + 0x0, // Translate + 0x1000 // Length + ) + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,scl-id", 0x01}, + Package () {"hisilicon,ch-id", 0x00}, + } + }) + + Method (_STA, 0x0, NotSerialized) + { + Return (0xf) + } + } + + // DDRC Channel 1 for CPU die #1 (scl #1) + Device (DDR1) { + Name (_HID, "HISI0232") // _HID: Hardware ID + Name (_UID, 1) // _UID: Unique ID + Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings + QWordMemory ( + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x40358000, // Min Base Address + 0x40358FFF, // Max Base Address + 0x0, // Translate + 0x1000 // Length + ) + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,scl-id", 0x01}, + Package () {"hisilicon,ch-id", 0x01}, + } + }) + + Method (_STA, 0x0, NotSerialized) + { + Return (0xf) + } + } + + // DDRC Channel 0 for CPU die #2 (scl #3) + Device (DDR2) { + Name (_HID, "HISI0232") // _HID: Hardware ID + Name (_UID, 2) // _UID: Unique ID + Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings + QWordMemory ( + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x60348000, // Min Base Address + 0x60348FFF, // Max Base Address + 0x0, // Translate + 0x1000 // Length + ) + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,scl-id", 0x03}, + Package () {"hisilicon,ch-id", 0x00}, + } + }) + + Method (_STA, 0x0, NotSerialized) + { + Return (0xf) + } + } + + // DDRC Channel 1 for CPU die #2 (scl #3) + Device (DDR3) { + Name (_HID, "HISI0232") // _HID: Hardware ID + Name (_UID, 3) // _UID: Unique ID + Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings + QWordMemory ( + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x60358000, // Min Base Address + 0x60358FFF, // Max Base Address + 0x0, // Translate + 0x1000 // Length + ) + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,scl-id", 0x03}, + Package () {"hisilicon,ch-id", 0x01}, + } + }) + + Method (_STA, 0x0, NotSerialized) + { + Return (0xf) + } + } + + // DDRC Channel 0 for CPU die #3 (scl #5) + Device (DDR4) { + Name (_HID, "HISI0232") // _HID: Hardware ID + Name (_UID, 4) // _UID: Unique ID + Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings + QWordMemory ( + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x40040348000, // Min Base Address + 0x40040348FFF, // Max Base Address + 0x0, // Translate + 0x1000 // Length + ) + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,scl-id", 0x05}, + Package () {"hisilicon,ch-id", 0x00}, + } + }) + + Method (_STA, 0x0, NotSerialized) + { + Return (0xf) + } + } + + // DDRC Channel 1 for CPU die #3 (scl #5) + Device (DDR5) { + Name (_HID, "HISI0232") // _HID: Hardware ID + Name (_UID, 5) // _UID: Unique ID + Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings + QWordMemory ( + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x40040358000, // Min Base Address + 0x40040358FFF, // Max Base Address + 0x0, // Translate + 0x1000 // Length + ) + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,scl-id", 0x05}, + Package () {"hisilicon,ch-id", 0x01}, + } + }) + + Method (_STA, 0x0, NotSerialized) + { + Return (0xf) + } + } + + // DDRC Channel 0 for CPU die #4 (scl #7) + Device (DDR6) { + Name (_HID, "HISI0232") // _HID: Hardware ID + Name (_UID, 6) // _UID: Unique ID + Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings + QWordMemory ( + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x40060348000, // Min Base Address + 0x40060348FFF, // Max Base Address + 0x0, // Translate + 0x1000 // Length + ) + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,scl-id", 0x07}, + Package () {"hisilicon,ch-id", 0x00}, + } + }) + + Method (_STA, 0x0, NotSerialized) + { + Return (0xf) + } + } + + // DDRC Channel 1 for CPU die #4 (scl #7) + Device (DDR7) { + Name (_HID, "HISI0232") // _HID: Hardware ID + Name (_UID, 7) // _UID: Unique ID + Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings + QWordMemory ( + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x40060358000, // Min Base Address + 0x40060358FFF, // Max Base Address + 0x0, // Translate + 0x1000 // Length + ) + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,scl-id", 0x07}, + Package () {"hisilicon,ch-id", 0x01}, + } + }) + + Method (_STA, 0x0, NotSerialized) + { + Return (0xf) + } + } } From patchwork Tue Sep 19 13:56:15 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 112993 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp4965806qgf; Tue, 19 Sep 2017 07:10:52 -0700 (PDT) X-Received: by 10.237.53.229 with SMTP id d34mr2099171qte.97.1505830252834; Tue, 19 Sep 2017 07:10:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505830252; cv=none; d=google.com; s=arc-20160816; b=al8fCWnVgXvaTgYOqLld5ugJ2MF4zzHheMgOiD3wkfbKvKz1Vsyj6jcK6bb54Lr3v8 sjOeYO6rKhz3SyyHdpu82GwQpHl3pkaZ6/GtC0mxOjUZ6pYPnQpKoTO1b6KKAD0TqnBR FiY6jojI6Civyi53QYPk72o7lt0noNZM+YnjlLgYMZUfLxETMQKO3dbFPv0ROcv0yQhS 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Not a substitute for edk2-devel." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" From: huangming On D05 PCIe now, 2p NA PCIe2 and 2p NB PCIe0's pci domain addresses are 0x20000000 and 0x30000000 based. These addresses overlap with the DDR memory range 0-1G. In this situation, on the inbound direction, our pcie will drop the DDR address access that are located in the pci range window and lead to a dataflow error. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ming Huang --- Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 8 ++++---- Platforms/Hisilicon/D05/D05.dsc | 12 ++++++------ 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl index 79267e5..55c7f50 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl @@ -646,10 +646,10 @@ Scope(_SB) Cacheable, ReadWrite, 0x0, // Granularity - 0x20000000, // Min Base Address + 0x40000000, // Min Base Address 0xefffffff, // Max Base Address 0x65000000000, // Translate - 0xd0000000 // Length + 0xb0000000 // Length ) QWordIO ( ResourceProducer, @@ -766,10 +766,10 @@ Scope(_SB) Cacheable, ReadWrite, 0x0, // Granularity - 0x30000000, // Min Base Address + 0x40000000, // Min Base Address 0xefffffff, // Max Base Address 0x75000000000, // Translate - 0xc0000000 // Length + 0xb0000000 // Length ) QWordIO ( ResourceProducer, diff --git a/Platforms/Hisilicon/D05/D05.dsc b/Platforms/Hisilicon/D05/D05.dsc index 2fa0508..ffa1897 100644 --- a/Platforms/Hisilicon/D05/D05.dsc +++ b/Platforms/Hisilicon/D05/D05.dsc @@ -328,12 +328,12 @@ gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize|0xbeffff gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress|0x400a9400000 gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize|0xbeffff - gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress|0x20000000 - gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize|0xcfffffff + gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress|0x40000000 + gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize|0xafffffff gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress|0x400ab400000 gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize|0xbeffff - gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress|0x30000000 - gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize|0xbfffffff + gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress|0x40000000 + gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize|0xafffffff gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress|0x40000000 gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize|0xafffffff gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress|0x408aa400000 @@ -351,9 +351,9 @@ gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase|0x8B9800000 gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase|0x400A8400000 gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase|0x400A9400000 - gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase|0x65020000000 + gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase|0x65040000000 gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase|0x400AB400000 - gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase|0x75030000000 + gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase|0x75040000000 gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase|0x79040000000 gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase|0x408AA400000 gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase|0x408AB400000 From patchwork Tue Sep 19 13:56:16 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 112999 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp4969699qgf; Tue, 19 Sep 2017 07:13:45 -0700 (PDT) X-Received: by 10.107.82.13 with SMTP id g13mr2323626iob.214.1505830425269; Tue, 19 Sep 2017 07:13:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505830425; cv=none; d=google.com; s=arc-20160816; b=RF6EWsS8H+KNiQDgyY0MvyjI+JAnmR2fzvKY4z8dUy0UzgxSmme9TlaBlk35D+iUL6 YHRjpssQGkrz7+hd6HmnoHCmLmK4yZj4lGn6MwzdfuHAnBSQLuzagICDi3w6hbk/iLo+ mV1+DZNr8LDBk1y6LsTsjkA2hdlf/MMMlv38Ug99iiLz9cdJEBC2an8SGhARpw4N/7z2 lfjL0ILjMF55eOqV3bMViE92p2LQKPBUpBGISw/UsPXxTZibArvSUY/M7mpwgItF+ntZ yxtKp4wgwhYZEbdBKFmyif0g4Ufqpp5XbCmWln6uKGGmoHSScMvOGbBchAjO4sjcpxg8 VMAQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:delivered-to:arc-authentication-results; bh=S6+xqD0JI08Rq46fHYk9Pbs5Rfmxjp6n6Q46dKmIouE=; b=eH+4b3pyKUokaf2kMI7ofDnXZK2ddV34S9hk4BwUO7X/SnwQ3lR0gOqPq2TCGI3IKI LKwHLqOoNYoo5H+hXMJLbQQbKQXWyGqFTvme22xQTUL2l5h/+op7TbMPVgsu4aHQ10jK /KgP3czEYZVxwA1pTR4COq+4jUIfWzOvhDRPT0S/GWQq+6nzHvCKTCPSKspwnKVmBW+Q gDtrKtVF7Gxw7YlYVEI3H4IV7omCCDSs2fBf8w29HJYPSPg3nLjkJF5zUE5GFi30RZkn AuAAa+OsUkV8Tud2E43sCSYBSM+U1djYQi3KoKNdK+QhJ+VwBMGy7TIYNpnH//QfFdpD fF2g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.linaro.org (lists.linaro.org. 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Not a substitute for edk2-devel." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" From: Chenhui Sun Signed-off-by: wangzhou Signed-off-by: Chenhui Sun Signed-off-by: Yi Li --- Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl | 315 ++++++++++++++++++++++- 1 file changed, 307 insertions(+), 8 deletions(-) diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl index 50ccac1..420cd20 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl @@ -109,7 +109,145 @@ [0004] ItsCount : 00000001 [0004] Identifiers : 00000007 +//f4 +/* 1P NA PCIe SMMU */ +[0001] Type : 04 +[0002] Length : 0050 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 0000003C + +[0008] Base Address : a0040000 +[0004] Flags (decoded below) : 00000001 + COHACC Override : 1 + HTTU Override : 0 +[0004] Reserved : 00000000 +[0008] VATOS Address : 0 +[0004] Model : 00000002 +[0004] Event Interrupt : 00000000 +[0004] PRI Interrupt : 00000000 +[0004] GERR Interrupt : 00000000 +[0004] Sync Interrupt : 00000000 +/* this is the map for PCIe2 in 1P NA */ +[0004] Input base : 00028000 +[0004] ID Count : 00000800 +[0004] Output Base : 00008000 +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000000 + Single Mapping : 0 + +//144 +/* 2P NB PCIe SMMU */ +[0001] Type : 04 +[0002] Length : 0064 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 0000003C + +[0008] Base Address : 700a0040000 +[0004] Flags (decoded below) : 00000001 + COHACC Override : 1 + HTTU Override : 0 +[0004] Reserved : 00000000 +[0008] VATOS Address : 0 +[0004] Model : 00000002 +[0004] Event Interrupt : 00000000 +[0004] PRI Interrupt : 00000000 +[0004] GERR Interrupt : 00000000 +[0004] Sync Interrupt : 00000000 +/* this is the map for pcie0 in 2p nb */ +[0004] Input base : 00002000 +[0004] Id count : 00001000 +[0004] Output base : 00002000 +[0004] Output reference : 00000064 +[0004] Flags (decoded below) : 00000000 + Single mapping : 0 +/* this is the map for PCIe1 in 2P NB */ +[0004] Input base : 00013000 +[0004] ID Count : 00001000 +[0004] Output Base : 00003000 +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000000 + Single Mapping : 0 + +//1a8 +[088h 0136 1] Type : 04 +[089h 0137 2] Length : 003C +[08Bh 0139 1] Revision : 00 +[08Ch 0140 4] Reserved : 00000000 +[090h 0144 4] Mapping Count : 00000000 +[094h 0148 4] Mapping Offset : 0000003C + +[098h 0152 8] Base Address : 00000000C0040000 +[0A0h 0160 4] Flags (decoded below) : 00000001 + COHACC Override : 1 + HTTU Override : 0 +[0A4h 0164 4] Reserved : 00000000 +[0A8h 0168 8] VATOS Address : 0000000000000000 +[0B0h 0176 4] Model : 00000002 +[0B4h 0180 4] Event GSIV : 00000000 +[0B8h 0184 4] PRI GSIV : 00000000 +[0BCh 0188 4] GERR GSIV : 00000000 +[0C0h 0192 4] Sync GSIV : 00000000 + + +//1e4 +/* 1P NB PCIe SMMU */ +[0001] Type : 04 +[0002] Length : 0050 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 0000003C + +[0008] Base Address : 8a0040000 +[0004] Flags (decoded below) : 00000001 + COHACC Override : 1 + HTTU Override : 0 +[0004] Reserved : 00000000 +[0008] VATOS Address : 0 +[0004] Model : 00000002 +[0004] Event Interrupt : 00000000 +[0004] PRI Interrupt : 00000000 +[0004] GERR Interrupt : 00000000 +[0004] Sync Interrupt : 00000000 +/* this is the map for PCIe0 in 1P NB */ +[0004] Input base : 00008800 +[0004] ID Count : 00000800 +[0004] Output Base : 00008800 +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000000 + Single Mapping : 0 + +//234 +/* 2P NA PCIe SMMU */ +[0001] Type : 04 +[0002] Length : 0050 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 0000003C +[0008] Base Address : 600a0040000 +[0004] Flags (decoded below) : 00000001 + COHACC Override : 1 + HTTU Override : 0 +[0004] Reserved : 00000000 +[0008] VATOS Address : 0 +[0004] Model : 00000002 +[0004] Event Interrupt : 00000000 +[0004] PRI Interrupt : 00000000 +[0004] GERR Interrupt : 00000000 +[0004] Sync Interrupt : 00000000 +/* this is the map for PCIe2 in 2P NA */ +[0004] Input base : 00021000 +[0004] ID Count : 00001000 +[0004] Output Base : 00001000 +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000000 + Single Mapping : 0 /* mbi-gen peri b, named component */ [0001] Type : 01 @@ -414,8 +552,8 @@ [0004] Input base : 00008000 [0004] ID Count : 00000800 -[0004] Output Base : 00008000 -[0004] Output Reference : 00000064 +[0004] Output Base : 00028000 +[0004] Output Reference : 000000f4 [0004] Flags (decoded below) : 00000000 Single Mapping : 0 /* 1P NB PCIe0 */ @@ -443,7 +581,7 @@ [0004] Input base : 00008800 [0004] ID Count : 00000800 [0004] Output Base : 00008800 -[0004] Output Reference : 0000007c +[0004] Output Reference : 000001e4 [0004] Flags (decoded below) : 00000000 Single Mapping : 0 @@ -556,8 +694,8 @@ [0004] Input base : 00001000 [0004] ID Count : 00001000 -[0004] Output Base : 00001000 -[0004] Output Reference : 000000c4 +[0004] Output Base : 00021000 +[0004] Output Reference : 00000234 [0004] Flags (decoded below) : 00000000 Single Mapping : 0 @@ -586,7 +724,7 @@ [0004] Input base : 00002000 [0004] ID Count : 00001000 [0004] Output Base : 00002000 -[0004] Output Reference : 000000dc +[0004] Output Reference : 00000144 [0004] Flags (decoded below) : 00000000 Single Mapping : 0 @@ -614,8 +752,8 @@ [0004] Input base : 00003000 [0004] ID Count : 00001000 -[0004] Output Base : 00003000 -[0004] Output Reference : 000000dc +[0004] Output Base : 00013000 +[0004] Output Reference : 00000144 [0004] Flags (decoded below) : 00000000 Single Mapping : 0 @@ -649,3 +787,164 @@ [0004] Output Reference : 000000c4 [0004] Flags (decoded below) : 00000001 Single Mapping : 1 + +[320h 0800 1] Type : 01 +[321h 0801 2] Length : 0040 +[323h 0803 1] Revision : 00 +[324h 0804 4] Reserved : 00000000 +[328h 0808 4] Mapping Count : 00000001 +[32Ch 0812 4] Mapping Offset : 0000002C + +[330h 0816 4] Node Flags : 00000000 +[334h 0820 8] Memory Properties : [IORT Memory Access Properties] +[334h 0820 4] Cache Coherency : 00000000 +[338h 0824 1] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[339h 0825 2] Reserved : 0000 +[33Bh 0827 1] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[33Ch 0828 1] Memory Size Limit : 00 +[33Dh 0829 11] Device Name : "\_SB_.USB0" +[348h 0840 24] Padding : \ + 00 00 00 00 00 00 00 00 01 00 00 00 80 00 04 00 \ + 4C 00 00 00 01 00 00 00 + +[34Ch 0844 4] Input base : 00000000 +[350h 0848 4] ID Count : 00000001 +[354h 0852 4] Output Base : 00040080 +[358h 0856 4] Output Reference : 000000F4 +[35Ch 0860 4] Flags (decoded below) : 00000001 + Single Mapping : 1 + +[360h 0864 1] Type : 01 +[361h 0865 2] Length : 0040 +[363h 0867 1] Revision : 00 +[364h 0868 4] Reserved : 00000000 +[368h 0872 4] Mapping Count : 00000001 +[36Ch 0876 4] Mapping Offset : 0000002C + +[370h 0880 4] Node Flags : 00000000 +[374h 0884 8] Memory Properties : [IORT Memory Access Properties] +[374h 0884 4] Cache Coherency : 00000000 +[378h 0888 1] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[379h 0889 2] Reserved : 0000 +[37Bh 0891 1] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[37Ch 0892 1] Memory Size Limit : 00 +[37Dh 0893 11] Device Name : "\_SB_.SAS0" +[388h 0904 24] Padding : \ + 00 00 00 00 00 00 00 00 01 00 00 00 00 01 00 00 \ + 88 00 00 00 01 00 00 00 + +[38Ch 0908 4] Input base : 00000000 +[390h 0912 4] ID Count : 00000001 +[394h 0916 4] Output Base : 00040900 +[398h 0920 4] Output Reference : 000001a8 +[39Ch 0924 4] Flags (decoded below) : 00000001 + Single Mapping : 1 + +[3A0h 0928 1] Type : 01 +[3A1h 0929 2] Length : 0040 +[3A3h 0931 1] Revision : 00 +[3A4h 0932 4] Reserved : 00000000 +[3A8h 0936 4] Mapping Count : 00000001 +[3ACh 0940 4] Mapping Offset : 0000002C + +[3B0h 0944 4] Node Flags : 00000000 +[3B4h 0948 8] Memory Properties : [IORT Memory Access Properties] +[3B4h 0948 4] Cache Coherency : 00000000 +[3B8h 0952 1] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[3B9h 0953 2] Reserved : 0000 +[3BBh 0955 1] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[3BCh 0956 1] Memory Size Limit : 00 +[3BDh 0957 11] Device Name : "\_SB_.SAS1" +[3C8h 0968 24] Padding : \ + 00 00 00 00 00 00 00 00 01 00 00 00 00 00 04 00 \ + 4C 00 00 00 01 00 00 00 + +[3CCh 0972 4] Input base : 00000000 +[3D0h 0976 4] ID Count : 00000001 +[3D4h 0980 4] Output Base : 00040000 +[3D8h 0984 4] Output Reference : 000000F4 +[3DCh 0988 4] Flags (decoded below) : 00000001 + Single Mapping : 1 + +[3E0h 0992 1] Type : 01 +[3E1h 0993 2] Length : 0040 +[3E3h 0995 1] Revision : 00 +[3E4h 0996 4] Reserved : 00000000 +[3E8h 1000 4] Mapping Count : 00000001 +[3ECh 1004 4] Mapping Offset : 0000002C + +[3F0h 1008 4] Node Flags : 00000000 +[3F4h 1012 8] Memory Properties : [IORT Memory Access Properties] +[3F4h 1012 4] Cache Coherency : 00000000 +[3F8h 1016 1] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[3F9h 1017 2] Reserved : 0000 +[3FBh 1019 1] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[3FCh 1020 1] Memory Size Limit : 00 +[3FDh 1021 11] Device Name : "\_SB_.SAS2" +[408h 1032 24] Padding : \ + 00 00 00 00 00 00 00 00 01 00 00 00 40 00 04 00 \ + 4C 00 00 00 01 00 00 00 + +[40Ch 1036 4] Input base : 00000000 +[410h 1040 4] ID Count : 00000001 +[414h 1044 4] Output Base : 00040040 +[418h 1048 4] Output Reference : 000000F4 +[41Ch 1052 4] Flags (decoded below) : 00000001 + Single Mapping : 1 + +/*HNS smmu*/ +[420h 1056 1] Type : 01 +[421h 1057 2] Length : 0040 +[423h 1059 1] Revision : 00 +[424h 1060 4] Reserved : 00000000 +[428h 1064 4] Mapping Count : 00000001 +[42Ch 1068 4] Mapping Offset : 0000002C + +[430h 1072 4] Node Flags : 00000000 +[434h 1076 8] Memory Properties : [IORT Memory Access Properties] +[434h 1076 4] Cache Coherency : 00000000 +[438h 1080 1] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[439h 1081 2] Reserved : 0000 +[43Bh 1083 1] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[43Ch 1084 1] Memory Size Limit : 00 +[43Dh 1085 11] Device Name : "\_SB_.DSF0" +[448h 1096 24] Padding : \ + 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 \ + 94 01 00 00 01 00 00 00 + +[44Ch 1100 4] Input base : 00000000 +[450h 1104 4] ID Count : 00000001 +[454h 1108 4] Output Base : 00000000 +[458h 1112 4] Output Reference : 000001a8 +[45Ch 1116 4] Flags (decoded below) : 00000001 + Single Mapping : 1 From patchwork Tue Sep 19 13:56:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 112997 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp4968672qgf; Tue, 19 Sep 2017 07:13:00 -0700 (PDT) X-Received: by 10.200.27.235 with SMTP id m40mr2292370qtk.228.1505830379887; Tue, 19 Sep 2017 07:12:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505830379; cv=none; d=google.com; s=arc-20160816; b=LzmpVPa7JDhiUjVCwkPDRY4caFyW38djoJV7fSwvXS1AnRGIkKb9Dl8RhNGamQTKau 1OPIRstFrYS4Htp57aCs8nfbPipulwraph/dttymwMv/9gR/uCs3EqPEbiWWOdPrxHfF BxX4//5M0TSsCpy2BxXD1GcZjJoSoXvqX6muRJXYC3QodHkDgGe2zOgE6xzN6COqC5TO Zj9h8dpZZPKAOnZydAWTLOVnf/7F40S56IhS4FX3sprSA6Am7Ksn5WouuSp3iCb6WRqI utE8/QeYmaT2D8OC5myiSzVnKzVxAAiAh+ZY0trwS1J7wpwCeTbv3ZuZj8SQRo52LaqY pM6A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; 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[54.225.227.206]) by mx.google.com with ESMTP id u128si2549643qkc.424.2017.09.19.07.12.59; Tue, 19 Sep 2017 07:12:59 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 6F14762D0D; Tue, 19 Sep 2017 14:12:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, RCVD_IN_SORBS_SPAM, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 4B3FA62D32; Tue, 19 Sep 2017 14:09:56 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 344EB62C6C; Tue, 19 Sep 2017 14:05:44 +0000 (UTC) Received: from mail-pg0-f46.google.com (mail-pg0-f46.google.com [74.125.83.46]) by lists.linaro.org (Postfix) with ESMTPS id 5F32962CF0 for ; Tue, 19 Sep 2017 14:05:23 +0000 (UTC) Received: by mail-pg0-f46.google.com with SMTP id 7so2041824pgd.13 for ; Tue, 19 Sep 2017 07:05:23 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=50Amd3U5hbPlrZBvzYD98IG5lVFdMIcFFEtpew74l1o=; b=UE70gEvsl5eGSo7DWBTZ9TC+34o4mgjFcbTfbci8wF5+cEiK0SUtnQ0onErYDOALUe SJrI+5FHRCSCSvQWdZbd67SXC7zbnEIXxayt//qlhAOolmN0Tk9QpkM/p3PAS6a55mDR MNA0jHL3HkeDGrWbH5NeIzT4nK/Qp+hU3ewQQCKAnsIZBPgJPD09BbH1YqCc50p6HGfz qqxepMVOwyN5rjlskC3IFCbl72TZSbxKzuNx/wPRv4ZKwFb/MFy3xWdnuKAZgu6MN37L qEZs/FnlefvoRZQInb8LIgpdsGCf3AhYtyI2FVBKC7vcS7MDGJCUY7NOa1VrEkr7v2Bo v5DA== X-Gm-Message-State: AHPjjUiOq+dJ6DX3uIbPB0ILlhInopDMrQTqgfHrqoyDy/grwZwLCiak c3piEVZlXTmaertiFb9Xo8JiKCTi X-Google-Smtp-Source: AOwi7QCN5JaWBNyjmI+5A4CDIrsTcutdqU6Kb2dJaX7ecmvaLP7vYXDj0vSi6POK3sIrDsHbd/ygkA== X-Received: by 10.84.179.67 with SMTP id a61mr1415633plc.230.1505829922698; Tue, 19 Sep 2017 07:05:22 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id 13sm4390439pfm.138.2017.09.19.07.05.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 19 Sep 2017 07:05:22 -0700 (PDT) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, graeme.gregory@linaro.org Date: Tue, 19 Sep 2017 21:56:17 +0800 Message-Id: <1505829398-52214-12-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1505829398-52214-1-git-send-email-heyi.guo@linaro.org> References: <1505829398-52214-1-git-send-email-heyi.guo@linaro.org> Cc: huangming23@huawei.com, zhangjinsong2@huawei.com, guoheyi@huawei.com, Chenhui Sun , wanghuiqiang@huawei.com Subject: [Linaro-uefi] [linaro-uefi v1 11/32] Hisilicon D05: add dbg2 table X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: "For discussions about Linaro-related UEFI development. Not a substitute for edk2-devel." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" From: Chenhui Sun Change-Id: Icf98e5cbf43c837e634fb37407da179d060be692 Signed-off-by: Chenhui Sun --- .../Hi1616/D05AcpiTables/AcpiTablesHi1616.inf | 2 + Chips/Hisilicon/Hi1616/D05AcpiTables/Dbg2.aslc | 86 ++++++++++++++++++++++ Platforms/Hisilicon/D05/D05.dsc | 2 + 3 files changed, 90 insertions(+) create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dbg2.aslc diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf b/Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf index 5e8f14d..9876a50 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf @@ -36,6 +36,7 @@ D05Slit.aslc D05Srat.aslc D05Spcr.aslc + Dbg2.aslc [Packages] ArmPkg/ArmPkg.dec @@ -55,5 +56,6 @@ gArmTokenSpaceGuid.PcdArmArchTimerIntrNum gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dbg2.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dbg2.aslc new file mode 100644 index 0000000..fb55a07 --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dbg2.aslc @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2017 Linaro Limited + * Copyright (c) 2017 Hisilicon Limited + * + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the BSD License which accompanies + * this distribution, and is available at + * http://opensource.org/licenses/bsd-license.php + * +*/ + +#include +#include +#include +#include +#include "Hi1616Platform.h" + +#define NUMBER_DEBUG_DEVICE_INFO 1 +#define NUMBER_OF_GENERIC_ADDRESS 1 +#define NAMESPACE_STRING_SIZE 8 +#define UART_LENGTH 0x1000 + +#pragma pack(1) + +typedef struct { + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT DdiHeader; + EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE Address[NUMBER_OF_GENERIC_ADDRESS]; + UINT32 AddressSize[NUMBER_OF_GENERIC_ADDRESS]; + CHAR8 NamespaceString[NAMESPACE_STRING_SIZE]; +} EFI_ACPI_DBG2_DDI_STRUCT; + +typedef struct { + EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE Desc; + EFI_ACPI_DBG2_DDI_STRUCT Ddi[NUMBER_DEBUG_DEVICE_INFO]; +} EFI_ACPI_DEBUG_PORT_2_TABLE; + +#pragma pack() + +EFI_ACPI_DEBUG_PORT_2_TABLE Dbg2 = { + { + ARM_ACPI_HEADER( + EFI_ACPI_6_1_DEBUG_PORT_2_TABLE_SIGNATURE, + EFI_ACPI_DEBUG_PORT_2_TABLE, + EFI_ACPI_DEBUG_PORT_2_TABLE_REVISION + ), + OFFSET_OF(EFI_ACPI_DEBUG_PORT_2_TABLE, Ddi), + NUMBER_DEBUG_DEVICE_INFO + }, + { + { + { + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION, + sizeof(EFI_ACPI_DBG2_DDI_STRUCT), + NUMBER_OF_GENERIC_ADDRESS, + NAMESPACE_STRING_SIZE, + OFFSET_OF(EFI_ACPI_DBG2_DDI_STRUCT, NamespaceString), + 0, //OemDataLength + 0, //OemDataOffset + EFI_ACPI_DBG2_PORT_TYPE_SERIAL, + EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_FULL_16550, + {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE}, + OFFSET_OF(EFI_ACPI_DBG2_DDI_STRUCT, Address), + OFFSET_OF(EFI_ACPI_DBG2_DDI_STRUCT, AddressSize), + }, + { + { + EFI_ACPI_6_1_SYSTEM_MEMORY, + 32, + 0, + EFI_ACPI_6_1_BYTE, + FixedPcdGet64 (PcdSerialDbgRegisterBase) + } + }, + { + UART_LENGTH + }, + "COM1" + } + } +}; + +// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Dbg2; diff --git a/Platforms/Hisilicon/D05/D05.dsc b/Platforms/Hisilicon/D05/D05.dsc index ffa1897..8191459 100644 --- a/Platforms/Hisilicon/D05/D05.dsc +++ b/Platforms/Hisilicon/D05/D05.dsc @@ -179,6 +179,8 @@ # use the TTY terminal type (which has a working backspace) gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4 + ## Serial Debug UART + gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|0xD00C0000 gHisiTokenSpaceGuid.PcdM3SmmuBaseAddress|0xa0040000 gHisiTokenSpaceGuid.PcdPcieSmmuBaseAddress|0xb0040000 From patchwork Tue Sep 19 13:56:18 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 113002 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp4971507qgf; Tue, 19 Sep 2017 07:15:07 -0700 (PDT) X-Received: by 10.55.160.88 with SMTP id j85mr2162534qke.113.1505830507053; Tue, 19 Sep 2017 07:15:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505830507; cv=none; d=google.com; s=arc-20160816; b=PmkWSNm7bdSPuDqEEL2zzZLh7Cy+ah5Q2PHWvc+vHgePq3J7ljrz8bmnMjcx9ctxMc 7HNnEVGOZn26WP+cRBfY1dvBW/OV1GvYPU/Dzh+Hol6IS62HA39a8iGcCdVvqzvZ6FO8 5drOi7lUo8iHqS1VAziV3V60DQK0Ys9Xr1WuxK+VBWCEYGulfCqMSGeIL1K8iTapnKo9 vT3Xen03KJm+yt1Sl/MF3X/LP7xq0eT48CeExqvSaXxIl2RSZ1iim+H/+F6ojpP+7FKB rYO9EoIk+RKukKk2e9IRNoV9tqpJPxTMF/hSQeXGzbXD8KbY9Qdtfpahe/r2l4dJsPfA k3zQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:delivered-to:arc-authentication-results; bh=wDNMTp0OJCFLX1qaB/Z2tQLhelTxgAXL5c7DBGo1O+A=; b=wgCm1DcMzHgbzP2TpFDSM2weKtYWc98Ig/NLD/dFuxbfPzFMYqAJ2okYfTj3gZpSQn FSE6TBNfyTXz9l8OBAhR1Jzj0TM46swOe3YZV4Qq3jmDgcmdOYJ4Z10B++CVu0P2XIaW eNVcfgGsx+lX0ED3XA7sluYxkOWl8GDNlWrxG6h8H2kKvQ5MkUPVYZ+E0x/B73yE0mDF 0iQvzH6m/5/1w84Q81cV9rGF0stmF7cYjaMSem9gG+znXIEX9lONtgu9jiu5Lw0h/w3s UUT+qc2MgoQw4KLRoStSjEFjQHgAQibW56bLQOwqCyJ0vzt9XpwV2cSgmIZ/eQD7LMnE 51+A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id k62si9134895qkb.492.2017.09.19.07.15.06; Tue, 19 Sep 2017 07:15:07 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 8DE4F62D1B; Tue, 19 Sep 2017 14:15:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, RCVD_IN_SORBS_SPAM, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 27B0D62F1C; Tue, 19 Sep 2017 14:10:29 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 73C3162CE2; Tue, 19 Sep 2017 14:05:51 +0000 (UTC) Received: from mail-pf0-f182.google.com (mail-pf0-f182.google.com [209.85.192.182]) by lists.linaro.org (Postfix) with ESMTPS id 026C362CFA for ; Tue, 19 Sep 2017 14:05:26 +0000 (UTC) Received: by mail-pf0-f182.google.com with SMTP id d187so28615pfg.11 for ; Tue, 19 Sep 2017 07:05:25 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BOWpWyonPQnh3zuz2/OjETGCg9YULg6xOjp4pkr9t1g=; b=NOWIOJxEmdzkVnl+uniHjreW4Iywk8PinGEtdUaO0C6nA1MoVNOafFTzU+Waw9RO+D 05Jl9RX88WZBrRZxXooaxa9rdlY1m0Wwi/2YHO3LXwzFub1GrIyPcdCSUC7F7CENldx1 LLngL3hQhXjgm2wkHd8TEPQvqHp9VEEe3hG2686AyAvCzbkFMiiRl5GZG8HpCMmqUkd5 ekhwmP6aHVAj/IAaJLQhZVZzSRfvsRU/gcFcuqh7LaBRiQv/9ai60Lue5KwpumEjChN9 ql3VjxSslYrllY2OjQCWlvgfvU/S8ZEEu9dvZQVDu2KAGsqvO3Dn2Jb3LQm+JOcIBMJr HiyQ== X-Gm-Message-State: AHPjjUi6OFI4KGqVxh3zW82aKFgIQcro07LeStYk86MLClLH1ybtx4mj GBEZHV6E2vQCym+D1fe4l5GN+LVb X-Google-Smtp-Source: AOwi7QA08oz4emDCNDG4KNcmwaUpZZKV7+KyBFiDNe/XjMGiFym5WsY/PFRn3qqyWgigbSDS2kyDbQ== X-Received: by 10.99.99.197 with SMTP id x188mr1450270pgb.421.1505829925123; Tue, 19 Sep 2017 07:05:25 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id 13sm4390439pfm.138.2017.09.19.07.05.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 19 Sep 2017 07:05:24 -0700 (PDT) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, graeme.gregory@linaro.org Date: Tue, 19 Sep 2017 21:56:18 +0800 Message-Id: <1505829398-52214-13-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1505829398-52214-1-git-send-email-heyi.guo@linaro.org> References: <1505829398-52214-1-git-send-email-heyi.guo@linaro.org> Cc: huangming23@huawei.com, Yan Zhang , zhangjinsong2@huawei.com, guoheyi@huawei.com, wanghuiqiang@huawei.com Subject: [Linaro-uefi] [linaro-uefi v1 12/32] Disable PCIE ASPM X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: "For discussions about Linaro-related UEFI development. Not a substitute for edk2-devel." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" From: Yan Zhang In order to replace command line parameter pcie_aspm=off, BIOS needs to disable Pcie Aspm support during Pcie initilization. Change-Id: Ie58f0616563318a86f2248e8eb5de29bf2c621c6 Signed-off-by: Yan Zhang --- .../Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 70 ++++++++++++++++++++++ .../Hi1610/Drivers/PcieInit1610/PcieInitLib.h | 2 + Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h | 2 + 3 files changed, 74 insertions(+) diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c index 8ab7fa3..e30f5d7 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c @@ -1077,6 +1077,73 @@ DisableRcOptionRom ( return; } +VOID +PcieDbiCs2Enable( + IN UINT32 HostBridgeNum, + IN UINT32 Port, + IN BOOLEAN Val + ) +{ + UINT32 RegVal; + RegRead (PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE_SYS_CTRL21, RegVal); + if (Val) { + RegVal = RegVal | BIT2; + /*BIT2: DBI Chip Select indicator. 0 indicates CS, 1 indicates CS2.*/ + } else { + RegVal = RegVal & (~BIT2); + } + RegWrite (PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE_SYS_CTRL21, RegVal); +} + +BOOLEAN +PcieDBIReadOnlyWriteEnable( + IN UINT32 HostBridgeNum, + IN UINT32 Port + ) +{ + UINT32 Val; + RegRead (PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_DBI_READ_ONLY_WRITE_ENABLE, Val); + if (Val == 0x1) { + return TRUE; + } else { + RegWrite (PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_DBI_READ_ONLY_WRITE_ENABLE, 0x1); + /*Delay 10us to make sure the PCIE device have enouph time to response. */ + MicroSecondDelay(10); + RegRead (PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_DBI_READ_ONLY_WRITE_ENABLE, Val); + if (Val == 0x1) { + return TRUE; + } + } + DEBUG ((DEBUG_ERROR,"PcieDBIReadOnlyWriteEnable Fail!!!\n")); + return FALSE; +} +VOID +PcieASPMSupportDisable( + IN UINT32 HostBridgeNum, + IN UINT32 Port, + IN UINT8 Val + ) +{ + PCIE_EP_PCIE_CAP3_U pcie_cap3; + if (Port >= PCIE_MAX_ROOTBRIDGE) { + DEBUG ((DEBUG_ERROR,"Port is not valid\n")); + return; + } + if (!PcieDBIReadOnlyWriteEnable (HostBridgeNum, Port)) { + DEBUG ((DEBUG_INFO,"PcieDeEmphasisLevelSet ReadOnly Reg do not Enable!!!\n")); + return; + } + PcieDbiCs2Enable (HostBridgeNum, Port, FALSE); + + RegRead (PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_EP_PCIE_CAP3_REG, pcie_cap3.UInt32); + pcie_cap3.Bits.active_state_power_management = Val; + RegWrite (PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_EP_PCIE_CAP3_REG, pcie_cap3.UInt32); + RegRead (PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_EP_PCIE_CAP3_REG, pcie_cap3.UInt32); + DEBUG ((DEBUG_INFO,"ASPI active state power management: %d\n", pcie_cap3.Bits.active_state_power_management)); + + PcieDbiCs2Enable (HostBridgeNum, Port, TRUE); +} + EFI_STATUS EFIAPI PciePortInit ( @@ -1134,6 +1201,9 @@ PciePortInit ( /* disable link up interrupt */ (VOID)PcieMaskLinkUpInit(soctype, HostBridgeNum, PortIndex); + //disable ASPM + PcieASPMSupportDisable (HostBridgeNum, PortIndex, PCIE_ASPM_DISABLE); + /* Pcie Equalization*/ (VOID)PcieEqualization(soctype ,HostBridgeNum, PortIndex); diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h index 9a0f636..e96c53c 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h @@ -77,6 +77,8 @@ #define RegWrite(addr,data) MmioWrite32((addr), (data)) #define RegRead(addr,data) ((data) = MmioRead32 (addr)) +#define PCIE_ASPM_DISABLE 0x0 +#define PCIE_ASPM_ENABLE 0x1 typedef struct tagPcieDebugInfo { diff --git a/Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h b/Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h index bf57652..c8b9781 100644 --- a/Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h +++ b/Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h @@ -135,6 +135,7 @@ #define PCIE_EEP_PORTLOGIC53_REG (0x888) #define PCIE_EEP_GEN3_CONTRL_REG (0x890) #define PCIE_EEP_PIPE_LOOPBACK_REG (0x8B8) +#define PCIE_DBI_READ_ONLY_WRITE_ENABLE (0x8BC) #define PCIE_EEP_PORTLOGIC54_REG (0x900) #define PCIE_EEP_PORTLOGIC55_REG (0x904) #define PCIE_EEP_PORTLOGIC56_REG (0x908) @@ -12556,6 +12557,7 @@ typedef union tagPortlogic93 #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG (PCIE_SUBCTRL_BASE + 0x1018) #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY6_REG (PCIE_SUBCTRL_BASE + 0x101C) #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY7_REG (PCIE_SUBCTRL_BASE + 0x1020) +#define PCIE_SUBCTRL_SC_PCIE_SYS_CTRL21 (PCIE_SUBCTRL_BASE + 0x1024) #define PCIE_SUBCTRL_SC_DISPATCH_RETRY_CONTROL_REG (PCIE_SUBCTRL_BASE + 0x1030) #define PCIE_SUBCTRL_SC_DISPATCH_INTMASK_REG (PCIE_SUBCTRL_BASE + 0x1100) #define PCIE_SUBCTRL_SC_DISPATCH_RAWINT_REG (PCIE_SUBCTRL_BASE + 0x1104) From patchwork Tue Sep 19 13:56:19 2017 Content-Type: text/plain; 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[54.225.227.206]) by mx.google.com with ESMTP id j65si8005610iod.89.2017.09.19.07.13.27; Tue, 19 Sep 2017 07:13:27 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id EB23862D0E; Tue, 19 Sep 2017 14:13:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 7A3E762D29; Tue, 19 Sep 2017 14:10:00 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 3C62F62C6C; Tue, 19 Sep 2017 14:05:45 +0000 (UTC) Received: from mail-pf0-f175.google.com (mail-pf0-f175.google.com [209.85.192.175]) by lists.linaro.org (Postfix) with ESMTPS id 6D7F962D08 for ; Tue, 19 Sep 2017 14:05:28 +0000 (UTC) Received: by mail-pf0-f175.google.com with SMTP id z84so40222pfi.2 for ; Tue, 19 Sep 2017 07:05:28 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ahyqqh6wnyJxaspl9s629EhBkkcnalBet1K0YRy669c=; b=fS78ZgZLE7FdOeW6pdLDGBklt3EjdtD6hh9OGJnpJqXuWM2wYC3pGvASo/Eo1Vxbfo uxtbtiZcAVTRJ6dhhSUfZQWeY5CZ1KpcFFQ6xhbj1uK4U3SZSVj8qB87ZqrtKpZQOry0 KZqfAWV/+vrtYOJ/AP2CS6RftmJpX/Vjkrn4bF54L1OgdCyKIF7HIlTaRZeVY3Q1C7Rp WoPFfcZebVqyCYxBrtb1rSc3mHsg7CNhs9ZDjs2Jk549KsegnVuiBMMY2tO8P6tEK/nj xB1se7lAJTaMs4xEttcRzd79OsOrifqfyqdvYWZwj2cT/evXy3UEjnuvgke5QXTS1Hnm kFmQ== X-Gm-Message-State: AHPjjUiMm5sP2ElwdgBVdNQ1VW5njn6ZrneiaTRNSq81ZWX7pWCSkNhr Fm6Obdxbfb9jvediY3hvJoGmHQPbG18/fg== X-Google-Smtp-Source: AOwi7QDXSpVQ28nwWfLyC2KVaw8g0f6odmD1TjDoFM8wXw5t06dgd6MZ5JntQN53/NaSyTbPkn/FYg== X-Received: by 10.99.109.65 with SMTP id i62mr1407416pgc.83.1505829927792; Tue, 19 Sep 2017 07:05:27 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id 13sm4390439pfm.138.2017.09.19.07.05.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 19 Sep 2017 07:05:27 -0700 (PDT) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, graeme.gregory@linaro.org Date: Tue, 19 Sep 2017 21:56:19 +0800 Message-Id: <1505829398-52214-14-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1505829398-52214-1-git-send-email-heyi.guo@linaro.org> References: <1505829398-52214-1-git-send-email-heyi.guo@linaro.org> Cc: huangming23@huawei.com, Chenhui Sun , zhangjinsong2@huawei.com, guoheyi@huawei.com, wanghuiqiang@huawei.com Subject: [Linaro-uefi] [linaro-uefi v1 13/32] Hisilicon/D05: fix vga emulation fail issue X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: "For discussions about Linaro-related UEFI development. Not a substitute for edk2-devel." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" From: Chenhui Sun This is a temporary program, need continue to investigate the root cause. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chenhui Sun --- Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 7 +++++++ 1 file changed, 7 insertions(+) // detected multiple times. We work around this by faking absent diff --git a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c index 8dfb4b9..2effd7c 100644 --- a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c @@ -1770,6 +1770,13 @@ RootBridgeIoPciRead ( return EFI_INVALID_PARAMETER; } + if ((EfiPciAddress->Bus == 0x81) && (PrivateData->MemBase == 0xAA000000) && (EfiPciAddress->Device > 0)) { + return EFI_NOT_FOUND; + } + if ((EfiPciAddress->Bus == 0x91) && (EfiPciAddress->Device > 0)) { + return EFI_NOT_FOUND; + } + // The UEFI PCI enumerator scans for devices at all possible addresses, // and ignores some PCI rules - this results in some hardware being From patchwork Tue Sep 19 13:56:20 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 113001 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp4971010qgf; Tue, 19 Sep 2017 07:14:43 -0700 (PDT) X-Received: by 10.129.174.94 with SMTP id g30mr1096635ywk.153.1505830482927; Tue, 19 Sep 2017 07:14:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505830482; cv=none; d=google.com; s=arc-20160816; b=i8WlC7iyX7J7dDtkjS6PNDvs/h8X1jRGLGAWX353ETQ1OJIYaMGMET12XiIbOPqNIR Wnlw9fMrxqeKre+ymG/WCkJSMlHVB+zVBPn+P0aer49emDui9/wOuuinMqb6oZGhNaMp Kir7TdCWO1nQ0MDHB5G5jsqbvQvbUcmV9ArbV+0VEkbO/wQKU9v+MdZ+634HidRCsZL1 l6qDhpGd0rtM47ORCZAOpkvr47Ky4NYjSjWV9Tttp1Kso1Zp34CtgsjPkXJnhAL6w+hU ZZqLmvTn0/pYMHR5yr94l3yLF3q3nIq/0f9P3VjJW+vnLpvu5iutUyVyThx3eW9s+BbS zc8Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:delivered-to:arc-authentication-results; bh=mQwsUqngHaEMKtsCNDKzLFgN/HwtkfBNng9Kzff7qvw=; b=sssCQyKzzlKnZR6ilP+0bZ3P5t5ZWn12eVSqyP7ktzj0AecODGhiYxhBdOESlQ0uQL kmt02t31uHPYP3048mS31ctQAF7kDohOmj/uv1VeJKY5ZRSHUlojkrE9JZohXHb5b+lP lmbR5gUrVGR3oX9VhOSBkPNDjJOfIBJUxlJ7ti0B0jCV2rbswSn4U8YmgpzKqFlet5KR c4DZ1zRDyzHLpG5RJ7fOLqPPRjRfn9DLfl2DkgqPQdf3qHD67Ql7iSoJWdPIsEzQHumV RjdGL9QcrJzGIb6tEMJFSYLKxTX4b/tcdmizl9RNAG9DBzpDlr64/SygWYYvTBrSqkvE 7gVg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.linaro.org (lists.linaro.org. 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Not a substitute for edk2-devel." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" From: Chenhui Sun Signed-off-by: Chenhui Sun --- Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl index 420cd20..9ab164f 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl @@ -213,10 +213,10 @@ [0004] PRI Interrupt : 00000000 [0004] GERR Interrupt : 00000000 [0004] Sync Interrupt : 00000000 -/* this is the map for PCIe0 in 1P NB */ -[0004] Input base : 00008800 +/* this is the map for PCIe1 in 1P NB */ +[0004] Input base : 00010000 [0004] ID Count : 00000800 -[0004] Output Base : 00008800 +[0004] Output Base : 00000000 [0004] Output Reference : 00000064 [0004] Flags (decoded below) : 00000000 Single Mapping : 0 @@ -581,7 +581,7 @@ [0004] Input base : 00008800 [0004] ID Count : 00000800 [0004] Output Base : 00008800 -[0004] Output Reference : 000001e4 +[0004] Output Reference : 0000007c [0004] Flags (decoded below) : 00000000 Single Mapping : 0 @@ -609,8 +609,8 @@ [0004] Input base : 00000000 [0004] ID Count : 00000800 -[0004] Output Base : 00000000 -[0004] Output Reference : 0000007c +[0004] Output Base : 00010000 +[0004] Output Reference : 000001e4 [0004] Flags (decoded below) : 00000000 Single Mapping : 0 From patchwork Tue Sep 19 13:56:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 113005 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp4973331qgf; Tue, 19 Sep 2017 07:16:22 -0700 (PDT) X-Received: by 10.55.103.14 with SMTP id b14mr2088979qkc.267.1505830582654; Tue, 19 Sep 2017 07:16:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505830582; cv=none; d=google.com; s=arc-20160816; b=fdrhbabXfJr3UejzJpiI3aTZDGZKuMbosYy9d4p3QXwtbsp8z/YsFr74j2gjQvhppP Dcc4ObugS982tvT67DxDbVcqeXiACdE0QA9K1On4hM2FT+/uYpfHw0xjC4ybRL9rkIdq KQDa3mEsTmDPyYZ5e9Zzrv2WuO+meKCLNLT9h8F+zrLPcygVH8tP6+TIfMMNCLl2HQID D/wSkN4Ss8Q15hKVMEOTEh+LM40RJ5InRK0xBkcsRCvNjIIPGLS0KodL0/US3zSITGn8 9zUSsArvKcvc8ZoqxTv11uoUMsmsddaEpb8SSCRsaSTOkK69EkhASsAqaDADPfRmQy9e UJpw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:delivered-to:arc-authentication-results; bh=Ih97Lr2J3TysE0lLXZyXSJI28pKb25yNEoBn2XQiB10=; b=GkJZaa0VaPZ6++eRauDxQ4Er0Rpnq+02s/FR9jZZsdgBDew2kAOHgmjWAOkWPpE6fV ZlEQFGcTJh8BdvE/N4QTsYpjlOhD6adJFDf0vRSOPEvTJxwkyn6UOyFQ4XPTBB97azRH EQ1Ak2DeLLB1/A3/UiRs5o8KaiXuGfs7Z+dXX/NqH0sKHBSJAB0s6Z2ZzTGgfwAfl4ol K6SW7CABF9gafzadSkDo7/UMuFbytYAyLxFsjyETTU2wiHh9jGoxe6n9xVxmNV3eJz1o PKlos9oGQfvOSpuJVoMw74hWJFvaRJKsNtIq4XwikPQRodps6cFjpQc53Ttbka8W58AC drGQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id o5si947078qkh.26.2017.09.19.07.16.22; Tue, 19 Sep 2017 07:16:22 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 5301A6064E; Tue, 19 Sep 2017 14:16:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 9D3AB63CB2; Tue, 19 Sep 2017 14:10:50 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 3C3CB62CF0; Tue, 19 Sep 2017 14:05:59 +0000 (UTC) Received: from mail-pg0-f43.google.com (mail-pg0-f43.google.com [74.125.83.43]) by lists.linaro.org (Postfix) with ESMTPS id D151562C59 for ; Tue, 19 Sep 2017 14:05:33 +0000 (UTC) Received: by mail-pg0-f43.google.com with SMTP id b11so2044651pgn.12 for ; Tue, 19 Sep 2017 07:05:33 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=gV4CJmIZo03MZbX5oKLNh8/3wFyjBPsVIHsjvb+G4XY=; b=X1o3gqgxI7Sa2PE/93JdzCqOgY0tzG2cEFzFwOymbWsLRGPKxTss4/26tyA+yhZgEz pmePdilBIV4TiNS4e7PN/nzOxvhiz1WnZz2Z8AMHpX9AB8LO0aizkFdnCGLhc+ghmRqt f8pA3ChQoR+Nf7nFnFtffVulD8/BWxOUgVA9c2Q/SA65EuvUT+RLjC4GncyJhYCbtVgC vQp2dTRXH7mjJ/eWQZGhoa3th0Utxuwt7E1ENNCtD/1nKy752LfKHYdMHjCz4zYovPJT XH/UIiS7fP9cWXiUzJJftN/CUNyGStp9E7kezeL1TqJj4Yx+1ZL7T8OV6mm54KN6kH5A qSYw== X-Gm-Message-State: AHPjjUhMONvTSwQXe953n+zt7VpY3oa+FEMglgQV7kXprLhqujdGtjo5 QocQvLF0c5oYQBRxglI8/P2mr2T3wQGrZQ== X-Google-Smtp-Source: AOwi7QDAQdeCEKDGe6sx378wchW1/uyckBsk4dFss02HCf0VvDEVxevjBMkO42uElz3FQJdBNacJ8Q== X-Received: by 10.84.234.2 with SMTP id m2mr1428472plk.391.1505829933007; Tue, 19 Sep 2017 07:05:33 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id 13sm4390439pfm.138.2017.09.19.07.05.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 19 Sep 2017 07:05:32 -0700 (PDT) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, graeme.gregory@linaro.org Date: Tue, 19 Sep 2017 21:56:21 +0800 Message-Id: <1505829398-52214-16-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1505829398-52214-1-git-send-email-heyi.guo@linaro.org> References: <1505829398-52214-1-git-send-email-heyi.guo@linaro.org> Cc: Ming Huang , zhangjinsong2@huawei.com, huangming23@huawei.com, guoheyi@huawei.com, Chenhui Sun , wanghuiqiang@huawei.com Subject: [Linaro-uefi] [linaro-uefi v1 15/32] Hisilicon D03: support APEI feature X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: "For discussions about Linaro-related UEFI development. Not a substitute for edk2-devel." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" From: Ming Huang Add APEI driver Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chenhui Sun --- Chips/Hisilicon/HisiPkg.dec | 16 +++++++++++++ .../Binary/D03/Drivers/Apei/AcpiApei.depex | Bin 0 -> 54 bytes .../Hisilicon/Binary/D03/Drivers/Apei/AcpiApei.efi | Bin 0 -> 9408 bytes .../Hisilicon/Binary/D03/Drivers/Apei/AcpiApei.inf | 26 +++++++++++++++++++++ Platforms/Hisilicon/D03/D03.fdf | 1 + 5 files changed, 43 insertions(+) create mode 100644 Platforms/Hisilicon/Binary/D03/Drivers/Apei/AcpiApei.depex create mode 100644 Platforms/Hisilicon/Binary/D03/Drivers/Apei/AcpiApei.efi create mode 100644 Platforms/Hisilicon/Binary/D03/Drivers/Apei/AcpiApei.inf diff --git a/Chips/Hisilicon/HisiPkg.dec b/Chips/Hisilicon/HisiPkg.dec index 2c02e14..023d784 100644 --- a/Chips/Hisilicon/HisiPkg.dec +++ b/Chips/Hisilicon/HisiPkg.dec @@ -21,6 +21,9 @@ [Includes] Include + Hi1610/Hi1610AcpiTables/ + Hi1616/D05AcpiTables/ + Pv660/Pv660AcpiTables/ [Ppis] gIpmiInterfacePpiGuid = {0x28ae4d88, 0xb658, 0x46b9, {0xa0, 0xe7, 0xd4, 0x95, 0xe2, 0xe8, 0x97, 0xf}} @@ -37,12 +40,25 @@ gBmcInfoProtocolGuid = {0x43fa6ffd, 0x35e4, 0x479e, {0xab, 0xec, 0x5, 0x3, 0xf6, 0x48, 0x0, 0xf5}} gSataEnableFlagProtocolGuid = {0xc2b3c770, 0x8b4a, 0x4796, {0xb2, 0xcf, 0x1d, 0xee, 0x44, 0xd0, 0x32, 0xf3}} gPlatformSasProtocolGuid = {0x40e9829f, 0x3a2c, 0x479a, {0x9a, 0x93, 0x45, 0x7d, 0x13, 0x50, 0x96, 0x5d}} + gEfiApeiBertProtocolGuid = {0x40e98200, 0x3a2c, 0x479a, {0x9a, 0x93, 0x45, 0x7d, 0x13, 0x50, 0x96, 0x5d}} + gEfiApeiHestProtocolGuid = { 0xb3fa54ee, 0x3729, 0x4942, { 0xb5, 0x36, 0x7e, 0xa3, 0xe0, 0x5e, 0xa, 0x8a }} [Guids] gHisiTokenSpaceGuid = {0xc8bc553e, 0x12bf, 0x11e6, {0x97, 0x4f, 0x87, 0xf7, 0x7c, 0xfd, 0x52, 0x1d}} gHisiEfiMemoryMapGuid = {0xf8870015, 0x6994, 0x4b98, {0x95, 0xa2, 0xbd, 0x56, 0xda, 0x91, 0xc0, 0x7f}} gVersionInfoHobGuid = {0xe13a14c, 0x859c, 0x4f22, {0x82, 0xbd, 0x18, 0xe, 0xe1, 0x42, 0x12, 0xbf}} + # + # APEI Support + # + gEfiCperArmProcessorSectionTypeGuid = { 0xe19e3d16, 0xbc11, 0x11e4, { 0x9c, 0xaa, 0xc2, 0x05, 0x1d, 0x5d, 0x46, 0xb0 }} + gEfiCperFirmwareErrorSectionTypeGuid = { 0x81212a96, 0x09ed, 0x4996, { 0x94, 0x71, 0x8d, 0x72, 0x9c, 0x8e, 0x69, 0xed }} + gEfiCperPciBusSectionTypeGuid = { 0xc5753963, 0x3b84, 0x4095, { 0xbf, 0x78, 0xed, 0xda, 0xd3, 0xf9, 0xc9, 0xdd }} + gEfiCperPciDevSectionTypeGuid = { 0xeb5e4685, 0xca66, 0x4769, { 0xb6, 0xa2, 0x26, 0x06, 0x8b, 0x00, 0x13, 0x26 }} + gEfiCperPcieSectionTypeGuid = { 0xd995e954, 0xbbc1, 0x430f, { 0xad, 0x91, 0xb4, 0x4d, 0xcb, 0x3c, 0x6f, 0x35 }} + gEfiCperPlatformMemory2SectionTypeGuid = { 0x61EC04FC, 0x48E6, 0xD813, { 0x25, 0xC9, 0x8D, 0xAA, 0x44, 0x75, 0x0B, 0x12 }} + gEfiCperPlatformMemorySectionTypeGuid = { 0xa5bc1114, 0x6f64, 0x4ede, { 0xb8, 0x63, 0x3e, 0x83, 0xed, 0x7c, 0x83, 0xb1 }} + gEfiCperProcessorGenericSectionTypeGuid = { 0x9876ccad, 0x47b4, 0x4bdb, { 0xb6, 0x5e, 0x16, 0xf1, 0x93, 0xc4, 0xf3, 0xdb }} [LibraryClasses] PlatformSysCtrlLib|Include/Library/PlatformSysCtrlLib.h diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/Apei/AcpiApei.depex b/Platforms/Hisilicon/Binary/D03/Drivers/Apei/AcpiApei.depex new file mode 100644 index 0000000000000000000000000000000000000000..163dbbe18c94d23e0100234e66f0f561bc7c891e GIT binary patch literal 54 zcmV-60LlLX-D}|g2Vtg0d$L-be#IwT0*(lm>)+4DNxnn+a literal 0 HcmV?d00001 diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/Apei/AcpiApei.efi b/Platforms/Hisilicon/Binary/D03/Drivers/Apei/AcpiApei.efi new file mode 100644 index 0000000000000000000000000000000000000000..6358de232ab07f25291a23aab918e48a418e1fb8 GIT binary patch literal 9408 zcmcgy4^&jwng8B<0|F8q1k__lcpw@}I6{@EBq(nNQP~*d0@?P|L$tb9Za*ERCjY6#iX028N_6hHE9HOWn9bb?|Xk>U`1QI zXWu#FefRtB{qFC6_xpDrKK28;>qouoncWj-77@+$O5Fs!U8d30UnG)K@QXHBD*6h3 z)+6JEf4v`nM)$b>y_tRV?S0U1MOIlp82;fzfcJm)j9xZx#WG0aJ@Y=THgW-($TfOy z#j*+>2feuN?`|WuC9ShRg|15EeVk~= z6|_gFww6=_FVkKB)|0-?qyxApDsqn)6HWazLWTJf=c9e^%eBPq}GE!kV4E4I~|&8Z!8z_;O@Z9>KPE310> z1>|0V?YXwx-$ArBPz~FveUI#N5{1w&ku%6g(P(Yt^Zx{}!yuLV9=Ck!1whhoM%DRoQ?bmpY{#vt4z zog_Qx1UijDhywk7Zu10ER;K4pKI^nmf+HhktU$D~%a%?5Zjr=H_Hnl7R@ltNaQLO_ z0gA6Cntat_a(!b7xohGG`bzRP{F3YCYV?n(Cum(MfuZg$I{D~+hD19-N4ewSYjivAg=ah$66#7xevWa zMt-n->iQ~CV>^BcF{?F|LiYeuU$)$|+rab_taI(Tlv2+gO0eu%j6(j2u;1E8TgUrkLkA#W=@bp@!iz z^!(z_$ls_HiPi_MAct?j`ezS84$1BKk;YP2r2&{MjKb~joN zTIeU;kM=m)AllPtNpOq5Ln{kzAqD!&!Y?1c=~(A$&=tX*=E9hppv4QJ)=F}x{a1G# z@qO&2N8N&bTlaw$5&-f5dUt8 z;m}`>ff^z(TThFD>vVJw|OeV^k~YF-jE>qwZBgg0@kQQ5BoKdW@<- zjB0>98NP4Dq^8K2gmv|pWS$}8=X(~gtW3?I#Z5LU^XxQqSqk5Sz_w(J^9+EE%kTsEnrDC#s+$D61C4n^VmLMhU#}Fk!JEkb80^O{8u7jP1uK6fdj;Cql|NiKd+u}o@ZjCb zAB}jwP>KBJB)7+uQH%XbGM|N!V|cDk!`xtY_gr13iuG{jewGP8*3TR7j_;ZGp*6S< z4Hw+jeTe5At1;%VtQKjg*U~Tdzb7D%Y*g}gifT!kJ$1|w75AKtls7nod@ANPV?CVF zVHH?;Jlk}VV(ZAo-E19lyhRh^l~8&->G7TA57+H-sPSzA^LP!G&1zyqNjlnegW2)CtynUOzL-sb%FB zYFqNxYU|@`bPS9qE=$znb0zIy{v_@7cmq>xys}ODdiA!fTt!Qx*i%l5tsj}4Mq7|;1BQI)2;A9=I zCkYs(Q_rW==z3+jo3hqun{#h!`*fbz_5yISuHQ&0!1^`%8a&RMHBle?R_<|qywk)w zI=>KD3a~GyK9+UJV>7c9tdXw`$d{l)Q9skTEb2N-USl$UGcj%JA7HES?Lee$S@Dv; z6(|pp9p4swT#q7e9DNe;g=-4VRj*>MFl}Q=i{M$Z8}FPWo&Z0IlIl|_>Czn7%wMDb zN8P4-esk09V;|jRgN$0bjA+c@5qV$G3LiOv^&7tLTNn)YX@~ z?{XtA{D&kWrzyURSfeR?Vi4Ega`%~>W z)C!_-Nrb=GKCFb6uO0eIP#WS*qrvqL^Eo5F1o3T21#d8D{y2_boKMsM=TWW&zJ(6_ z5j7p(Cpms`JhSeV!GWnA(J6(REy<~g@%WZvQ#90q=f3La=t#du(Bvr6f>Nv=i`dTi zEROsQ*WUP!2^;c{AUmJO`#2k>MV^IampF@;7+0ijWYZ=%*K_SjtA$sL^TRzdrfC>gmz4zQIMR{u} z3VY~xX)pN3dj0CTzXv)&TYn7pd_hX}N_ItKyTIQvv;xRfX!4EVkk^K>zB$IA4z;tN z@g1cCn3fHo1l&V1xn>*z-*LrJLJR2WcxQU;Ky?uRy}}hw_GHZA7MA8aitjneG0ns9 zT{06fGIKD-z^@V-*2a`_e~>w!*BGe3CuRzGhrQ}?xOeReTQY1t_((HjRm@h8i(P*Q zq0C(P_ISupQ3I!;ZgNSD?Gsog_aUGAxy;9R9Mt5Q+|OaY-cQu~S?GhVk1sv9H82YO zvE*qd!~-7Bdsl>*@z_sW1N1$V`)19Z0GuB9=VE+Yx(c219EZ6s>p%sMWndiMW5&gz zg?$Iuk5Los2o7`{{$F>EBdMeS6Qy z=z2;Vxid4Z_M6z9#XA=Nc**W9Ro_f+&-=TNwx3Jb^)PLHprGk7s{2aGdU)5=UE7P+ zB+lIV)E~-j9Qn?8XYtW-Yxf3c$8FjY^U|fyKK$q6e|q${(fbY$c)l{P`n~m!yr`U5 z@y)-V4Sn!wQo`|la~J-8#<9vt>%LjN?iUA6FMqjl>L-uBJ$rE5_FrH5Gr@4biZ`aLI{bs(Yu|g|$%gOVJ8RC1frKpua&zS@#- z{9?jx@5!k9o|Zckc7E0s)bq zt!BI5Z2e~YvDscW+ZZGdeny#XQSpqwy3=~h=La#FNW!@(WJ)6nhndK&@ur_@1mECx z^Fp@%Ojeu8;fGZTY&5-v&SbKMT4I zKmHEZS9uoz+zf=4MaM8Cz;_N{XfzIZBJlrxq6G=4Cq^ zC56+*%o@~dJgVCcAJlm=Q3hT- Td-m@+wCC6!{~n#%!3 literal 0 HcmV?d00001 diff --git a/Platforms/Hisilicon/Binary/D03/Drivers/Apei/AcpiApei.inf b/Platforms/Hisilicon/Binary/D03/Drivers/Apei/AcpiApei.inf new file mode 100644 index 0000000..6e51a1d --- /dev/null +++ b/Platforms/Hisilicon/Binary/D03/Drivers/Apei/AcpiApei.inf @@ -0,0 +1,26 @@ +#/** @file +# +# Copyright (c) 2017, Hisilicon Limited. All rights reserved. +# Copyright (c) 2017, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + + +[defines] + INF_VERSION = 0x00010019 + BASE_NAME = AcpiApei + FILE_GUID = E4630F5E-EBC2-FD3a-86BB-3CFDC4398C5F + MODULE_TYPE = UEFI_DRIVER + VERSION_STRING = 1.0 + +[Binaries] + PE32|AcpiApei.efi|* + diff --git a/Platforms/Hisilicon/D03/D03.fdf b/Platforms/Hisilicon/D03/D03.fdf index ff65af3..6d21ffe 100644 --- a/Platforms/Hisilicon/D03/D03.fdf +++ b/Platforms/Hisilicon/D03/D03.fdf @@ -238,6 +238,7 @@ READ_LOCK_STATUS = TRUE INF RuleOverride=ACPITABLE OpenPlatformPkg/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/AcpiTablesHi1610.inf INF OpenPlatformPkg/Chips/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf + INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/Apei/AcpiApei.inf # #Network # From patchwork Tue Sep 19 13:56:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 113004 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp4972828qgf; Tue, 19 Sep 2017 07:15:59 -0700 (PDT) X-Received: by 10.233.223.68 with SMTP id t65mr1946844qkf.321.1505830558896; Tue, 19 Sep 2017 07:15:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505830558; cv=none; d=google.com; s=arc-20160816; b=I5NBf1T6WsGchkjKIxWIp1ilu5jDXFDTWLDErTB1vFrukI1QUdcDRX0qzGw8RnKGxl ubsWg2TUkAGLh7+4+zLFH9newySBp+nhAXGaRN3j0kWltb5fqe8aZdEmy74w+gV6bVJO /S2kDg5ePNoUKfp/peIe32qsWzmB85fwNXz9Kkp5GqktrvD0TquYrJbVdIzFGQToRKcN /fSCvpz3d4eVpzamrw5FqmkxIjAjiUEIAJuOUCM4zAwbE0cLYs8aPFzE/NWCSppLMjau XblyFCwd9kbzgO5tdlbFD17WE9F6uXskRJfs4NO4lKHAZFL6p1zRUV5zC4j0NrcLx7eI i8Cw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:delivered-to:arc-authentication-results; bh=oKie26QtO9bpMI/0bkcnUE30Zv3LLci2jdfR3SII+oQ=; b=yBHxm2Ip0brsYupRDnWucCHSYP+yQP2coKlKhYRsR98A7BTs+5W4+ld+uQHmMYR1z8 K865trzgn7RJPc1uPK4yjFacgEocLlpX9likFMCkmTrUx5i6cmaGtH4eM41BFBCs5DDA iyHF+pS369JhQ8fcJrC5t1HaKzLsI8oAaDwoIT+0thWS5qSi+kW30rkWDv/Wmv8tsBu1 gEQKzWFkj3zmIuOBP9BqnB5xiArp+bJ9xdMakGHeJeOe4fAp9V3oB342aIQRXEusYExT MCXA4EqvtY6yRYDjthoUQynPcl9CDAc6XQ3NdHtXyYN0cwTEXDAVlgvnw7dtgNWQSsB8 5m3g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id i66si3740636qkd.378.2017.09.19.07.15.58; Tue, 19 Sep 2017 07:15:58 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 6A62362D0C; Tue, 19 Sep 2017 14:15:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 6B0E9636A2; Tue, 19 Sep 2017 14:10:41 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 370BA62CF5; Tue, 19 Sep 2017 14:05:58 +0000 (UTC) Received: from mail-pg0-f51.google.com (mail-pg0-f51.google.com [74.125.83.51]) by lists.linaro.org (Postfix) with ESMTPS id 77CB56065A for ; Tue, 19 Sep 2017 14:05:36 +0000 (UTC) Received: by mail-pg0-f51.google.com with SMTP id b11so2044713pgn.12 for ; Tue, 19 Sep 2017 07:05:36 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hPgPXAfXRZOMQcemksF/VtBM3GHbcrSpgP6SOn33Yqg=; b=LHjVKGs9wU5bF7hK0NKqtlIb2ZfxnM0MiXdMqJTCdkeEEchIZJ9WGH97EuHqm/ssKx Tn+u1YXwVhCorhlHebFIjowSIi+aT+gUNu/J+XBicRTVAvdaOPfZ4cjrcijkfzKfABUq MXK0UPBnPEIvoeLVH3xnfjVH3dtoPyHJkQU5r47N5q+6n6MZKZhnWqVfaYIY96MJzdLF H5PnqzXMkMeAs295CD7tQj6QsD7yURA/b61FcWVTKimJneLIIPWJC/U+yZObSOl9NWgJ xIhDf2iOxRmT0nGO1mftdaw+Kj7z9yFcGOvCQtoQMAnS5q8HwRUjzQitDfaln5OgiGQr WrVg== X-Gm-Message-State: AHPjjUhkVo1aTx2DVlreNAOQSajFYkaP2y42aqnCO1DvDHC5fh2VmWW3 Cw1eUdIlw9IS4OdhaDvOWOTwPPuL X-Google-Smtp-Source: AOwi7QCpaSyZeTfPTl3o3z/kLyf09oNWRHCTsIlerV23ryqRYjLnDhGjImGofRSfs/keaTBgy8h+QQ== X-Received: by 10.84.228.215 with SMTP id y23mr1481291pli.398.1505829935801; Tue, 19 Sep 2017 07:05:35 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id 13sm4390439pfm.138.2017.09.19.07.05.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 19 Sep 2017 07:05:35 -0700 (PDT) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, graeme.gregory@linaro.org Date: Tue, 19 Sep 2017 21:56:22 +0800 Message-Id: <1505829398-52214-17-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1505829398-52214-1-git-send-email-heyi.guo@linaro.org> References: <1505829398-52214-1-git-send-email-heyi.guo@linaro.org> Cc: Ming Huang , zhangjinsong2@huawei.com, huangming23@huawei.com, guoheyi@huawei.com, Chenhui Sun , wanghuiqiang@huawei.com Subject: [Linaro-uefi] [linaro-uefi v1 16/32] Hisilicon/D03: Add Apei asl code to support APEI feature X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: "For discussions about Linaro-related UEFI development. Not a substitute for edk2-devel." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" From: Ming Huang Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chenhui Sun --- .../Hi1610/Hi1610AcpiTables/Dsdt/Apei.asl | 48 ++++++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Apei.asl diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Apei.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Apei.asl new file mode 100644 index 0000000..b692103 --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Apei.asl @@ -0,0 +1,48 @@ +/** @file +* +* Copyright (c) 2017 Hisilicon Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +Device (\_SB.GED1) +{ + Name(_HID, "ACPI0013") + Name (_UID, 0) + Name(_CRS, ResourceTemplate () { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {178} + }) + + OperationRegion (TMR2, SystemMemory, 0x40080000, 0x10) + Field (TMR2, AnyAcc, NoLock, Preserve) { + Offset (0x08), + CNTL, 32, + INTC, 32, + } + + Method (_EVT, 1) { + Switch (Arg0) { + Case (178) { + Store (0x1, INTC) + Notify (\_SB.ERRD, 0x80) + } + } + } +} + +Device (\_SB.ERRD) +{ + Name(_HID, EISAID("PNP0C33")) + Name (_UID, 0) + + Method (_STA, 0x0, NotSerialized) { + Return(0xF) + } +} From patchwork Tue Sep 19 13:56:23 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 113003 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp4972125qgf; Tue, 19 Sep 2017 07:15:33 -0700 (PDT) X-Received: by 10.200.46.209 with SMTP id i17mr2284381qta.235.1505830533396; Tue, 19 Sep 2017 07:15:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505830533; cv=none; d=google.com; s=arc-20160816; b=Qm3R+GvXpCeMtK7Rw4ZuqXBbBJAglsaYLS3xJplWs9juekSvRcd/osI0BqMMQHTTYK 9g6ge9+lr5mLBguMa+2gocN2hE8VLwFokZIr73FYZ5C6erwVSbwfGFMLAdQ5DgyYfBRu rHtvJRAQiW4NeCMCoTGBscZ11qg4V486CEVh2kuuk1V1rEKzuea79TFyAlvypBm+2BdX qa1HFDZKNl7v3rXeqj29XiHeppcvwsDDXkCzS0qWZ0Ej1bY2yNn11v/m9yBYxQNO6hoK pr+Hf0NFGp1rwS5MVhNOj7dqp3/NffZUbMAHEpmJlnn4H2bpYAnPZ2nW/OsznotEOwaH RhFg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:delivered-to:arc-authentication-results; bh=QrnHkfmjgUeK5Hi2DwiuJRvhsBoVWblF2V5S+9sRcbE=; b=IJ3qhgGw6IDGFsiTK5hAgWGB7yhGxE6C7+6JzXFOe40i85yRQikTGUUjEdMOp5wh0b i/xo6Env2GM48LgnAhSjWv1h3mB8SZJe+de0xumuXTGs091uj0T4SmHNErg1v5bRYRAg ELlH0zs9XLEDNjhlbc8os+4Yh13TmNnyOQWsR8SIA5CEaW90xRWxh9KPTDhBeZOphyO9 0G6B5fS8unacZI8GrEtokug116icKMSx0pq4GXkdRT5+UATOps6VWdVMqzxUwUel6IDG Ub9jGqYe7GvURUIPe9wGIcdzS8yhtCzDzGyRrVl3qTpXrinx1JUrIPsLMp+p941tg+ju I9VA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id w198si9616477qkw.302.2017.09.19.07.15.33; Tue, 19 Sep 2017 07:15:33 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id DCA9562D20; Tue, 19 Sep 2017 14:15:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 41D1463574; Tue, 19 Sep 2017 14:10:34 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 473B562CE2; Tue, 19 Sep 2017 14:05:53 +0000 (UTC) Received: from mail-pf0-f175.google.com (mail-pf0-f175.google.com [209.85.192.175]) by lists.linaro.org (Postfix) with ESMTPS id EA99F60F34 for ; Tue, 19 Sep 2017 14:05:38 +0000 (UTC) Received: by mail-pf0-f175.google.com with SMTP id y29so42695pff.0 for ; Tue, 19 Sep 2017 07:05:38 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xiE64eiNHRom9Edb4DFVPEHENb384DB7jx3ZpBTU5K8=; b=nXcceTE35wsWHfjhw0qlvg8kCbloEER7kEdeGcTA38u8O+kbZGClYTmzVo4KTrdXwp UKkLxcMlmSofI22L/kYjtft8AaPiY9smIkXBphYII/Cx6MjNcKzOAkNWGgJhz1CZhlls rDVONdTo0t+Qr3WF/ask5SUrxOIit+O6O7ShGk9LEBEq5uVNqakyqh1UhOKqQLxlQuwc O0MHifMmIRkYNmjqmfz5T8CZFuZczy20p6R/9YyoGUPH3gOGwYlJ8NmLEZSnLU/Dw9bc xeyk+0d1ch+9ofRMn2ts1XyrHJB/roUv0Y7PGjno2awc++m4058J1X3UZsJd8D907boC SI8g== X-Gm-Message-State: AHPjjUhGaXrUFHlLqJHXsw/0iy9otm/Y8GXRecP40Nfjcz7kDTHgrL9W LopRfWpQe/6RGiIV9/h9ymw1ESnz X-Google-Smtp-Source: AOwi7QBK/h5KxlvT/+c2KgR2/Av7hiAy2P48oSdZQIB+BObwKeHAG1sDGqBAffFRGbyiowKrLdc3Vg== X-Received: by 10.99.44.86 with SMTP id s83mr1457891pgs.341.1505829938234; Tue, 19 Sep 2017 07:05:38 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id 13sm4390439pfm.138.2017.09.19.07.05.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 19 Sep 2017 07:05:37 -0700 (PDT) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, graeme.gregory@linaro.org Date: Tue, 19 Sep 2017 21:56:23 +0800 Message-Id: <1505829398-52214-18-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1505829398-52214-1-git-send-email-heyi.guo@linaro.org> References: <1505829398-52214-1-git-send-email-heyi.guo@linaro.org> Cc: huangming23@huawei.com, Chenhui Sun , zhangjinsong2@huawei.com, guoheyi@huawei.com, wanghuiqiang@huawei.com Subject: [Linaro-uefi] [linaro-uefi v1 17/32] Hisilicon/D03: remove the implemention of PerfTuning X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: "For discussions about Linaro-related UEFI development. Not a substitute for edk2-devel." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" From: Chenhui Sun The PerTuning function is not stable, it will cause the 3008/3108 crash, remove this function first. Signed-off-by: Chenhui Sun --- Platforms/Hisilicon/D03/D03.dsc | 1 - 1 file changed, 1 deletion(-) diff --git a/Platforms/Hisilicon/D03/D03.dsc b/Platforms/Hisilicon/D03/D03.dsc index ff8d613..8f5df1c 100644 --- a/Platforms/Hisilicon/D03/D03.dsc +++ b/Platforms/Hisilicon/D03/D03.dsc @@ -112,7 +112,6 @@ # It could be set FALSE to save size. gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE gHisiTokenSpaceGuid.PcdIsItsSupported|TRUE - gHisiTokenSpaceGuid.PcdIsPciPerfTuningEnable|TRUE [PcdsFixedAtBuild.common] gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"D03" From patchwork Tue Sep 19 13:56:24 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 113007 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp4974628qgf; Tue, 19 Sep 2017 07:17:20 -0700 (PDT) X-Received: by 10.55.217.155 with SMTP id q27mr2080197qkl.323.1505830640684; Tue, 19 Sep 2017 07:17:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505830640; cv=none; d=google.com; s=arc-20160816; b=EFMrGhVWgB9BXTmQsKhx5/TvO8ujfjJ0BsPwpGX8JiJYJK6KDcd/FzLw9ZuYl6Pepz vN0CrlMOtzlfLDAHnWKRtPnSERM+FPhaoy29yxrDY7098FtOFw09eGwX/tf2mO6c7mk/ 0sfucHd6zLP/kJwAzA2VqIx5gcKbN0pJiurKgDWsu1JtBJRcbD62Mc040eKzvuIIx9Wh imXCYq9tUJmckBSjaTlAqdb1AlNZWsR18Ntfsm5AJ4xWcSDx/S0NYqu3pEdti1xbbnQ6 060cwuVIa8g6BwoHishIpAlGdifXr9UFXnJnpwRmtzUpBgBp82cUUv7B6iNAsdxR/N/C l+Pw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:delivered-to:arc-authentication-results; bh=a2o0FJFG/La6E2sA/jdxW3hDVvpsuh0o96z6T/Sg7vY=; b=LSrOIg+OWb8khOaoXJqPW1sIe1gZUA7uBE34M/tVBRLB08c6JBF3zOi6z7NJHo8xS8 Uz47RtrLGJP14sjN640YVyBZ1KXLH7fCqVW2qHmVeHfnnJZGmcYbQZaD3VgA2vTNJkUt WmrZiYIu0AZLx1uCpy19KYf1L/wAE6oQ5Iv0R+C2dmVFNi8NY4xkIE/e+XqFOHneS668 PNJRB7ew7H/Go5++4WT5VeVM+oB4+QxVtS8OtNwwOrBr4iripiKJddzmdQfCO6U7zfgF WJiEeJBj8UZEU2BdwIIzy4gxsK+84G1SmY7YEUA+RL+PXeoGEa+Nv+SscS8aBhzcd/d3 hibw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id i1si92214qkb.248.2017.09.19.07.17.20; Tue, 19 Sep 2017 07:17:20 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 457DE60665; Tue, 19 Sep 2017 14:17:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id E319B64451; Tue, 19 Sep 2017 14:11:03 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 6CC9262C59; Tue, 19 Sep 2017 14:06:00 +0000 (UTC) Received: from mail-pg0-f50.google.com (mail-pg0-f50.google.com [74.125.83.50]) by lists.linaro.org (Postfix) with ESMTPS id A111762C5C for ; Tue, 19 Sep 2017 14:05:41 +0000 (UTC) Received: by mail-pg0-f50.google.com with SMTP id d8so2054352pgt.4 for ; Tue, 19 Sep 2017 07:05:41 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hYZIHUAzKsAyfYaM/i+j6X+lVDFWVmHL/tevuDW4EeI=; b=jEHN9LTravFkl5RsxDjcLMUX+EjBfbQcfsPLUlxZWH1ueHHd6Wk/6n1yJq9yIwW6Hu bzPaB2c0s2ok2SpBOQojO6HHgqantACQHAVtjOPp2+aTPoMaG+qHzIIb15xTG4VaS0BH XIoe7pIh0LX8Ta5tOljY8EyIl5skcfaaYEKQKCCDV7wAmcrKsXNXliG8OzGpxoHLWGms 7WAJwG6+3m8Ht0NF/7tGNVrVt5ukKP1AOD1vyojSeoHofWUhTW7yOEZcNKqMlD9zti93 ZGbORgrGOWVMaG/fPHoxG8qXFY953pzZ/wylakfKBbfJO+4UbnCUOifhIwjckwB0EZY+ +3qQ== X-Gm-Message-State: AHPjjUhrcuLcPy7nymGxByD0AsJBUpjgbSGeozE/QiC2bffr2uza78rl O39Gvwk32yEi+x4Er2hQJnZfBuuX X-Google-Smtp-Source: AOwi7QC3BUNSFZOotWU0kh3mz74Cjhqa2f+9BSSpECnpKuZ+CLwrgV6tuedWiRQ/cA93eyScQSM0cg== X-Received: by 10.84.235.65 with SMTP id g1mr1397668plt.353.1505829940836; Tue, 19 Sep 2017 07:05:40 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id 13sm4390439pfm.138.2017.09.19.07.05.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 19 Sep 2017 07:05:40 -0700 (PDT) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, graeme.gregory@linaro.org Date: Tue, 19 Sep 2017 21:56:24 +0800 Message-Id: <1505829398-52214-19-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1505829398-52214-1-git-send-email-heyi.guo@linaro.org> References: <1505829398-52214-1-git-send-email-heyi.guo@linaro.org> Cc: huangming23@huawei.com, zhangjinsong2@huawei.com, guoheyi@huawei.com, Chenhui Sun , wanghuiqiang@huawei.com Subject: [Linaro-uefi] [linaro-uefi v1 18/32] D05: add es3000 performance driver X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: "For discussions about Linaro-related UEFI development. Not a substitute for edk2-devel." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" From: Chenhui Sun Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chenhui Sun --- .../Drivers/Es3000PerformanceDxe/Es3000Dxe.c | 137 +++++++++++++++++++++ .../Drivers/Es3000PerformanceDxe/Es3000Dxe.inf | 57 +++++++++ Platforms/Hisilicon/D05/D05.dsc | 1 + Platforms/Hisilicon/D05/D05.fdf | 3 +- 4 files changed, 197 insertions(+), 1 deletion(-) create mode 100644 Chips/Hisilicon/Hi1610/Drivers/Es3000PerformanceDxe/Es3000Dxe.c create mode 100644 Chips/Hisilicon/Hi1610/Drivers/Es3000PerformanceDxe/Es3000Dxe.inf diff --git a/Chips/Hisilicon/Hi1610/Drivers/Es3000PerformanceDxe/Es3000Dxe.c b/Chips/Hisilicon/Hi1610/Drivers/Es3000PerformanceDxe/Es3000Dxe.c new file mode 100644 index 0000000..4968f82 --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Drivers/Es3000PerformanceDxe/Es3000Dxe.c @@ -0,0 +1,137 @@ +/** @file +* +* Copyright (c) 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include +#include +#include + +#include +#include +#include +#include +#include + +UINT64 PCIE_APB_SLVAE_BASE_1616[2][8] = {{0xa0090000, 0xa0200000, 0xa00a0000, 0xa00b0000, 0x8a0090000, 0x8a0200000, 0x8a00a0000, 0x8a00b0000}, + {0x600a0090000, 0x600a0200000, 0x600a00a0000, 0x600a00b0000, 0x700a0090000, 0x700a0200000, 0x700a00a0000, 0x700a00b0000},}; +UINT8 PCIE_ROOT_BRIDGE_BUS_NUM_1P[8] = {0x10, 0x21, 0x81, 0x30, 0x40, 0x1, 0x60, 0x70}; +UINT8 PCIE_ROOT_BRIDGE_BUS_NUM_2P[8] = {0x80, 0x90, 0x11, 0x40, 0x21, 0x31, 0x60, 0x70}; + +#define RegWrite(addr,data) (*(volatile UINT32*)(UINTN)(addr) = (data)) +#define RegRead(addr,data) ((data) = *(volatile UINT32*)(UINTN)(addr)) + + +VOID +EFIAPI +OemEs3000PerformaceOperation( + IN EFI_EVENT Event, + IN VOID *Context + ) + +{ + EFI_STATUS Status; + UINTN HandleIndex; + EFI_HANDLE *HandleBuffer; + UINTN HandleCount; + EFI_PCI_IO_PROTOCOL *PciIo; + UINTN SegmentNumber; + UINTN BusNumber; + UINTN DeviceNumber; + UINTN FunctionNumber; + UINT16 DeviceId = 0; + UINT16 VenderId = 0; + UINT8 i = 0; + UINT32 Value = 0; + + Status = gBS->LocateHandleBuffer ( + ByProtocol, + &gEfiPciIoProtocolGuid, + NULL, + &HandleCount, + &HandleBuffer + ); + if(EFI_ERROR(Status)) { + DEBUG((EFI_D_ERROR, " Locate gEfiPciIoProtocol Failed.\n")); + //gBS->FreePool ((VOID *)HandleBuffer); + return; + } + DEBUG((EFI_D_ERROR, "HandleCount = %d\n", HandleCount)); + for (HandleIndex = 0; HandleIndex < HandleCount; HandleIndex++) { + (VOID)gBS->HandleProtocol ( + HandleBuffer[HandleIndex], + &gEfiPciIoProtocolGuid, + (VOID **)&PciIo + ); + + (VOID)PciIo->GetLocation(PciIo,&SegmentNumber,&BusNumber,&DeviceNumber,&FunctionNumber); + + DEBUG((EFI_D_ERROR,"PCIe device plot in slot Seg %d bdf %d %d %d\r\n",SegmentNumber,BusNumber,DeviceNumber,FunctionNumber)); + (VOID)PciIo->Pci.Read(PciIo,EfiPciIoWidthUint16,PCI_DEVICE_ID_OFFSET,1,&DeviceId); + (VOID)PciIo->Pci.Read(PciIo,EfiPciIoWidthUint16,PCI_VENDOR_ID_OFFSET,1,&VenderId); + if((DeviceId == 0x0123) && (VenderId == 0x19e5)) { + if (SegmentNumber == 0) { + for(i = 0; i < 8; i ++) { + if (BusNumber == PCIE_ROOT_BRIDGE_BUS_NUM_1P[i]) + break; + } + } + if (SegmentNumber == 1) { + for(i = 0; i < 8; i ++) { + if (BusNumber == PCIE_ROOT_BRIDGE_BUS_NUM_2P[i]) + break; + } + } + DEBUG((EFI_D_ERROR,"find es3000...............\n")); + DEBUG((EFI_D_ERROR,"Segment = %d, i = %d, PCIE APB SLAVE BASE = %lx\n",SegmentNumber, i, PCIE_APB_SLVAE_BASE_1616[SegmentNumber][i])); + RegWrite((UINT64)PCIE_APB_SLVAE_BASE_1616[SegmentNumber][i] + 0x1110, 0x28002fff); + RegRead((UINT64)PCIE_APB_SLVAE_BASE_1616[SegmentNumber][i] + 0x1110, Value); + DEBUG((EFI_D_ERROR,"Read value = %lx\n",Value)); + DEBUG((EFI_D_ERROR, "Device Id = %x, Vender Id = %x\n",VenderId, DeviceId)); + + } + + } + + return; +} + +EFI_STATUS +EFIAPI +Es3000PerformanceDxeEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable) +{ + EFI_STATUS Status; + EFI_EVENT Event = NULL; + + // + // Register notify function + // + Status = gBS->CreateEvent ( + EVT_SIGNAL_EXIT_BOOT_SERVICES, + TPL_CALLBACK, + OemEs3000PerformaceOperation, + NULL, + &Event + ); + + if (EFI_ERROR(Status)) + { + DEBUG ((EFI_D_ERROR, "[%a:%d] - Es3000 performace createEvent failed: %r\n", __FUNCTION__, + __LINE__, Status)); + } + + return Status; +} + diff --git a/Chips/Hisilicon/Hi1610/Drivers/Es3000PerformanceDxe/Es3000Dxe.inf b/Chips/Hisilicon/Hi1610/Drivers/Es3000PerformanceDxe/Es3000Dxe.inf new file mode 100644 index 0000000..e0d3429 --- /dev/null +++ b/Chips/Hisilicon/Hi1610/Drivers/Es3000PerformanceDxe/Es3000Dxe.inf @@ -0,0 +1,57 @@ +#/** @file +# +# Copyright (c) 2015, Hisilicon Limited. All rights reserved. +# Copyright (c) 2015, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = Es3000Dxe + FILE_GUID = f99c606a-5826-11e6-b09e-bb93f4e4c402 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + + ENTRY_POINT = Es3000PerformanceDxeEntry + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = AARCH64 +# + +[Sources.common] + Es3000Dxe.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + ArmPkg/ArmPkg.dec + OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec + +[LibraryClasses] + UefiBootServicesTableLib + UefiDriverEntryPoint + DebugLib + BaseLib + PcdLib + CacheMaintenanceLib + +[Guids] + +[Protocols] + gEfiPciIoProtocolGuid + +[Pcd] + +[Depex] + gEfiPciIoProtocolGuid + diff --git a/Platforms/Hisilicon/D05/D05.dsc b/Platforms/Hisilicon/D05/D05.dsc index 8191459..8dfcca4 100644 --- a/Platforms/Hisilicon/D05/D05.dsc +++ b/Platforms/Hisilicon/D05/D05.dsc @@ -619,6 +619,7 @@ OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Sm750Dxe/UefiSmi.inf MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/Es3000PerformanceDxe/Es3000Dxe.inf OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf diff --git a/Platforms/Hisilicon/D05/D05.fdf b/Platforms/Hisilicon/D05/D05.fdf index 3081058..82a6a7e 100644 --- a/Platforms/Hisilicon/D05/D05.fdf +++ b/Platforms/Hisilicon/D05/D05.fdf @@ -292,8 +292,9 @@ READ_LOCK_STATUS = TRUE # INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Sm750Dxe/UefiSmi.inf INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf - INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/SasPlatform/SasPlatform.inf + INF OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/Es3000PerformanceDxe/Es3000Dxe.inf INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Sas/SasDxeDriver.inf + INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/SasPlatform/SasPlatform.inf # # UEFI application (Shell Embedded Boot Loader) # From patchwork Tue Sep 19 13:56:25 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 113006 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp4974131qgf; Tue, 19 Sep 2017 07:16:59 -0700 (PDT) X-Received: by 10.55.138.7 with SMTP id m7mr2229432qkd.121.1505830619359; Tue, 19 Sep 2017 07:16:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505830619; cv=none; d=google.com; s=arc-20160816; b=PThuJTqHuxta6hNxjZDTR7zSL1diufbV7laTYdbdT+N8AXqy+CtJB7NtK104z9twlc 0vSuIG34mgwj/iDu60o7gVyJpQiIJ1U4PJuyddJVPTeEVTp2W0MneJGiRXlrNSAHrvj9 IBICE6m63UUlGD/+vs6RBRD+6e/oUHpY2Lno3Q8ug04BTWARIpVusW4KWN+fs8ULj+9S 2l7KNctlJ3tqcTfrKkRNH8GgSgoOX38qq62g4glXkap4P+Ocep7U1a5ECNoUe9B1KWUZ VFmxKSook/7gQ1C89JRCzEmipkqStY27L7IPkvxgqbTc5j0piwk5gg3IPUfWa0eHbcv0 gomQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:delivered-to:arc-authentication-results; bh=Ql5XNCEjYKYDxq5KFO0l92xJovbfEKzpR/TpTGvkWlE=; b=jaAsYokBXVsThjgErxtt1gK4n4/2WCi/OciBGlPi4Tcvo95Q2Uva0dymQxw8+B5G3k q8dhWwkO+jPkjUs2bptTfOxSQzgUjScM6i6WG+hBpfjsYaIFtiKHjABbKztrm3Bzwrkt TQSrBU8K/3oawxi+g0RvdKPO5Q/MUCsHmYeBZoWg8rLvtIqUqDM32qyRRBAFbKX8lbPv bBaSCxuKrmSfmCkweY6t90pZLhReL9/HAwgh0PLckorBjyCRact0F82AJYhIKqpnX4Br 0eg+ZVY53+Ny9VuoSeyEk/159vNtUafbn+R80hkZ6UBPB2oOAGGWWgRiZRRNlbBwkqGx wpdg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id x25si1494909qtc.247.2017.09.19.07.16.58; Tue, 19 Sep 2017 07:16:59 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id D823462D05; Tue, 19 Sep 2017 14:16:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id B7DBC6444A; Tue, 19 Sep 2017 14:10:56 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 0C74A62C59; Tue, 19 Sep 2017 14:06:00 +0000 (UTC) Received: from mail-pg0-f54.google.com (mail-pg0-f54.google.com [74.125.83.54]) by lists.linaro.org (Postfix) with ESMTPS id D9CCB62C60 for ; Tue, 19 Sep 2017 14:05:43 +0000 (UTC) Received: by mail-pg0-f54.google.com with SMTP id p5so2051895pgn.7 for ; Tue, 19 Sep 2017 07:05:43 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ZV7+IQc4vxI7AVJ71/of5OG7XUYsEIlHNuERry2uJMY=; b=SdrUC5ylJNx49fYADG1OcHixTNACF3HRdNqT+h/KbB66rlT39hZ/agrB3HrXFP65pP LX3qHAK5qZVj6bvW2rBFIAH0HG/BeFQT+QU5ox1qBzOJPo7YuU/wufgzmrZZ9G9kw25L PTzsu6iC3yS1b8d4iuW5vn9fAIpw4hu8ZznlaAXMfC42dXpfIVq6diaN/67zptnvKZq4 R7hDeh6vWhgiJA3zsM3BZYgbp7bdekG61T4RJz2n45/ug1SO+dQ8hthjuRcxsuyuvIfv eH7kd7eGhtcAFCqI5tZ7y8U+bCsDD76hReeBFGfo5K39l/7MiGmPJnEd5n5JQK6XvTHf ejNg== X-Gm-Message-State: AHPjjUiVCqsmr9XuRP5X5oylRsm0XDpJXL9GMWO4CiGAxAXKGzljEBbj z7Alk4B0W3iGGNl/thNT8Ur/MwH5 X-Google-Smtp-Source: AOwi7QAMmFLZDGShmdRGs538PO893ubb+cL6cNv4D1X5f8KwAH9Y80L2gC0mdGod1ZDx/wBHqjlEuw== X-Received: by 10.99.109.65 with SMTP id i62mr1408285pgc.83.1505829943243; Tue, 19 Sep 2017 07:05:43 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id 13sm4390439pfm.138.2017.09.19.07.05.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 19 Sep 2017 07:05:42 -0700 (PDT) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, graeme.gregory@linaro.org Date: Tue, 19 Sep 2017 21:56:25 +0800 Message-Id: <1505829398-52214-20-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1505829398-52214-1-git-send-email-heyi.guo@linaro.org> References: <1505829398-52214-1-git-send-email-heyi.guo@linaro.org> Cc: guoheyi@huawei.com, huangming23@huawei.com, zhangjinsong2@huawei.com, wanghuiqiang@huawei.com Subject: [Linaro-uefi] [linaro-uefi v1 19/32] Hisilicon/Smbios: modify type 4 X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: "For discussions about Linaro-related UEFI development. Not a substitute for edk2-devel." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" From: huangming modify processorFamily of type 4 to ProcessorFamilyIndicatorFamily2, indicator to obtain the processor family from the Processor Family 2 field. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ming Huang --- .../Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c b/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c index 61473e8..c9903ba 100644 --- a/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c +++ b/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c @@ -125,7 +125,7 @@ SMBIOS_TABLE_TYPE4 mSmbiosProcessorTable[] = { }, 1, //Socket CentralProcessor, //ProcessorType - ProcessorFamilyOther, //ProcessorFamily + ProcessorFamilyIndicatorFamily2, //ProcessorFamily 2, //ProcessorManufacture { //ProcessorId { //Signature @@ -172,7 +172,7 @@ SMBIOS_TABLE_TYPE4 mSmbiosProcessorTable[] = { }, 1, //Socket CentralProcessor, //ProcessorType - ProcessorFamilyOther, //ProcessorFamily + ProcessorFamilyIndicatorFamily2, //ProcessorFamily 2, //ProcessorManufacture { //ProcessorId { //Signature From patchwork Tue Sep 19 13:56:26 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 113010 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp4976244qgf; Tue, 19 Sep 2017 07:18:40 -0700 (PDT) X-Received: by 10.200.37.8 with SMTP id 8mr2270177qtm.77.1505830720892; Tue, 19 Sep 2017 07:18:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505830720; cv=none; d=google.com; s=arc-20160816; b=M9/C6UppX/DClEMmfhIVh0N5OmPBr7/Coc423Rt7tCP3U/12+HZv2ri0Mp/rUmcRWf 3Q1PTUlae4x99FYkXfo0cfqqZ+f+iG9boeGvdD1tp8CSV2dmiyAsTiy1RqOf95pYJGsC P3/0vLsVktfAL/YPPXNu9BamqHoG/Bp57kqpK/OkqJPT/K0DQIWK0aS/7i00KgKjXAmq MqCXPNs5OJbXNo4Ozy3k+wfndyr60MD72O7kMwtU51M8vWy/isBDw8oOQZFguhiMf/jF obWXSKwLgSTGP4iLVnRVnQk6s27IbRF7wYtdsgvpzU1TViB5rz0ZzylwHQ/5aZ//H3xn 16jQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:delivered-to:arc-authentication-results; bh=Kc9L87BxJA3UeghJCjgsZOLXrvKfW815vyJlhwWZTYc=; b=Hx4UDIyaxNQetdcwYqbLK8TtUVCeP6+4Q0UaKEWUJyobeaqsiyGCUTgMffSmuEpnJ7 KedjakVq4pFGJt/Y3dgICun9pQtVglh3Fp92eQiuzfWPeVdVxwTGzrpiidbwhs9W2xXp mKYBzy2VO17PtfFmRoZpw4OYKetV1JKkGQ+KrvNC5X9SwowZb8M5SFw5SODFVvjL/Ojb j5zRNwkGbrjxpaddljPA1Dlm1KVrxMgCfcgF/voNi4xmO1fiJxsd9f6mGfvCKNo8MKHO KVymctFGLZ3J267qNihGNFreOB/hQAbVtgT1phHlNQtnAwDtXb8saBa2+0cTIeetaKoJ CDLA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id l38si9686133qtk.138.2017.09.19.07.18.40; Tue, 19 Sep 2017 07:18:40 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 80DAC62DF5; Tue, 19 Sep 2017 14:18:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 5B12164462; Tue, 19 Sep 2017 14:11:10 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id B1D0D62C60; Tue, 19 Sep 2017 14:06:07 +0000 (UTC) Received: from mail-pg0-f43.google.com (mail-pg0-f43.google.com [74.125.83.43]) by lists.linaro.org (Postfix) with ESMTPS id 7562C62C62 for ; Tue, 19 Sep 2017 14:05:46 +0000 (UTC) Received: by mail-pg0-f43.google.com with SMTP id c137so2046945pga.11 for ; Tue, 19 Sep 2017 07:05:46 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xY5mAqDR04fgrwwypMDQ4yocC99an3iVm+tTZG4p8Ew=; b=gQBZK/7ToWSSSZc8sGP/fD9Smvz1UhCBg+O8A5uIhdycN4OqVRVTTvMUC3C2cZZJRw KBGE7Si9U1SAeVdUXdIEDJTso30oEAX4G0SeZI4aXfFKFjEZvOZqUqEooOt7eyghbLSO eWaKa6YnYqzPyiVkPrY+5ifw0TwsPsHH/GoZT490snr3dfqg3/ne3hQ+ctx8Lr9XFotO 4PUzgSEakl6uNiZ42gSWXa0YPkOHar1DsF8YYuo3QXYSrq+8bN7qsu1LGKgXA6Fdooa/ Jim5XSkujCgUH5yjz505pvQiV8c3VNACi3z6JCRR4fW7uWKXMmgxCwo6bVNNwRIpTNSJ C7Hg== X-Gm-Message-State: AHPjjUigZuoRod2o/XPe3T1Rjwzh/wXaUxHcXKbEdLOOfvq0ef0muG5D DDheOdTYXqaWZ4PJpKqOfhuYD9h3RXCgWg== X-Google-Smtp-Source: AOwi7QDrTmoizByTbk8hMIZioPM6WpbJGXIrcAKB66hZH5bW5Frus4wUa6yjAWFAIUGyZAh6eE+iTw== X-Received: by 10.84.210.196 with SMTP id a62mr1426644pli.356.1505829945776; Tue, 19 Sep 2017 07:05:45 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id 13sm4390439pfm.138.2017.09.19.07.05.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 19 Sep 2017 07:05:44 -0700 (PDT) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, graeme.gregory@linaro.org Date: Tue, 19 Sep 2017 21:56:26 +0800 Message-Id: <1505829398-52214-21-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1505829398-52214-1-git-send-email-heyi.guo@linaro.org> References: <1505829398-52214-1-git-send-email-heyi.guo@linaro.org> Cc: guoheyi@huawei.com, huangming23@huawei.com, zhangjinsong2@huawei.com, wanghuiqiang@huawei.com Subject: [Linaro-uefi] [linaro-uefi v1 20/32] Hisilicon/D05/Pcie: fix bug of size definition X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: "For discussions about Linaro-related UEFI development. Not a substitute for edk2-devel." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" From: huangming Fix bug of PcieRegion size definition and IO size definition. DTS2017041802990 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ming Huang Change-Id: I3d66cd5099274becdb752203c244dcee9db85dfa --- Platforms/Hisilicon/D05/D05.dsc | 64 ++++++++++++++++++++--------------------- 1 file changed, 32 insertions(+), 32 deletions(-) diff --git a/Platforms/Hisilicon/D05/D05.dsc b/Platforms/Hisilicon/D05/D05.dsc index 8dfcca4..4e4baeb 100644 --- a/Platforms/Hisilicon/D05/D05.dsc +++ b/Platforms/Hisilicon/D05/D05.dsc @@ -311,37 +311,37 @@ gHisiTokenSpaceGuid.PciHb1Rb7Base|0x700a00b0000 gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress|0xa8400000 - gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize|0xbeffff + gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize|0xbf0000 gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress|0xa9400000 - gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize|0xbeffff + gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize|0xbf0000 gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress|0xa8800000 - gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize|0x77effff + gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize|0x77f0000 gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress|0xab400000 - gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize|0xbeffff + gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize|0xbf0000 gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress|0xa9000000 - gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize|0x2feffff + gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize|0x2ff0000 gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress|0xb0800000 - gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize|0x77effff + gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize|0x77f0000 gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress|0xac900000 - gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize|0x36effff + gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize|0x36f0000 gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionBaseAddress|0xb9800000 - gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize|0x67effff + gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize|0x67f0000 gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionBaseAddress|0x400a8400000 - gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize|0xbeffff + gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize|0xbf0000 gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress|0x400a9400000 - gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize|0xbeffff + gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize|0xbf0000 gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress|0x40000000 - gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize|0xafffffff + gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize|0xb0000000 gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress|0x400ab400000 - gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize|0xbeffff + gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize|0xbf0000 gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress|0x40000000 - gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize|0xafffffff + gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize|0xb0000000 gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress|0x40000000 - gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize|0xafffffff + gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize|0xb0000000 gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress|0x408aa400000 - gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize|0xbeffff + gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize|0xbf0000 gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionBaseAddress|0x408ab400000 - gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize|0xbeffff + gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize|0xbf0000 gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase|0xA8400000 gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase|0xA9400000 @@ -378,52 +378,52 @@ gHisiTokenSpaceGuid.PcdHb1Rb7CpuIoRegionBase|0x408abff0000 gHisiTokenSpaceGuid.PcdHb0Rb0IoBase|0 - gHisiTokenSpaceGuid.PcdHb0Rb0IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb0Rb0IoSize|0x10000 #64K gHisiTokenSpaceGuid.PcdHb0Rb1IoBase|0 - gHisiTokenSpaceGuid.PcdHb0Rb1IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb0Rb1IoSize|0x10000 #64K gHisiTokenSpaceGuid.PcdHb0Rb2IoBase|0 - gHisiTokenSpaceGuid.PcdHb0Rb2IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb0Rb2IoSize|0x10000 #64K gHisiTokenSpaceGuid.PcdHb0Rb3IoBase|0 - gHisiTokenSpaceGuid.PcdHb0Rb3IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb0Rb3IoSize|0x10000 #64K gHisiTokenSpaceGuid.PcdHb0Rb4IoBase|0 - gHisiTokenSpaceGuid.PcdHb0Rb4IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb0Rb4IoSize|0x10000 #64K gHisiTokenSpaceGuid.PcdHb0Rb5IoBase|0 - gHisiTokenSpaceGuid.PcdHb0Rb5IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb0Rb5IoSize|0x10000 #64K gHisiTokenSpaceGuid.PcdHb0Rb6IoBase|0 - gHisiTokenSpaceGuid.PcdHb0Rb6IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb0Rb6IoSize|0x10000 #64K gHisiTokenSpaceGuid.PcdHb0Rb7IoBase|0 - gHisiTokenSpaceGuid.PcdHb0Rb7IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb0Rb7IoSize|0x10000 #64K gHisiTokenSpaceGuid.PcdHb1Rb0IoBase|0 - gHisiTokenSpaceGuid.PcdHb1Rb0IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb1Rb0IoSize|0x10000 #64K gHisiTokenSpaceGuid.PcdHb1Rb1IoBase|0 - gHisiTokenSpaceGuid.PcdHb1Rb1IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb1Rb1IoSize|0x10000 #64K gHisiTokenSpaceGuid.PcdHb1Rb2IoBase|0 - gHisiTokenSpaceGuid.PcdHb1Rb2IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb1Rb2IoSize|0x10000 #64K gHisiTokenSpaceGuid.PcdHb1Rb3IoBase|0 - gHisiTokenSpaceGuid.PcdHb1Rb3IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb1Rb3IoSize|0x10000 #64K gHisiTokenSpaceGuid.PcdHb1Rb4IoBase|0 - gHisiTokenSpaceGuid.PcdHb1Rb4IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb1Rb4IoSize|0x10000 #64K gHisiTokenSpaceGuid.PcdHb1Rb5IoBase|0 - gHisiTokenSpaceGuid.PcdHb1Rb5IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb1Rb5IoSize|0x10000 #64K gHisiTokenSpaceGuid.PcdHb1Rb6IoBase|0 - gHisiTokenSpaceGuid.PcdHb1Rb6IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb1Rb6IoSize|0x10000 #64K gHisiTokenSpaceGuid.PcdHb1Rb7IoBase|0 - gHisiTokenSpaceGuid.PcdHb1Rb7IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb1Rb7IoSize|0x10000 #64K gHisiTokenSpaceGuid.Pcdsoctype|0x1610 From patchwork Tue Sep 19 13:56:27 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 113011 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp4976810qgf; Tue, 19 Sep 2017 07:19:09 -0700 (PDT) X-Received: by 10.233.232.8 with SMTP id a8mr1969594qkg.265.1505830749695; Tue, 19 Sep 2017 07:19:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505830749; cv=none; d=google.com; s=arc-20160816; b=mvrLxnPzbb59Jp/TzT6F6ioY/qXWLkYPNd7SdcVQJMmxUxnAQfs3hNF5SPLL/Xaj/O vtg2EGdDObP1eNlnZavrrJNlURYsj6VjmXWQfsI56ue4S6O4FPumXRroSvIvrpXDJzv7 ou4AhN/71B6UINF9saLEqKpQ2F4LBdqG/3+gc3IXHFxnItAhI/LTBmi/P2csnERTi5c2 eYwN3AQnYsXggLtptSLLN8XdgRuyLbNurL2NVaXXEfX/sccUGkAsrO4w7cOcCGpNRDDF 3XCJ2J2sNN4RosvkuoS/5IOu8Wv5vBWj2+L5AxKDMqM0igpX/fYbpx7rlEG6QaazsWqb ZqrA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:delivered-to:arc-authentication-results; bh=dO1z/usz2DgmRRwyDPe3nXNgleqqjVVw0fcxwLuvZNE=; b=0a1XERDxlKQ/kFvDgyP9mqoCMkh5ylpLQTe9VvMfi7Cm6MyNsWM+cvK+2RXwodi409 v5Wg7zTm6rSkZFAzXDdmtbPtUPKwXBJ4eyvX7ny2mKD/r0hjwxQZwDHZe6sgexhj3asl Kao6RV65mS5fbMrDOvvLkbz8LDDvrZWceQw5av6oNvOZ7HhyrfoE26k1pCRXMip8+wmS OUJCBREiCtsawY54Zwa10ugg7SwRP0awvCdqmXYag0I0QXhiD9pyBF/kuqTkdtlmdM13 aOXbxmicSH24mfQVc4PR7yROe/Wbw40iOWPw4AyY00z38MLUV97WhICUAsY54SlBQ8bL EpyQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.linaro.org (lists.linaro.org. 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Not a substitute for edk2-devel." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" From: huangming Optimize pcie space for promoting usage rate.Change regions order of NA-Pcie2 and NB-Pcie1 to MEM-ECAM-IO in DAW,so MemoryRegion can satisfy the requirement of larger address alignment. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ming Huang --- Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl | 16 +++++------ Chips/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc | 8 +++--- .../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 32 +++++++++++----------- Platforms/Hisilicon/D05/D05.dsc | 12 ++++---- .../D05/Library/PlatformPciLib/PlatformPciLib.c | 8 +++--- 5 files changed, 38 insertions(+), 38 deletions(-) diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl index 9ab164f..494f3f1 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl @@ -130,9 +130,9 @@ [0004] GERR Interrupt : 00000000 [0004] Sync Interrupt : 00000000 /* this is the map for PCIe2 in 1P NA */ -[0004] Input base : 00028000 +[0004] Input base : 0002f800 [0004] ID Count : 00000800 -[0004] Output Base : 00008000 +[0004] Output Base : 0000f800 [0004] Output Reference : 00000064 [0004] Flags (decoded below) : 00000000 Single Mapping : 0 @@ -214,9 +214,9 @@ [0004] GERR Interrupt : 00000000 [0004] Sync Interrupt : 00000000 /* this is the map for PCIe1 in 1P NB */ -[0004] Input base : 00010000 +[0004] Input base : 00017800 [0004] ID Count : 00000800 -[0004] Output Base : 00000000 +[0004] Output Base : 00007800 [0004] Output Reference : 00000064 [0004] Flags (decoded below) : 00000000 Single Mapping : 0 @@ -550,9 +550,9 @@ [0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 00000002 -[0004] Input base : 00008000 +[0004] Input base : 0000f800 [0004] ID Count : 00000800 -[0004] Output Base : 00028000 +[0004] Output Base : 0002f800 [0004] Output Reference : 000000f4 [0004] Flags (decoded below) : 00000000 Single Mapping : 0 @@ -607,9 +607,9 @@ [0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 00000005 -[0004] Input base : 00000000 +[0004] Input base : 00007800 [0004] ID Count : 00000800 -[0004] Output Base : 00010000 +[0004] Output Base : 00017800 [0004] Output Reference : 000001e4 [0004] Flags (decoded below) : 00000000 Single Mapping : 0 diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc index b47cfec..64807b1 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc @@ -57,8 +57,8 @@ EFI_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg= { 0xa0000000, //Base Address 0x2, //Segment Group Number - 0x80, //Start Bus Number - 0x87, //End Bus Number + 0xF8, //Start Bus Number + 0xFF, //End Bus Number 0x00000000, //Reserved }, //1p NB PCIe0 @@ -73,8 +73,8 @@ EFI_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg= { 0x8b0000000, //Base Address 0x5, //Segment Group Number - 0x0, //Start Bus Number - 0x7, //End Bus Number + 0x78, //Start Bus Number + 0x7F, //End Bus Number 0x00000000, //Reserved }, //1p NB PCIe2 diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl index 55c7f50..71a8f2d 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl @@ -89,15 +89,15 @@ Scope(_SB) Name (_HID, "PNP0A08") // PCI Express Root Bridge Name (_CID, "PNP0A03") // Compatible PCI Root Bridge Name(_SEG, 2) // Segment of this Root complex - Name(_BBN, 0x80) // Base Bus Number + Name(_BBN, 0xF8) // Base Bus Number Name(_CCA, 1) Method (_CRS, 0, Serialized) { // Root complex resources Name (RBUF, ResourceTemplate () { WordBusNumber ( // Bus numbers assigned to this root ResourceProducer, MinFixed, MaxFixed, PosDecode, 0, // AddressGranularity - 0x80, // AddressMinimum - Minimum Bus Number - 0x87, // AddressMaximum - Maximum Bus Number + 0xF8, // AddressMinimum - Minimum Bus Number + 0xFF, // AddressMaximum - Maximum Bus Number 0, // AddressTranslation - Set to 0 0x8 // RangeLength - Number of Busses ) @@ -109,8 +109,8 @@ Scope(_SB) Cacheable, ReadWrite, 0x0, // Granularity - 0xa8800000, // Min Base Address - 0xaffeffff, // Max Base Address + 0xa8000000, // Min Base Address + 0xaf7effff, // Max Base Address 0x0, // Translate 0x77f0000 // Length ) @@ -123,7 +123,7 @@ Scope(_SB) 0x0, // Granularity 0x0, // Min Base Address 0xffff, // Max Base Address - 0xafff0000, // Translate + 0xaf7f0000, // Translate 0x10000 // Length ) }) // Name(RBUF) @@ -162,7 +162,7 @@ Scope(_SB) { Name (_HID, "PNP0C02") // Motherboard reserved resource Name (_CRS, ResourceTemplate (){ - Memory32Fixed (ReadWrite, 0xa8000000 , 0x800000) //ECAM space for [bus 80-87] + Memory32Fixed (ReadWrite, 0xaf800000 , 0x800000) //ECAM space for [bus f8-ff] }) Method (_STA, 0x0, NotSerialized) { @@ -274,15 +274,15 @@ Scope(_SB) Name (_HID, "PNP0A08") // PCI Express Root Bridge Name (_CID, "PNP0A03") // Compatible PCI Root Bridge Name(_SEG, 5) // Segment of this Root complex - Name(_BBN, 0x0) // Base Bus Number + Name(_BBN, 0x78) // Base Bus Number Name(_CCA, 1) Method (_CRS, 0, Serialized) { // Root complex resources Name (RBUF, ResourceTemplate () { WordBusNumber ( // Bus numbers assigned to this root ResourceProducer, MinFixed, MaxFixed, PosDecode, 0, // AddressGranularity - 0x0, // AddressMinimum - Minimum Bus Number - 0x7, // AddressMaximum - Maximum Bus Number + 0x78, // AddressMinimum - Minimum Bus Number + 0x7f, // AddressMaximum - Maximum Bus Number 0, // AddressTranslation - Set to 0 0x8 // RangeLength - Number of Busses ) @@ -294,8 +294,8 @@ Scope(_SB) Cacheable, ReadWrite, 0x0, // Granularity - 0xb0800000, // Min Base Address - 0xb7feffff, // Max Base Address + 0xb0000000, // Min Base Address + 0xb77effff, // Max Base Address 0x800000000, // Translate 0x77f0000 // Length ) @@ -308,7 +308,7 @@ Scope(_SB) 0x0, // Granularity 0x0, // Min Base Address 0xffff, // Max Base Address - 0x8b7ff0000, // Translate + 0x8b77f0000, // Translate 0x10000 // Length ) }) // Name(RBUF) @@ -575,7 +575,7 @@ Scope(_SB) 0x0, // Translate 0x800000 // Length ) - QwordMemory ( //ECAM space for [bus 0-7] + QwordMemory ( //ECAM space for [bus 78-7f] ResourceConsumer, PosDecode, MinFixed, @@ -583,8 +583,8 @@ Scope(_SB) NonCacheable, ReadWrite, 0x0, // Granularity - 0x8b0000000, // Min Base Address - 0x8b07fffff, // Max Base Address + 0x8b7800000, // Min Base Address + 0x8b7ffffff, // Max Base Address 0x0, // Translate 0x800000 // Length ) diff --git a/Platforms/Hisilicon/D05/D05.dsc b/Platforms/Hisilicon/D05/D05.dsc index 4e4baeb..cb12879 100644 --- a/Platforms/Hisilicon/D05/D05.dsc +++ b/Platforms/Hisilicon/D05/D05.dsc @@ -314,13 +314,13 @@ gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize|0xbf0000 gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress|0xa9400000 gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize|0xbf0000 - gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress|0xa8800000 + gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress|0xa8000000 gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize|0x77f0000 gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress|0xab400000 gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize|0xbf0000 gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress|0xa9000000 gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize|0x2ff0000 - gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress|0xb0800000 + gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress|0xb0000000 gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize|0x77f0000 gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress|0xac900000 gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize|0x36f0000 @@ -345,10 +345,10 @@ gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase|0xA8400000 gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase|0xA9400000 - gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase|0xA8800000 + gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase|0xA8000000 gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase|0xAB400000 gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase|0x8A9000000 - gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase|0x8B0800000 + gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase|0x8B0000000 gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase|0x8AC900000 gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase|0x8B9800000 gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase|0x400A8400000 @@ -362,10 +362,10 @@ gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase|0xa8ff0000 gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase|0xa9ff0000 - gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase|0xafff0000 + gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase|0xaf7f0000 gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase|0xabff0000 gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase|0x8abff0000 - gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase|0x8b7ff0000 + gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase|0x8b77f0000 gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase|0x8afff0000 gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase|0x8bfff0000 gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase|0x400a8ff0000 diff --git a/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c b/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c index 57283a1..ed6c4ac 100644 --- a/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c +++ b/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c @@ -60,8 +60,8 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO /* Port 2 */ { PCI_HB0RB2_ECAM_BASE, - 0x80, //BusBase - 0x87, //BusLimit + 0xF8, //BusBase + 0xFF, //BusLimit PCI_HB0RB2_CPUMEMREGIONBASE ,//MemBase PCI_HB0RB2_CPUMEMREGIONBASE + PCI_HB0RB2_PCIREGION_SIZE - 1, //MemLimit (PCI_HB0RB2_IO_BASE), //IOBase @@ -106,8 +106,8 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO /* Port 5 */ { PCI_HB0RB5_ECAM_BASE,//ecam - 0x0, //BusBase - 0x7, //BusLimit + 0x78, //BusBase + 0x7F, //BusLimit PCI_HB0RB5_CPUMEMREGIONBASE, //Membase PCI_HB0RB5_CPUMEMREGIONBASE + PCI_HB0RB5_PCIREGION_SIZE - 1, //MemLimit (PCI_HB0RB5_IO_BASE), //IoBase From patchwork Tue Sep 19 13:56:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 113008 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp4975242qgf; Tue, 19 Sep 2017 07:17:49 -0700 (PDT) X-Received: by 10.200.25.246 with SMTP id s51mr2182593qtk.70.1505830669480; Tue, 19 Sep 2017 07:17:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505830669; cv=none; d=google.com; s=arc-20160816; b=hb4T9xEMBq3z8uterE/7CVq9srQkjt/nwtq0CvORJvl+cqK9uwP5OwX/jwdxLo2KRx y+GdcSnLGZuoN0bNTlCQEpmnUlFZmQqOtLUQMSTrwJM7u37HOq6Mi/c/35rQ60yzxyfT xhskPDKkCGURq66GfrLFH3ELOUm/LJxIRrmB38j2bO2Yqe3J1QsJcFeSePMW2w8sO7tQ 7oUw/vfcL8haPrYigKmgIaZMgz79gr0CN7yGzhkf/FiIA2TiKUh3M91O3Iugz0+rKIQz gCdpi6dSULsSVHjzbQCYDjY3VcceCVjYmy5hwH7nrHQIA3YA0+uvkL5bqKvtXp9dK6gw +t/g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:delivered-to:arc-authentication-results; bh=uUKPGz5Q3pF9/Ci6ZcO0lSD5silLT6C3278rkvH6k74=; b=qSBPsut7t39lXgLLJsf6f0bR1wzmngRgWb46oPUrwFSGsRy7IafF5cvcmNDO3snwkG kec9lhWH6ed4ENNQtEc1CfC41/NUeDNAM/WiDaFUEp0hI/JhOP38gfVhYQAorJrixdv1 od6fBB+wwMan18vvmD3BbtsWnUoTDRywPlKyzXdEmCSVfyXdPAsP7s8ygQRPrnT1SCQA LEg7Bs0YXTK1YrJOqSENbTQVBpPQB7aEuGE1+SGdUF/sNklX0MTsvzppzxL/2O6JWYNO kB0TpRQtSLjG42r+X4DVEgiPkAWDOfbQy7sRWLJrVS279Nvsx8ZN7/v9KXah3xvk8NfZ Pm5A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.linaro.org (lists.linaro.org. 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Not a substitute for edk2-devel." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" From: huangming Modify smmu Model from 2 to 1, improve es3000 read performance. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ming Huang --- Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl index 494f3f1..be47671 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl @@ -124,7 +124,7 @@ HTTU Override : 0 [0004] Reserved : 00000000 [0008] VATOS Address : 0 -[0004] Model : 00000002 +[0004] Model : 00000001 [0004] Event Interrupt : 00000000 [0004] PRI Interrupt : 00000000 [0004] GERR Interrupt : 00000000 @@ -152,7 +152,7 @@ HTTU Override : 0 [0004] Reserved : 00000000 [0008] VATOS Address : 0 -[0004] Model : 00000002 +[0004] Model : 00000001 [0004] Event Interrupt : 00000000 [0004] PRI Interrupt : 00000000 [0004] GERR Interrupt : 00000000 @@ -186,7 +186,7 @@ HTTU Override : 0 [0A4h 0164 4] Reserved : 00000000 [0A8h 0168 8] VATOS Address : 0000000000000000 -[0B0h 0176 4] Model : 00000002 +[0B0h 0176 4] Model : 00000001 [0B4h 0180 4] Event GSIV : 00000000 [0B8h 0184 4] PRI GSIV : 00000000 [0BCh 0188 4] GERR GSIV : 00000000 @@ -208,7 +208,7 @@ HTTU Override : 0 [0004] Reserved : 00000000 [0008] VATOS Address : 0 -[0004] Model : 00000002 +[0004] Model : 00000001 [0004] Event Interrupt : 00000000 [0004] PRI Interrupt : 00000000 [0004] GERR Interrupt : 00000000 @@ -236,7 +236,7 @@ HTTU Override : 0 [0004] Reserved : 00000000 [0008] VATOS Address : 0 -[0004] Model : 00000002 +[0004] Model : 00000001 [0004] Event Interrupt : 00000000 [0004] PRI Interrupt : 00000000 [0004] GERR Interrupt : 00000000 From patchwork Tue Sep 19 13:56:29 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 113009 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp4975885qgf; Tue, 19 Sep 2017 07:18:21 -0700 (PDT) X-Received: by 10.129.79.67 with SMTP id d64mr1172493ywb.129.1505830701030; Tue, 19 Sep 2017 07:18:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505830701; cv=none; d=google.com; s=arc-20160816; b=wjjI4BaVHWsc1CZN6cj30POBvOngYEezQyz5w/jzmEG8ex76goEcXK/l6dftzAkDB3 ssghmtCWQpbAl8ZnvLXA+4f0AmecD8lb2Ao9hxB1ojDs/5cYGH7e1LmEnXD0p9YPmxT0 sF8zRmbYeScVlYiHlJm82l/wlUOVl9Ilf/oeNkRPSaIOmx2ISc36ZS3Xdovf7DhsHjED ek50gvAmksee2BX3XsFYcPxfBo0D3HaC2cxkDfYsrjZnmbRwaPto3WpYqgb/yxKv3rpS eIA+QqniG4T+JbaumFdb3cDoTCyM11MMb2f+v2hAMrfu3etIM8CSdzxUA3Gp9rTMtt7L hLbg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:delivered-to:arc-authentication-results; bh=UKkiGL/kuGVwerbhJlKrC8fOWEzFmT+wtEpSoESkvE4=; b=KrT8U5+h6SJcy7SU+iOQE/nKcvTRLnErYALRuxeat51YZJI1cI0jXzgXbIPzdvwZ42 yZQGfTZzed52IaU8hk/0EGQJzs/NJDzb4LBeiyp+h4hrmy1wM+qxjefD6O1u6TGirR/H aa/L2AfDz9+wLr9oehOOCtpo+23508HDM7zSOFIExIcFpwwajFvmmUHD90kBU4drVMJE I8I0ZHXHG9T7Baphoxf7/Kn56cG5lnLZu/9STb2szIesEP6+C+2c0QIfIMurx7S7RelD rvEPnNP4WLc7GvZkWP6I9y+zjSqBjIvW6s9h2FfHgZ/VAPruJgBdo726/0usBe6zkLql SnbQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.linaro.org (lists.linaro.org. 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Not a substitute for edk2-devel." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" From: huangming Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: wangzhou --- Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl index be47671..f62b4fc 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl @@ -220,8 +220,15 @@ [0004] Output Reference : 00000064 [0004] Flags (decoded below) : 00000000 Single Mapping : 0 +/* this is the map for PCIe0 in 1P NB */ +[0004] Input base : 00008800 +[0004] ID Count : 00000800 +[0004] Output Base : 00008800 +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000000 + Single Mapping : 0 -//234 +//248 /* 2P NA PCIe SMMU */ [0001] Type : 04 [0002] Length : 0050 @@ -581,7 +588,7 @@ [0004] Input base : 00008800 [0004] ID Count : 00000800 [0004] Output Base : 00008800 -[0004] Output Reference : 0000007c +[0004] Output Reference : 000001e4 [0004] Flags (decoded below) : 00000000 Single Mapping : 0 @@ -695,7 +702,7 @@ [0004] Input base : 00001000 [0004] ID Count : 00001000 [0004] Output Base : 00021000 -[0004] Output Reference : 00000234 +[0004] Output Reference : 00000248 [0004] Flags (decoded below) : 00000000 Single Mapping : 0 From patchwork Tue Sep 19 13:56:30 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 113013 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp4977936qgf; Tue, 19 Sep 2017 07:20:08 -0700 (PDT) X-Received: by 10.200.6.141 with SMTP id f13mr2372175qth.328.1505830808605; Tue, 19 Sep 2017 07:20:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505830808; cv=none; d=google.com; s=arc-20160816; b=AnudaJEqSXAznmK/u5qWfp63C7oL/o8snCIlZsJFt5ifnfi2Cs8nlH+e1ZXID/inEl yuzddVVnz7CtpF0hb1m+TjevXGI4CQ7hUqrFdIAwoJce6OjxtULVVapPId7WnAnbog0i z4rsxLTCZpU2B+Tcl3qQC1V3uv1uvuOvfc2dJ93nsbffWnjK+WjHQXO5C1G17UrQ0Pqf 8YTDpOn4SnukM2AMy0Cn/za1dRYgu+4+tCGt91SoDFfhOFwhv31duq7PgsJvh90AJ5vR CU5Ajp8KYmQtkXqAOvmgvsLDh6Ek7ond/LmYuZGRNsGK+VrRaMI1yG2SPTzApHVOG8oU r+xQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:delivered-to:arc-authentication-results; bh=E0ENomity6CNvEFCWmVmchB8J+dS4fdjP+4QEBvhsL8=; b=oRG0hV+wKXKUNWCWFZ1JLmzDyR+zW0qXgtSnsENqwi/TjHVHk90LOSbzqwL7RfSyQY 5+zEsBM7CGUB2bvjbdFa6hJKFh2AdfUdV7w4CJ0Uic5kIcQiuFVu3lojO5GJXW7T1yLe hRmq4M6GhZgyHfuYpcrJVICstvnscyBnK6PM1wX+/qZXKkIVY5bZULCAhok0kvf76lJA Ys/dU5IvKJUpQKB0tB1hAhfD8WgP5+UTxNTF8vKGf+0fuj2SlX8kZ4TgUw5OYqVh2rHG pxl4J1Dko3gGUkESLGmOi0Pf9vT1Hh1Vz2sj3RRDRmQG6kk0NRT9MnS7JV0yspKxNFZN 2bRg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id j10si9620498qtf.453.2017.09.19.07.20.07; Tue, 19 Sep 2017 07:20:08 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 48FD562C6C; Tue, 19 Sep 2017 14:20:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, RCVD_IN_SORBS_SPAM, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id D2E0D6446B; Tue, 19 Sep 2017 14:11:18 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 079EF62C62; Tue, 19 Sep 2017 14:06:15 +0000 (UTC) Received: from mail-pf0-f170.google.com (mail-pf0-f170.google.com [209.85.192.170]) by lists.linaro.org (Postfix) with ESMTPS id 311B762CE2 for ; Tue, 19 Sep 2017 14:05:56 +0000 (UTC) Received: by mail-pf0-f170.google.com with SMTP id u12so37978pfl.4 for ; Tue, 19 Sep 2017 07:05:56 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=rwNm4jmuiyhJ6009z4AIggWt10mO2JRio3M6HTDImaU=; b=hc5jmGd/zEnOAOTtISgnWgs2XrC4WAArjgUplj1G/cknDjfFaw5aptjWsyog3lx0yT MOXdraDgNoF0749w6KlWrfyQZ2y3HtMNOilf4Q4+a8lpmgsG5a/HTO8/tJJQIEhft00O LTVdTxZnEVVOku4l9VsvIDoGzBxMxIZU0ohT/aoL9W0lqg96/is6TuYFHU1VRmPzG+i3 sTar83zCGYd15Bg/qOkjxAIWy9KHcD7vY4X1klw6bzavG1t2/zlv1LiIeElQ4g/Lm1kF Ga1ORUksBrbrEbddPqbgfxpAO+g0XrLKv1MGcP7NvyGRlTyDEeTlwrQdQncKOSm7fj1t 894Q== X-Gm-Message-State: AHPjjUhI6meRjTxu/o96XfUqQmBwXAxJf8OV+Fk6XzfkenZp3uYrNPvg aivTVsHqozisBmEgHMRDjZKZuML2 X-Google-Smtp-Source: AOwi7QDmVjIztSwpTtes+WQYb5+rrXE8yVIpGyCMeQ3K8oX6mmh2kcBXR8DStxgpBwb+vekPUUR6Mw== X-Received: by 10.159.207.139 with SMTP id z11mr1392680plo.335.1505829955484; Tue, 19 Sep 2017 07:05:55 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id 13sm4390439pfm.138.2017.09.19.07.05.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 19 Sep 2017 07:05:54 -0700 (PDT) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, graeme.gregory@linaro.org Date: Tue, 19 Sep 2017 21:56:30 +0800 Message-Id: <1505829398-52214-25-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1505829398-52214-1-git-send-email-heyi.guo@linaro.org> References: <1505829398-52214-1-git-send-email-heyi.guo@linaro.org> Cc: Ming Huang , zhangjinsong2@huawei.com, huangming23@huawei.com, guoheyi@huawei.com, wanghuiqiang@huawei.com Subject: [Linaro-uefi] [linaro-uefi v1 24/32] D05/ACPI: Disable D05 SAS0 and SAS2 X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: "For discussions about Linaro-related UEFI development. Not a substitute for edk2-devel." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" From: Ming Huang Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ming Huang --- Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl index 93beb95..6455130 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl @@ -88,6 +88,11 @@ Scope(_SB) Store(0x7ffff, CLK) Sleep(1) } + + Method (_STA, 0, NotSerialized) + { + Return (0x0) + } } Device(SAS1) { @@ -239,6 +244,11 @@ Scope(_SB) Store(0x7ffff, CLK) Sleep(1) } + + Method (_STA, 0, NotSerialized) + { + Return (0x0) + } } } From patchwork Tue Sep 19 13:56:31 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 113012 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp4977435qgf; Tue, 19 Sep 2017 07:19:39 -0700 (PDT) X-Received: by 10.37.161.106 with SMTP id z97mr808724ybh.126.1505830779801; Tue, 19 Sep 2017 07:19:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505830779; cv=none; d=google.com; s=arc-20160816; b=mI3xAomVMgg/NwVXIUh3e6v0XfVgDWxt8PWFQPULm1XniQ7MJXPu+w89CA+c1UQOFa B6trR8KlUslRgQTsTLuumSMYf/l1xNSJT4p6wGsnnEPp7fohnRcbL7AUQYjOaxyhWS6s pHCK89/XHZ8pdkc/SKMKTc7xwGd6fXSZhVniX0yCc9lNVQkmrXgEV7FrDd+05cgB8oZA K6Ln5bGfIJ/8ejQrCXVwViItU4UjSPDfEQT0PHje6b5Kt56tzjH+j7zorUgnA0L4FZ+B 2+nSLMhVOCpfE7ErCYOR29FpC4PrWsD+X700t45PDFeodKH72G6fGYEfqiUuUDhRL2Ua aAxg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:delivered-to:arc-authentication-results; bh=y4r1+7kWXWVcyrwp+ZN+x77kOOwp+IMOtaLv4iD8N8M=; b=fN5JNegczOyhiRnNdEQVe+4lYxPIN0+gfpNq626dS+pQbgrjkHuFKyJUFoluaEEQU1 jqVCb01XOBhuXFOOJzjORTLLY+xwH09DHguzgG8hAY7ver5x2D6MH4IIIjKi5Qdf8wEG Dg+ZiSBPQrU8TRmOhJp8/HRmKmFoLgmD/AO1d8gQyu2ughtwX5wXzheWAuqmMAVww9uN Dr0bwC9Dl2vYO/EJ29EQcd2YXNgFBQPVif0swlch/8v8FQgGrZ5ZemG20g2elW8E407/ gjJQRpgUYMmJwhkOllUWQ3GsDi3qWSSza20MqELQnZfl+Bf3Bu2mFl/PuhMLPdSmeV6T +5aQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id n66si9173400qka.134.2017.09.19.07.19.39; Tue, 19 Sep 2017 07:19:39 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 65EB862DF4; Tue, 19 Sep 2017 14:19:39 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id B66E162C7E; Tue, 19 Sep 2017 14:11:16 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 5656A62C6C; Tue, 19 Sep 2017 14:06:14 +0000 (UTC) Received: from mail-pf0-f179.google.com (mail-pf0-f179.google.com [209.85.192.179]) by lists.linaro.org (Postfix) with ESMTPS id 7EA176065A for ; Tue, 19 Sep 2017 14:05:58 +0000 (UTC) Received: by mail-pf0-f179.google.com with SMTP id u12so38028pfl.4 for ; Tue, 19 Sep 2017 07:05:58 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=L2err+evB5FJqHomIagL22Jr0s3aNFWrE4pF5dL76hQ=; b=UOnELosEH/wSJ28K9w50MaeSVb8G2Lh33ZCTAU/udSk08LHcmVIwlG9TihMd44wVOV cel5IIvhK1v+OLfSAxPxqBTpENO+7tCCL+QBZLyMZL3ZgU+5a8pJWYBoUekNi3EiJgCn jD22McOuJqgv2TaNqe/4jiaLPo7bkddNdI11+ATkt6HAVMsRTuGyQVfr4+JxiB2KglOc +u4/7JHfyMnYe8X0UdQHRYKijuW5B9o6KTq6RR/2rn5/domE98Ksh2VhvFmyNKiLVdYn vyQS5cPMsdS4MtYApdNHZYg1p9oQlDA2EDLc2jOz0assvnaRJZYEUBES2a2cvrA4qFJ3 5q+w== X-Gm-Message-State: AHPjjUgw92eBaKloRAd5z1Kl1QOcvoiikq6N/8o+Swox0mxj1OCSNmSH ZLgrN3jA+f02HyVuSi1J/AONw3wX8uD3JA== X-Google-Smtp-Source: AOwi7QBSzVxMWIdTVDkwHiOpf6BylNEVh1JdkjgDBGSr+hVfqIStDJQmRhBzJ/3z08UMYetQt6WPbA== X-Received: by 10.98.217.133 with SMTP id b5mr1432052pfl.227.1505829957841; Tue, 19 Sep 2017 07:05:57 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id 13sm4390439pfm.138.2017.09.19.07.05.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 19 Sep 2017 07:05:57 -0700 (PDT) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, graeme.gregory@linaro.org Date: Tue, 19 Sep 2017 21:56:31 +0800 Message-Id: <1505829398-52214-26-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1505829398-52214-1-git-send-email-heyi.guo@linaro.org> References: <1505829398-52214-1-git-send-email-heyi.guo@linaro.org> Cc: Ming Huang , zhangjinsong2@huawei.com, huangming23@huawei.com, guoheyi@huawei.com, wanghuiqiang@huawei.com Subject: [Linaro-uefi] [linaro-uefi v1 25/32] D05/ACPI: Modify I2C device X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: "For discussions about Linaro-related UEFI development. Not a substitute for edk2-devel." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" From: Ming Huang 1. Disable I2C0 device avoiding access conflict in OS; 2. Modify name of _HID for matching the string in OS driver; Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ming Huang --- Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl | 20 +------------------- 1 file changed, 1 insertion(+), 19 deletions(-) diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl index eb906ef..3cc60d1 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl @@ -18,26 +18,8 @@ Scope(_SB) { - Device(I2C0) { - Name(_HID, "APMC0D0F") - Name(_CID, "APMC0D0F") - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xd00e0000, 0x10000) - Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI6") { 705 } - }) - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"clock-frequency", 100000}, - Package () {"i2c-sda-falling-time-ns", 913}, - Package () {"i2c-scl-falling-time-ns", 303}, - Package () {"i2c-sda-hold-time-ns", 0x9c2}, - } - }) - } - Device(I2C2) { - Name(_HID, "APMC0D0F") + Name(_HID, "HISI02A1") Name(_CID, "APMC0D0F") Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xd0100000, 0x10000) From patchwork Tue Sep 19 13:56:32 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 113015 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp4979064qgf; Tue, 19 Sep 2017 07:21:10 -0700 (PDT) X-Received: by 10.55.10.77 with SMTP id 74mr2144001qkk.226.1505830870048; Tue, 19 Sep 2017 07:21:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505830870; cv=none; d=google.com; s=arc-20160816; b=Qv/cEjCE+6UPphNFm8xSEfKmqU9n342zU+fd/608nhwviWAuxjrwwxG8OiTLLbGivt k3eZ4wTMDr4e5lMWlCGyWgsZ1D+476VY/aIT5In5IsjJCLyYgVBZlt/AJUzi01/KxgUY JI/LSYetcFKcozOKaf6Zm51qz5+ZPKuvG+YUlqhoIr9D/NcLq5rLCg2AlBPh8/k00Ux9 hYddxhoWyoqGOqFHT9RIuyzIOWKrYML+ZVPNAsZyvvsGUuf9LJGccXxQukt2sisxfGFJ OzI3IDYrQSFA4DDznM24T9CbGqkMynft3nburNq/o/mypidIj1uohWjcAyV97jxUaxJn onyw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:delivered-to:arc-authentication-results; bh=vinUrp3jVHK/HD2gwUybwPl9LFFhovd2fF+HoTyGVOg=; b=Zk5R1AfV2gGcIgLZIlQNblIGzChbHm/vvV7+WSORF6epJ3Q9PwQXrGYRRAf64qcjtG PCVPY9FrxbwCPw1w41MhwmtSOFjanoi95p+1wA6lBVmKYEsvE2yFwrz6bG9zKlnzbUQs sl8LYgc4Bmah86bBN4GAObc2yWejU8cahJBqHJZH1P6rfMs8PVwU6IIudLrBYc9uj+Dl OfcFIU+v228nLWg5mttv2SMfmI/RwR5MtG8OqOAIE5KV2LW15i57Gf2RIRbvN8SP2UnK EnSeu9PeyniudOedwRkkUFHlNXGQXE4alokOqK7FeF4Y6bIXRvzKBk80QBUrSB2HFGAE JyWA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id n42si9399277qtc.308.2017.09.19.07.21.09; Tue, 19 Sep 2017 07:21:09 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 63DCA62CE0; Tue, 19 Sep 2017 14:21:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, RCVD_IN_SORBS_SPAM, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 251F762AE3; Tue, 19 Sep 2017 14:11:31 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 1512C62C62; Tue, 19 Sep 2017 14:06:19 +0000 (UTC) Received: from mail-pg0-f41.google.com (mail-pg0-f41.google.com [74.125.83.41]) by lists.linaro.org (Postfix) with ESMTPS id 07A7062B5D for ; Tue, 19 Sep 2017 14:06:01 +0000 (UTC) Received: by mail-pg0-f41.google.com with SMTP id c137so2047354pga.11 for ; Tue, 19 Sep 2017 07:06:00 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5JbMBHZ8k/ydQ+NS5a/OVPKpqp4HcXKwiu4r/HdDiyE=; b=Qvw8t3jWSUIyJhxuIi1gnP4mQp7MVovJwpFGxMmbVHYV6Z6ivfDMwaZQzTJ+TTTGRC FDut1OiPls0JM0lZgbYYstKhoj1nX9wQwpLnxQaqWPfLRIHd2cPo7p45S2x5VZFXP2af KClUTXANDF4+LvY18kLMsu35d9mGdkpBBbYkWJaKNz7ccgpbNvBAHOz24/fvvwnjpQn9 vPgLvfA0A3b2+FuhbAfwVqFJ4RysnnMHd1mor/PJ3A/ZKIep5panwdeQY4r4YgbMzppD +kLHYwUwSQt5x+5bG5bwLGjEHkv69i9Q1fl/rIEJkZK9rsJX6BvYK+S/Be5huZOPy1UO 2jdg== X-Gm-Message-State: AHPjjUhanRxeJZgiiA7GnNkjP7GHfjQJJ+MPDn2aSEFnPdYWtbbXLQ1q K2ZD912cCRrxoWVW23hN/BK1F0tm X-Google-Smtp-Source: AOwi7QAb0NS+DmzmCC7TLaPp7J+vwhi/N/nJhOJUDq2teW0W6LLUq1ki4LKT5fK/Y58DgOoSS6KcJw== X-Received: by 10.98.68.215 with SMTP id m84mr1430487pfi.85.1505829960221; Tue, 19 Sep 2017 07:06:00 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id 13sm4390439pfm.138.2017.09.19.07.05.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 19 Sep 2017 07:05:59 -0700 (PDT) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, graeme.gregory@linaro.org Date: Tue, 19 Sep 2017 21:56:32 +0800 Message-Id: <1505829398-52214-27-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1505829398-52214-1-git-send-email-heyi.guo@linaro.org> References: <1505829398-52214-1-git-send-email-heyi.guo@linaro.org> Cc: Ming Huang , zhangjinsong2@huawei.com, huangming23@huawei.com, guoheyi@huawei.com, wanghuiqiang@huawei.com Subject: [Linaro-uefi] [linaro-uefi v1 26/32] Hisilicon D03/D05: Enlarge iATU for RP with ARI capable device. X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: "For discussions about Linaro-related UEFI development. Not a substitute for edk2-devel." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" From: Ming Huang 1. Because Hi161x chip doesn't support "ARI Forwarding Enable" function, BIOS will enumerate 32 same devices (Device Number 0~31) when attach a Non-ARI capable device in the RP. Hi161x chip will not fix it, need BIOS patch. 2. Just enlarge iatu for those root port with ARI capable device attached, Non-ARI capable device's RP, keep iatu limitation. 3. Remove previous temporary solution as below commit id: "7d157da88852cc91df2b11b10ade2edbbfbe77da" Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jason zhang Conflicts: Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c --- .../Drivers/PciHostBridgeDxe/PciHostBridge.c | 1 + .../Drivers/PciHostBridgeDxe/PciHostBridge.h | 4 ++ .../Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 83 ++++++++++++++++++++-- 3 files changed, 81 insertions(+), 7 deletions(-) // detected multiple times. We work around this by faking absent @@ -2329,3 +2323,78 @@ RootBridgeIoConfiguration ( return EFI_SUCCESS; } +BOOLEAN +PcieCheckAriFwdEn ( + UINTN PciBaseAddr + ) +{ + UINT8 PciPrimaryStatus; + UINT8 CapabilityOffset; + UINT8 CapId; + UINT8 TempData; + + PciPrimaryStatus = MmioRead16 (PciBaseAddr + PCI_PRIMARY_STATUS_OFFSET); + + if (PciPrimaryStatus & EFI_PCI_STATUS_CAPABILITY) { + CapabilityOffset = MmioRead8 (PciBaseAddr + PCI_CAPBILITY_POINTER_OFFSET); + CapabilityOffset &= ~(BIT0 | BIT1); + + while ((CapabilityOffset != 0) && (CapabilityOffset != 0xff)) { + CapId = MmioRead8 (PciBaseAddr + CapabilityOffset); + if (CapId == EFI_PCI_CAPABILITY_ID_PCIEXP) { + break; + } + CapabilityOffset = MmioRead8 (PciBaseAddr + CapabilityOffset + 1); + CapabilityOffset &= ~(BIT0 | BIT1); + } + } else { + PCIE_DEBUG ("[%a:%d] - No PCIE Capability.\n", __FUNCTION__, __LINE__); + return FALSE; + } + + if ((CapabilityOffset == 0xff) || (CapabilityOffset == 0x0)) { + PCIE_DEBUG ("[%a:%d] - No PCIE Capability.\n", __FUNCTION__, __LINE__); + return FALSE; + } + + TempData = MmioRead16 (PciBaseAddr + CapabilityOffset + EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET); + TempData &= EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING; + + if (TempData == EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING) { + return TRUE; + } else { + return FALSE; + } +} + +VOID +EnlargeAtuConfig0 ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This + ) +{ + UINTN RbPciBase; + UINT64 MemLimit; + LIST_ENTRY *List; + PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance; + PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; + + PCIE_DEBUG ("In Enlarge RP iatu Config 0.\n"); + + HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); + List = HostBridgeInstance->Head.ForwardLink; + + while (List != &HostBridgeInstance->Head) { + PCIE_DEBUG ("HostBridge has data.\n"); + RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List); + + RbPciBase = RootBridgeInstance->RbPciBar; + + // Those ARI FWD Enable Root Bridge, need enlarge iatu window. + if (PcieCheckAriFwdEn (RbPciBase)) { + MemLimit = GetPcieCfgAddress (RootBridgeInstance->Ecam, RootBridgeInstance->BusBase + 2, 0, 0, 0) - 1; + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, 1); + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit); + } + List = List->ForwardLink; + } +} diff --git a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c index 6ecc1e5..5bc04a2 100644 --- a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c +++ b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c @@ -839,6 +839,7 @@ NotifyPhase( case EfiPciHostBridgeEndEnumeration: PCIE_DEBUG("Case EfiPciHostBridgeEndEnumeration\n"); + EnlargeAtuConfig0 (This); break; case EfiPciHostBridgeBeginBusAllocation: diff --git a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h index cddda6b..925ed40 100644 --- a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h +++ b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h @@ -518,4 +518,8 @@ RootBridgeConstructor ( IN UINT32 Seg ); +VOID +EnlargeAtuConfig0 ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This + ); #endif diff --git a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c index 2effd7c..b41dbe2 100644 --- a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c @@ -14,6 +14,7 @@ **/ #include "PciHostBridge.h" +#include #include #include #include @@ -1770,13 +1771,6 @@ RootBridgeIoPciRead ( return EFI_INVALID_PARAMETER; } - if ((EfiPciAddress->Bus == 0x81) && (PrivateData->MemBase == 0xAA000000) && (EfiPciAddress->Device > 0)) { - return EFI_NOT_FOUND; - } - if ((EfiPciAddress->Bus == 0x91) && (EfiPciAddress->Device > 0)) { - return EFI_NOT_FOUND; - } - // The UEFI PCI enumerator scans for devices at all possible addresses, // and ignores some PCI rules - this results in some hardware being From patchwork Tue Sep 19 13:56:33 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 113014 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp4978362qgf; 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[54.225.227.206]) by mx.google.com with ESMTP id k71si9741540qke.171.2017.09.19.07.20.31; Tue, 19 Sep 2017 07:20:32 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 4387162C62; Tue, 19 Sep 2017 14:20:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id F0EA46446F; Tue, 19 Sep 2017 14:11:20 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 5D6C762C6C; Tue, 19 Sep 2017 14:06:18 +0000 (UTC) Received: from mail-pf0-f179.google.com (mail-pf0-f179.google.com [209.85.192.179]) by lists.linaro.org (Postfix) with ESMTPS id 517BE62C59 for ; Tue, 19 Sep 2017 14:06:03 +0000 (UTC) Received: by mail-pf0-f179.google.com with SMTP id x78so30659pff.10 for ; Tue, 19 Sep 2017 07:06:03 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=rISdZj+raxHDZd+DZ8Z0fW03N5TQLaij2eT/F+z34Hs=; b=hzUesI6PwSV6WYYsLppTTOxLkQ8okLSPavLB4xYVoJc1TSm2xadaIEU6QFyO8hZCFd M5eRmFM4qcMgLOGYMN0CbKPynfZWlxsvpd3XbbNIESJ6oOyHViZOuuISJiycfcaxLAix svTRQQhIvyX+GPmY0/AEMBnFx9PAaTIYTxuWhWO4OsGwQnCX0MIot1l09hKN8Z2Jp8Kr jeLdbhQKXzlwGiOXhENQc5xPC7ATmgw3WjNyFB/Ft3Smhm8A9UgtalPeqLUCiOIrFOsR BhILVHU+/EoEpSpuqjP0/mk03ivuWM5ATuC8eyq1UAVy2lGrB5nbn/iLF92tMz7w2RFW VSYg== X-Gm-Message-State: AHPjjUhh2EiwChQE2uafLTh32EwPsAI0XUzsoARNLLCFExMwCDhs6wfX 5UK+nxanXf/kXTwvQEtsmlI7zvWW X-Google-Smtp-Source: AOwi7QBTF3QACseq+Ge9XgNrFhtEFwqmc7Opw/ts/6uBXwpoq3xiCscljF2KH2ws7NS3DsgnKLaH9w== X-Received: by 10.99.114.76 with SMTP id c12mr1424907pgn.296.1505829962615; Tue, 19 Sep 2017 07:06:02 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id 13sm4390439pfm.138.2017.09.19.07.06.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 19 Sep 2017 07:06:02 -0700 (PDT) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, graeme.gregory@linaro.org Date: Tue, 19 Sep 2017 21:56:33 +0800 Message-Id: <1505829398-52214-28-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1505829398-52214-1-git-send-email-heyi.guo@linaro.org> References: <1505829398-52214-1-git-send-email-heyi.guo@linaro.org> Cc: Ming Huang , zhangjinsong2@huawei.com, huangming23@huawei.com, guoheyi@huawei.com, wanghuiqiang@huawei.com Subject: [Linaro-uefi] [linaro-uefi v1 27/32] D05/ACPI: Add CPU _STA method X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: "For discussions about Linaro-related UEFI development. Not a substitute for edk2-devel." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" From: Ming Huang Add _STA method for all CPU core device. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: hensonwang --- Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/CPU.asl | 256 ++++++++++++++++++++++ 1 file changed, 256 insertions(+) diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/CPU.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/CPU.asl index 5ecbf50..61a48d6 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/CPU.asl +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/CPU.asl @@ -24,257 +24,513 @@ Scope(_SB) Device(CPU0) { Name(_HID, "ACPI0007") Name(_UID, 0) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CPU1) { Name(_HID, "ACPI0007") Name(_UID, 1) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CPU2) { Name(_HID, "ACPI0007") Name(_UID, 2) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CPU3) { Name(_HID, "ACPI0007") Name(_UID, 3) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CPU4) { Name(_HID, "ACPI0007") Name(_UID, 4) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CPU5) { Name(_HID, "ACPI0007") Name(_UID, 5) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CPU6) { Name(_HID, "ACPI0007") Name(_UID, 6) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CPU7) { Name(_HID, "ACPI0007") Name(_UID, 7) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CPU8) { Name(_HID, "ACPI0007") Name(_UID, 8) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CPU9) { Name(_HID, "ACPI0007") Name(_UID, 9) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CP10) { Name(_HID, "ACPI0007") Name(_UID, 10) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CP11) { Name(_HID, "ACPI0007") Name(_UID, 11) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CP12) { Name(_HID, "ACPI0007") Name(_UID, 12) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CP13) { Name(_HID, "ACPI0007") Name(_UID, 13) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CP14) { Name(_HID, "ACPI0007") Name(_UID, 14) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CP15) { Name(_HID, "ACPI0007") Name(_UID, 15) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CP16) { Name(_HID, "ACPI0007") Name(_UID, 16) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CP17) { Name(_HID, "ACPI0007") Name(_UID, 17) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CP18) { Name(_HID, "ACPI0007") Name(_UID, 18) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CP19) { Name(_HID, "ACPI0007") Name(_UID, 19) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CP20) { Name(_HID, "ACPI0007") Name(_UID, 20) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CP21) { Name(_HID, "ACPI0007") Name(_UID, 21) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CP22) { Name(_HID, "ACPI0007") Name(_UID, 22) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CP23) { Name(_HID, "ACPI0007") Name(_UID, 23) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CP24) { Name(_HID, "ACPI0007") Name(_UID, 24) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CP25) { Name(_HID, "ACPI0007") Name(_UID, 25) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CP26) { Name(_HID, "ACPI0007") Name(_UID, 26) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CP27) { Name(_HID, "ACPI0007") Name(_UID, 27) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CP28) { Name(_HID, "ACPI0007") Name(_UID, 28) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CP29) { Name(_HID, "ACPI0007") Name(_UID, 29) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CP30) { Name(_HID, "ACPI0007") Name(_UID, 30) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CP31) { Name(_HID, "ACPI0007") Name(_UID, 31) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CP32) { Name(_HID, "ACPI0007") Name(_UID, 32) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CP33) { Name(_HID, "ACPI0007") Name(_UID, 33) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CP34) { Name(_HID, "ACPI0007") Name(_UID, 34) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CP35) { Name(_HID, "ACPI0007") Name(_UID, 35) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CP36) { Name(_HID, "ACPI0007") Name(_UID, 36) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CP37) { Name(_HID, "ACPI0007") Name(_UID, 37) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CP38) { Name(_HID, "ACPI0007") Name(_UID, 38) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CP39) { Name(_HID, "ACPI0007") Name(_UID, 39) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CP40) { Name(_HID, "ACPI0007") Name(_UID, 40) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CP41) { Name(_HID, "ACPI0007") Name(_UID, 41) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CP42) { Name(_HID, "ACPI0007") Name(_UID, 42) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CP43) { Name(_HID, "ACPI0007") Name(_UID, 43) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CP44) { Name(_HID, "ACPI0007") Name(_UID, 44) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CP45) { Name(_HID, "ACPI0007") Name(_UID, 45) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CP46) { Name(_HID, "ACPI0007") Name(_UID, 46) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CP47) { Name(_HID, "ACPI0007") Name(_UID, 47) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CP48) { Name(_HID, "ACPI0007") Name(_UID, 48) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CP49) { Name(_HID, "ACPI0007") Name(_UID, 49) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CP50) { Name(_HID, "ACPI0007") Name(_UID, 50) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CP51) { Name(_HID, "ACPI0007") Name(_UID, 51) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CP52) { Name(_HID, "ACPI0007") Name(_UID, 52) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CP53) { Name(_HID, "ACPI0007") Name(_UID, 53) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CP54) { Name(_HID, "ACPI0007") Name(_UID, 54) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CP55) { Name(_HID, "ACPI0007") Name(_UID, 55) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CP56) { Name(_HID, "ACPI0007") Name(_UID, 56) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CP57) { Name(_HID, "ACPI0007") Name(_UID, 57) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CP58) { Name(_HID, "ACPI0007") Name(_UID, 58) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CP59) { Name(_HID, "ACPI0007") Name(_UID, 59) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CP60) { Name(_HID, "ACPI0007") Name(_UID, 60) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CP61) { Name(_HID, "ACPI0007") Name(_UID, 61) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CP62) { Name(_HID, "ACPI0007") Name(_UID, 62) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } Device(CP63) { Name(_HID, "ACPI0007") Name(_UID, 63) + Method(_STA, 0, NotSerialized) + { + Return(0x0F) + } } } From patchwork Tue Sep 19 13:56:34 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 113019 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp4980598qgf; Tue, 19 Sep 2017 07:22:28 -0700 (PDT) X-Received: by 10.237.58.7 with SMTP id n7mr2341517qte.205.1505830948608; Tue, 19 Sep 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[54.225.227.206]) by mx.google.com with ESMTP id g4si982147qkf.442.2017.09.19.07.22.28; Tue, 19 Sep 2017 07:22:28 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 3E48C6091E; Tue, 19 Sep 2017 14:22:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id D4E566447A; Tue, 19 Sep 2017 14:11:49 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 924E06063E; Tue, 19 Sep 2017 14:06:23 +0000 (UTC) Received: from mail-pf0-f175.google.com (mail-pf0-f175.google.com [209.85.192.175]) by lists.linaro.org (Postfix) with ESMTPS id D673262C5C for ; Tue, 19 Sep 2017 14:06:05 +0000 (UTC) Received: by mail-pf0-f175.google.com with SMTP id r71so27552pfe.12 for ; Tue, 19 Sep 2017 07:06:05 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LhdF3/fKmhzERXD1VTrhsNmMizHfPdzY8A+5guDD9mQ=; b=NtHFbVhOI9m1cdHH5bGCImlg61NSkN0MlgyWaFuYDxVDANV46wZT0N5mO5JUmnE/ud BLl1Hvtq9LfY59MrWpcF89vaW1T8Qwlnf34iI7IO2g4SXh+PrfFrCJWQSciJpkE4PPuY 4l6Lb99JBdSchYf+rX3N5TlWA0KXJR927aTeKHcXYXp0th2xdWUVqROG7HhvhdeJS6jE 4LVoGrBV2mVh8epHTjNajxpUVGFvCWvx/qxd0/9oy5w5BWqsxQC9jBpq5FWrruUuvTzf 5S9yq0Iy/OVJ/y18O7ebznHMzTUNpQzlRqCWWVOC9Te2/OspIBICXR1hRR9yjjE/StJG JyBw== X-Gm-Message-State: AHPjjUg4rX8vYIv44k8yffR0chFEuRDDPAAS7z856h9RLVBwMsQBjkEp LeZiLUtTLgTkir4Qqbae2qAdboiK X-Google-Smtp-Source: AOwi7QDcc1mbopq6SVXmf2h7p9+VNxkN1t5Oe0f6I4PM3LQsi1MRVYvn9vmo4vBy/7WckTYpwxtBIw== X-Received: by 10.99.9.65 with SMTP id 62mr1410861pgj.395.1505829965133; Tue, 19 Sep 2017 07:06:05 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id 13sm4390439pfm.138.2017.09.19.07.06.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 19 Sep 2017 07:06:04 -0700 (PDT) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, graeme.gregory@linaro.org Date: Tue, 19 Sep 2017 21:56:34 +0800 Message-Id: <1505829398-52214-29-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1505829398-52214-1-git-send-email-heyi.guo@linaro.org> References: <1505829398-52214-1-git-send-email-heyi.guo@linaro.org> Cc: Ming Huang , zhangjinsong2@huawei.com, huangming23@huawei.com, guoheyi@huawei.com, wanghuiqiang@huawei.com Subject: [Linaro-uefi] [linaro-uefi v1 28/32] D05/ACPI: Update PXM information according to Iort spec. X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: "For discussions about Linaro-related UEFI development. Not a substitute for edk2-devel." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" From: Ming Huang 1. Fix 1P NB PCIe SMMU Length bug. 2. Update PXM information according to Iort spec. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: hensonwang --- Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl | 73 +++++++++++++++--------- 1 file changed, 46 insertions(+), 27 deletions(-) diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl index f62b4fc..1f6f313 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl @@ -112,16 +112,17 @@ //f4 /* 1P NA PCIe SMMU */ [0001] Type : 04 -[0002] Length : 0050 +[0002] Length : 0054 //length added 4 [0001] Revision : 00 [0004] Reserved : 00000000 [0004] Mapping Count : 00000001 -[0004] Mapping Offset : 0000003C +[0004] Mapping Offset : 00000040 //new spec define the length [0008] Base Address : a0040000 -[0004] Flags (decoded below) : 00000001 +[0004] Flags (decoded below) : 00000009 //PXM COHACC Override : 1 HTTU Override : 0 + Proximity Domain Valid: 1 //added for PXM [0004] Reserved : 00000000 [0008] VATOS Address : 0 [0004] Model : 00000001 @@ -129,6 +130,9 @@ [0004] PRI Interrupt : 00000000 [0004] GERR Interrupt : 00000000 [0004] Sync Interrupt : 00000000 +[0001] Proximity domain: 00 +[0001] Reserved1: 00 +[0002] Reserved2: 0000 /* this is the map for PCIe2 in 1P NA */ [0004] Input base : 0002f800 [0004] ID Count : 00000800 @@ -137,19 +141,20 @@ [0004] Flags (decoded below) : 00000000 Single Mapping : 0 -//144 +//148 /* 2P NB PCIe SMMU */ [0001] Type : 04 -[0002] Length : 0064 +[0002] Length : 0068 //length added 4 [0001] Revision : 00 [0004] Reserved : 00000000 [0004] Mapping Count : 00000001 -[0004] Mapping Offset : 0000003C +[0004] Mapping Offset : 00000040 //new spec define the length [0008] Base Address : 700a0040000 -[0004] Flags (decoded below) : 00000001 +[0004] Flags (decoded below) : 00000009 //PXM COHACC Override : 1 HTTU Override : 0 + Proximity Domain Valid: 1 //added for PXM [0004] Reserved : 00000000 [0008] VATOS Address : 0 [0004] Model : 00000001 @@ -157,6 +162,9 @@ [0004] PRI Interrupt : 00000000 [0004] GERR Interrupt : 00000000 [0004] Sync Interrupt : 00000000 +[0001] Proximity domain: 03 +[0001] Reserved1: 00 +[0002] Reserved2: 0000 /* this is the map for pcie0 in 2p nb */ [0004] Input base : 00002000 [0004] Id count : 00001000 @@ -172,18 +180,19 @@ [0004] Flags (decoded below) : 00000000 Single Mapping : 0 -//1a8 +//1b0 [088h 0136 1] Type : 04 -[089h 0137 2] Length : 003C +[089h 0137 2] Length : 0040 //length added 4 [08Bh 0139 1] Revision : 00 [08Ch 0140 4] Reserved : 00000000 [090h 0144 4] Mapping Count : 00000000 -[094h 0148 4] Mapping Offset : 0000003C +[094h 0148 4] Mapping Offset : 00000040 //new spec define the length [098h 0152 8] Base Address : 00000000C0040000 -[0A0h 0160 4] Flags (decoded below) : 00000001 +[0A0h 0160 4] Flags (decoded below) : 00000009 //PXM COHACC Override : 1 HTTU Override : 0 + Proximity Domain Valid: 1 //added for PXM [0A4h 0164 4] Reserved : 00000000 [0A8h 0168 8] VATOS Address : 0000000000000000 [0B0h 0176 4] Model : 00000001 @@ -191,21 +200,24 @@ [0B8h 0184 4] PRI GSIV : 00000000 [0BCh 0188 4] GERR GSIV : 00000000 [0C0h 0192 4] Sync GSIV : 00000000 +[0001] Proximity domain: 00 +[0001] Reserved1: 00 +[0002] Reserved2: 0000 - -//1e4 +//1F0 /* 1P NB PCIe SMMU */ [0001] Type : 04 -[0002] Length : 0050 +[0002] Length : 0068 //length added 4 [0001] Revision : 00 [0004] Reserved : 00000000 [0004] Mapping Count : 00000001 -[0004] Mapping Offset : 0000003C +[0004] Mapping Offset : 00000040 //new spec define the length [0008] Base Address : 8a0040000 -[0004] Flags (decoded below) : 00000001 +[0004] Flags (decoded below) : 00000009 //PXM COHACC Override : 1 HTTU Override : 0 + Proximity Domain Valid: 1 //added for PXM [0004] Reserved : 00000000 [0008] VATOS Address : 0 [0004] Model : 00000001 @@ -213,6 +225,9 @@ [0004] PRI Interrupt : 00000000 [0004] GERR Interrupt : 00000000 [0004] Sync Interrupt : 00000000 +[0001] Proximity domain: 01 +[0001] Reserved1: 00 +[0002] Reserved2: 0000 /* this is the map for PCIe1 in 1P NB */ [0004] Input base : 00017800 [0004] ID Count : 00000800 @@ -228,19 +243,20 @@ [0004] Flags (decoded below) : 00000000 Single Mapping : 0 -//248 +//258 /* 2P NA PCIe SMMU */ [0001] Type : 04 -[0002] Length : 0050 +[0002] Length : 0054 //length added 4 [0001] Revision : 00 [0004] Reserved : 00000000 [0004] Mapping Count : 00000001 -[0004] Mapping Offset : 0000003C +[0004] Mapping Offset : 00000040 //new spec define the length [0008] Base Address : 600a0040000 -[0004] Flags (decoded below) : 00000001 +[0004] Flags (decoded below) : 00000009 //PXM COHACC Override : 1 HTTU Override : 0 + Proximity Domain Valid: 1 //added for PXM [0004] Reserved : 00000000 [0008] VATOS Address : 0 [0004] Model : 00000001 @@ -248,6 +264,9 @@ [0004] PRI Interrupt : 00000000 [0004] GERR Interrupt : 00000000 [0004] Sync Interrupt : 00000000 +[0001] Proximity domain: 02 +[0001] Reserved1: 00 +[0002] Reserved2: 0000 /* this is the map for PCIe2 in 2P NA */ [0004] Input base : 00021000 [0004] ID Count : 00001000 @@ -588,7 +607,7 @@ [0004] Input base : 00008800 [0004] ID Count : 00000800 [0004] Output Base : 00008800 -[0004] Output Reference : 000001e4 +[0004] Output Reference : 000001F0 [0004] Flags (decoded below) : 00000000 Single Mapping : 0 @@ -617,7 +636,7 @@ [0004] Input base : 00007800 [0004] ID Count : 00000800 [0004] Output Base : 00017800 -[0004] Output Reference : 000001e4 +[0004] Output Reference : 000001F0 [0004] Flags (decoded below) : 00000000 Single Mapping : 0 @@ -702,7 +721,7 @@ [0004] Input base : 00001000 [0004] ID Count : 00001000 [0004] Output Base : 00021000 -[0004] Output Reference : 00000248 +[0004] Output Reference : 00000258 [0004] Flags (decoded below) : 00000000 Single Mapping : 0 @@ -731,7 +750,7 @@ [0004] Input base : 00002000 [0004] ID Count : 00001000 [0004] Output Base : 00002000 -[0004] Output Reference : 00000144 +[0004] Output Reference : 00000148 [0004] Flags (decoded below) : 00000000 Single Mapping : 0 @@ -760,7 +779,7 @@ [0004] Input base : 00003000 [0004] ID Count : 00001000 [0004] Output Base : 00013000 -[0004] Output Reference : 00000144 +[0004] Output Reference : 00000148 [0004] Flags (decoded below) : 00000000 Single Mapping : 0 @@ -855,7 +874,7 @@ [38Ch 0908 4] Input base : 00000000 [390h 0912 4] ID Count : 00000001 [394h 0916 4] Output Base : 00040900 -[398h 0920 4] Output Reference : 000001a8 +[398h 0920 4] Output Reference : 000001b0 [39Ch 0924 4] Flags (decoded below) : 00000001 Single Mapping : 1 @@ -952,6 +971,6 @@ [44Ch 1100 4] Input base : 00000000 [450h 1104 4] ID Count : 00000001 [454h 1108 4] Output Base : 00000000 -[458h 1112 4] Output Reference : 000001a8 +[458h 1112 4] Output Reference : 000001b0 [45Ch 1116 4] Flags (decoded below) : 00000001 Single Mapping : 1 From patchwork Tue Sep 19 13:56:35 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 113018 Delivered-To: patch@linaro.org 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Not a substitute for edk2-devel." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" From: Ming Huang Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ming Huang --- Platforms/Hisilicon/D03/D03.dsc | 2 +- Platforms/Hisilicon/D05/D05.dsc | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Platforms/Hisilicon/D03/D03.dsc b/Platforms/Hisilicon/D03/D03.dsc index 8f5df1c..128eab9 100644 --- a/Platforms/Hisilicon/D03/D03.dsc +++ b/Platforms/Hisilicon/D03/D03.dsc @@ -169,7 +169,7 @@ gHisiTokenSpaceGuid.PcdAlgSmmuBaseAddress|0xd0040000 - gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Hisilicon D03 UEFI 16.12 Release" + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Hisilicon D03 UEFI 17.10 Release" gHisiTokenSpaceGuid.PcdBiosVersionString|L"10.01.01T18" diff --git a/Platforms/Hisilicon/D05/D05.dsc b/Platforms/Hisilicon/D05/D05.dsc index cb12879..07aa98f 100644 --- a/Platforms/Hisilicon/D05/D05.dsc +++ b/Platforms/Hisilicon/D05/D05.dsc @@ -190,7 +190,7 @@ gHisiTokenSpaceGuid.PcdIsMPBoot|1 gHisiTokenSpaceGuid.PcdSocketMask|0x3 - gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Hisilicon D05 UEFI 16.12 Release" + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Hisilicon D05 UEFI 17.10 Release" gHisiTokenSpaceGuid.PcdBiosVersionString|L"10.01.01T18" From patchwork Tue Sep 19 13:56:36 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 113016 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp4979470qgf; Tue, 19 Sep 2017 07:21:30 -0700 (PDT) X-Received: by 10.200.50.24 with SMTP id x24mr2350503qta.55.1505830890130; Tue, 19 Sep 2017 07:21:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505830890; cv=none; d=google.com; s=arc-20160816; b=n8fYRwzlvMhxPqkQNY+hyA4KRw6xLWX7RgfupYS9yEjKySg1UJ9y9jFxLGO+4K5FSu mmywuVQ6/JdZ4E0lbCQ3noAPZM45cwir+6ipDH95O9QNgVFVlIjoo/biYs00dvB3nOPK DZk3J69Uammby8eHrcFLtjmTe/8nRF8Of0pMjW9WHqXr99LfIqLE//KSqHx4mdN1/ask qoq4oq1Dl2wZn8N2UM3d21luV2z64PKqRdXdwIw5Z3zi6jMR6HuWLmbATJNWPepi8ni3 TCjZzpa+j7vjcEeOi2tNcBD7PrOE9gskd17rUZJQCZv5cCSH6daMgLw6PS/xcB3b2bYY gBbQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:delivered-to:arc-authentication-results; bh=yrBfXUVI8ovR4K/I/StbIuyWcQBrJQgZ3EZgD2tEdNQ=; b=gFhNXqR/CwjBu/xvrhAovG3neXLg/qN2gDWZmF96FRJflTHA9dCqGuCaovXEpM3oca UAy23nO4YmFMt0/TRBG9NGC1HYQGBcEalwhuGWMLN5aGiHH++6XDDN02BWKkeRfPQ0be wvDspRtW/mBMziIQmxtsswePUJgxPtnw4Cx3cJ03FNEyaJXEyTnErPc2LpOCXh/a79ji Wvy4LPzAvni5ImUsWueZNnuCx4BXHbWCcpb5ipJzt3YPHKKGoUSQgOESGdR2Vz/sQu+X 5ITuQiokNrtG5sRye0UfjRx/jLRuOFTlmV2gylIq8MjRTJEzva+T/pHR84f7vi/Rucbi YOFg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id s124si2216063qkc.307.2017.09.19.07.21.29; Tue, 19 Sep 2017 07:21:30 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 9732660D7F; Tue, 19 Sep 2017 14:21:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, RCVD_IN_SORBS_SPAM, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 49C2A64460; Tue, 19 Sep 2017 14:11:34 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id F3F5E62C59; Tue, 19 Sep 2017 14:06:19 +0000 (UTC) Received: from mail-pf0-f170.google.com (mail-pf0-f170.google.com [209.85.192.170]) by lists.linaro.org (Postfix) with ESMTPS id CF6D062BE4 for ; Tue, 19 Sep 2017 14:06:10 +0000 (UTC) Received: by mail-pf0-f170.google.com with SMTP id d187so29619pfg.11 for ; Tue, 19 Sep 2017 07:06:10 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=yLtXFKi+NzFdSPRgixtdXrBRPZPWrpruBmy+D2f3lBY=; b=d7kYnNS9iS+R6g65IWq1/2mUid8n8VsZoBlI8kAm+ATyLtPDqzoz4VK6mRcueYnXUd irsLDgutKqk8WQjpeOTc8S8VvsQ/bpU6yD+d/19AQE+Bv6JRmSkJ3lStL6Bvis1w734b eDRl6yAFNUJbgzBWTmJLc6qbC4ctG979NWvxfdzVlA2tgkD1H2e3BwWwEJLa008JBeU/ qEyR/m1O80AmnKZ5Sx+Lz1/OkUTjHo2vELSuMyX1tv1Rdb25XA33Vm578jUkVRc1razx Kk40NZbdQxKnA1jbp8iWqfObP6jzpy1Qk3D3mahy1R2NK/9c70kWTEoSgfPy8O7reQyM 3EIA== X-Gm-Message-State: AHPjjUh+WJ4MU0BoHYb7132aJJ4g7FrJEyT/4kC9VmGjIAmoa/UcROFo 8kFlR3sJ2fEFFR3THSi1gA/wleYX X-Google-Smtp-Source: AOwi7QD3mCgI0hYxJIko+25hl7vGuRGEx/9l3dkTI8rxJrWVp7a2LsMind6kAeKV5iViY0Gh55YjgQ== X-Received: by 10.99.168.72 with SMTP id i8mr1458119pgp.427.1505829970123; Tue, 19 Sep 2017 07:06:10 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id 13sm4390439pfm.138.2017.09.19.07.06.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 19 Sep 2017 07:06:09 -0700 (PDT) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, graeme.gregory@linaro.org Date: Tue, 19 Sep 2017 21:56:36 +0800 Message-Id: <1505829398-52214-31-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1505829398-52214-1-git-send-email-heyi.guo@linaro.org> References: <1505829398-52214-1-git-send-email-heyi.guo@linaro.org> Cc: huangming23@huawei.com, zhangjinsong2@huawei.com, guoheyi@huawei.com, Chenhui Sun , wanghuiqiang@huawei.com Subject: [Linaro-uefi] [linaro-uefi v1 30/32] Hisilicon/d03: support nvme pcie driver X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: "For discussions about Linaro-related UEFI development. Not a substitute for edk2-devel." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" Signed-off-by: Chenhui Sun --- Platforms/Hisilicon/D03/D03.dsc | 1 + Platforms/Hisilicon/D03/D03.fdf | 1 + 2 files changed, 2 insertions(+) diff --git a/Platforms/Hisilicon/D03/D03.dsc b/Platforms/Hisilicon/D03/D03.dsc index 128eab9..d856e2b 100644 --- a/Platforms/Hisilicon/D03/D03.dsc +++ b/Platforms/Hisilicon/D03/D03.dsc @@ -479,6 +479,7 @@ OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/Sm750Dxe/UefiSmi.inf + MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf diff --git a/Platforms/Hisilicon/D03/D03.fdf b/Platforms/Hisilicon/D03/D03.fdf index 6d21ffe..599043d 100644 --- a/Platforms/Hisilicon/D03/D03.fdf +++ b/Platforms/Hisilicon/D03/D03.fdf @@ -271,6 +271,7 @@ READ_LOCK_STATUS = TRUE # VGA Driver # INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/Sm750Dxe/UefiSmi.inf + INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/SasPlatform/SasPlatform.inf INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/Drivers/Sas/SasDxeDriver.inf From patchwork Tue Sep 19 13:56:37 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 113017 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp4979953qgf; Tue, 19 Sep 2017 07:21:54 -0700 (PDT) X-Received: by 10.55.162.7 with SMTP id l7mr2007903qke.154.1505830914625; Tue, 19 Sep 2017 07:21:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505830914; cv=none; d=google.com; s=arc-20160816; b=YT5t9SOU/Y1XUfE4kyGf0IBmuu0Zjh2AJvCoEgsEGgjNjDyEoH8HbkP4e363NOMJLI ymPlPZhsGJ4vs8HSdPppl6T37qiwE6xZT0Pv10ywEeVJ5Cb32XPlqpdc7JABAIEFl6aZ /LMpPjkbmOa9cWGHYr6E+Ur3TK3KbFXneZL1uJi4Z1QKrsMDlsUeIalqTUB15+m5gkIe 1Ojs7mAWxysSGqqfJXK9JUHuxGMv6IGvWW6UOSpPbX7tjaFr/uluiho2vHRu4rpN2yI+ 7EPB+dLeoreQrfxJiRE3mC4FuIi3+nKpnNEpyp9mTg1HdV4wHjU687kMkkW2hJh0kjnU DRuQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:delivered-to:arc-authentication-results; bh=F7zb6LbGSbg5E+ZnNwfu0MjGIDyE1HSGu2ECYuYyhI0=; b=v0PHS8de27MtCYVuVpXaByIat69I07TZPXWS5PoeHSOzFWuX8ID36dHvMRr41krfNS ecazb2DyT+vh3rnO2Yc3vogEvhVjW8/rPafM6T9TU02qxRZtsmDrzn7lAkkhVUX9aC9L uQMqk+1YRShtTAxxrghb6yVMgJxARzdVZgqdmjKEQamZL44G3L3w3RH1igNLzukTXkKS dIeu+LAZdpo12Nat6WVq2VZfsz0IDITO9m+vSd1VgamdcS5Rzrg6s8ANWVsvK/URCFiB dCHbeKwvQoBQ08VG93wpQx9iodMB+Rb7JMGZB2FZpvYS9ObXiCxm3VJjZ3EF/4Xz3GYY RTiQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.linaro.org (lists.linaro.org. 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Not a substitute for edk2-devel." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" From: Ming Huang Value of the environment variable FIRMWARE_VER is GIT SHA by default, and you can add the environment variable FIRMWARE_VER to EXTRA_OPTIONS at build time to specify something else, eg. "16.12-". Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ming Huang --- Platforms/Hisilicon/D03/D03.dsc | 6 +++++- Platforms/Hisilicon/D05/D05.dsc | 6 +++++- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/Platforms/Hisilicon/D03/D03.dsc b/Platforms/Hisilicon/D03/D03.dsc index d856e2b..a37adfc 100644 --- a/Platforms/Hisilicon/D03/D03.dsc +++ b/Platforms/Hisilicon/D03/D03.dsc @@ -169,7 +169,11 @@ gHisiTokenSpaceGuid.PcdAlgSmmuBaseAddress|0xd0040000 - gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Hisilicon D03 UEFI 17.10 Release" + !ifdef $(FIRMWARE_VER) + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_VER)" + !else + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Hisilicon D03 UEFI 17.10 Release" + !endif gHisiTokenSpaceGuid.PcdBiosVersionString|L"10.01.01T18" diff --git a/Platforms/Hisilicon/D05/D05.dsc b/Platforms/Hisilicon/D05/D05.dsc index 07aa98f..0ba3eaa 100644 --- a/Platforms/Hisilicon/D05/D05.dsc +++ b/Platforms/Hisilicon/D05/D05.dsc @@ -190,7 +190,11 @@ gHisiTokenSpaceGuid.PcdIsMPBoot|1 gHisiTokenSpaceGuid.PcdSocketMask|0x3 - gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Hisilicon D05 UEFI 17.10 Release" + !ifdef $(FIRMWARE_VER) + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_VER)" + !else + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Hisilicon D05 UEFI 17.10 Release" + !endif gHisiTokenSpaceGuid.PcdBiosVersionString|L"10.01.01T18" From patchwork Tue Sep 19 13:56:38 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 113020 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp4981339qgf; Tue, 19 Sep 2017 07:23:10 -0700 (PDT) X-Received: by 10.200.1.30 with SMTP id e30mr2249040qtg.232.1505830989809; Tue, 19 Sep 2017 07:23:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505830989; cv=none; d=google.com; s=arc-20160816; b=KTbCFDgxN47GCXj7ZQGx//fiaTCkMXMeS3o2/CC/zEI08t5upvWb+QDcc3ORb8xEtP R5v20hAmjTRTXV8IQoOVBhrwbvdNuNcieB2yfH6FYzhdsJWsrI4km7FsUd40S1oRoygF AeNTeI4NetFnmaIIBPsVyZY93cTUBnJ2EJFjaEh0TwUe+a3yPWJ+6UOHcsW6nrfVLxjP XNKpr/oj7q54DIdToC0wkuITV0iO4v0IekdYmfh6r82GAJ8rHd09hZgPnLj100U/6DzP ZmLFlvVGF08ENwd5VpocjZkvycKxcEDm49IhPA3xj0e4JIiIBdDWm/MexEkikr63gfcF qcuw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:delivered-to:arc-authentication-results; bh=AiypNomKRNFIbFyoqLBOf6nHfSd7+FIuYi/RZ55olbk=; b=SrHVUY9P31T2WPj97JMG/ar43nV1XvrzeHUIlD9/zvKC+hDKX89FW5ar+icUb0QEkN U6TcqtiDgyEMi8HuseeCTTHjfZ0j62dhngZgunGTbMrw1aikKRcif+h3LNYDeuhGFuQf LVAop3M3POIt0RTsHgoAcvnKUMCWtQQKBs2O5fKF+1+m/mpRzO3UOEWEXyui6jdR3vsQ g5DosduNpwrsAzzEPJlEM/6whe3Y8WLvnVA21TwGeie01g6jIC0qRA9kYFHPgqyK5SWO Sy1FXD42+Xo8hLsbcseYOohn8QcjVDRXeKIpxb5fPx73uWlqO9GZ74ZpHk5cbsl8c9+w cVGA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id a63si8997906qkf.93.2017.09.19.07.23.09; Tue, 19 Sep 2017 07:23:09 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 63CE46084C; Tue, 19 Sep 2017 14:23:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 3BA1364481; Tue, 19 Sep 2017 14:12:00 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 9CB196063E; Tue, 19 Sep 2017 14:06:27 +0000 (UTC) Received: from mail-pf0-f179.google.com (mail-pf0-f179.google.com [209.85.192.179]) by lists.linaro.org (Postfix) with ESMTPS id 216E16065A for ; Tue, 19 Sep 2017 14:06:17 +0000 (UTC) Received: by mail-pf0-f179.google.com with SMTP id b70so33583pfl.8 for ; Tue, 19 Sep 2017 07:06:17 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=QLggkYilUbJ5cOD1xj4sdYe4vpe/VLFdHZr6dRMQpGA=; b=OkyVP925ThFeJMGCoYMIMVPluQXLWL/Q1svIHzQ1E36tK4rF+ivdIBmZ18fItaQ2sg xXILPRFsNVNTZMmuSFyTUJXeK1xE/qKdXm7dRSdvwgcVUwbljT7nimmsUJWMZRW58O9N AUS4dzdQP/MRCMY9KqUK/H5HzfisLE1TWymHr4UEjYseC8Dw/lOvsGpwqlNlJcYXfXl8 KHvSrGcAu6cuBmXg3n9D8tXZRuTnUPo6RU5sWSJ2aDS9sRVj9cR2d5gnZQPpx6xUg4AE 1AWkEgDmuJv/8UnE7uCPthAcm0KzQnWHJTDyLhqVlDeDy8lTxrKXI3lGHxU6yBEv+3lc axLg== X-Gm-Message-State: AHPjjUg0l1RnVgVBBXURC0uxSHWVZmP/IDD0XSeZrhlfoih39mu3J8Ln 6XdiYKSRTnVQavx+mCjVQ1cFFHnG X-Google-Smtp-Source: AOwi7QDtq1j5hDHqsjXM3AhmM7l0rsXjbgmaKn+M7bgmksE6+aDJhQ28jHsJbkkId1/UzIVP4MmopA== X-Received: by 10.84.217.206 with SMTP id d14mr1474078plj.157.1505829975634; Tue, 19 Sep 2017 07:06:15 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id 13sm4390439pfm.138.2017.09.19.07.06.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 19 Sep 2017 07:06:14 -0700 (PDT) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, graeme.gregory@linaro.org Date: Tue, 19 Sep 2017 21:56:38 +0800 Message-Id: <1505829398-52214-33-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1505829398-52214-1-git-send-email-heyi.guo@linaro.org> References: <1505829398-52214-1-git-send-email-heyi.guo@linaro.org> Cc: huangming23@huawei.com, zhangjinsong2@huawei.com, guoheyi@huawei.com, wanghuiqiang@huawei.com Subject: [Linaro-uefi] [linaro-uefi v1 32/32] Hisilicon/D05: Support Smmu switch X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: "For discussions about Linaro-related UEFI development. Not a substitute for edk2-devel." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" Add file D05IortSmmu.asl and Add 'OemConfig->Support Smmu' setup menu to support Smu enable or disable. Remove Smmu node from D05Iort.asl. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ming Huang --- .../Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c | 74 ++ .../Hi1616/D05AcpiTables/AcpiTablesHi1616.inf | 5 +- Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl | 345 +------- .../Hisilicon/Hi1616/D05AcpiTables/D05IortSmmu.asl | 976 +++++++++++++++++++++ 4 files changed, 1063 insertions(+), 337 deletions(-) create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/D05IortSmmu.asl diff --git a/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c index 7d06fcc..9266c4b 100644 --- a/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c +++ b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c @@ -24,6 +24,76 @@ #define NODE_IN_SOCKET 2 #define CORECOUNT(X) ((X) * CORE_NUM_PER_SOCKET) +#define FIELD_IORT_NODE_OFFSET 40 + +typedef enum { + NodeTypeIts = 0, + NodeTypeNameComponent, + NodeTypePciRC, + NodeTypeSmmuV1, + NodeTypeSmmuV3, + NodeTypePMCG +} IORT_NODE_TYPE; + +#pragma pack(1) +typedef struct { + UINT8 Type; + UINT16 Length; + UINT8 Revision; + UINT32 Reserved; + UINT32 IdMapNumber; + UINT32 IdArrayOffset; +} IORT_NODE_HEAD; +#pragma pack() + +BOOLEAN +IsIortWithSmmu ( + IN EFI_ACPI_DESCRIPTION_HEADER *TableHeader + ) +{ + UINT32 *NodeOffset; + UINT32 NextOffset; + IORT_NODE_HEAD *Node; + + NodeOffset = (UINT32 *)((UINT8 *)TableHeader + FIELD_IORT_NODE_OFFSET); + NextOffset = *NodeOffset; + + while (NextOffset < TableHeader->Length) { + Node = (IORT_NODE_HEAD *)((UINT8 *)TableHeader + NextOffset); + NextOffset += Node->Length; + + if ((Node->Type == NodeTypeSmmuV1) || (Node->Type == NodeTypeSmmuV3)) { + return TRUE; + } + } + + return FALSE; +} + +EFI_STATUS +SelectIort ( + IN EFI_ACPI_DESCRIPTION_HEADER *TableHeader + ) +{ + EFI_STATUS Status; + BOOLEAN EnableSmmu; + + EnableSmmu = 0; + Status = EFI_SUCCESS; + if (IsIortWithSmmu(TableHeader)) { + if (!EnableSmmu) { + Status = EFI_ABORTED; + } + } else { + if (EnableSmmu) { + Status = EFI_ABORTED; + } + } + DEBUG((DEBUG_INFO, "SmmuEnable=%x, return %r for Iort table.\n", EnableSmmu, Status)); + + return Status; +} + STATIC VOID RemoveUnusedMemoryNode ( @@ -132,6 +202,10 @@ UpdateAcpiTable ( case EFI_ACPI_6_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE: Status = UpdateSlit (TableHeader); break; + + case EFI_ACPI_6_1_IO_REMAPPING_TABLE_SIGNATURE: + Status = SelectIort(TableHeader); + break; } return Status; } diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf b/Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf index 9876a50..f3dad78 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf @@ -33,10 +33,11 @@ MadtHi1616.aslc D05Mcfg.aslc D05Iort.asl + D05IortSmmu.asl D05Slit.aslc D05Srat.aslc D05Spcr.aslc - Dbg2.aslc + Dbg2.aslc [Packages] ArmPkg/ArmPkg.dec @@ -56,6 +57,6 @@ gArmTokenSpaceGuid.PcdArmArchTimerIntrNum gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum - gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase + gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl index 1f6f313..9955f6d 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl @@ -109,171 +109,7 @@ [0004] ItsCount : 00000001 [0004] Identifiers : 00000007 -//f4 -/* 1P NA PCIe SMMU */ -[0001] Type : 04 -[0002] Length : 0054 //length added 4 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000040 //new spec define the length - -[0008] Base Address : a0040000 -[0004] Flags (decoded below) : 00000009 //PXM - COHACC Override : 1 - HTTU Override : 0 - Proximity Domain Valid: 1 //added for PXM -[0004] Reserved : 00000000 -[0008] VATOS Address : 0 -[0004] Model : 00000001 -[0004] Event Interrupt : 00000000 -[0004] PRI Interrupt : 00000000 -[0004] GERR Interrupt : 00000000 -[0004] Sync Interrupt : 00000000 -[0001] Proximity domain: 00 -[0001] Reserved1: 00 -[0002] Reserved2: 0000 -/* this is the map for PCIe2 in 1P NA */ -[0004] Input base : 0002f800 -[0004] ID Count : 00000800 -[0004] Output Base : 0000f800 -[0004] Output Reference : 00000064 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 0 - -//148 -/* 2P NB PCIe SMMU */ -[0001] Type : 04 -[0002] Length : 0068 //length added 4 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000040 //new spec define the length - -[0008] Base Address : 700a0040000 -[0004] Flags (decoded below) : 00000009 //PXM - COHACC Override : 1 - HTTU Override : 0 - Proximity Domain Valid: 1 //added for PXM -[0004] Reserved : 00000000 -[0008] VATOS Address : 0 -[0004] Model : 00000001 -[0004] Event Interrupt : 00000000 -[0004] PRI Interrupt : 00000000 -[0004] GERR Interrupt : 00000000 -[0004] Sync Interrupt : 00000000 -[0001] Proximity domain: 03 -[0001] Reserved1: 00 -[0002] Reserved2: 0000 -/* this is the map for pcie0 in 2p nb */ -[0004] Input base : 00002000 -[0004] Id count : 00001000 -[0004] Output base : 00002000 -[0004] Output reference : 00000064 -[0004] Flags (decoded below) : 00000000 - Single mapping : 0 -/* this is the map for PCIe1 in 2P NB */ -[0004] Input base : 00013000 -[0004] ID Count : 00001000 -[0004] Output Base : 00003000 -[0004] Output Reference : 00000064 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 0 -//1b0 -[088h 0136 1] Type : 04 -[089h 0137 2] Length : 0040 //length added 4 -[08Bh 0139 1] Revision : 00 -[08Ch 0140 4] Reserved : 00000000 -[090h 0144 4] Mapping Count : 00000000 -[094h 0148 4] Mapping Offset : 00000040 //new spec define the length - -[098h 0152 8] Base Address : 00000000C0040000 -[0A0h 0160 4] Flags (decoded below) : 00000009 //PXM - COHACC Override : 1 - HTTU Override : 0 - Proximity Domain Valid: 1 //added for PXM -[0A4h 0164 4] Reserved : 00000000 -[0A8h 0168 8] VATOS Address : 0000000000000000 -[0B0h 0176 4] Model : 00000001 -[0B4h 0180 4] Event GSIV : 00000000 -[0B8h 0184 4] PRI GSIV : 00000000 -[0BCh 0188 4] GERR GSIV : 00000000 -[0C0h 0192 4] Sync GSIV : 00000000 -[0001] Proximity domain: 00 -[0001] Reserved1: 00 -[0002] Reserved2: 0000 - -//1F0 -/* 1P NB PCIe SMMU */ -[0001] Type : 04 -[0002] Length : 0068 //length added 4 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000040 //new spec define the length - -[0008] Base Address : 8a0040000 -[0004] Flags (decoded below) : 00000009 //PXM - COHACC Override : 1 - HTTU Override : 0 - Proximity Domain Valid: 1 //added for PXM -[0004] Reserved : 00000000 -[0008] VATOS Address : 0 -[0004] Model : 00000001 -[0004] Event Interrupt : 00000000 -[0004] PRI Interrupt : 00000000 -[0004] GERR Interrupt : 00000000 -[0004] Sync Interrupt : 00000000 -[0001] Proximity domain: 01 -[0001] Reserved1: 00 -[0002] Reserved2: 0000 -/* this is the map for PCIe1 in 1P NB */ -[0004] Input base : 00017800 -[0004] ID Count : 00000800 -[0004] Output Base : 00007800 -[0004] Output Reference : 00000064 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 0 -/* this is the map for PCIe0 in 1P NB */ -[0004] Input base : 00008800 -[0004] ID Count : 00000800 -[0004] Output Base : 00008800 -[0004] Output Reference : 00000064 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 0 - -//258 -/* 2P NA PCIe SMMU */ -[0001] Type : 04 -[0002] Length : 0054 //length added 4 -[0001] Revision : 00 -[0004] Reserved : 00000000 -[0004] Mapping Count : 00000001 -[0004] Mapping Offset : 00000040 //new spec define the length - -[0008] Base Address : 600a0040000 -[0004] Flags (decoded below) : 00000009 //PXM - COHACC Override : 1 - HTTU Override : 0 - Proximity Domain Valid: 1 //added for PXM -[0004] Reserved : 00000000 -[0008] VATOS Address : 0 -[0004] Model : 00000001 -[0004] Event Interrupt : 00000000 -[0004] PRI Interrupt : 00000000 -[0004] GERR Interrupt : 00000000 -[0004] Sync Interrupt : 00000000 -[0001] Proximity domain: 02 -[0001] Reserved1: 00 -[0002] Reserved2: 0000 -/* this is the map for PCIe2 in 2P NA */ -[0004] Input base : 00021000 -[0004] ID Count : 00001000 -[0004] Output Base : 00001000 -[0004] Output Reference : 00000064 -[0004] Flags (decoded below) : 00000000 - Single Mapping : 0 /* mbi-gen peri b, named component */ [0001] Type : 01 @@ -578,8 +414,8 @@ [0004] Input base : 0000f800 [0004] ID Count : 00000800 -[0004] Output Base : 0002f800 -[0004] Output Reference : 000000f4 +[0004] Output Base : 0000f800 +[0004] Output Reference : 00000064 [0004] Flags (decoded below) : 00000000 Single Mapping : 0 /* 1P NB PCIe0 */ @@ -607,7 +443,7 @@ [0004] Input base : 00008800 [0004] ID Count : 00000800 [0004] Output Base : 00008800 -[0004] Output Reference : 000001F0 +[0004] Output Reference : 0000007c [0004] Flags (decoded below) : 00000000 Single Mapping : 0 @@ -635,8 +471,8 @@ [0004] Input base : 00007800 [0004] ID Count : 00000800 -[0004] Output Base : 00017800 -[0004] Output Reference : 000001F0 +[0004] Output Base : 00007800 +[0004] Output Reference : 0000007c [0004] Flags (decoded below) : 00000000 Single Mapping : 0 @@ -720,8 +556,8 @@ [0004] Input base : 00001000 [0004] ID Count : 00001000 -[0004] Output Base : 00021000 -[0004] Output Reference : 00000258 +[0004] Output Base : 00001000 +[0004] Output Reference : 000000c4 [0004] Flags (decoded below) : 00000000 Single Mapping : 0 @@ -750,7 +586,7 @@ [0004] Input base : 00002000 [0004] ID Count : 00001000 [0004] Output Base : 00002000 -[0004] Output Reference : 00000148 +[0004] Output Reference : 000000dc [0004] Flags (decoded below) : 00000000 Single Mapping : 0 @@ -778,8 +614,8 @@ [0004] Input base : 00003000 [0004] ID Count : 00001000 -[0004] Output Base : 00013000 -[0004] Output Reference : 00000148 +[0004] Output Base : 00003000 +[0004] Output Reference : 000000dc [0004] Flags (decoded below) : 00000000 Single Mapping : 0 @@ -813,164 +649,3 @@ [0004] Output Reference : 000000c4 [0004] Flags (decoded below) : 00000001 Single Mapping : 1 - -[320h 0800 1] Type : 01 -[321h 0801 2] Length : 0040 -[323h 0803 1] Revision : 00 -[324h 0804 4] Reserved : 00000000 -[328h 0808 4] Mapping Count : 00000001 -[32Ch 0812 4] Mapping Offset : 0000002C - -[330h 0816 4] Node Flags : 00000000 -[334h 0820 8] Memory Properties : [IORT Memory Access Properties] -[334h 0820 4] Cache Coherency : 00000000 -[338h 0824 1] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[339h 0825 2] Reserved : 0000 -[33Bh 0827 1] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[33Ch 0828 1] Memory Size Limit : 00 -[33Dh 0829 11] Device Name : "\_SB_.USB0" -[348h 0840 24] Padding : \ - 00 00 00 00 00 00 00 00 01 00 00 00 80 00 04 00 \ - 4C 00 00 00 01 00 00 00 - -[34Ch 0844 4] Input base : 00000000 -[350h 0848 4] ID Count : 00000001 -[354h 0852 4] Output Base : 00040080 -[358h 0856 4] Output Reference : 000000F4 -[35Ch 0860 4] Flags (decoded below) : 00000001 - Single Mapping : 1 - -[360h 0864 1] Type : 01 -[361h 0865 2] Length : 0040 -[363h 0867 1] Revision : 00 -[364h 0868 4] Reserved : 00000000 -[368h 0872 4] Mapping Count : 00000001 -[36Ch 0876 4] Mapping Offset : 0000002C - -[370h 0880 4] Node Flags : 00000000 -[374h 0884 8] Memory Properties : [IORT Memory Access Properties] -[374h 0884 4] Cache Coherency : 00000000 -[378h 0888 1] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[379h 0889 2] Reserved : 0000 -[37Bh 0891 1] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[37Ch 0892 1] Memory Size Limit : 00 -[37Dh 0893 11] Device Name : "\_SB_.SAS0" -[388h 0904 24] Padding : \ - 00 00 00 00 00 00 00 00 01 00 00 00 00 01 00 00 \ - 88 00 00 00 01 00 00 00 - -[38Ch 0908 4] Input base : 00000000 -[390h 0912 4] ID Count : 00000001 -[394h 0916 4] Output Base : 00040900 -[398h 0920 4] Output Reference : 000001b0 -[39Ch 0924 4] Flags (decoded below) : 00000001 - Single Mapping : 1 - -[3A0h 0928 1] Type : 01 -[3A1h 0929 2] Length : 0040 -[3A3h 0931 1] Revision : 00 -[3A4h 0932 4] Reserved : 00000000 -[3A8h 0936 4] Mapping Count : 00000001 -[3ACh 0940 4] Mapping Offset : 0000002C - -[3B0h 0944 4] Node Flags : 00000000 -[3B4h 0948 8] Memory Properties : [IORT Memory Access Properties] -[3B4h 0948 4] Cache Coherency : 00000000 -[3B8h 0952 1] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[3B9h 0953 2] Reserved : 0000 -[3BBh 0955 1] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[3BCh 0956 1] Memory Size Limit : 00 -[3BDh 0957 11] Device Name : "\_SB_.SAS1" -[3C8h 0968 24] Padding : \ - 00 00 00 00 00 00 00 00 01 00 00 00 00 00 04 00 \ - 4C 00 00 00 01 00 00 00 - -[3CCh 0972 4] Input base : 00000000 -[3D0h 0976 4] ID Count : 00000001 -[3D4h 0980 4] Output Base : 00040000 -[3D8h 0984 4] Output Reference : 000000F4 -[3DCh 0988 4] Flags (decoded below) : 00000001 - Single Mapping : 1 - -[3E0h 0992 1] Type : 01 -[3E1h 0993 2] Length : 0040 -[3E3h 0995 1] Revision : 00 -[3E4h 0996 4] Reserved : 00000000 -[3E8h 1000 4] Mapping Count : 00000001 -[3ECh 1004 4] Mapping Offset : 0000002C - -[3F0h 1008 4] Node Flags : 00000000 -[3F4h 1012 8] Memory Properties : [IORT Memory Access Properties] -[3F4h 1012 4] Cache Coherency : 00000000 -[3F8h 1016 1] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[3F9h 1017 2] Reserved : 0000 -[3FBh 1019 1] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[3FCh 1020 1] Memory Size Limit : 00 -[3FDh 1021 11] Device Name : "\_SB_.SAS2" -[408h 1032 24] Padding : \ - 00 00 00 00 00 00 00 00 01 00 00 00 40 00 04 00 \ - 4C 00 00 00 01 00 00 00 - -[40Ch 1036 4] Input base : 00000000 -[410h 1040 4] ID Count : 00000001 -[414h 1044 4] Output Base : 00040040 -[418h 1048 4] Output Reference : 000000F4 -[41Ch 1052 4] Flags (decoded below) : 00000001 - Single Mapping : 1 - -/*HNS smmu*/ -[420h 1056 1] Type : 01 -[421h 1057 2] Length : 0040 -[423h 1059 1] Revision : 00 -[424h 1060 4] Reserved : 00000000 -[428h 1064 4] Mapping Count : 00000001 -[42Ch 1068 4] Mapping Offset : 0000002C - -[430h 1072 4] Node Flags : 00000000 -[434h 1076 8] Memory Properties : [IORT Memory Access Properties] -[434h 1076 4] Cache Coherency : 00000000 -[438h 1080 1] Hints (decoded below) : 00 - Transient : 0 - Write Allocate : 0 - Read Allocate : 0 - Override : 0 -[439h 1081 2] Reserved : 0000 -[43Bh 1083 1] Memory Flags (decoded below) : 00 - Coherency : 0 - Device Attribute : 0 -[43Ch 1084 1] Memory Size Limit : 00 -[43Dh 1085 11] Device Name : "\_SB_.DSF0" -[448h 1096 24] Padding : \ - 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 \ - 94 01 00 00 01 00 00 00 - -[44Ch 1100 4] Input base : 00000000 -[450h 1104 4] ID Count : 00000001 -[454h 1108 4] Output Base : 00000000 -[458h 1112 4] Output Reference : 000001b0 -[45Ch 1116 4] Flags (decoded below) : 00000001 - Single Mapping : 1 diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05IortSmmu.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05IortSmmu.asl new file mode 100644 index 0000000..9ae7a43 --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05IortSmmu.asl @@ -0,0 +1,976 @@ +/* + * Intel ACPI Component Architecture + * iASL Compiler/Disassembler version 20151124-64 + * Copyright (c) 2000 - 2017 Intel Corporation + * + * Template for [IORT] ACPI Table (static data table) + * Format: [ByteLength] FieldName : HexFieldValue + */ +[0004] Signature : "IORT" [IO Remapping Table] +[0004] Table Length : 000002e4 +[0001] Revision : 00 +[0001] Checksum : BC +[0006] Oem ID : "HISI " +[0008] Oem Table ID : "HIP07 " +[0004] Oem Revision : 00000000 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20151124 + +[0004] Node Count : 00000008 +[0004] Node Offset : 00000034 +[0004] Reserved : 00000000 +[0004] Optional Padding : 00 00 00 00 + +/* ITS 0, for peri a */ +[0001] Type : 00 +[0002] Length : 0018 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000000 +[0004] Mapping Offset : 00000000 + +[0004] ItsCount : 00000001 +[0004] Identifiers : 00000000 +//4c +/* ITS 1, for peri b */ +[0001] Type : 00 +[0002] Length : 0018 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000000 +[0004] Mapping Offset : 00000000 + +[0004] ItsCount : 00000001 +[0004] Identifiers : 00000001 +//64 +/* ITS 2, for dsa a */ +[0001] Type : 00 +[0002] Length : 0018 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000000 +[0004] Mapping Offset : 00000000 + +[0004] ItsCount : 00000001 +[0004] Identifiers : 00000002 +//7c +/* ITS 3, for dsa b */ +[0001] Type : 00 +[0002] Length : 0018 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000000 +[0004] Mapping Offset : 00000000 + +[0004] ItsCount : 00000001 +[0004] Identifiers : 00000003 +//94 +/*Sec CPU ITS 0, for peri a */ +[0001] Type : 00 +[0002] Length : 0018 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000000 +[0004] Mapping Offset : 00000000 + +[0004] ItsCount : 00000001 +[0004] Identifiers : 00000004 +//ac +/* SEC CPU ITS 1, for peri b */ +[0001] Type : 00 +[0002] Length : 0018 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000000 +[0004] Mapping Offset : 00000000 + +[0004] ItsCount : 00000001 +[0004] Identifiers : 00000005 +//c4 +/* SEC CPU ITS 2, for dsa a */ +[0001] Type : 00 +[0002] Length : 0018 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000000 +[0004] Mapping Offset : 00000000 + +[0004] ItsCount : 00000001 +[0004] Identifiers : 00000006 +//dc +/* SEC CPU ITS 3, for dsa b */ +[0001] Type : 00 +[0002] Length : 0018 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000000 +[0004] Mapping Offset : 00000000 + +[0004] ItsCount : 00000001 +[0004] Identifiers : 00000007 + +//f4 +/* 1P NA PCIe SMMU */ +[0001] Type : 04 +[0002] Length : 0054 //length added 4 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000040 //new spec define the length + +[0008] Base Address : a0040000 +[0004] Flags (decoded below) : 00000009 //PXM + COHACC Override : 1 + HTTU Override : 0 + Proximity Domain Valid: 1 //added for PXM +[0004] Reserved : 00000000 +[0008] VATOS Address : 0 +[0004] Model : 00000001 +[0004] Event Interrupt : 00000000 +[0004] PRI Interrupt : 00000000 +[0004] GERR Interrupt : 00000000 +[0004] Sync Interrupt : 00000000 +[0001] Proximity domain: 00 +[0001] Reserved1: 00 +[0002] Reserved2: 0000 +/* this is the map for PCIe2 in 1P NA */ +[0004] Input base : 0002f800 +[0004] ID Count : 00000800 +[0004] Output Base : 0000f800 +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000000 + Single Mapping : 0 + +//148 +/* 2P NB PCIe SMMU */ +[0001] Type : 04 +[0002] Length : 0068 //length added 4 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000040 //new spec define the length + +[0008] Base Address : 700a0040000 +[0004] Flags (decoded below) : 00000009 //PXM + COHACC Override : 1 + HTTU Override : 0 + Proximity Domain Valid: 1 //added for PXM +[0004] Reserved : 00000000 +[0008] VATOS Address : 0 +[0004] Model : 00000001 +[0004] Event Interrupt : 00000000 +[0004] PRI Interrupt : 00000000 +[0004] GERR Interrupt : 00000000 +[0004] Sync Interrupt : 00000000 +[0001] Proximity domain: 03 +[0001] Reserved1: 00 +[0002] Reserved2: 0000 +/* this is the map for pcie0 in 2p nb */ +[0004] Input base : 00002000 +[0004] Id count : 00001000 +[0004] Output base : 00002000 +[0004] Output reference : 00000064 +[0004] Flags (decoded below) : 00000000 + Single mapping : 0 +/* this is the map for PCIe1 in 2P NB */ +[0004] Input base : 00013000 +[0004] ID Count : 00001000 +[0004] Output Base : 00003000 +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000000 + Single Mapping : 0 + +//1b0 +[088h 0136 1] Type : 04 +[089h 0137 2] Length : 0040 //length added 4 +[08Bh 0139 1] Revision : 00 +[08Ch 0140 4] Reserved : 00000000 +[090h 0144 4] Mapping Count : 00000000 +[094h 0148 4] Mapping Offset : 00000040 //new spec define the length + +[098h 0152 8] Base Address : 00000000C0040000 +[0A0h 0160 4] Flags (decoded below) : 00000009 //PXM + COHACC Override : 1 + HTTU Override : 0 + Proximity Domain Valid: 1 //added for PXM +[0A4h 0164 4] Reserved : 00000000 +[0A8h 0168 8] VATOS Address : 0000000000000000 +[0B0h 0176 4] Model : 00000001 +[0B4h 0180 4] Event GSIV : 00000000 +[0B8h 0184 4] PRI GSIV : 00000000 +[0BCh 0188 4] GERR GSIV : 00000000 +[0C0h 0192 4] Sync GSIV : 00000000 +[0001] Proximity domain: 00 +[0001] Reserved1: 00 +[0002] Reserved2: 0000 + +//1F0 +/* 1P NB PCIe SMMU */ +[0001] Type : 04 +[0002] Length : 0068 //length added 4 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000040 //new spec define the length + +[0008] Base Address : 8a0040000 +[0004] Flags (decoded below) : 00000009 //PXM + COHACC Override : 1 + HTTU Override : 0 + Proximity Domain Valid: 1 //added for PXM +[0004] Reserved : 00000000 +[0008] VATOS Address : 0 +[0004] Model : 00000001 +[0004] Event Interrupt : 00000000 +[0004] PRI Interrupt : 00000000 +[0004] GERR Interrupt : 00000000 +[0004] Sync Interrupt : 00000000 +[0001] Proximity domain: 01 +[0001] Reserved1: 00 +[0002] Reserved2: 0000 +/* this is the map for PCIe1 in 1P NB */ +[0004] Input base : 00017800 +[0004] ID Count : 00000800 +[0004] Output Base : 00007800 +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000000 + Single Mapping : 0 +/* this is the map for PCIe0 in 1P NB */ +[0004] Input base : 00008800 +[0004] ID Count : 00000800 +[0004] Output Base : 00008800 +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000000 + Single Mapping : 0 + +//258 +/* 2P NA PCIe SMMU */ +[0001] Type : 04 +[0002] Length : 0054 //length added 4 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000040 //new spec define the length + +[0008] Base Address : 600a0040000 +[0004] Flags (decoded below) : 00000009 //PXM + COHACC Override : 1 + HTTU Override : 0 + Proximity Domain Valid: 1 //added for PXM +[0004] Reserved : 00000000 +[0008] VATOS Address : 0 +[0004] Model : 00000001 +[0004] Event Interrupt : 00000000 +[0004] PRI Interrupt : 00000000 +[0004] GERR Interrupt : 00000000 +[0004] Sync Interrupt : 00000000 +[0001] Proximity domain: 02 +[0001] Reserved1: 00 +[0002] Reserved2: 0000 +/* this is the map for PCIe2 in 2P NA */ +[0004] Input base : 00021000 +[0004] ID Count : 00001000 +[0004] Output Base : 00001000 +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000000 + Single Mapping : 0 + +/* mbi-gen peri b, named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032 + +[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0001] Memory Size Limit : 00 +[0016] Device Name : "\_SB_.MBI0" +[0004] Padding : 00 00 00 00 + +[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 000120c7 //device id +[0004] Output Reference : 0000004C +[0004] Flags (decoded below) : 00000001 + Single Mapping : 1 + +/* mbi-gen1 dsa a, named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032 + +[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0001] Memory Size Limit : 00 +[0016] Device Name : "\_SB_.MBI1" +[0004] Padding : 00 00 00 00 + +[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040800 //device id +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000001 + Single Mapping : 1 + +/* mbi-gen mbi7 - RoCE named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032 + +[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0001] Memory Size Limit : 00 +[0016] Device Name : "\_SB_.MBI9" +[0004] Padding : 00 00 00 00 + +[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040b1e +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000001 + Single Mapping : 1 + +/* mbi-gen dsa a - usb named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032 + +[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0001] Memory Size Limit : 00 +[0016] Device Name : "\_SB_.MBI5" +[0004] Padding : 00 00 00 00 + +[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040080 //device id +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000001 + Single Mapping : 1 + +/* mbi-gen1 dsa a, named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032 + +[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0001] Memory Size Limit : 00 +[0016] Device Name : "\_SB_.MBI2" +[0004] Padding : 00 00 00 00 + +[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040900 //device id +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000001 + Single Mapping : 1 + +/* mbi-gen1 pcie, named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032 + +[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0001] Memory Size Limit : 00 +[0016] Device Name : "\_SB_.MBI3" +[0004] Padding : 00 00 00 00 + +[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040000 //device id +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000001 + Single Mapping : 1 + +/* mbi-gen1 pcie, named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032 + +[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0001] Memory Size Limit : 00 +[0016] Device Name : "\_SB_.MBI4" +[0004] Padding : 00 00 00 00 + +[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040040 //device id +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000001 + Single Mapping : 1 + +/* mbi-gen1 alg a, i2c 0 named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032 + +[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0001] Memory Size Limit : 00 +[0016] Device Name : "\_SB_.MBI6" +[0004] Padding : 00 00 00 00 + +[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040B0E //device id +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000001 + Single Mapping : 1 + +/* mbi-gen1 alg a, i2c 2 named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032 + +[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0001] Memory Size Limit : 00 +[0016] Device Name : "\_SB_.MBI7" +[0004] Padding : 00 00 00 00 + +[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040B10 //device id +[0004] Output Reference : 00000064 +[0004] Flags (decoded below) : 00000001 + Single Mapping : 1 + +/*1P NA PCIe2 */ +[0001] Type : 02 +[0002] Length : 0034 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000020 + +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000001 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 01 + Coherency : 1 + Device Attribute : 0 +[0004] ATS Attribute : 00000000 +[0004] PCI Segment Number : 00000002 + +[0004] Input base : 0000f800 +[0004] ID Count : 00000800 +[0004] Output Base : 0002f800 +[0004] Output Reference : 000000f4 +[0004] Flags (decoded below) : 00000000 + Single Mapping : 0 +/* 1P NB PCIe0 */ +[0001] Type : 02 +[0002] Length : 0034 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000020 + +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000001 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 01 + Coherency : 1 + Device Attribute : 0 +[0004] ATS Attribute : 00000000 +[0004] PCI Segment Number : 00000004 + +[0004] Input base : 00008800 +[0004] ID Count : 00000800 +[0004] Output Base : 00008800 +[0004] Output Reference : 000001F0 +[0004] Flags (decoded below) : 00000000 + Single Mapping : 0 + +/* 1P NB PCIe1 */ +[0001] Type : 02 +[0002] Length : 0034 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000020 + +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000001 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 01 + Coherency : 1 + Device Attribute : 0 +[0004] ATS Attribute : 00000000 +[0004] PCI Segment Number : 00000005 + +[0004] Input base : 00007800 +[0004] ID Count : 00000800 +[0004] Output Base : 00017800 +[0004] Output Reference : 000001F0 +[0004] Flags (decoded below) : 00000000 + Single Mapping : 0 + +/* 1P NB PCIe2 */ +[0001] Type : 02 +[0002] Length : 0034 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000020 + +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000001 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 01 + Coherency : 1 + Device Attribute : 0 +[0004] ATS Attribute : 00000000 +[0004] PCI Segment Number : 00000006 + +[0004] Input base : 0000c000 +[0004] ID Count : 00000800 +[0004] Output Base : 0000c000 +[0004] Output Reference : 0000007c +[0004] Flags (decoded below) : 00000000 + Single Mapping : 0 +/* 1P NB PCIe3 */ +[0001] Type : 02 +[0002] Length : 0034 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000020 + +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000001 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 01 + Coherency : 1 + Device Attribute : 0 +[0004] ATS Attribute : 00000000 +[0004] PCI Segment Number : 00000007 + +[0004] Input base : 00009000 +[0004] ID Count : 00000800 +[0004] Output Base : 00009000 +[0004] Output Reference : 0000007c +[0004] Flags (decoded below) : 00000000 + Single Mapping : 0 +/* 2P NA PCIe2*/ +[0001] Type : 02 +[0002] Length : 0034 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000020 + +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000001 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 01 + Coherency : 1 + Device Attribute : 0 +[0004] ATS Attribute : 00000000 +[0004] PCI Segment Number : 0000000a + +[0004] Input base : 00001000 +[0004] ID Count : 00001000 +[0004] Output Base : 00021000 +[0004] Output Reference : 00000258 +[0004] Flags (decoded below) : 00000000 + Single Mapping : 0 + +/* 2P NB PCIe0*/ +[0001] Type : 02 +[0002] Length : 0034 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000020 + +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000001 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 01 + Coherency : 1 + Device Attribute : 0 +[0004] ATS Attribute : 00000000 +[0004] PCI Segment Number : 0000000c + +[0004] Input base : 00002000 +[0004] ID Count : 00001000 +[0004] Output Base : 00002000 +[0004] Output Reference : 00000148 +[0004] Flags (decoded below) : 00000000 + Single Mapping : 0 + + /* 2P NB PCIe1*/ +[0001] Type : 02 +[0002] Length : 0034 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000020 + +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000001 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 01 + Coherency : 1 + Device Attribute : 0 +[0004] ATS Attribute : 00000000 +[0004] PCI Segment Number : 0000000d + +[0004] Input base : 00003000 +[0004] ID Count : 00001000 +[0004] Output Base : 00013000 +[0004] Output Reference : 00000148 +[0004] Flags (decoded below) : 00000000 + Single Mapping : 0 + +/* mbi-gen1 P1 dsa a, named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032 + +[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0001] Memory Size Limit : 00 +[0016] Device Name : "\_SB_.MBI8" +[0004] Padding : 00 00 00 00 + +[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00044800 //device id +[0004] Output Reference : 000000c4 +[0004] Flags (decoded below) : 00000001 + Single Mapping : 1 + +[320h 0800 1] Type : 01 +[321h 0801 2] Length : 0040 +[323h 0803 1] Revision : 00 +[324h 0804 4] Reserved : 00000000 +[328h 0808 4] Mapping Count : 00000001 +[32Ch 0812 4] Mapping Offset : 0000002C + +[330h 0816 4] Node Flags : 00000000 +[334h 0820 8] Memory Properties : [IORT Memory Access Properties] +[334h 0820 4] Cache Coherency : 00000000 +[338h 0824 1] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[339h 0825 2] Reserved : 0000 +[33Bh 0827 1] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[33Ch 0828 1] Memory Size Limit : 00 +[33Dh 0829 11] Device Name : "\_SB_.USB0" +[348h 0840 24] Padding : \ + 00 00 00 00 00 00 00 00 01 00 00 00 80 00 04 00 \ + 4C 00 00 00 01 00 00 00 + +[34Ch 0844 4] Input base : 00000000 +[350h 0848 4] ID Count : 00000001 +[354h 0852 4] Output Base : 00040080 +[358h 0856 4] Output Reference : 000000F4 +[35Ch 0860 4] Flags (decoded below) : 00000001 + Single Mapping : 1 + +[360h 0864 1] Type : 01 +[361h 0865 2] Length : 0040 +[363h 0867 1] Revision : 00 +[364h 0868 4] Reserved : 00000000 +[368h 0872 4] Mapping Count : 00000001 +[36Ch 0876 4] Mapping Offset : 0000002C + +[370h 0880 4] Node Flags : 00000000 +[374h 0884 8] Memory Properties : [IORT Memory Access Properties] +[374h 0884 4] Cache Coherency : 00000000 +[378h 0888 1] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[379h 0889 2] Reserved : 0000 +[37Bh 0891 1] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[37Ch 0892 1] Memory Size Limit : 00 +[37Dh 0893 11] Device Name : "\_SB_.SAS0" +[388h 0904 24] Padding : \ + 00 00 00 00 00 00 00 00 01 00 00 00 00 01 00 00 \ + 88 00 00 00 01 00 00 00 + +[38Ch 0908 4] Input base : 00000000 +[390h 0912 4] ID Count : 00000001 +[394h 0916 4] Output Base : 00040900 +[398h 0920 4] Output Reference : 000001b0 +[39Ch 0924 4] Flags (decoded below) : 00000001 + Single Mapping : 1 + +[3A0h 0928 1] Type : 01 +[3A1h 0929 2] Length : 0040 +[3A3h 0931 1] Revision : 00 +[3A4h 0932 4] Reserved : 00000000 +[3A8h 0936 4] Mapping Count : 00000001 +[3ACh 0940 4] Mapping Offset : 0000002C + +[3B0h 0944 4] Node Flags : 00000000 +[3B4h 0948 8] Memory Properties : [IORT Memory Access Properties] +[3B4h 0948 4] Cache Coherency : 00000000 +[3B8h 0952 1] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[3B9h 0953 2] Reserved : 0000 +[3BBh 0955 1] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[3BCh 0956 1] Memory Size Limit : 00 +[3BDh 0957 11] Device Name : "\_SB_.SAS1" +[3C8h 0968 24] Padding : \ + 00 00 00 00 00 00 00 00 01 00 00 00 00 00 04 00 \ + 4C 00 00 00 01 00 00 00 + +[3CCh 0972 4] Input base : 00000000 +[3D0h 0976 4] ID Count : 00000001 +[3D4h 0980 4] Output Base : 00040000 +[3D8h 0984 4] Output Reference : 000000F4 +[3DCh 0988 4] Flags (decoded below) : 00000001 + Single Mapping : 1 + +[3E0h 0992 1] Type : 01 +[3E1h 0993 2] Length : 0040 +[3E3h 0995 1] Revision : 00 +[3E4h 0996 4] Reserved : 00000000 +[3E8h 1000 4] Mapping Count : 00000001 +[3ECh 1004 4] Mapping Offset : 0000002C + +[3F0h 1008 4] Node Flags : 00000000 +[3F4h 1012 8] Memory Properties : [IORT Memory Access Properties] +[3F4h 1012 4] Cache Coherency : 00000000 +[3F8h 1016 1] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[3F9h 1017 2] Reserved : 0000 +[3FBh 1019 1] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[3FCh 1020 1] Memory Size Limit : 00 +[3FDh 1021 11] Device Name : "\_SB_.SAS2" +[408h 1032 24] Padding : \ + 00 00 00 00 00 00 00 00 01 00 00 00 40 00 04 00 \ + 4C 00 00 00 01 00 00 00 + +[40Ch 1036 4] Input base : 00000000 +[410h 1040 4] ID Count : 00000001 +[414h 1044 4] Output Base : 00040040 +[418h 1048 4] Output Reference : 000000F4 +[41Ch 1052 4] Flags (decoded below) : 00000001 + Single Mapping : 1 + +/*HNS smmu*/ +[420h 1056 1] Type : 01 +[421h 1057 2] Length : 0040 +[423h 1059 1] Revision : 00 +[424h 1060 4] Reserved : 00000000 +[428h 1064 4] Mapping Count : 00000001 +[42Ch 1068 4] Mapping Offset : 0000002C + +[430h 1072 4] Node Flags : 00000000 +[434h 1076 8] Memory Properties : [IORT Memory Access Properties] +[434h 1076 4] Cache Coherency : 00000000 +[438h 1080 1] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[439h 1081 2] Reserved : 0000 +[43Bh 1083 1] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[43Ch 1084 1] Memory Size Limit : 00 +[43Dh 1085 11] Device Name : "\_SB_.DSF0" +[448h 1096 24] Padding : \ + 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 \ + 94 01 00 00 01 00 00 00 + +[44Ch 1100 4] Input base : 00000000 +[450h 1104 4] ID Count : 00000001 +[454h 1108 4] Output Base : 00000000 +[458h 1112 4] Output Reference : 000001b0 +[45Ch 1116 4] Flags (decoded below) : 00000001 + Single Mapping : 1