From patchwork Fri Sep 22 03:46:38 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 113954 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp2798505qgf; Thu, 21 Sep 2017 20:49:54 -0700 (PDT) X-Google-Smtp-Source: AOwi7QBEanI/G/CBONjj0gkoYUh2Q9bromvCp8JZqyHbjbyJ/FRY5DkgM35OhrCf5V/PTZooqSbS X-Received: by 10.99.186.12 with SMTP id k12mr7778185pgf.276.1506052194768; Thu, 21 Sep 2017 20:49:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506052194; cv=none; d=google.com; s=arc-20160816; b=0ftua5qluQyph/5Po8+7Pqa1eIpR///Zmv1GacztJlbFLeuGVKES3OoSp+cZhUE47i l/qwUi6ip/x26jCzT+1DwNjrIfSycveRBgLQbzkOecQ6rDsbfgVY6uiO6SqTpAZrYrr5 HXVD8OGoRvWifj/HYHFa+9H6YyaTVftUAmXtjZ1vldCLHhI2rs2u0+u90PNWigLzW5+K BpQMGZk0med3vmAPLbjszdK+eFaw6q6ec6YaTfgtij+QlNPvzxkVoxGqLhi6//QYNauJ 6Nfr8SHHuKdw8y0912uRg0iGGun7pOZ9kEy/V+bYmChCNU/Bqq+95nbGzmkWGN4eAtWM 0lcg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:dkim-filter :arc-authentication-results; bh=59fdI7+UE95X4PNnOZNZNKCOmyNFFdGozGYIY/JOjgk=; b=vkyemHDHsG/31/GvigHZF0x3QjmGOX5fymJtiiYfDj+7seIemWVCRRHbyDbigSwUFr +AtRedffY0itNEp6aJh9ed11oQU2QVzGYwWLpv+cH8yk9tm3uUtbjId7nvnTqaXC4boU SENHUyEVlZpGmm38NQA4CB9s4IlrMxDkHVPBA7eYi6JO+s7L6+oHXxQP3a8Uxax+E26p T1477ngkKkzpA8GUhEiaTQu/soH1T83hL2+BjQAOIfqcyEwPv0rYqsEnsHNuW9S9lp3a MCCFIgq8TUcKCCgnVzIoDCrURHTMTpybAoQR39y9xh44TRU7QzAe5lHzyPnHzNIArHjb eAKQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=mHNUJFbL; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l7si2171110pgf.102.2017.09.21.20.49.54; Thu, 21 Sep 2017 20:49:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=mHNUJFbL; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751968AbdIVDt1 (ORCPT + 26 others); Thu, 21 Sep 2017 23:49:27 -0400 Received: from conuserg-09.nifty.com ([210.131.2.76]:59726 "EHLO conuserg-09.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751891AbdIVDtB (ORCPT ); Thu, 21 Sep 2017 23:49:01 -0400 Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-09.nifty.com with ESMTP id v8M3kwAK029389; Fri, 22 Sep 2017 12:47:00 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-09.nifty.com v8M3kwAK029389 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1506052020; bh=59fdI7+UE95X4PNnOZNZNKCOmyNFFdGozGYIY/JOjgk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mHNUJFbLTCeNJmhfWV+NIhXLq0bLHEQLrfbnz1Vq9HIBy39LVZ4qciab+O216YcN3 ua99UCqzcZdFRV0xFDqH1B4/xoVQb+seWyiQV+aYBMX0PtzQVBi0HXhAEL+Tc7IMSZ 8wpqmXNTiT2/8ngbRKjAJp5wKvVAfoQ21JqGZ6MFB0NqH2nEOhGu2k/45HT8xqoGWe 7aUBk5wpTjUeANhyuAUegML1G4dZUq/lH7DKAYYPC8LUfzj64QNuR+Km3P/IYgWNDr ph1umNSdRTux7m1IsaZWd5ncL4mHJGRBW3aWCeMIyZS1jm2IzXXxjw/5P+m5ejYPOu povlGe4du4s9g== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: linux-mtd@lists.infradead.org Cc: Masahiro Yamada , Cyrille Pitchen , linux-kernel@vger.kernel.org, Boris Brezillon , Marek Vasut , Brian Norris , Richard Weinberger , David Woodhouse Subject: [PATCH v2 01/12] mtd: nand: denali: squash setup_ecc_for_xfer() helper into caller Date: Fri, 22 Sep 2017 12:46:38 +0900 Message-Id: <1506052009-8285-2-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1506052009-8285-1-git-send-email-yamada.masahiro@socionext.com> References: <1506052009-8285-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The setup_ecc_for_xfer() is only called from denali_data_xfer(). This helper is small enough, so squash it into the caller. This looks cleaner to me. Signed-off-by: Masahiro Yamada --- Changes in v2: None drivers/mtd/nand/denali.c | 22 +++------------------- 1 file changed, 3 insertions(+), 19 deletions(-) -- 2.7.4 diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index aefdc83..d847ae4 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -208,24 +208,6 @@ static uint32_t denali_check_irq(struct denali_nand_info *denali) return irq_status; } -/* - * This helper function setups the registers for ECC and whether or not - * the spare area will be transferred. - */ -static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en, - bool transfer_spare) -{ - int ecc_en_flag, transfer_spare_flag; - - /* set ECC, transfer spare bits if needed */ - ecc_en_flag = ecc_en ? ECC_ENABLE__FLAG : 0; - transfer_spare_flag = transfer_spare ? TRANSFER_SPARE_REG__FLAG : 0; - - /* Enable spare area/ECC per user's request. */ - iowrite32(ecc_en_flag, denali->reg + ECC_ENABLE); - iowrite32(transfer_spare_flag, denali->reg + TRANSFER_SPARE_REG); -} - static void denali_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) { struct denali_nand_info *denali = mtd_to_denali(mtd); @@ -659,7 +641,9 @@ static int denali_dma_xfer(struct denali_nand_info *denali, void *buf, static int denali_data_xfer(struct denali_nand_info *denali, void *buf, size_t size, int page, int raw, int write) { - setup_ecc_for_xfer(denali, !raw, raw); + iowrite32(raw ? 0 : ECC_ENABLE__FLAG, denali->reg + ECC_ENABLE); + iowrite32(raw ? TRANSFER_SPARE_REG__FLAG : 0, + denali->reg + TRANSFER_SPARE_REG); if (denali->dma_avail) return denali_dma_xfer(denali, buf, size, page, raw, write); From patchwork Fri Sep 22 03:46:40 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 113951 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp2798263qgf; Thu, 21 Sep 2017 20:49:32 -0700 (PDT) X-Google-Smtp-Source: AOwi7QBC0yi1jYrjtcVkBBjP6wCDbyrrWqNgjABh40DlSQUNon1oAegK2+z/+p2iPx57jW+CdWPc X-Received: by 10.98.211.76 with SMTP id q73mr7791945pfg.348.1506052172169; Thu, 21 Sep 2017 20:49:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506052172; cv=none; d=google.com; s=arc-20160816; b=YDUMx3kZcadjMV+8ckswsaXwbchd1uDtxp5ODArFfwcMVXumh0ynGZDW2FspQA/jZR Pk1GbCFNOm6uGHL3elN/e/BkJpinYxDlpIMT1p5BGuHmfHItSckIKtrZq1Q6G1c/VcT4 45QcqJSmwUYRpC+Rb4EaIDQcYb0v3L+vYPvV8AOZuj8avQmWh/+ELDfHNDEFuWuoSK2A EaLQhiBmPya3b3ybjrm+ag9Biy9kJTGmpTJPIDfb9UxXGPQgzf27Pa+sIKS1j9Ja4W1H +RxKvZjKlWR7/TROEqShjLTa2pOQ3hdXIZK7tjkO9tLPyEftGX/sFF3Qf2e6od9g8/W5 LhhA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:dkim-filter :arc-authentication-results; bh=nCxCYJ4o/HY6G4JSiifqz9J7Vody8AeKbn7ojOw1fz4=; b=e+il61jhGeGDeKJMZAwbDhlA/Zzb8W8bNQiMasMWMRNy+cWoHhjnMtpHefmljvH3WD k06hC/fCYdx9PFO5lCcAUPnWXQB+DAOv61jlkb2h4M3XW3djXMe38yzOrWq2Hf97IJCR qiedGJxFsja1Y7QHhUSumvGxPdYuL2nUeoE5MJZISJdMNN65CHFI8KfFsLxbTs24FJ+6 XKqLieL0ncQoME2Y3iN+Ox2gr7cv4Dz4daClg4tpoUSEfNqNfnv3CuHbg4JpVpmSK4Np S9Xo0zNrFvaWPUJOt7xwk19tgtngn1xY9WQS8rNL7lk+qtOawvJvZswndtOMCCcoLcHf ExAw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=wcXeahkJ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Also, sort them alphabetically. , , turned out bogus, so removed. Signed-off-by: Masahiro Yamada --- Changes in v2: None drivers/mtd/nand/denali.c | 12 +++++++----- drivers/mtd/nand/denali.h | 3 +++ drivers/mtd/nand/denali_dt.c | 3 ++- drivers/mtd/nand/denali_pci.c | 3 +++ 4 files changed, 15 insertions(+), 6 deletions(-) -- 2.7.4 diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index 48193f9..4daeb7f 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -16,14 +16,16 @@ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. * */ -#include -#include + +#include #include -#include -#include -#include +#include +#include #include +#include +#include #include +#include #include "denali.h" diff --git a/drivers/mtd/nand/denali.h b/drivers/mtd/nand/denali.h index 9239e67..dc3f970 100644 --- a/drivers/mtd/nand/denali.h +++ b/drivers/mtd/nand/denali.h @@ -21,7 +21,10 @@ #define __DENALI_H__ #include +#include #include +#include +#include #define DEVICE_RESET 0x0 #define DEVICE_RESET__BANK(bank) BIT(bank) diff --git a/drivers/mtd/nand/denali_dt.c b/drivers/mtd/nand/denali_dt.c index 56e2e17..01e0100 100644 --- a/drivers/mtd/nand/denali_dt.c +++ b/drivers/mtd/nand/denali_dt.c @@ -12,15 +12,16 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. */ + #include #include #include #include #include #include -#include #include #include +#include #include "denali.h" diff --git a/drivers/mtd/nand/denali_pci.c b/drivers/mtd/nand/denali_pci.c index 81370c7..7d5600b 100644 --- a/drivers/mtd/nand/denali_pci.c +++ b/drivers/mtd/nand/denali_pci.c @@ -11,6 +11,9 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. */ + +#include +#include #include #include #include From patchwork Fri Sep 22 03:46:41 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 113949 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp2797958qgf; Thu, 21 Sep 2017 20:49:07 -0700 (PDT) X-Google-Smtp-Source: AOwi7QDXPs9KpG2gKymj0LkVPG30MasMCtr8QOQDHImUbZd/UtnrIZtgSo6kSWPVdRKnG+11ow4F X-Received: by 10.159.207.139 with SMTP id z11mr7546296plo.335.1506052147295; Thu, 21 Sep 2017 20:49:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506052147; cv=none; d=google.com; s=arc-20160816; b=sfYPPlVQC58SjgvGfkYk55Jpp1NF7lhtKvsicZSfVu8ZHs7bLaOui4i/0xDtZdUYVX n2QV0sAOHa3dw8xL9NdYpeMtgAsSZ/SE5H6Ir2c9fPsD16Uy+cQXooc7cNjaL7ZD8r9Q P1p9Yv+ZXzozS5cA0qi9fOIj6fMn5jqBglWQrMY3O/il5bEqok5w/z+fdb3qcMp9UYVq YJF98WH0tRZGJKFjkWZEYYjvNucYu38qTjOMEk9qWr8KLVLXix6rV2//mjVULyCdMzc7 GI4/I96Xu5YCn+5FUkvhry6vxMmSmUsvlKCgglZyfiG+owfWMVRSc4MSRHE+IkYy+iLn l6HA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:dkim-filter :arc-authentication-results; bh=ZsdAJUIqTO4KvPRvFWjKzBnNDptNNDtvB0GG9itOgS4=; b=qSre50E1IbQl7GmzCCKQXWdMcdnwr1DoXxl0/jJ5m6R9L+ZSuQhpbg/zIYr80lf3LX WxBesByBSbbTHs76g+AQtKF2lKl7ax6XmVJCC1mu4nOOScfmY2b3ZqJrkCq94NqvuPH9 4gvr4ZSktKeKtIoBtrn6NyM09rigFQJ3UuoaGk8LkUv9mZsuNhBOTsjwu1opGhCitCmz qHbN/2D+wuzPoIsLNUyuS/OOg0AFVXT4ZounnrzI/hlZkw1S8OqQiJyEp2cxnbTsYJnO omyj4meUXEMVK2SZBjni/wd9FwyJshUzZBiXSPyjNWJYEu4YczVAlL4S5zKz7ydR8KVJ tW4w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=vBp1cnQ+; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s189si2055398pgb.737.2017.09.21.20.49.07; Thu, 21 Sep 2017 20:49:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=vBp1cnQ+; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751940AbdIVDtE (ORCPT + 26 others); Thu, 21 Sep 2017 23:49:04 -0400 Received: from conuserg-09.nifty.com ([210.131.2.76]:59774 "EHLO conuserg-09.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751906AbdIVDtC (ORCPT ); Thu, 21 Sep 2017 23:49:02 -0400 Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-09.nifty.com with ESMTP id v8M3kwAN029389; Fri, 22 Sep 2017 12:47:02 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-09.nifty.com v8M3kwAN029389 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1506052023; bh=ZsdAJUIqTO4KvPRvFWjKzBnNDptNNDtvB0GG9itOgS4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=vBp1cnQ+iWDOKqYY7s9ZsRHh6mW27je3By78zMfOOIKkkR5cedu2njXK+1X+USTIL eL/leQcw50ImY8wZsckuib44a23qilXhkzjKE7aardjk5P2TDuUmK2K+9a0bG7zswA Gw/jyNJe5LRuIOkDY5RVD98rCo+xTF8VG/NDwnCW9cXig7M3Xji0KpMYdOq4sPnIK8 5qIexWsTU3Dzz4bhhuT2lLwj12/RMZfehMKZITmgqd2Sq/YQKWZBWB9CzH9gVen2Gf mBNv/jV9tGP/Dn8smMv+3tMznpaMDnPBMnOplHTeFsNPKUqmbc0LcSjZq+kgs9ysox 47ALGfkzxyWOw== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: linux-mtd@lists.infradead.org Cc: Masahiro Yamada , Cyrille Pitchen , linux-kernel@vger.kernel.org, Boris Brezillon , Marek Vasut , Brian Norris , Richard Weinberger , David Woodhouse Subject: [PATCH v2 04/12] mtd: nand: denali: squash denali_enable_dma() helper into caller Date: Fri, 22 Sep 2017 12:46:41 +0900 Message-Id: <1506052009-8285-5-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1506052009-8285-1-git-send-email-yamada.masahiro@socionext.com> References: <1506052009-8285-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This helper just sets/clears a flag of DMA_ENABLE register (with register read-back, I do not know why it is necessary). Move the register write code to the caller, and remove the helper. It works for me without the register read-back. Signed-off-by: Masahiro Yamada --- Changes in v2: None drivers/mtd/nand/denali.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) -- 2.7.4 diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index 4daeb7f..e7b25de 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -465,13 +465,6 @@ static int denali_sw_ecc_fixup(struct mtd_info *mtd, return max_bitflips; } -/* programs the controller to either enable/disable DMA transfers */ -static void denali_enable_dma(struct denali_nand_info *denali, bool en) -{ - iowrite32(en ? DMA_ENABLE__FLAG : 0, denali->reg + DMA_ENABLE); - ioread32(denali->reg + DMA_ENABLE); -} - static void denali_setup_dma64(struct denali_nand_info *denali, dma_addr_t dma_addr, int page, int write) { @@ -619,7 +612,7 @@ static int denali_dma_xfer(struct denali_nand_info *denali, void *buf, ecc_err_mask = INTR__ECC_ERR; } - denali_enable_dma(denali, true); + iowrite32(DMA_ENABLE__FLAG, denali->reg + DMA_ENABLE); denali_reset_irq(denali); denali_setup_dma(denali, dma_addr, page, write); @@ -631,7 +624,8 @@ static int denali_dma_xfer(struct denali_nand_info *denali, void *buf, else if (irq_status & ecc_err_mask) ret = -EBADMSG; - denali_enable_dma(denali, false); + iowrite32(0, denali->reg + DMA_ENABLE); + dma_unmap_single(denali->dev, dma_addr, size, dir); if (irq_status & INTR__ERASED_PAGE) From patchwork Fri Sep 22 03:46:42 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 113952 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp2798267qgf; Thu, 21 Sep 2017 20:49:32 -0700 (PDT) X-Google-Smtp-Source: AOwi7QCdWR64xS17L44iL6TVpDs7fPJ+usSP9ZmP13wWBhYWkoryExhYUmzszMVjquaeLUazjVBn X-Received: by 10.84.204.136 with SMTP id b8mr7617615ple.361.1506052172547; Thu, 21 Sep 2017 20:49:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506052172; cv=none; d=google.com; s=arc-20160816; b=jQLQ4XYe3xx0qMQTZbGsZ+YRFWM0iPNYTHOJD90e9sKEtPK9Dk6OQoZPOg4RuW8iZx wtSOKhIfG3eVb3jNa4JUMroCTjYz9NOfwAJvL/9RKv5o7peGL4D6l1C3wPxZ4iz5smRO 4Pp+B7YvCa4vOHftL+WAmxjQdF92luBVo/Fi2j4LmzYR94Boav9Xn20epKfPCrAL9e4H woQAOh/vmD6xrdc2IFFj/9U++CjMjdJTzOBUorWXDhsHCPUdNEj+byjqRQ9gudicEF4X 3jCGXNC728Rlgg149cDqE3Ey46315texZyIQgphLFA4n0t7+yxcLf6z1e4HF96fmtSa+ KxuQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:dkim-filter :arc-authentication-results; bh=T8Y7lTuMmomqVtFpcXbDE0X8EE/AezNtRSQg9WVaso8=; b=HxMbtMEgJx+RguyZ+qZ03dXI+IAKZubOSTg8yNrH1HxTE66wn9SpV+WRwHucgtFqb7 S2IVfchBsbHvOWStOFuK5o2xao9m7G5eHLRtaDPD6vQUa/3rr3qTFFWXaaMG+sEouotS Nsi0Gify05C7VzVWbZVzcXAAJzt89OIOKm00lt1bYy9SQBlEVCBeIhYejbacl/HcwzAg L4xas7skA+pN1+C6qbsrAWoODp9jlPWgp36mz9ZCc1JSNdnwWrGw2QH95fSZFZ9uWslH Y42BAWnewuIgugXVkVlXa+Tj6vqqmtVg+gIasnSzqeXWLAoZ43x+1h+6dyY38Hk6JJh8 Ih8g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=XJvfEL5E; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id m68si2008494pfm.561.2017.09.21.20.49.32; Thu, 21 Sep 2017 20:49:32 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=XJvfEL5E; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752011AbdIVDta (ORCPT + 26 others); Thu, 21 Sep 2017 23:49:30 -0400 Received: from conuserg-09.nifty.com ([210.131.2.76]:59697 "EHLO conuserg-09.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751887AbdIVDtA (ORCPT ); Thu, 21 Sep 2017 23:49:00 -0400 Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-09.nifty.com with ESMTP id v8M3kwAO029389; Fri, 22 Sep 2017 12:47:03 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-09.nifty.com v8M3kwAO029389 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1506052023; bh=T8Y7lTuMmomqVtFpcXbDE0X8EE/AezNtRSQg9WVaso8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XJvfEL5Eze7FzfVzHG12i6mmV/uOisED7DY7VyynTz9ziYYAFN/EexYB5NFeuyzRO CHRP5kCh3Wc4KCkyVB3RD/0sCyLZaIYCZ8JqhU18oMHKA7zpcXb16OdR5udzteTnEZ 0dmEK4Ka37s1Wj+msEZ0h+hJtOt/v2lQvGOU3f9qkO1n6qttapqxbqTOs6uuc+1cBs EHF0n6kjDBqpLUTdbJx7wdNpgscQ7/1NdTQOMlgZGll/LFhKfAF2avca/Hu6ixS9/n EwiYTrgdXFMH5oukrZeZqKzKS20iDNQI9mFEg+glhonujOIXw8Yz6JdOdI2bBiBPOr HqRUSV7k1F2HQ== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: linux-mtd@lists.infradead.org Cc: Masahiro Yamada , Cyrille Pitchen , linux-kernel@vger.kernel.org, Boris Brezillon , Marek Vasut , Brian Norris , Richard Weinberger , David Woodhouse Subject: [PATCH v2 05/12] mtd: nand: denali: slight clean up of denali_wait_for_irq() Date: Fri, 22 Sep 2017 12:46:42 +0900 Message-Id: <1506052009-8285-6-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1506052009-8285-1-git-send-email-yamada.masahiro@socionext.com> References: <1506052009-8285-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This function has a local variable "irq_mask" and its value is the same as denali->irq_mask. Clean up the code a little. Signed-off-by: Masahiro Yamada --- Changes in v2: None drivers/mtd/nand/denali.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index e7b25de..3cc56de 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -191,7 +191,7 @@ static uint32_t denali_wait_for_irq(struct denali_nand_info *denali, msecs_to_jiffies(1000)); if (!time_left) { dev_err(denali->dev, "timeout while waiting for irq 0x%x\n", - denali->irq_mask); + irq_mask); return 0; } From patchwork Fri Sep 22 03:46:44 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 113956 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp2798931qgf; Thu, 21 Sep 2017 20:50:33 -0700 (PDT) X-Google-Smtp-Source: AOwi7QD//AnVYAFgM6e1s/pDj+zMmVptOGO9Bj2ufxm+i8FGr1ghfAOPNp5Ix+3FRCJfzHPLm+L6 X-Received: by 10.99.51.15 with SMTP id z15mr7766300pgz.287.1506052233367; Thu, 21 Sep 2017 20:50:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506052233; cv=none; d=google.com; s=arc-20160816; b=Yadre3Uwdz4Jb14NAaN5GwQurLy5mSNz3OdRCyGsj+Zvxz1tjQFdhw7/qPAh/zpy6X i/FdUlIRwhE7HbPTYed8lQ5y5TkXl/j+vRt7LsfbcgDSigGIexXcEskPJDJJNvWD1C4k pmtsgRB61G12SUEPghmpzkDX+dl0/ud2o7W2NvuMGtLEw9OADkNX+CuEF1lEXftasvfF 2B3i6yVVc2qyqmvB0CCKyLWcMGEKE137UJRKSDdVOKS/vlPYVXreA2sshzZL4ou80qGn ujQGKmnnlctRjc2q0lZ+R3vyv0avGsGEb3xYl6YZoAj1G3A0JuIqZ1dfoVTVILuuZ73Q DpWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:dkim-filter :arc-authentication-results; bh=kKwi5RZmABL8IX6i/h0RYZXHIeP+oiLXX9aIpj7Ojb8=; b=tI+HOrw2XzaQag/8yqydc7CFRIlFbJvjIx2QMCKcJE3uAIj6u5sLWZn7ps4lpbx6gv XPe3g5sPz8e4wPT2yqL0hdVG77/YOQCIqQsEh0sqkwVQmKvsFoy8MlVsUSN1fXqnWkEY hrpYvHxRBSDSTPQRHhmPBphpE/+y+abcmcZmaxqHBGsYOfH/Sa77szd7coBX55A6ziuo KP5hq+oZE0KkYr5EX3bwcUYmfxhVS55D6M2ngyaRWWMYdDf1kNObrvMf9qcK5lRK47MT eTpHa28jpWGQRXe9WiYMP5CYOchqVoL4QlDlET6LSgMP5XcsCjwCGZlU0K92YUsIYuZH g5hQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=oPsR3+mB; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x137si2058493pfd.259.2017.09.21.20.50.33; Thu, 21 Sep 2017 20:50:33 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=oPsR3+mB; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752038AbdIVDub (ORCPT + 26 others); Thu, 21 Sep 2017 23:50:31 -0400 Received: from conuserg-09.nifty.com ([210.131.2.76]:59411 "EHLO conuserg-09.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751726AbdIVDst (ORCPT ); Thu, 21 Sep 2017 23:48:49 -0400 Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-09.nifty.com with ESMTP id v8M3kwAQ029389; Fri, 22 Sep 2017 12:47:05 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-09.nifty.com v8M3kwAQ029389 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1506052025; bh=kKwi5RZmABL8IX6i/h0RYZXHIeP+oiLXX9aIpj7Ojb8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oPsR3+mBHTX2IZNNaNkgVQSbDBKbWWKw39k5ixZyqQi+jHboxwwQ6yHTKDTlGaqfB KoOuNOvACjUOFzXmcvSEoKpna8GyqIwlZhFlWe6kfqHNfQ083L+g/BgCoouKG4eXx7 oHGCazet1VF9rp2dQJ28l9I76tExb1loPgjY67BUuZ1unZMpgEH8F5+LG33nMTrOjh KZTMfQWQ+Wkg/Dw4EhIJMBSr4HZmIhJeto7ovVPGnIpJcpbSrt4ks0oQljxif9byWt WaIuCPf74BWoHU5s7ki+/Cof7Sl5V0SWWT+L5L63CqhkbNX0Cp6xzgeYU38FQMF2Uj tlqowqleLqzzA== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: linux-mtd@lists.infradead.org Cc: Masahiro Yamada , Cyrille Pitchen , linux-kernel@vger.kernel.org, Boris Brezillon , Marek Vasut , Brian Norris , Richard Weinberger , David Woodhouse Subject: [PATCH v2 07/12] mtd: nand: denali: use more FIELD_PREP / FIELD_GET where appropriate Date: Fri, 22 Sep 2017 12:46:44 +0900 Message-Id: <1506052009-8285-8-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1506052009-8285-1-git-send-email-yamada.masahiro@socionext.com> References: <1506052009-8285-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In several places in this driver, the register fields are retrieved as follows: val = reg & FOO_MASK; Then, modified as follows: reg &= ~FOO_MASK; reg |= val; This code relies on its shift is 0, which we will never know until we check the definition of FOO_MASK. Use FIELD_PREP / FIELD_GET where appropriate. Signed-off-by: Masahiro Yamada --- Changes in v2: None drivers/mtd/nand/denali.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) -- 2.7.4 diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index 1525c4e..ca98015 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -88,7 +88,7 @@ static void denali_detect_max_banks(struct denali_nand_info *denali) { uint32_t features = ioread32(denali->reg + FEATURES); - denali->max_banks = 1 << (features & FEATURES__N_BANKS); + denali->max_banks = 1 << FIELD_GET(FEATURES__N_BANKS, features); /* the encoding changed from rev 5.0 to 5.1 */ if (denali->revision < 0x0501) @@ -374,7 +374,7 @@ static int denali_hw_ecc_fixup(struct mtd_info *mtd, return 0; } - max_bitflips = ecc_cor & ECC_COR_INFO__MAX_ERRORS; + max_bitflips = FIELD_GET(ECC_COR_INFO__MAX_ERRORS, ecc_cor); /* * The register holds the maximum of per-sector corrected bitflips. @@ -985,7 +985,7 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, tmp = ioread32(denali->reg + ACC_CLKS); tmp &= ~ACC_CLKS__VALUE; - tmp |= acc_clks; + tmp |= FIELD_PREP(ACC_CLKS__VALUE, acc_clks); iowrite32(tmp, denali->reg + ACC_CLKS); /* tRWH -> RE_2_WE */ @@ -994,7 +994,7 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, tmp = ioread32(denali->reg + RE_2_WE); tmp &= ~RE_2_WE__VALUE; - tmp |= re_2_we; + tmp |= FIELD_PREP(RE_2_WE__VALUE, re_2_we); iowrite32(tmp, denali->reg + RE_2_WE); /* tRHZ -> RE_2_RE */ @@ -1003,7 +1003,7 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, tmp = ioread32(denali->reg + RE_2_RE); tmp &= ~RE_2_RE__VALUE; - tmp |= re_2_re; + tmp |= FIELD_PREP(RE_2_RE__VALUE, re_2_re); iowrite32(tmp, denali->reg + RE_2_RE); /* tWHR -> WE_2_RE */ @@ -1012,7 +1012,7 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, tmp = ioread32(denali->reg + TWHR2_AND_WE_2_RE); tmp &= ~TWHR2_AND_WE_2_RE__WE_2_RE; - tmp |= we_2_re; + tmp |= FIELD_PREP(TWHR2_AND_WE_2_RE__WE_2_RE, we_2_re); iowrite32(tmp, denali->reg + TWHR2_AND_WE_2_RE); /* tADL -> ADDR_2_DATA */ @@ -1026,8 +1026,8 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, addr_2_data = min_t(int, addr_2_data, addr_2_data_mask); tmp = ioread32(denali->reg + TCWAW_AND_ADDR_2_DATA); - tmp &= ~addr_2_data_mask; - tmp |= addr_2_data; + tmp &= ~TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA; + tmp |= FIELD_PREP(TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA, addr_2_data); iowrite32(tmp, denali->reg + TCWAW_AND_ADDR_2_DATA); /* tREH, tWH -> RDWR_EN_HI_CNT */ @@ -1037,7 +1037,7 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, tmp = ioread32(denali->reg + RDWR_EN_HI_CNT); tmp &= ~RDWR_EN_HI_CNT__VALUE; - tmp |= rdwr_en_hi; + tmp |= FIELD_PREP(RDWR_EN_HI_CNT__VALUE, rdwr_en_hi); iowrite32(tmp, denali->reg + RDWR_EN_HI_CNT); /* tRP, tWP -> RDWR_EN_LO_CNT */ @@ -1051,7 +1051,7 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, tmp = ioread32(denali->reg + RDWR_EN_LO_CNT); tmp &= ~RDWR_EN_LO_CNT__VALUE; - tmp |= rdwr_en_lo; + tmp |= FIELD_PREP(RDWR_EN_LO_CNT__VALUE, rdwr_en_lo); iowrite32(tmp, denali->reg + RDWR_EN_LO_CNT); /* tCS, tCEA -> CS_SETUP_CNT */ @@ -1062,7 +1062,7 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, tmp = ioread32(denali->reg + CS_SETUP_CNT); tmp &= ~CS_SETUP_CNT__VALUE; - tmp |= cs_setup; + tmp |= FIELD_PREP(CS_SETUP_CNT__VALUE, cs_setup); iowrite32(tmp, denali->reg + CS_SETUP_CNT); return 0; From patchwork Fri Sep 22 03:46:45 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 113955 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp2798634qgf; Thu, 21 Sep 2017 20:50:08 -0700 (PDT) X-Google-Smtp-Source: AOwi7QCjSIppFFu+8Po5faIGp4lxMBioacvxPUFJVgRBKYdehExXiPARJ0LvFo2I46fk92vnWfVZ X-Received: by 10.98.16.80 with SMTP id y77mr7746607pfi.261.1506052208809; Thu, 21 Sep 2017 20:50:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506052208; 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[209.132.180.67]) by mx.google.com with ESMTP id l7si2171110pgf.102.2017.09.21.20.50.08; Thu, 21 Sep 2017 20:50:08 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=dgj6pEF/; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752024AbdIVDuH (ORCPT + 26 others); Thu, 21 Sep 2017 23:50:07 -0400 Received: from conuserg-09.nifty.com ([210.131.2.76]:59488 "EHLO conuserg-09.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751871AbdIVDsx (ORCPT ); Thu, 21 Sep 2017 23:48:53 -0400 Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-09.nifty.com with ESMTP id v8M3kwAR029389; Fri, 22 Sep 2017 12:47:05 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-09.nifty.com v8M3kwAR029389 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1506052026; bh=pWWM1QhHhO0KtMdj0Q6470CMqQyJr3iyfJBFlOHblAk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dgj6pEF/Zkk+E1Pp10xLbTQ+gSuIeII88qAV9xLHXYwurV6bb/ySvcglqYX8WzroE yb/2PEfS7m/KqJrWJbjMZJjpQKw9L9bDLHYXLltlwXiia1n1TmSUr8iXAXAT0lJWkl RhdYT2oLQLCS999G1p6UPdLlouiY5bhnBQBKGZ0z5qXHuGWdP9onInMaD5uExKJhqy HwbT+N1LDFxwpyiEwnQrZcQo4W/0Xy9d0jv4aOB6ZzKb9A0HycZFjWaxpZpsd6aKe7 fw+IN7Px4QM0xQX/pGfDW/MflRZnjvGnp07rd9Zj/fCQA5c0/GSZGwnmfFNqjhNd4/ WIJowuOkHitZQ== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: linux-mtd@lists.infradead.org Cc: Masahiro Yamada , Cyrille Pitchen , linux-kernel@vger.kernel.org, Boris Brezillon , Marek Vasut , Brian Norris , Richard Weinberger , David Woodhouse Subject: [PATCH v2 08/12] mtd: nand: denali: clean up comments Date: Fri, 22 Sep 2017 12:46:45 +0900 Message-Id: <1506052009-8285-9-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1506052009-8285-1-git-send-email-yamada.masahiro@socionext.com> References: <1506052009-8285-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This driver explains too much about what is apparent from the code. Comments around basic APIs such as init_completion(), spin_lock_init(), etc. seem unneeded lessons to kernel developers. (With those comments dropped, denali_drv_init() is small enough, so it has been merged into the probe function.) Also, NAND driver developers should know the NAND init procedure, so there is no need to explain nand_scan_ident/tail. I removed FSF's address from the license blocks, and added simple comments to struct members. Signed-off-by: Masahiro Yamada --- Changes in v2: - Add more comments to struct members drivers/mtd/nand/denali.c | 52 +++++-------------------------------------- drivers/mtd/nand/denali.h | 24 +++++++------------- drivers/mtd/nand/denali_dt.c | 1 - drivers/mtd/nand/denali_pci.c | 2 -- 4 files changed, 13 insertions(+), 66 deletions(-) -- 2.7.4 diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index ca98015..02ce310 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -10,11 +10,6 @@ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. - * */ #include @@ -64,10 +59,6 @@ MODULE_LICENSE("GPL"); */ #define DENALI_CLK_X_MULT 6 -/* - * this macro allows us to convert from an MTD structure to our own - * device context (denali) structure. - */ static inline struct denali_nand_info *mtd_to_denali(struct mtd_info *mtd) { return container_of(mtd_to_nand(mtd), struct denali_nand_info, nand); @@ -450,9 +441,8 @@ static int denali_sw_ecc_fixup(struct mtd_info *mtd, } while (!(err_cor_info & ERR_CORRECTION_INFO__LAST_ERR)); /* - * Once handle all ecc errors, controller will trigger a - * ECC_TRANSACTION_DONE interrupt, so here just wait for - * a while for this interrupt + * Once handle all ECC errors, controller will trigger an + * ECC_TRANSACTION_DONE interrupt. */ irq_status = denali_wait_for_irq(denali, INTR__ECC_TRANSACTION_DONE); if (!(irq_status & INTR__ECC_TRANSACTION_DONE)) @@ -613,7 +603,6 @@ static int denali_dma_xfer(struct denali_nand_info *denali, void *buf, denali_reset_irq(denali); denali_setup_dma(denali, dma_addr, page, write); - /* wait for operation to complete */ irq_status = denali_wait_for_irq(denali, irq_mask); if (!(irq_status & INTR__DMA_CMD_COMP)) ret = -EIO; @@ -1185,22 +1174,6 @@ static const struct mtd_ooblayout_ops denali_ooblayout_ops = { .free = denali_ooblayout_free, }; -/* initialize driver data structures */ -static void denali_drv_init(struct denali_nand_info *denali) -{ - /* - * the completion object will be used to notify - * the callee that the interrupt is done - */ - init_completion(&denali->complete); - - /* - * the spinlock will be used to synchronize the ISR with any - * element that might be access shared data (interrupt status) - */ - spin_lock_init(&denali->irq_lock); -} - static int denali_multidev_fixup(struct denali_nand_info *denali) { struct nand_chip *chip = &denali->nand; @@ -1260,11 +1233,12 @@ int denali_init(struct denali_nand_info *denali) mtd->dev.parent = denali->dev; denali_hw_init(denali); - denali_drv_init(denali); + + init_completion(&denali->complete); + spin_lock_init(&denali->irq_lock); denali_clear_irq_all(denali); - /* Request IRQ after all the hardware initialization is finished */ ret = devm_request_irq(denali->dev, denali->irq, denali_isr, IRQF_SHARED, DENALI_NAND_NAME, denali); if (ret) { @@ -1282,7 +1256,6 @@ int denali_init(struct denali_nand_info *denali) if (!mtd->name) mtd->name = "denali-nand"; - /* register the driver with the NAND core subsystem */ chip->select_chip = denali_select_chip; chip->read_byte = denali_read_byte; chip->write_byte = denali_write_byte; @@ -1295,11 +1268,6 @@ int denali_init(struct denali_nand_info *denali) if (denali->clk_x_rate) chip->setup_data_interface = denali_setup_data_interface; - /* - * scan for NAND devices attached to the controller - * this is the first stage in a two step process to register - * with the nand subsystem - */ ret = nand_scan_ident(mtd, denali->max_banks, NULL); if (ret) goto disable_irq; @@ -1323,18 +1291,9 @@ int denali_init(struct denali_nand_info *denali) chip->buf_align = 16; } - /* - * second stage of the NAND scan - * this stage requires information regarding ECC and - * bad block management. - */ - chip->bbt_options |= NAND_BBT_USE_FLASH; chip->bbt_options |= NAND_BBT_NO_OOB; - chip->ecc.mode = NAND_ECC_HW_SYNDROME; - - /* no subpage writes on denali */ chip->options |= NAND_NO_SUBPAGE_WRITE; ret = denali_ecc_setup(mtd, chip, denali); @@ -1418,7 +1377,6 @@ int denali_init(struct denali_nand_info *denali) } EXPORT_SYMBOL(denali_init); -/* driver exit point */ void denali_remove(struct denali_nand_info *denali) { struct mtd_info *mtd = nand_to_mtd(&denali->nand); diff --git a/drivers/mtd/nand/denali.h b/drivers/mtd/nand/denali.h index 73aad3a..f55ee10 100644 --- a/drivers/mtd/nand/denali.h +++ b/drivers/mtd/nand/denali.h @@ -10,11 +10,6 @@ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. - * */ #ifndef __DENALI_H__ @@ -310,22 +305,19 @@ struct denali_nand_info { struct device *dev; void __iomem *reg; /* Register Interface */ void __iomem *host; /* Host Data/Command Interface */ - - /* elements used by ISR */ struct completion complete; - spinlock_t irq_lock; - uint32_t irq_mask; - uint32_t irq_status; + spinlock_t irq_lock; /* protect irq_mask and irq_status */ + u32 irq_mask; /* interrupts we are waiting for */ + u32 irq_status; /* interrupts that have happened */ int irq; - - void *buf; + void *buf; /* for syndrome layout conversion */ dma_addr_t dma_addr; - int dma_avail; + int dma_avail; /* can support DMA? */ int devs_per_cs; /* devices connected in parallel */ - int oob_skip_bytes; + int oob_skip_bytes; /* number of bytes reserved for BBM */ int max_banks; - unsigned int revision; - unsigned int caps; + unsigned int revision; /* IP revision */ + unsigned int caps; /* IP capability (or quirk) */ const struct nand_ecc_caps *ecc_caps; }; diff --git a/drivers/mtd/nand/denali_dt.c b/drivers/mtd/nand/denali_dt.c index 01e0100..cfd33e6 100644 --- a/drivers/mtd/nand/denali_dt.c +++ b/drivers/mtd/nand/denali_dt.c @@ -156,7 +156,6 @@ static struct platform_driver denali_dt_driver = { .of_match_table = denali_nand_dt_ids, }, }; - module_platform_driver(denali_dt_driver); MODULE_LICENSE("GPL"); diff --git a/drivers/mtd/nand/denali_pci.c b/drivers/mtd/nand/denali_pci.c index 7d5600b..57fb7ae 100644 --- a/drivers/mtd/nand/denali_pci.c +++ b/drivers/mtd/nand/denali_pci.c @@ -109,7 +109,6 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) return ret; } -/* driver exit point */ static void denali_pci_remove(struct pci_dev *dev) { struct denali_nand_info *denali = pci_get_drvdata(dev); @@ -125,5 +124,4 @@ static struct pci_driver denali_pci_driver = { .probe = denali_pci_probe, .remove = denali_pci_remove, }; - module_pci_driver(denali_pci_driver); From patchwork Fri Sep 22 03:46:47 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 113947 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp2797842qgf; Thu, 21 Sep 2017 20:48:57 -0700 (PDT) X-Google-Smtp-Source: AOwi7QCdvW7D2bdY+ZDeOWZ8s3s/G7dA+3ovp3shUVzyYgIV/p2qxEU7ab4BwawXv7IlO9eszYLt X-Received: by 10.98.59.11 with SMTP id i11mr7838326pfa.238.1506052137856; Thu, 21 Sep 2017 20:48:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506052137; cv=none; d=google.com; s=arc-20160816; b=qxtZjgIVLUgSNlpRpC52myIytL/m4MhLl/cOiRm/JtfWjhERVnlIDFX8Jb3QBgBGRn RSWs0iFoVyNYDVt3X8AOJzM4Xm/5YCyKD5aKqtjRKQ4+KeaxbVnE8hoOdeAY3NTTl2IF 1Xc9otg48L23h1aNgwG5F03ErCpQYvXMQl3fzeC4vO+xCwlQ9x46EZMG6/uoLaSkGj1l MZKEuBSGfBoOW+HGJd2+nOQm0XbEK5Z7BgQpZmK5e/G3yNjwy7LCmdRQSHZKz8nz39/C lSdIEPs9VxVYIxxzAGoqa94Fce5RbjZEIc506kcO/UtaE5vplBJtaSAdOvUCoYLr+HFb SpYQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:dkim-filter :arc-authentication-results; bh=Px9Bz1KUShn7FbbonFeQUxK0/RFww/2IR4wmCchO9yM=; b=bh1WgKX0Dk/yFW5yYoO3iaVIOTHCbmHf6xLyTvwAZ7jD3lRNGq5kwfYIcytweiunh6 07QPxE0nKn3cdRKaJp+cxU+QeV018Yq8A9T2g+oVG+RmuUzE1w7W+DY4oDEZNeCBpJVg 6O2JmkHkEWf/KB/3JGSzTHszy0rlC0tXIWn+uaVPusAsonSg54OZ5LRFZQbJkiK3hxQr MBAMFu55rFoPNGI1tdUHMVJlMavdXG9CRlhglSyrJpkEXopONvzaeUxmcucsdUDheQLW 2QCv07sRpbUTv9S0cIJMuxd0JnaVgiCR9DyMn9kIEfIDpZtoIAiiWrywoMIgINh1fWn/ 04Qw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=ybvLmdwz; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b29si2019541pfl.594.2017.09.21.20.48.57; Thu, 21 Sep 2017 20:48:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=ybvLmdwz; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751886AbdIVDsz (ORCPT + 26 others); Thu, 21 Sep 2017 23:48:55 -0400 Received: from conuserg-09.nifty.com ([210.131.2.76]:59375 "EHLO conuserg-09.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751819AbdIVDst (ORCPT ); Thu, 21 Sep 2017 23:48:49 -0400 Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-09.nifty.com with ESMTP id v8M3kwAT029389; Fri, 22 Sep 2017 12:47:07 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-09.nifty.com v8M3kwAT029389 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1506052028; bh=Px9Bz1KUShn7FbbonFeQUxK0/RFww/2IR4wmCchO9yM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ybvLmdwz7nFc+cg9LAkVDQTcHBaZbqsZMRTWRO0L8VJjS+sg0DW5sPE3OG7rwC2g5 ElxgtRC9QXsKJ5GolPeVwrritsn0MFaF/PpvCirqcK4UVhbqTNlcQHqGIaaWyhqt/t c53q1/gGKj+QmSW0o9eGOiMtpKHUp324A2WOhK8tSkwnsdk5Bj+j8KW8270HANXYRD Mbfc2aTsXKd5PxF7u/r81HCZZhF6vaZGaLEx56JSABxi62AF+Uo4q2490v/VApfCjs Y37JuSA6dUaIaRm6JcwA9YLtS4M9A4ofbn3FK9gS9SHpZcw5+YiScmQxhyeb2lGEJ7 kUMBIMnMk2nlA== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: linux-mtd@lists.infradead.org Cc: Masahiro Yamada , Cyrille Pitchen , linux-kernel@vger.kernel.org, Boris Brezillon , Marek Vasut , Brian Norris , Richard Weinberger , David Woodhouse Subject: [PATCH v2 10/12] mtd: nand: denali: remove unneeded init of ECC_ENABLE register Date: Fri, 22 Sep 2017 12:46:47 +0900 Message-Id: <1506052009-8285-11-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1506052009-8285-1-git-send-email-yamada.masahiro@socionext.com> References: <1506052009-8285-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The ECC correction is properly enabled/disabled before the page read/write. There is no need to set up this at the beginning of the probe. Signed-off-by: Masahiro Yamada --- This patch may cause a conflict unless http://patchwork.ozlabs.org/patch/813125/ is applied first. Changes in v2: - Newly added drivers/mtd/nand/denali.c | 2 -- 1 file changed, 2 deletions(-) -- 2.7.4 diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index e567ad9..ee688e0 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -1101,8 +1101,6 @@ static void denali_hw_init(struct denali_nand_info *denali) iowrite32(CHIP_EN_DONT_CARE__FLAG, denali->reg + CHIP_ENABLE_DONT_CARE); iowrite32(0xffff, denali->reg + SPARE_AREA_MARKER); - - iowrite32(1, denali->reg + ECC_ENABLE); } int denali_calc_ecc_bytes(int step_size, int strength) From patchwork Fri Sep 22 03:46:48 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 113948 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp2797927qgf; Thu, 21 Sep 2017 20:49:04 -0700 (PDT) X-Google-Smtp-Source: AOwi7QCulB2c6CBG+8jJTmg3UaX6Dp5rMQuWB5o1iMGqh/jLV7u+4SjxRaRjZ51z4qVL+ywdyfxJ X-Received: by 10.84.235.135 with SMTP id p7mr7688120plk.181.1506052144860; Thu, 21 Sep 2017 20:49:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506052144; cv=none; d=google.com; s=arc-20160816; b=vRwHTEzTL7ec8mc7HNK/pd/EQ/KhILCnNIjfDXHuFIx3PXdAqFBIPdOTmqF0KCywrL DlMz4g5m1usAymxD1OamqKyKr6eec0LZY62s+qM0oVZQHNEh89VPxbLi4GUuOVkBzaR1 WyfWdqlMPO7I1GKbDPRnCiPH352r8AtSvh4EHN7JvRdWRwlruSeLOci27xAW321JeZcs cOC9xA+r56bx9nfaOIpQzWSYfmN7QKLnYvhfhjwlq5+h9zSmBidvuhLi/9eRTH22o3hy IrEqyT1bkCk1C3iTILRtOUJ89ic/i4O8u3FAm783sVIJ8+c3MOQz804/n1yVQqQzaSpm xpSQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:dkim-filter :arc-authentication-results; bh=/CFjeb58SmX5wca+i9MbQrGzEJUS5WnR+N8vlXmF7VY=; b=kXoPVBQkw7+LXLK1at3pewwWlRYvDWlzJfwlibwvg6abKm7LUzGDK7HWmsBhhna+t+ lwDLlp8In60Tdh0EkciUUSJtJ5tTXzMlwHdTige7nC3iyOzafWK6cnVhM16Yf0ject2W kJHMeYseSdyeHtpzsJ6y/4+ioPBp0U6oBhjSWSKFV+W5SkxdCbDmxShEBNYCctwimay2 R8VUerCUUvzlqrI7vvOJZ2lhYIUNQl9T+7Vk5wBBLb0zzMGLQ0qZFg0qdTO1bTYPpa6i tCf2zW1rJHPaKyboKEXks9pp55Gi35iW605KP6DPFh76QXdk0mOUaVIYisb/LM+AFVhq unvw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=BC2Ue3oN; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x85si2107106pfj.175.2017.09.21.20.49.04; Thu, 21 Sep 2017 20:49:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=BC2Ue3oN; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751920AbdIVDtC (ORCPT + 26 others); Thu, 21 Sep 2017 23:49:02 -0400 Received: from conuserg-09.nifty.com ([210.131.2.76]:59670 "EHLO conuserg-09.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751819AbdIVDs7 (ORCPT ); Thu, 21 Sep 2017 23:48:59 -0400 Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-09.nifty.com with ESMTP id v8M3kwAU029389; Fri, 22 Sep 2017 12:47:08 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-09.nifty.com v8M3kwAU029389 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1506052029; bh=/CFjeb58SmX5wca+i9MbQrGzEJUS5WnR+N8vlXmF7VY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BC2Ue3oNJRlYmegAc3T6H9lWll7sEePt+lhkd/IQmp6yL+P0Eese5JT8uNR5fHn9s jdlQS+eXdvq406Mc4umHxMTu9qPF0DowEIiuoAsLGsr9r+pundKX/XAUel5lTd0HBE 7q0nVaAzCLKbG7WpRUgu6cQfTb0NQZf/eaprejN5yHiLmh2FBGaaKyQtzjOi/i2EZW aq5R6BBECzbnWM1Vq2IKvnepnbBDo/Q8kdfTqo5H7aiPc7qm/dE+4sX8FWPmtYQ1tm fzudKQ2sMf6/mQCL0QqWxwy57+Tg8hwl6XbUGTFDgB7zjInMcpOMXGNZ5PaPNUu60h MeopNo7McPr/A== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: linux-mtd@lists.infradead.org Cc: Masahiro Yamada , Cyrille Pitchen , linux-kernel@vger.kernel.org, Boris Brezillon , Marek Vasut , Brian Norris , Richard Weinberger , David Woodhouse Subject: [PATCH v2 11/12] mtd: nand: denali: support direct addressing mode Date: Fri, 22 Sep 2017 12:46:48 +0900 Message-Id: <1506052009-8285-12-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1506052009-8285-1-git-send-email-yamada.masahiro@socionext.com> References: <1506052009-8285-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The Denali NAND IP core decodes the lower 28 bits of the slave address to get the control information; bit[27:26]=mode, bit[25:24]=bank, etc. This means 256MB address range must be allocated for this IP. (Direct Addressing) For systems with address space limitation, the Denali IP provides an optional module that translates the addressing - address and data are latched by the registers in the translation module. (Indexed Addressing) The addressing mode can be selected when the delivered RTL is configured, and it can be read out from the FEATURES register. Most of SoC vendors would choose Indexed Addressing to save the address space, but Direct Addressing is possible as well, and it can be easily supported by adding ->host_{read,write} hooks. Signed-off-by: Masahiro Yamada --- Changes in v2: - Newly added drivers/mtd/nand/denali.c | 109 +++++++++++++++++++++++++++++----------------- drivers/mtd/nand/denali.h | 2 + 2 files changed, 70 insertions(+), 41 deletions(-) -- 2.7.4 diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index ee688e0..7c24983 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -29,9 +29,9 @@ MODULE_LICENSE("GPL"); #define DENALI_NAND_NAME "denali-nand" -/* Host Data/Command Interface */ -#define DENALI_HOST_ADDR 0x00 -#define DENALI_HOST_DATA 0x10 +/* for Indexed Addressing */ +#define DENALI_INDEXED_CTRL 0x00 +#define DENALI_INDEXED_DATA 0x10 #define DENALI_MAP00 (0 << 26) /* direct access to buffer */ #define DENALI_MAP01 (1 << 26) /* read/write pages in PIO */ @@ -64,11 +64,39 @@ static inline struct denali_nand_info *mtd_to_denali(struct mtd_info *mtd) return container_of(mtd_to_nand(mtd), struct denali_nand_info, nand); } -static void denali_host_write(struct denali_nand_info *denali, - uint32_t addr, uint32_t data) +/* + * Direct Addressing - the slave address forms the control information (command + * type, bank, block, and page address). The slave data is the actual data to + * be transferred. This mode requires 28 bits of address region allocated. + */ +static u32 denali_direct_read(struct denali_nand_info *denali, u32 addr) +{ + return ioread32(denali->host + addr); +} + +static void denali_direct_write(struct denali_nand_info *denali, u32 addr, + u32 data) +{ + iowrite32(data, denali->host + addr); +} + +/* + * Indexed Addressing - address translation module intervenes in passing the + * control information. This mode reduces the required address range. The + * control information and transferred data are latched by the registers in + * the translation module. + */ +static u32 denali_indexed_read(struct denali_nand_info *denali, u32 addr) { - iowrite32(addr, denali->host + DENALI_HOST_ADDR); - iowrite32(data, denali->host + DENALI_HOST_DATA); + iowrite32(addr, denali->host + DENALI_INDEXED_CTRL); + return ioread32(denali->host + DENALI_INDEXED_DATA); +} + +static void denali_indexed_write(struct denali_nand_info *denali, u32 addr, + u32 data) +{ + iowrite32(addr, denali->host + DENALI_INDEXED_CTRL); + iowrite32(data, denali->host + DENALI_INDEXED_DATA); } /* @@ -205,52 +233,44 @@ static uint32_t denali_check_irq(struct denali_nand_info *denali) static void denali_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) { struct denali_nand_info *denali = mtd_to_denali(mtd); + u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali); int i; - iowrite32(DENALI_MAP11_DATA | DENALI_BANK(denali), - denali->host + DENALI_HOST_ADDR); - for (i = 0; i < len; i++) - buf[i] = ioread32(denali->host + DENALI_HOST_DATA); + buf[i] = denali->host_read(denali, addr); } static void denali_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) { struct denali_nand_info *denali = mtd_to_denali(mtd); + u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali); int i; - iowrite32(DENALI_MAP11_DATA | DENALI_BANK(denali), - denali->host + DENALI_HOST_ADDR); - for (i = 0; i < len; i++) - iowrite32(buf[i], denali->host + DENALI_HOST_DATA); + denali->host_write(denali, addr, buf[i]); } static void denali_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len) { struct denali_nand_info *denali = mtd_to_denali(mtd); + u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali); uint16_t *buf16 = (uint16_t *)buf; int i; - iowrite32(DENALI_MAP11_DATA | DENALI_BANK(denali), - denali->host + DENALI_HOST_ADDR); - for (i = 0; i < len / 2; i++) - buf16[i] = ioread32(denali->host + DENALI_HOST_DATA); + buf16[i] = denali->host_read(denali, addr); } static void denali_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) { struct denali_nand_info *denali = mtd_to_denali(mtd); + u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali); const uint16_t *buf16 = (const uint16_t *)buf; int i; - iowrite32(DENALI_MAP11_DATA | DENALI_BANK(denali), - denali->host + DENALI_HOST_ADDR); - for (i = 0; i < len / 2; i++) - iowrite32(buf16[i], denali->host + DENALI_HOST_DATA); + denali->host_write(denali, addr, buf16[i]); } static uint8_t denali_read_byte(struct mtd_info *mtd) @@ -295,7 +315,7 @@ static void denali_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl) if (ctrl & NAND_CTRL_CHANGE) denali_reset_irq(denali); - denali_host_write(denali, DENALI_BANK(denali) | type, dat); + denali->host_write(denali, DENALI_BANK(denali) | type, dat); } static int denali_dev_ready(struct mtd_info *mtd) @@ -465,14 +485,14 @@ static void denali_setup_dma64(struct denali_nand_info *denali, * 1. setup transfer type, interrupt when complete, * burst len = 64 bytes, the number of pages */ - denali_host_write(denali, mode, - 0x01002000 | (64 << 16) | (write << 8) | page_count); + denali->host_write(denali, mode, + 0x01002000 | (64 << 16) | (write << 8) | page_count); /* 2. set memory low address */ - denali_host_write(denali, mode, lower_32_bits(dma_addr)); + denali->host_write(denali, mode, lower_32_bits(dma_addr)); /* 3. set memory high address */ - denali_host_write(denali, mode, upper_32_bits(dma_addr)); + denali->host_write(denali, mode, upper_32_bits(dma_addr)); } static void denali_setup_dma32(struct denali_nand_info *denali, @@ -486,17 +506,17 @@ static void denali_setup_dma32(struct denali_nand_info *denali, /* DMA is a four step process */ /* 1. setup transfer type and # of pages */ - denali_host_write(denali, mode | page, - 0x2000 | (write << 8) | page_count); + denali->host_write(denali, mode | page, + 0x2000 | (write << 8) | page_count); /* 2. set memory high address bits 23:8 */ - denali_host_write(denali, mode | ((dma_addr >> 16) << 8), 0x2200); + denali->host_write(denali, mode | ((dma_addr >> 16) << 8), 0x2200); /* 3. set memory low address bits 23:8 */ - denali_host_write(denali, mode | ((dma_addr & 0xffff) << 8), 0x2300); + denali->host_write(denali, mode | ((dma_addr & 0xffff) << 8), 0x2300); /* 4. interrupt when complete, burst len = 64 bytes */ - denali_host_write(denali, mode | 0x14000, 0x2400); + denali->host_write(denali, mode | 0x14000, 0x2400); } static void denali_setup_dma(struct denali_nand_info *denali, @@ -511,7 +531,7 @@ static void denali_setup_dma(struct denali_nand_info *denali, static int denali_pio_read(struct denali_nand_info *denali, void *buf, size_t size, int page, int raw) { - uint32_t addr = DENALI_BANK(denali) | page; + u32 addr = DENALI_MAP01 | DENALI_BANK(denali) | page; uint32_t *buf32 = (uint32_t *)buf; uint32_t irq_status, ecc_err_mask; int i; @@ -523,9 +543,8 @@ static int denali_pio_read(struct denali_nand_info *denali, void *buf, denali_reset_irq(denali); - iowrite32(DENALI_MAP01 | addr, denali->host + DENALI_HOST_ADDR); for (i = 0; i < size / 4; i++) - *buf32++ = ioread32(denali->host + DENALI_HOST_DATA); + *buf32++ = denali->host_read(denali, addr); irq_status = denali_wait_for_irq(denali, INTR__PAGE_XFER_INC); if (!(irq_status & INTR__PAGE_XFER_INC)) @@ -540,16 +559,15 @@ static int denali_pio_read(struct denali_nand_info *denali, void *buf, static int denali_pio_write(struct denali_nand_info *denali, const void *buf, size_t size, int page, int raw) { - uint32_t addr = DENALI_BANK(denali) | page; + u32 addr = DENALI_MAP01 | DENALI_BANK(denali) | page; const uint32_t *buf32 = (uint32_t *)buf; uint32_t irq_status; int i; denali_reset_irq(denali); - iowrite32(DENALI_MAP01 | addr, denali->host + DENALI_HOST_ADDR); for (i = 0; i < size / 4; i++) - iowrite32(*buf32++, denali->host + DENALI_HOST_DATA); + denali->host_write(denali, addr, *buf32++); irq_status = denali_wait_for_irq(denali, INTR__PROGRAM_COMP | INTR__PROGRAM_FAIL); @@ -935,8 +953,8 @@ static int denali_erase(struct mtd_info *mtd, int page) denali_reset_irq(denali); - denali_host_write(denali, DENALI_MAP10 | DENALI_BANK(denali) | page, - DENALI_ERASE); + denali->host_write(denali, DENALI_MAP10 | DENALI_BANK(denali) | page, + DENALI_ERASE); /* wait for erase to complete or failure to occur */ irq_status = denali_wait_for_irq(denali, @@ -1227,6 +1245,7 @@ int denali_init(struct denali_nand_info *denali) { struct nand_chip *chip = &denali->nand; struct mtd_info *mtd = nand_to_mtd(chip); + u32 features = ioread32(denali->reg + FEATURES); int ret; mtd->dev.parent = denali->dev; @@ -1262,6 +1281,14 @@ int denali_init(struct denali_nand_info *denali) chip->dev_ready = denali_dev_ready; chip->waitfunc = denali_waitfunc; + if (features & FEATURES__INDEX_ADDR) { + denali->host_read = denali_indexed_read; + denali->host_write = denali_indexed_write; + } else { + denali->host_read = denali_direct_read; + denali->host_write = denali_direct_write; + } + /* clk rate info is needed for setup_data_interface */ if (denali->clk_x_rate) chip->setup_data_interface = denali_setup_data_interface; diff --git a/drivers/mtd/nand/denali.h b/drivers/mtd/nand/denali.h index f55ee10..3aeb272 100644 --- a/drivers/mtd/nand/denali.h +++ b/drivers/mtd/nand/denali.h @@ -319,6 +319,8 @@ struct denali_nand_info { unsigned int revision; /* IP revision */ unsigned int caps; /* IP capability (or quirk) */ const struct nand_ecc_caps *ecc_caps; + u32 (*host_read)(struct denali_nand_info *denali, u32 addr); + void (*host_write)(struct denali_nand_info *denali, u32 addr, u32 data); }; #define DENALI_CAP_HW_ECC_FIXUP BIT(0) From patchwork Fri Sep 22 03:46:49 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 113946 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp2797789qgf; Thu, 21 Sep 2017 20:48:53 -0700 (PDT) X-Google-Smtp-Source: AOwi7QA7RChpEEoePdDAjg3huYZuJX5UmMHUn5ELbD/amWtK4zN7e7jyjsjsqn7FkhZYLIb30Qys X-Received: by 10.99.115.92 with SMTP id d28mr8007703pgn.280.1506052132976; Thu, 21 Sep 2017 20:48:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506052132; cv=none; d=google.com; s=arc-20160816; b=iMi1AAC5tqzIMWXOLVuQtBZScRu5GQHwrYGYce7iPyvGLy+jwqez7KlMG9M2DeliVd l6L5t6FC3GV4gJqQk6N5Onar0CdsPFdWfnYlbYre5ufeN+fzkeTQJVEKkfxa9HfuYhDy Xd+Jh9YgHUK4o+QcXSbTngfBFML9o4MXMElPZUWs04ubsUmkhfCm72DIlVakJwMKj/Xi 73VewrjhGA1WgvuPIrH96IJFq1LJm7S9mU8aZrgX++bLtYLpwtLLl0MqN2y2ePtVdVUU fz8NXcH1kx2lqJVS5IF1imcdJ1IFTx8qTJDjxJuLeFlI3Fy9npY2+4F9z0E3JneBSrnV rfUA== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id t2si2053219pgb.259.2017.09.21.20.48.52; Thu, 21 Sep 2017 20:48:52 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=GHqaq2JC; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751847AbdIVDst (ORCPT + 26 others); Thu, 21 Sep 2017 23:48:49 -0400 Received: from conuserg-09.nifty.com ([210.131.2.76]:59293 "EHLO conuserg-09.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751726AbdIVDsq (ORCPT ); Thu, 21 Sep 2017 23:48:46 -0400 Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-09.nifty.com with ESMTP id v8M3kwAV029389; Fri, 22 Sep 2017 12:47:09 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-09.nifty.com v8M3kwAV029389 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1506052029; bh=3luMy4L57nnx0Dq3jtJCQGpVx5fmTXxWjwCXaeyTPac=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GHqaq2JCJaG5udEyUq27bWDobZr9jMPKMSAT49T/C7jPtJ6znm26b2JYZpYzps6TS v1u/wyBTkr957UxXg81QX0lrznkA5qG9jCvy3WhqlXtT3c5Hk7X2tQ/F+p0XZESycU 9qngH1C3+NAajWC1R9SbEOsdtP9sj/1YYLAZsTCjCGeyLy+OnCVmyr2R6a8cFtgHtL WQ30lLy8vQhv2u2ixpBxarUKEqkXQ2maMs/pAiutwiT/kvDDIXPpfNvin6pyBnWusZ FuC9nNzj9LUaxCmj8CN/jP0rhIkDdPPFEqPJEdP96yp2GxfwwCd2n0N23uYzRFmbcH mv4Q/T1Wvo0qA== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: linux-mtd@lists.infradead.org Cc: Masahiro Yamada , Cyrille Pitchen , linux-kernel@vger.kernel.org, Boris Brezillon , Marek Vasut , Brian Norris , Richard Weinberger , David Woodhouse Subject: [PATCH v2 12/12] mtd: nand: denali: change the setup_dma choice into hook Date: Fri, 22 Sep 2017 12:46:49 +0900 Message-Id: <1506052009-8285-13-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1506052009-8285-1-git-send-email-yamada.masahiro@socionext.com> References: <1506052009-8285-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The previous commit added some hooks into struct denali_nand_info, so here is one more for clean-up. Signed-off-by: Masahiro Yamada --- Changes in v2: - Newly added drivers/mtd/nand/denali.c | 15 +++++---------- drivers/mtd/nand/denali.h | 2 ++ 2 files changed, 7 insertions(+), 10 deletions(-) -- 2.7.4 diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index 7c24983..0b268ec 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -519,15 +519,6 @@ static void denali_setup_dma32(struct denali_nand_info *denali, denali->host_write(denali, mode | 0x14000, 0x2400); } -static void denali_setup_dma(struct denali_nand_info *denali, - dma_addr_t dma_addr, int page, int write) -{ - if (denali->caps & DENALI_CAP_DMA_64BIT) - denali_setup_dma64(denali, dma_addr, page, write); - else - denali_setup_dma32(denali, dma_addr, page, write); -} - static int denali_pio_read(struct denali_nand_info *denali, void *buf, size_t size, int page, int raw) { @@ -619,7 +610,7 @@ static int denali_dma_xfer(struct denali_nand_info *denali, void *buf, iowrite32(DMA_ENABLE__FLAG, denali->reg + DMA_ENABLE); denali_reset_irq(denali); - denali_setup_dma(denali, dma_addr, page, write); + denali->setup_dma(denali, dma_addr, page, write); irq_status = denali_wait_for_irq(denali, irq_mask); if (!(irq_status & INTR__DMA_CMD_COMP)) @@ -1314,6 +1305,10 @@ int denali_init(struct denali_nand_info *denali) if (denali->dma_avail) { chip->options |= NAND_USE_BOUNCE_BUFFER; chip->buf_align = 16; + if (denali->caps & DENALI_CAP_DMA_64BIT) + denali->setup_dma = denali_setup_dma64; + else + denali->setup_dma = denali_setup_dma32; } chip->bbt_options |= NAND_BBT_USE_FLASH; diff --git a/drivers/mtd/nand/denali.h b/drivers/mtd/nand/denali.h index 3aeb272..2911066 100644 --- a/drivers/mtd/nand/denali.h +++ b/drivers/mtd/nand/denali.h @@ -321,6 +321,8 @@ struct denali_nand_info { const struct nand_ecc_caps *ecc_caps; u32 (*host_read)(struct denali_nand_info *denali, u32 addr); void (*host_write)(struct denali_nand_info *denali, u32 addr, u32 data); + void (*setup_dma)(struct denali_nand_info *denali, dma_addr_t dma_addr, + int page, int write); }; #define DENALI_CAP_HW_ECC_FIXUP BIT(0)