From patchwork Fri Jul 3 21:23:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 232788 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2732451ilg; Fri, 3 Jul 2020 14:23:52 -0700 (PDT) X-Google-Smtp-Source: ABdhPJybu0qY9qELkgb8pwHwxiEsegsDwgB8PZyhYt2UPciLqD9U5imUZ9WMBq91fQVOt1ut2I4y X-Received: by 2002:a17:907:2149:: with SMTP id rk9mr33256243ejb.553.1593811432026; Fri, 03 Jul 2020 14:23:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593811432; cv=none; d=google.com; s=arc-20160816; b=xDdUAUpbMsc7GIAOMRXpscPG/MbUtF1rcMDpZzbFCgmJYPuNssLGGpepC/BBm1jjGq bFPVNGIkk1JnCr63Lcs9HY4JK60hvrmVbAkx91UNYi/oQI4zSlg1rgsYirL5QwVX8FNK 4GZpDKGJB0pDeVQIaAQFmJ1f/ux3/ZzJIa9RPK+zs1zq8PR3BUy4DDTNl0yHKMyxeQko pKJdyqXw/eAlwn7LnoO5ZdGBktd7Xxx8VStaQCVguJeXeu4hADEhsOTbrZCRHbosjCOw 0BahEbTAKKdILjLc8Hbfi1E2Z0scz2EQVuLyuJkJ81ZF63HWmzIkTfAY2O0x89jtdpzL pqrQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=GOZruoDFDXv5kLGp9J9FoBUytV2ZuP8UVxYNd0ERIPw=; b=nlC4pnszTZJ1vCWo7fhpnN8Fij0GSa1UejYcmilg3YIBwY5q0Ha5oPS8oattOFKj6q e6b9EXV4KdJP+pjr+E8odc47KdKVXgIXjwPVfXA6qJIui37aq5GZXU9xBNYHsL6l3kRU bUJ5CXQfQYzvvZlNffZ+GJUzk5dzZLdNEARtJPerl0H8EUi7JwobyGUEL3k7oLQe1p5J yj8qPZMNnDtWGxu8jGKqz9jTzjWfv5O+dM3DrxEI9MLN4l5HOqYEEFGQyA7+bFtiA3I8 recp6xOQl+aLJE2kO/O3p1lkURzTlXc2kfwNvZU0g1ifnp7tDw5Q2lh79aR1b5SKxgKg 3pnA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SFF7Iduq; spf=pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[73.185.129.58]) by smtp.gmail.com with ESMTPSA id m6sm7485292ilb.39.2020.07.03.14.23.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jul 2020 14:23:38 -0700 (PDT) From: Alex Elder To: davem@davemloft.net, kuba@kernel.org Cc: evgreen@chromium.org, subashab@codeaurora.org, cpratapa@codeaurora.org, bjorn.andersson@linaro.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 1/2] net: ipa: introduce ipa_clock_rate() Date: Fri, 3 Jul 2020 16:23:34 -0500 Message-Id: <20200703212335.465355-2-elder@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200703212335.465355-1-elder@linaro.org> References: <20200703212335.465355-1-elder@linaro.org> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Create a new function that returns the current rate of the IPA core clock. Signed-off-by: Alex Elder --- drivers/net/ipa/ipa_clock.c | 6 ++++++ drivers/net/ipa/ipa_clock.h | 8 ++++++++ 2 files changed, 14 insertions(+) -- 2.25.1 diff --git a/drivers/net/ipa/ipa_clock.c b/drivers/net/ipa/ipa_clock.c index c5204fd58ac4..0fbc8b1bdf41 100644 --- a/drivers/net/ipa/ipa_clock.c +++ b/drivers/net/ipa/ipa_clock.c @@ -256,6 +256,12 @@ void ipa_clock_put(struct ipa *ipa) mutex_unlock(&clock->mutex); } +/* Return the current IPA core clock rate */ +u32 ipa_clock_rate(struct ipa *ipa) +{ + return ipa->clock ? (u32)clk_get_rate(ipa->clock->core) : 0; +} + /* Initialize IPA clocking */ struct ipa_clock *ipa_clock_init(struct device *dev) { diff --git a/drivers/net/ipa/ipa_clock.h b/drivers/net/ipa/ipa_clock.h index bc52b35e6bb2..0f4e2877a6df 100644 --- a/drivers/net/ipa/ipa_clock.h +++ b/drivers/net/ipa/ipa_clock.h @@ -10,6 +10,14 @@ struct device; struct ipa; +/** + * ipa_clock_rate() - Return the current IPA core clock rate + * @ipa: IPA structure + * + * Return: The current clock rate (in Hz), or 0. + */ +u32 ipa_clock_rate(struct ipa *ipa); + /** * ipa_clock_init() - Initialize IPA clocking * @dev: IPA device From patchwork Fri Jul 3 21:23:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 232787 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp2732433ilg; Fri, 3 Jul 2020 14:23:50 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwrcz2tW9f/c4PbTMRFLU145tCInTRByERdbLNFNQsrnP42sHQlta18LA3pe6HRqSA3KPgL X-Received: by 2002:a05:6402:17f6:: with SMTP id t22mr44367004edy.141.1593811430138; Fri, 03 Jul 2020 14:23:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593811430; cv=none; d=google.com; s=arc-20160816; b=Ltkh5uz+w47uhp531T6HtTLEKPOUi3N0dXv+Rokxfp5u15WPs1cXEpDultnzvN44Vo g2djvX6K7GnwpHMSzhxux5MsXKaZi7MYG4QzyKtQFDY1Jg+upCYosubESjXtUpqYoeBw M5oZeO/C4I0GgG3SHhYu60fmH2FV9nAkT7YvttkvOoFWLlf6n+QT13aS0iwp34PjcYFv BmBUB3GEYg4Z/Q/6QoeudcH2hx2vcsCqZCopN2w3UIynhathIxgI7Isyl/aSJhxZA25L A3jGASybXDUREvD3L4MksbcqyKNk+EPh2UKhm6KTz5mdHaJBPvP8m5KF4ToRGtY0tkYC f3SA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=a1fvvSd4Jv5N25/XSLdxX+JF3MOyj15/ornprnLeFOY=; b=pcIj3+cTkgOeGdm44NrdTfcNUVPsFYLZSBaTyzDgwyP6MtJBXoxTuY0Y4Jo4IjSeqA k6viTVkoMb2Kw10FqQ52r7AioC+f35oRilu/DJh+xNpmEkYUPCsdfsMreJP1h4d4aqnt R9Gc78gbqRE/c2v0oWsjWQ4CiEqusm4gA2lmnkVYVmOv5VqeXEOykR7lNrJyM6nQw4GZ szmTxhuju/OtCR2zG3ovs686k66zwZsRMPMEe4LLoahKH3rorGFBPWmLw8bbBOILIZ2V 8dHzGfbJAdPm+T2c6Xi6336gooxHdZ+WbqO/u0P15Um3MVIVqEQaZVc+Nmo8ZZ78pXUg 2A/w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=v3+4z0zZ; spf=pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[73.185.129.58]) by smtp.gmail.com with ESMTPSA id m6sm7485292ilb.39.2020.07.03.14.23.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jul 2020 14:23:39 -0700 (PDT) From: Alex Elder To: davem@davemloft.net, kuba@kernel.org Cc: evgreen@chromium.org, subashab@codeaurora.org, cpratapa@codeaurora.org, bjorn.andersson@linaro.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 2/2] net: ipa: fix HOLB timer calculation Date: Fri, 3 Jul 2020 16:23:35 -0500 Message-Id: <20200703212335.465355-3-elder@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200703212335.465355-1-elder@linaro.org> References: <20200703212335.465355-1-elder@linaro.org> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org For IPA v4.2, the exact interpretation of the register that defines the timeout for avoiding head-of-line blocking was a little unclear. We're only assigning a 0 timeout to it right now, so that wasn't very important. But now that I know how it's supposed to work, I'm fixing it. The register represents a tick counter, where each tick is equal to 128 IPA core clock cycles. For IPA v3.5.1, the register contains a simple counter value. But for IPA v4.2, the register contains two fields, base and scale, which approximate the tick counter as: ticks = base << scale The base and scale values to use for a given tick count are computed using clever bit operations, and measures are taken to make the resulting time period as close as possible to that requested. There's no need for ipa_endpoint_init_hol_block_timer() to return an error, so change its return type to void. Signed-off-by: Alex Elder --- drivers/net/ipa/ipa_endpoint.c | 78 +++++++++++++++++++--------------- 1 file changed, 43 insertions(+), 35 deletions(-) -- 2.25.1 diff --git a/drivers/net/ipa/ipa_endpoint.c b/drivers/net/ipa/ipa_endpoint.c index 99115a2a29ae..d4be12385bcc 100644 --- a/drivers/net/ipa/ipa_endpoint.c +++ b/drivers/net/ipa/ipa_endpoint.c @@ -21,6 +21,7 @@ #include "ipa_modem.h" #include "ipa_table.h" #include "ipa_gsi.h" +#include "ipa_clock.h" #define atomic_dec_not_zero(v) atomic_add_unless((v), -1, 0) @@ -675,63 +676,70 @@ static void ipa_endpoint_init_aggr(struct ipa_endpoint *endpoint) iowrite32(val, endpoint->ipa->reg_virt + offset); } -/* A return value of 0 indicates an error */ +/* The head-of-line blocking timer is defined as a tick count, where each + * tick represents 128 cycles of the IPA core clock. Return the value + * that should be written to that register that represents the timeout + * period provided. + */ static u32 ipa_reg_init_hol_block_timer_val(struct ipa *ipa, u32 microseconds) { + u32 width; u32 scale; - u32 base; + u64 ticks; + u64 rate; + u32 high; u32 val; if (!microseconds) - return 0; /* invalid delay */ + return 0; /* Nothing to compute if timer period is 0 */ - /* Timer is represented in units of clock ticks. */ - if (ipa->version < IPA_VERSION_4_2) - return microseconds; /* XXX Needs to be computed */ + /* Use 64 bit arithmetic to avoid overflow... */ + rate = ipa_clock_rate(ipa); + ticks = DIV_ROUND_CLOSEST(microseconds * rate, 128 * USEC_PER_SEC); + /* ...but we still need to fit into a 32-bit register */ + WARN_ON(ticks > U32_MAX); - /* IPA v4.2 represents the tick count as base * scale */ - scale = 1; /* XXX Needs to be computed */ - if (scale > field_max(SCALE_FMASK)) - return 0; /* scale too big */ + /* IPA v3.5.1 just records the tick count */ + if (ipa->version == IPA_VERSION_3_5_1) + return (u32)ticks; - base = DIV_ROUND_CLOSEST(microseconds, scale); - if (base > field_max(BASE_VALUE_FMASK)) - return 0; /* microseconds too big */ + /* For IPA v4.2, the tick count is represented by base and + * scale fields within the 32-bit timer register, where: + * ticks = base << scale; + * The best precision is achieved when the base value is as + * large as possible. Find the highest set bit in the tick + * count, and extract the number of bits in the base field + * such that that high bit is included. + */ + high = fls(ticks); /* 1..32 */ + width = HWEIGHT32(BASE_VALUE_FMASK); + scale = high > width ? high - width : 0; + if (scale) { + /* If we're scaling, round up to get a closer result */ + ticks += 1 << (scale - 1); + /* High bit was set, so rounding might have affected it */ + if (fls(ticks) != high) + scale++; + } val = u32_encode_bits(scale, SCALE_FMASK); - val |= u32_encode_bits(base, BASE_VALUE_FMASK); + val |= u32_encode_bits(ticks >> scale, BASE_VALUE_FMASK); return val; } -static int ipa_endpoint_init_hol_block_timer(struct ipa_endpoint *endpoint, - u32 microseconds) +/* If microseconds is 0, timeout is immediate */ +static void ipa_endpoint_init_hol_block_timer(struct ipa_endpoint *endpoint, + u32 microseconds) { u32 endpoint_id = endpoint->endpoint_id; struct ipa *ipa = endpoint->ipa; u32 offset; u32 val; - /* XXX We'll fix this when the register definition is clear */ - if (microseconds) { - struct device *dev = &ipa->pdev->dev; - - dev_err(dev, "endpoint %u non-zero HOLB period (ignoring)\n", - endpoint_id); - microseconds = 0; - } - - if (microseconds) { - val = ipa_reg_init_hol_block_timer_val(ipa, microseconds); - if (!val) - return -EINVAL; - } else { - val = 0; /* timeout is immediate */ - } offset = IPA_REG_ENDP_INIT_HOL_BLOCK_TIMER_N_OFFSET(endpoint_id); + val = ipa_reg_init_hol_block_timer_val(ipa, microseconds); iowrite32(val, ipa->reg_virt + offset); - - return 0; } static void @@ -756,7 +764,7 @@ void ipa_endpoint_modem_hol_block_clear_all(struct ipa *ipa) if (endpoint->toward_ipa || endpoint->ee_id != GSI_EE_MODEM) continue; - (void)ipa_endpoint_init_hol_block_timer(endpoint, 0); + ipa_endpoint_init_hol_block_timer(endpoint, 0); ipa_endpoint_init_hol_block_enable(endpoint, true); } }