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[92.34.215.146]) by smtp.gmail.com with ESMTPSA id t10sm624714ljg.60.2020.07.06.13.52.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jul 2020 13:52:56 -0700 (PDT) From: Linus Walleij To: Andrew Lunn , Vivien Didelot , Florian Fainelli , netdev@vger.kernel.org, "David S . Miller" Cc: Linus Walleij , DENG Qingfang , Mauri Sandberg Subject: [net-next PATCH 1/5 v4] net: dsa: tag_rtl4_a: Implement Realtek 4 byte A tag Date: Mon, 6 Jul 2020 22:52:41 +0200 Message-Id: <20200706205245.937091-2-linus.walleij@linaro.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200706205245.937091-1-linus.walleij@linaro.org> References: <20200706205245.937091-1-linus.walleij@linaro.org> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This implements the known parts of the Realtek 4 byte tag protocol version 0xA, as found in the RTL8366RB DSA switch. It is designated as protocol version 0xA as a different Realtek 4 byte tag format with protocol version 0x9 is known to exist in the Realtek RTL8306 chips. The tag and switch chip lacks public documentation, so the tag format has been reverse-engineered from packet dumps. As only ingress traffic has been available for analysis an egress tag has not been possible to develop (even using educated guesses about bit fields) so this is as far as it gets. It is not known if the switch even supports egress tagging. Excessive attempts to figure out the egress tag format was made. When nothing else worked, I just tried all bit combinations with 0xannp where a is protocol and p is port. I looped through all values several times trying to get a response from ping, without any positive result. Using just these ingress tags however, the switch functionality is vastly improved and the packets find their way into the destination port without any tricky VLAN configuration. On the D-Link DIR-685 the LAN ports now come up and respond to ping without any command line configuration so this is a real improvement for users. Egress packets need to be restricted to the proper target ports using VLAN, which the RTL8366RB DSA switch driver already sets up. Cc: DENG Qingfang Cc: Mauri Sandberg Reviewed-by: Andrew Lunn Signed-off-by: Linus Walleij --- ChangeLog v3->v4: - Drop an unused variable found with -Wunused-variable ChangeLog v2->v3: - Collect Andrew's review tag. ChangeLog v1->v2: - Drop some netdev_dbg() calls that was just littering. - Rebase on v5.8-rc1 --- include/net/dsa.h | 2 + net/dsa/Kconfig | 7 +++ net/dsa/Makefile | 1 + net/dsa/tag_rtl4_a.c | 130 +++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 140 insertions(+) create mode 100644 net/dsa/tag_rtl4_a.c -- 2.26.2 diff --git a/include/net/dsa.h b/include/net/dsa.h index 50389772c597..2b37943f09a4 100644 --- a/include/net/dsa.h +++ b/include/net/dsa.h @@ -44,6 +44,7 @@ struct phylink_link_state; #define DSA_TAG_PROTO_KSZ8795_VALUE 14 #define DSA_TAG_PROTO_OCELOT_VALUE 15 #define DSA_TAG_PROTO_AR9331_VALUE 16 +#define DSA_TAG_PROTO_RTL4_A_VALUE 17 enum dsa_tag_protocol { DSA_TAG_PROTO_NONE = DSA_TAG_PROTO_NONE_VALUE, @@ -63,6 +64,7 @@ enum dsa_tag_protocol { DSA_TAG_PROTO_KSZ8795 = DSA_TAG_PROTO_KSZ8795_VALUE, DSA_TAG_PROTO_OCELOT = DSA_TAG_PROTO_OCELOT_VALUE, DSA_TAG_PROTO_AR9331 = DSA_TAG_PROTO_AR9331_VALUE, + DSA_TAG_PROTO_RTL4_A = DSA_TAG_PROTO_RTL4_A_VALUE, }; struct packet_type; diff --git a/net/dsa/Kconfig b/net/dsa/Kconfig index d5bc6ac599ef..1f9b9b11008c 100644 --- a/net/dsa/Kconfig +++ b/net/dsa/Kconfig @@ -86,6 +86,13 @@ config NET_DSA_TAG_KSZ Say Y if you want to enable support for tagging frames for the Microchip 8795/9477/9893 families of switches. +config NET_DSA_TAG_RTL4_A + tristate "Tag driver for Realtek 4 byte protocol A tags" + help + Say Y or M if you want to enable support for tagging frames for the + Realtek switches with 4 byte protocol A tags, sich as found in + the Realtek RTL8366RB. + config NET_DSA_TAG_OCELOT tristate "Tag driver for Ocelot family of switches" select PACKING diff --git a/net/dsa/Makefile b/net/dsa/Makefile index 108486cfdeef..4f47b2025ff5 100644 --- a/net/dsa/Makefile +++ b/net/dsa/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_NET_DSA_TAG_DSA) += tag_dsa.o obj-$(CONFIG_NET_DSA_TAG_EDSA) += tag_edsa.o obj-$(CONFIG_NET_DSA_TAG_GSWIP) += tag_gswip.o obj-$(CONFIG_NET_DSA_TAG_KSZ) += tag_ksz.o +obj-$(CONFIG_NET_DSA_TAG_RTL4_A) += tag_rtl4_a.o obj-$(CONFIG_NET_DSA_TAG_LAN9303) += tag_lan9303.o obj-$(CONFIG_NET_DSA_TAG_MTK) += tag_mtk.o obj-$(CONFIG_NET_DSA_TAG_OCELOT) += tag_ocelot.o diff --git a/net/dsa/tag_rtl4_a.c b/net/dsa/tag_rtl4_a.c new file mode 100644 index 000000000000..36af1f49fd75 --- /dev/null +++ b/net/dsa/tag_rtl4_a.c @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Handler for Realtek 4 byte DSA switch tags + * Currently only supports protocol "A" found in RTL8366RB + * Copyright (c) 2020 Linus Walleij + * + * This "proprietary tag" header looks like so: + * + * ------------------------------------------------- + * | MAC DA | MAC SA | 0x8899 | 2 bytes tag | Type | + * ------------------------------------------------- + * + * The 2 bytes tag form a 16 bit big endian word. The exact + * meaning has been guess from packet dumps from ingress + * frames, as no working egress traffic has been available + * we do not know the format of the egress tags or if they + * are even supported. + */ + +#include +#include + +#include "dsa_priv.h" + +#define RTL4_A_HDR_LEN 4 +#define RTL4_A_ETHERTYPE 0x8899 +#define RTL4_A_PROTOCOL_SHIFT 12 +/* + * 0x1 = Realtek Remote Control protocol (RRCP) + * 0x2/0x3 seems to be used for loopback testing + * 0x9 = RTL8306 DSA protocol + * 0xa = RTL8366RB DSA protocol + */ +#define RTL4_A_PROTOCOL_RTL8366RB 0xa + +static struct sk_buff *rtl4a_tag_xmit(struct sk_buff *skb, + struct net_device *dev) +{ + /* + * Just let it pass thru, we don't know if it is possible + * to tag a frame with the 0x8899 ethertype and direct it + * to a specific port, all attempts at reverse-engineering have + * ended up with the frames getting dropped. + * + * The VLAN set-up needs to restrict the frames to the right port. + * + * If you have documentation on the tagging format for RTL8366RB + * (tag type A) then please contribute. + */ + return skb; +} + +static struct sk_buff *rtl4a_tag_rcv(struct sk_buff *skb, + struct net_device *dev, + struct packet_type *pt) +{ + u16 protport; + __be16 *p; + u16 etype; + u8 *tag; + u8 prot; + u8 port; + + if (unlikely(!pskb_may_pull(skb, RTL4_A_HDR_LEN))) + return NULL; + + /* The RTL4 header has its own custom Ethertype 0x8899 and that + * starts right at the beginning of the packet, after the src + * ethernet addr. Apparantly skb->data always points 2 bytes in, + * behind the Ethertype. + */ + tag = skb->data - 2; + p = (__be16 *)tag; + etype = ntohs(*p); + if (etype != RTL4_A_ETHERTYPE) { + /* Not custom, just pass through */ + netdev_dbg(dev, "non-realtek ethertype 0x%04x\n", etype); + return skb; + } + p = (__be16 *)(tag + 2); + protport = ntohs(*p); + /* The 4 upper bits are the protocol */ + prot = (protport >> RTL4_A_PROTOCOL_SHIFT) & 0x0f; + if (prot != RTL4_A_PROTOCOL_RTL8366RB) { + netdev_err(dev, "unknown realtek protocol 0x%01x\n", prot); + return NULL; + } + port = protport & 0xff; + + /* Remove RTL4 tag and recalculate checksum */ + skb_pull_rcsum(skb, RTL4_A_HDR_LEN); + + /* Move ethernet DA and SA in front of the data */ + memmove(skb->data - ETH_HLEN, + skb->data - ETH_HLEN - RTL4_A_HDR_LEN, + 2 * ETH_ALEN); + + skb->dev = dsa_master_find_slave(dev, 0, port); + if (!skb->dev) { + netdev_dbg(dev, "could not find slave for port %d\n", port); + return NULL; + } + + skb->offload_fwd_mark = 1; + + return skb; +} + +static int rtl4a_tag_flow_dissect(const struct sk_buff *skb, __be16 *proto, + int *offset) +{ + *offset = RTL4_A_HDR_LEN; + /* Skip past the tag and fetch the encapsulated Ethertype */ + *proto = ((__be16 *)skb->data)[1]; + + return 0; +} + +static const struct dsa_device_ops rtl4a_netdev_ops = { + .name = "rtl4a", + .proto = DSA_TAG_PROTO_RTL4_A, + .xmit = rtl4a_tag_xmit, + .rcv = rtl4a_tag_rcv, + .flow_dissect = rtl4a_tag_flow_dissect, + .overhead = RTL4_A_HDR_LEN, +}; +module_dsa_tag_driver(rtl4a_netdev_ops); + +MODULE_LICENSE("GPL"); +MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_RTL4_A); From patchwork Mon Jul 6 20:52:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 234888 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp307830ilg; Mon, 6 Jul 2020 13:53:02 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxV62a0AIUabbC69FWUIOwM3AY0UsIYnXpoFBt52a7cBhMLO1oloARILChsNtGPrR3th8G3 X-Received: by 2002:a17:907:426c:: with SMTP id nx20mr43999072ejb.548.1594068782509; Mon, 06 Jul 2020 13:53:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594068782; cv=none; d=google.com; s=arc-20160816; b=EBfumFbFofYv5hlLkzRlVQjCXK31tM22sLUNtHBtyBBqOr/6Y6b/AbKnoOxr0opXQt Gwdrd7JKakWKRMKVpXKC83PLdam1PrMjOJYsBgg3GzzWFHICLqOwhuMicS3j3MftxduC AurMAmgYq+JNF2WaCivuA0Cm4dWM0MPD+CjZOu/zQho+N8P0C64IJJDK2H664375Rr/4 Bc//injACnd5uy/wGMXa+R35nyPosjKRsfqB1swsPsxxnzTANXFkZ53ZdHT03UbyspN3 xDqrbIDmP8k+GUCmIxLxpjK4S3hpLlAE7MK1qH9oJh+T/OnfFXpHBWrGXGlNYLt3DMs5 PJVA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=c+ak1vCwUbkOf/U1XrGYOgY9Jz2T36VyPtI9qVgHch0=; b=NW3hDiu1aAz0VuS697Y4ZLluAhPHmgSmUm3uXH0B/gl2DVsSpVwfMSZ+yXc4i3Z1WR QYcI6nodXZPOMc1hCcsGcPLhuH/GrLmGZNC4GD455Ic3k/RPUuHDMUeDytn2zXzM+jp7 CJwcmWFFm8m4ME2DPFNBtRIvOssx8BbXPTbYzUQTBtf49/c5YejiPVFH4mzb7qEgFz1w uQ39z5q3LtsaxDcomV/P5apJeOCyo1+e3BKWuhQqulkiB5ou3E/U+FiFom4FH2P7bdqG miymroPOUC+fjs0VoXM1bN8tRHIccvHVtmWDdFETCYrmVpZL4tLwxw1cWlMxPBEf82je 7RFQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=q4141YYr; spf=pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[92.34.215.146]) by smtp.gmail.com with ESMTPSA id t10sm624714ljg.60.2020.07.06.13.52.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jul 2020 13:52:58 -0700 (PDT) From: Linus Walleij To: Andrew Lunn , Vivien Didelot , Florian Fainelli , netdev@vger.kernel.org, "David S . Miller" Cc: Linus Walleij , DENG Qingfang , Mauri Sandberg Subject: [net-next PATCH 2/5 v4] net: dsa: rtl8366rb: Support the CPU DSA tag Date: Mon, 6 Jul 2020 22:52:42 +0200 Message-Id: <20200706205245.937091-3-linus.walleij@linaro.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200706205245.937091-1-linus.walleij@linaro.org> References: <20200706205245.937091-1-linus.walleij@linaro.org> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This activates the support to use the CPU tag to properly direct ingress traffic to the right port. Bit 15 in register RTL8368RB_CPU_CTRL_REG can be set to 1 to disable the insertion of the CPU tag which is what the code currently does. The bit 15 define calls this setting RTL8368RB_CPU_INSTAG which is confusing since the inverse meaning is implied: programmers may think that setting this bit to 1 will *enable* inserting the tag rather than disabling it, so rename this setting in bit 15 to RTL8368RB_CPU_NO_TAG which is more to the point. After this e.g. ping works out-of-the-box with the RTL8366RB. Cc: DENG Qingfang Cc: Mauri Sandberg Reviewed-by: Andrew Lunn Signed-off-by: Linus Walleij --- ChangeLog v3->v4: - Resend with the rest ChangeLog v2->v3: - Fix up the commit message. - Collect Andrew's review tag. ChangeLog v1->v2: - Update the commit message to explain why we are renaming bit 15 in RTL8368RB_CPU_CTRL_REG. --- drivers/net/dsa/Kconfig | 1 + drivers/net/dsa/rtl8366rb.c | 31 ++++++++----------------------- 2 files changed, 9 insertions(+), 23 deletions(-) -- 2.26.2 diff --git a/drivers/net/dsa/Kconfig b/drivers/net/dsa/Kconfig index d0024cb30a7b..468b3c4273c5 100644 --- a/drivers/net/dsa/Kconfig +++ b/drivers/net/dsa/Kconfig @@ -70,6 +70,7 @@ config NET_DSA_QCA8K config NET_DSA_REALTEK_SMI tristate "Realtek SMI Ethernet switch family support" depends on NET_DSA + select NET_DSA_TAG_RTL4_A select FIXED_PHY select IRQ_DOMAIN select REALTEK_PHY diff --git a/drivers/net/dsa/rtl8366rb.c b/drivers/net/dsa/rtl8366rb.c index fd1977590cb4..48f1ff746799 100644 --- a/drivers/net/dsa/rtl8366rb.c +++ b/drivers/net/dsa/rtl8366rb.c @@ -109,8 +109,8 @@ /* CPU port control reg */ #define RTL8368RB_CPU_CTRL_REG 0x0061 #define RTL8368RB_CPU_PORTS_MSK 0x00FF -/* Enables inserting custom tag length/type 0x8899 */ -#define RTL8368RB_CPU_INSTAG BIT(15) +/* Disables inserting custom tag length/type 0x8899 */ +#define RTL8368RB_CPU_NO_TAG BIT(15) #define RTL8366RB_SMAR0 0x0070 /* bits 0..15 */ #define RTL8366RB_SMAR1 0x0071 /* bits 16..31 */ @@ -844,16 +844,14 @@ static int rtl8366rb_setup(struct dsa_switch *ds) if (ret) return ret; - /* Enable CPU port and enable inserting CPU tag + /* Enable CPU port with custom DSA tag 8899. * - * Disabling RTL8368RB_CPU_INSTAG here will change the behaviour - * of the switch totally and it will start talking Realtek RRCP - * internally. It is probably possible to experiment with this, - * but then the kernel needs to understand and handle RRCP first. + * If you set RTL8368RB_CPU_NO_TAG (bit 15) in this registers + * the custom tag is turned off. */ ret = regmap_update_bits(smi->map, RTL8368RB_CPU_CTRL_REG, 0xFFFF, - RTL8368RB_CPU_INSTAG | BIT(smi->cpu_port)); + BIT(smi->cpu_port)); if (ret) return ret; @@ -967,21 +965,8 @@ static enum dsa_tag_protocol rtl8366_get_tag_protocol(struct dsa_switch *ds, int port, enum dsa_tag_protocol mp) { - /* For now, the RTL switches are handled without any custom tags. - * - * It is possible to turn on "custom tags" by removing the - * RTL8368RB_CPU_INSTAG flag when enabling the port but what it - * does is unfamiliar to DSA: ethernet frames of type 8899, the Realtek - * Remote Control Protocol (RRCP) start to appear on the CPU port of - * the device. So this is not the ordinary few extra bytes in the - * frame. Instead it appears that the switch starts to talk Realtek - * RRCP internally which means a pretty complex RRCP implementation - * decoding and responding the RRCP protocol is needed to exploit this. - * - * The OpenRRCP project (dormant since 2009) have reverse-egineered - * parts of the protocol. - */ - return DSA_TAG_PROTO_NONE; + /* This switch uses the 4 byte protocol A Realtek DSA tag */ + return DSA_TAG_PROTO_RTL4_A; } static void rtl8366rb_adjust_link(struct dsa_switch *ds, int port, From patchwork Mon Jul 6 20:52:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 234889 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp307860ilg; Mon, 6 Jul 2020 13:53:05 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwchSnFT3NO4K7uLEDjsk7oUfRqWnK7TCmdsSYZtjXKBm3KspbabFddipaghCSY7sdqgR3v X-Received: by 2002:aa7:d3cd:: with SMTP id o13mr56536324edr.176.1594068785331; Mon, 06 Jul 2020 13:53:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594068785; cv=none; d=google.com; s=arc-20160816; b=aBmfitESTfXQULHPZ6oidSoE7u/s44ByuwSRMA9uAMz+R+QErYlrGGRGEb0qiI0DIR wydqi9JWlmlvDCGcE2GZ3Lz04yyD3k+vw9ImC4EuVF+Oc2Gciw2y0fJmbhGprP5KgaiF 6NdBwzZ814zpWulTPTDyPk2NHpeSBAa0FqTCJLliE8ZzkvCtU1xQPvwmsYQRiTroS6Ji h2DECUAA69+SuFe7d4MAMnHDZmasYyEMhbt1pMokWpAhOkgC+FXHBgm5P5Fy+0pp48RZ T9JJ57M5rPQg+pT0l6CCiIW+IM8NUhk9opb6tl/umPu3b+i7fcaB0UNdhIFWGKXojDms pkKg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=IGRiCDosImo09IoK/bbV7wmdxtWQy6UAfjTnx38Q7Bo=; b=K33DaaFAHw5iP/I0jaDrudJFWx6+USMHxONlPPaeMI7ujF7a2V2ffb1kPIp9Yu13nB fEw3+gjTr3e9OECfNSqlY4NFaF9td5BB2ovOxpfc8o2pqG0yFRb9sXWfp3eMqOmy6SdK t4lpQARMOELmDOIbpy1YAXnE81bf1iVgGxfv3gZUhLQ+Rissz0tq7pnKGIIr+IY2pU6f 7C4NmmXkhe2OwbiGAI0es86LjaA944Uy1694aQXA4w+zpKcm9p3pYAa98DRlCG8kWYi5 /b+SugllnnN8yg2/kGVz2vgysXla7mX/zRHPELxs+1eIJCLZ9faVlbpoaauYq5Ef8j13 HOlA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YbumsW7b; spf=pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[92.34.215.146]) by smtp.gmail.com with ESMTPSA id t10sm624714ljg.60.2020.07.06.13.53.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jul 2020 13:53:00 -0700 (PDT) From: Linus Walleij To: Andrew Lunn , Vivien Didelot , Florian Fainelli , netdev@vger.kernel.org, "David S . Miller" Cc: Linus Walleij , DENG Qingfang , Mauri Sandberg Subject: [net-next PATCH 3/5 v4] net: dsa: rtl8366: Split out default VLAN config Date: Mon, 6 Jul 2020 22:52:43 +0200 Message-Id: <20200706205245.937091-4-linus.walleij@linaro.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200706205245.937091-1-linus.walleij@linaro.org> References: <20200706205245.937091-1-linus.walleij@linaro.org> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org We loop over the ports to initialize the default VLAN and PVID for each port. As we need to reuse the code to reinitialize a single port, break out the function rtl8366_set_default_vlan_and_pvid(). Cc: DENG Qingfang Cc: Mauri Sandberg Reviewed-by: Andrew Lunn Signed-off-by: Linus Walleij --- ChangeLog v3->v4: - Resend with the rest ChangeLog v2->v3: - Rebased on Andrew's patch for the (int) compile warning on GENMASK(). change is carried over. - Collect Andrew's review tag. ChangeLog v1->v2: - Rebased on v5.8-rc1 and other changes. --- drivers/net/dsa/rtl8366.c | 70 ++++++++++++++++++++++++--------------- 1 file changed, 43 insertions(+), 27 deletions(-) -- 2.26.2 diff --git a/drivers/net/dsa/rtl8366.c b/drivers/net/dsa/rtl8366.c index 993cf3ac59d9..b907c0ed9697 100644 --- a/drivers/net/dsa/rtl8366.c +++ b/drivers/net/dsa/rtl8366.c @@ -253,6 +253,48 @@ int rtl8366_reset_vlan(struct realtek_smi *smi) } EXPORT_SYMBOL_GPL(rtl8366_reset_vlan); +static int rtl8366_set_default_vlan_and_pvid(struct realtek_smi *smi, + int port) +{ + u32 mask; + u16 vid; + int ret; + + /* This is the reserved default VLAN for this port */ + vid = port + 1; + + if (port == smi->cpu_port) + /* For the CPU port, make all ports members of this + * VLAN. + */ + mask = GENMASK((int)smi->num_ports - 1, 0); + else + /* For all other ports, enable itself plus the + * CPU port. + */ + mask = BIT(port) | BIT(smi->cpu_port); + + /* For each port, set the port as member of VLAN (port+1) + * and untagged, except for the CPU port: the CPU port (5) is + * member of VLAN 6 and so are ALL the other ports as well. + * Use filter 0 (no filter). + */ + dev_info(smi->dev, "Set VLAN %04x portmask to %08x (port %d %s)\n", + vid, mask, port, (port == smi->cpu_port) ? + "CPU PORT and all other ports" : "and CPU port"); + ret = rtl8366_set_vlan(smi, vid, mask, mask, 0); + if (ret) + return ret; + + dev_info(smi->dev, "Set PVID %04x on port %d\n", + vid, port); + ret = rtl8366_set_pvid(smi, port, vid); + if (ret) + return ret; + + return 0; +} + int rtl8366_init_vlan(struct realtek_smi *smi) { int port; @@ -266,33 +308,7 @@ int rtl8366_init_vlan(struct realtek_smi *smi) * it with the VLAN (port+1) */ for (port = 0; port < smi->num_ports; port++) { - u32 mask; - - if (port == smi->cpu_port) - /* For the CPU port, make all ports members of this - * VLAN. - */ - mask = GENMASK((int)smi->num_ports - 1, 0); - else - /* For all other ports, enable itself plus the - * CPU port. - */ - mask = BIT(port) | BIT(smi->cpu_port); - - /* For each port, set the port as member of VLAN (port+1) - * and untagged, except for the CPU port: the CPU port (5) is - * member of VLAN 6 and so are ALL the other ports as well. - * Use filter 0 (no filter). - */ - dev_info(smi->dev, "VLAN%d port mask for port %d, %08x\n", - (port + 1), port, mask); - ret = rtl8366_set_vlan(smi, (port + 1), mask, mask, 0); - if (ret) - return ret; - - dev_info(smi->dev, "VLAN%d port %d, PVID set to %d\n", - (port + 1), port, (port + 1)); - ret = rtl8366_set_pvid(smi, port, (port + 1)); + ret = rtl8366_set_default_vlan_and_pvid(smi, port); if (ret) return ret; } From patchwork Mon Jul 6 20:52:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 234890 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp307871ilg; Mon, 6 Jul 2020 13:53:06 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwCBJo4bGmmPlKWRhJehUyie8bh4kpz28g6YxDTETACSZ5HA2qow+3h8/gPKOGAidepCYQF X-Received: by 2002:a50:ee01:: with SMTP id g1mr49999601eds.264.1594068786227; Mon, 06 Jul 2020 13:53:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594068786; cv=none; d=google.com; s=arc-20160816; b=N3vxvLjO3IFVGxp3mgFtVnClCfYtZCmaiIRgxmskXwWPVFT7f5q0Uz/vxRccz+Q96P Hc7BzLyfPtVbDFuAb6D2ZWVHl/z95UmMHsfIHrvjWWJikqUcMDbfKv9n+hXpD5uI/IWr X+xZF5dXqXIz5fjapQPFy7exJkbGHHMUqjFEmsjxy5Vd6mlxpc1L7qM6tfo3/Z+3cUF7 xTszO9qNih/IjEd3HzPC1yA7eCcVvVREL3nVhFuig3sLsYxa+/kmRtYBv3y2YXqWwrCS qm71AxIQ+Qq2LAZGWZHWTTcKwm31D8DaPYfZU4zRuho7QghgF04XxZyop6qXLxLC8cXs +sqw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=qoKUfx+bRpgzp/ddkVCT09K2I1cceu5SICdacEnRFsc=; b=a1OhlBGTxSi9pbQPpSjFW0oP6Z4TGA9yYePGlUCf/8YJPZzi9t00PrU+GDaxtcfHFx RTaQSo7ep+QzsSyFVVsmPEyJSqi7hWSiGciq17cpc6zW+E6Itx1gQaiKr46LcQN0hFrE s7QCl/DdHx69lEN3YEqRWsU+rUyI2QWEkNJ7ibaenZNX7xx4QF9KlJ3iWVeCCYDulaJw AAASYF7HGE7zx+tdooxFGqiIJulg4APCmSv14Sqiiq/MUopRE304+8HNP3VCkqg1Fmv5 BYo18gxXYw/qG6GHKPWY/iIaIIp307wyvlgTrw1w892CVodBgCzlQytxuMerbZXnWSev wU2Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dXL2nwR1; spf=pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[92.34.215.146]) by smtp.gmail.com with ESMTPSA id t10sm624714ljg.60.2020.07.06.13.53.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jul 2020 13:53:02 -0700 (PDT) From: Linus Walleij To: Andrew Lunn , Vivien Didelot , Florian Fainelli , netdev@vger.kernel.org, "David S . Miller" Cc: Linus Walleij , DENG Qingfang , Mauri Sandberg Subject: [net-next PATCH 4/5 v4] net: dsa: rtl8366: VLAN 0 as disable tagging Date: Mon, 6 Jul 2020 22:52:44 +0200 Message-Id: <20200706205245.937091-5-linus.walleij@linaro.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200706205245.937091-1-linus.walleij@linaro.org> References: <20200706205245.937091-1-linus.walleij@linaro.org> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The code in net/8021q/vlan.c, vlan_device_event() sets VLAN 0 for a VLAN-capable ethernet device when it comes up. Since the RTL8366 DSA switches must have a VLAN and PVID set up for any packets to come through we have already set up default VLAN for each port as part of bringing the switch online. Make sure that setting VLAN 0 has the same effect and does not try to actually tell the hardware to use VLAN 0 on the port because that will not work. Cc: DENG Qingfang Cc: Mauri Sandberg Reviewed-by: Andrew Lunn Signed-off-by: Linus Walleij --- ChangeLog v3->v4: - Resend with the rest ChangeLog v2->v3: - Collected Andrew's review tag. ChangeLog v1->v2: - Rebased on v5.8-rc1 and other changes. --- drivers/net/dsa/rtl8366.c | 65 +++++++++++++++++++++++++++++++-------- 1 file changed, 52 insertions(+), 13 deletions(-) -- 2.26.2 diff --git a/drivers/net/dsa/rtl8366.c b/drivers/net/dsa/rtl8366.c index b907c0ed9697..a000d458d121 100644 --- a/drivers/net/dsa/rtl8366.c +++ b/drivers/net/dsa/rtl8366.c @@ -355,15 +355,25 @@ int rtl8366_vlan_prepare(struct dsa_switch *ds, int port, const struct switchdev_obj_port_vlan *vlan) { struct realtek_smi *smi = ds->priv; + u16 vid_begin = vlan->vid_begin; + u16 vid_end = vlan->vid_end; u16 vid; int ret; - for (vid = vlan->vid_begin; vid < vlan->vid_end; vid++) + if (vid_begin == 0) { + dev_info(smi->dev, "prepare VLAN 0 - ignored\n"); + if (vid_end == 0) + return 0; + /* Skip VLAN 0 and start with VLAN 1 */ + vid_begin = 1; + } + + for (vid = vid_begin; vid < vid_end; vid++) if (!smi->ops->is_vlan_valid(smi, vid)) return -EINVAL; dev_info(smi->dev, "prepare VLANs %04x..%04x\n", - vlan->vid_begin, vlan->vid_end); + vid_begin, vid_end); /* Enable VLAN in the hardware * FIXME: what's with this 4k business? @@ -383,27 +393,46 @@ void rtl8366_vlan_add(struct dsa_switch *ds, int port, bool untagged = !!(vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED); bool pvid = !!(vlan->flags & BRIDGE_VLAN_INFO_PVID); struct realtek_smi *smi = ds->priv; + u16 vid_begin = vlan->vid_begin; + u16 vid_end = vlan->vid_end; u32 member = 0; u32 untag = 0; u16 vid; int ret; - for (vid = vlan->vid_begin; vid < vlan->vid_end; vid++) - if (!smi->ops->is_vlan_valid(smi, vid)) + if (vid_begin == 0) { + dev_info(smi->dev, "set VLAN 0 on port %d = default VLAN\n", + port); + /* Set up default tagging */ + ret = rtl8366_set_default_vlan_and_pvid(smi, port); + if (ret) { + dev_err(smi->dev, + "error setting default VLAN on port %d\n", + port); return; + } + if (vid_end == 0) + return; + /* Skip VLAN 0 and start with VLAN 1 */ + vid_begin = 1; + } - dev_info(smi->dev, "add VLAN on port %d, %s, %s\n", - port, - untagged ? "untagged" : "tagged", - pvid ? " PVID" : "no PVID"); + for (vid = vid_begin; vid < vid_end; vid++) + if (!smi->ops->is_vlan_valid(smi, vid)) + return; if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) dev_err(smi->dev, "port is DSA or CPU port\n"); - for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { + for (vid = vid_begin; vid <= vid_end; ++vid) { int pvid_val = 0; - dev_info(smi->dev, "add VLAN %04x\n", vid); + dev_info(smi->dev, "add VLAN %04x to port %d, %s, %s\n", + vid, + port, + untagged ? "untagged" : "tagged", + pvid ? " PVID" : "no PVID"); + member |= BIT(port); if (untagged) @@ -437,15 +466,25 @@ int rtl8366_vlan_del(struct dsa_switch *ds, int port, const struct switchdev_obj_port_vlan *vlan) { struct realtek_smi *smi = ds->priv; + u16 vid_begin = vlan->vid_begin; + u16 vid_end = vlan->vid_end; u16 vid; int ret; - dev_info(smi->dev, "del VLAN on port %d\n", port); + if (vid_begin == 0) { + dev_info(smi->dev, "remove port %d from VLAN 0 (no-op)\n", + port); + if (vid_end == 0) + return 0; + /* Skip VLAN 0 and start with VLAN 1 */ + vid_begin = 1; + } - for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { + for (vid = vid_begin; vid <= vid_end; ++vid) { int i; - dev_info(smi->dev, "del VLAN %04x\n", vid); + dev_info(smi->dev, "remove VLAN %04x from port %d\n", + vid, port); for (i = 0; i < smi->num_vlan_mc; i++) { struct rtl8366_vlan_mc vlanmc; From patchwork Mon Jul 6 20:52:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 234891 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp307895ilg; Mon, 6 Jul 2020 13:53:08 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwZ+TjlHayQ3ORB2ED9AYiXfun/kCziLuBIvVNKK8Jho+tr7Eb9H2QWvvmf6JRZqrX7Qxxk X-Received: by 2002:a17:906:19c7:: with SMTP id h7mr43653548ejd.403.1594068788687; Mon, 06 Jul 2020 13:53:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594068788; cv=none; d=google.com; s=arc-20160816; b=We+mTE1bwDY65gv80q4JRiXxTvJQXRmvGBCJf64jAmBXWMQaRDvBTLZjPJ+vjNY9u6 J5bsDzRmSGrqI3YIdj0LxDChZWJAzRmW5+bwtGx2MMb3sr2fquZCqxdQSV8ai+9DRlEf 8lySHiYlZdYcttFFEHixj8a+QT0hhPM0U3dNMxVct4r5snH736Gqy09XXV313OVlixGF 2JDtjTnzQe9JOchLXgMDHQBOB4k7wB461yI9WGsUqObf+iTG7KzC98jQZrdJ9n2fIY4q SNxzn9qhHs9WHXTAFCvR5PdwI5xDbL6+ToU4p820quPyekX2jVUHneiYW//6jg2/n0rq fgnA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=f4F27NvYH7YHeuYKRHbuc0Pqyyr+0B+jF6d12ClwIkI=; b=QNarXGFSZeD5iMEwJm4w9r2pM8tifROqgZYa0DR/Eu4c84Tqi4Y9do2+vdB728SpKC uvr1LZMOlxMw+UIIWOJnZwx3dawwy0oJfyMI13Mc37rYhjG+9CGegdmEQ3Ya/vKJhgi+ iwI1fLPupEX7oDf71UpfRQ5kJVqEJxLf2llIAbEcb8w7gdjWniRCYIMEc09KkuPURjzL JsFHWCwi+oW5WD6Au/BEd2vW4cQsrMQ2+hDt4InsoYlgnRlKF0PgDcUms8jLVZl+utvJ zvJgDRqmBqo03WWWxl2ZGOT7FU+MFlgjG8RtS/130MkcFXdjnQkSxvCSQzOMF8GH4V4O qHtQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="lOW1Wg/P"; spf=pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[92.34.215.146]) by smtp.gmail.com with ESMTPSA id t10sm624714ljg.60.2020.07.06.13.53.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jul 2020 13:53:03 -0700 (PDT) From: Linus Walleij To: Andrew Lunn , Vivien Didelot , Florian Fainelli , netdev@vger.kernel.org, "David S . Miller" Cc: Linus Walleij , DENG Qingfang , Mauri Sandberg Subject: [net-next PATCH 5/5 v4] net: dsa: rtl8366: Use top VLANs for default Date: Mon, 6 Jul 2020 22:52:45 +0200 Message-Id: <20200706205245.937091-6-linus.walleij@linaro.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200706205245.937091-1-linus.walleij@linaro.org> References: <20200706205245.937091-1-linus.walleij@linaro.org> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The RTL8366 DSA switches will not work unless we set up a default VLAN for each port. We are currently using e.g. VLAN 1..6 for a 5-port switch as default VLANs. This is not very helpful for users, move it to allocate the top VLANs for default instead, for example on RTL8366RB there are 16 VLANs so instead of using VLAN 1..6 as default use VLAN 10..15 so VLAN 1 thru VLAN 9 is available for users. Cc: DENG Qingfang Cc: Mauri Sandberg Reviewed-by: Andrew Lunn Signed-off-by: Linus Walleij --- ChangeLog v3->v4: - Resend with the rest ChangeLog v2->v3: - Collect Andrew's reviewed-by. ChangeLog v1->v2: - Rebase on v5.8-rc1. --- drivers/net/dsa/rtl8366.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.26.2 diff --git a/drivers/net/dsa/rtl8366.c b/drivers/net/dsa/rtl8366.c index a000d458d121..06adcf68ff8d 100644 --- a/drivers/net/dsa/rtl8366.c +++ b/drivers/net/dsa/rtl8366.c @@ -260,8 +260,8 @@ static int rtl8366_set_default_vlan_and_pvid(struct realtek_smi *smi, u16 vid; int ret; - /* This is the reserved default VLAN for this port */ - vid = port + 1; + /* Use the top VLANs for per-port default VLAN */ + vid = smi->num_vlan_mc - smi->num_ports + port; if (port == smi->cpu_port) /* For the CPU port, make all ports members of this