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[209.132.180.67]) by mx.google.com with ESMTP id p33si6971536pld.231.2017.09.26.23.27.41; Tue, 26 Sep 2017 23:27:41 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=HCxp1vFr; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752054AbdI0G1i (ORCPT + 26 others); Wed, 27 Sep 2017 02:27:38 -0400 Received: from mail-pg0-f68.google.com ([74.125.83.68]:33702 "EHLO mail-pg0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751987AbdI0G1f (ORCPT ); Wed, 27 Sep 2017 02:27:35 -0400 Received: by mail-pg0-f68.google.com with SMTP id i130so8148213pgc.0; Tue, 26 Sep 2017 23:27:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=/+/QHvc++HsdjrbnyO0DLu4TMSKOFqsjOZSw9pvgbDI=; b=HCxp1vFrvHGIbrXSMJ6J3JV8KAyaoJMYwnxKtrUvRzAEf2V5noR3iwobAza/sEKbWA RodhzgP7mXcjerw/XXS2xVUwDuvlcQwZoQLUStSEj2mCXMLJrcU/HXw/wh7D04xmJo9Q VPPHNYWA7ZnIZ7POqUMm4iPouDUfOKnzc/hzht0xOlDzbGzX0BPyzjN/6vB7BIKoVjGA pwajBJndJp8aj6gZ1F302HBcuUtyBwysNu7OKyVrekPDHm/dom+PY2PV0rPi7AyGJcka w0S23WYZoJVM8zdhTbP9FPjLDXcj5tXTb7imIF3BJjDPzep7lK4dsPIEI8C0le8wGI1n O2hw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=/+/QHvc++HsdjrbnyO0DLu4TMSKOFqsjOZSw9pvgbDI=; b=HpB1OaSX3rL168idZt3lbbbBgUBgHSa7o8yroE9BcP5VcpXDYOfgQLRwBotUxAjD82 z1bZ/RrNjXjcaM8C58bOcxVSeIM8nxE+213F6Q6fSFvEevqfwgL0JOjxBtxDgdHro8ig z0TGAwvD9P9ot2E+3GSjNWIjGCL51dW9Xs3wmnxC2jjjmgQm7ekr6twXc7JPNNvoJWAX JfXoYHKHPYbb95ySwDH/GfMQy5SyD8JJQelAYJ1iNNmv83bfZoBXtsJvroIIVVBPZQLM UGIZwroS1ll7U3xNp3+r3OOqSX/MbG4L3zdK1sELkWYzn1UUJw+t0PhYQN38UYf1pi+n POgQ== X-Gm-Message-State: AHPjjUjYTDRVPzW9Tnnwlg9bdbG95ePb9HzNTIWoxzmb9ZDH8zvbA9po mUi+9wJ3SNhLpbewb0qJX2M= X-Google-Smtp-Source: AOwi7QASO96x87jkPnCMVBHOHf8friVyhqf6VY/KF0P0/bCqwhL9aDvPvI0COd1ckIAiNfUiai0hdw== X-Received: by 10.101.77.137 with SMTP id p9mr396627pgq.88.1506493654958; Tue, 26 Sep 2017 23:27:34 -0700 (PDT) Received: from aurora.jms.id.au ([203.0.153.9]) by smtp.gmail.com with ESMTPSA id s76sm19319787pfj.119.2017.09.26.23.27.28 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 26 Sep 2017 23:27:33 -0700 (PDT) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Wed, 27 Sep 2017 15:57:26 +0930 From: Joel Stanley To: Lee Jones , Michael Turquette , Stephen Boyd Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Andrew Jeffery , Benjamin Herrenschmidt , Jeremy Kerr , Rick Altherr , Ryan Chen , Arnd Bergmann Subject: [PATCH v3 1/5] clk: Add clock driver for ASPEED BMC SoCs Date: Wed, 27 Sep 2017 15:56:58 +0930 Message-Id: <20170927062702.11350-2-joel@jms.id.au> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170927062702.11350-1-joel@jms.id.au> References: <20170927062702.11350-1-joel@jms.id.au> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This adds the stub of a driver for the ASPEED SoCs. The clocks are defined and the static registration is set up. Signed-off-by: Joel Stanley --- v3: - use named initlisers for aspeed_gates table - fix clocks typo - Move ASPEED_NUM_CLKS to the bottom of the list - Put gates at the start of the list, so we can use them to initalise the aspeed_gates table - Add ASPEED_CLK_SELECTION_2 - Set parent of network MAC gates --- drivers/clk/Kconfig | 12 +++ drivers/clk/Makefile | 1 + drivers/clk/clk-aspeed.c | 155 +++++++++++++++++++++++++++++++ include/dt-bindings/clock/aspeed-clock.h | 42 +++++++++ 4 files changed, 210 insertions(+) create mode 100644 drivers/clk/clk-aspeed.c create mode 100644 include/dt-bindings/clock/aspeed-clock.h -- 2.14.1 diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 1c4e1aa6767e..9abe063ef8d2 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -142,6 +142,18 @@ config COMMON_CLK_GEMINI This driver supports the SoC clocks on the Cortina Systems Gemini platform, also known as SL3516 or CS3516. +config COMMON_CLK_ASPEED + bool "Clock driver for Aspeed BMC SoCs" + depends on ARCH_ASPEED || COMPILE_TEST + default ARCH_ASPEED + select MFD_SYSCON + select RESET_CONTROLLER + ---help--- + This driver supports the SoC clocks on the Aspeed BMC platforms. + + The G4 and G5 series, including the ast2400 and ast2500, are supported + by this driver. + config COMMON_CLK_S2MPS11 tristate "Clock driver for S2MPS1X/S5M8767 MFD" depends on MFD_SEC_CORE || COMPILE_TEST diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index c99f363826f0..575c68919d9b 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -26,6 +26,7 @@ obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o obj-$(CONFIG_COMMON_CLK_GEMINI) += clk-gemini.o +obj-$(CONFIG_COMMON_CLK_ASPEED) += clk-aspeed.o obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o obj-$(CONFIG_CLK_HSDK) += clk-hsdk-pll.o obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c new file mode 100644 index 000000000000..36b79a378f73 --- /dev/null +++ b/drivers/clk/clk-aspeed.c @@ -0,0 +1,155 @@ +/* + * Copyright 2017 IBM Corporation + * + * Joel Stanley + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#define pr_fmt(fmt) "clk-aspeed: " fmt + +#include +#include +#include +#include +#include +#include + +#include + +#define ASPEED_RESET_CTRL 0x04 +#define ASPEED_CLK_SELECTION 0x08 +#define ASPEED_CLK_STOP_CTRL 0x0c +#define ASPEED_MPLL_PARAM 0x20 +#define ASPEED_HPLL_PARAM 0x24 +#define ASPEED_MISC_CTRL 0x2c +#define ASPEED_STRAP 0x70 +#define ASPEED_CLK_SELECTION_2 0xd8 + +/* Keeps track of all clocks */ +static struct clk_hw_onecell_data *aspeed_clk_data; + +static void __iomem *scu_base; + +/** + * struct aspeed_gate_data - Aspeed gated clocks + * @clock_idx: bit used to gate this clock in the clock register + * @reset_idx: bit used to reset this IP in the reset register. -1 if no + * reset is required when enabling the clock + * @name: the clock name + * @parent_name: the name of the parent clock + * @flags: standard clock framework flags + */ +struct aspeed_gate_data { + u8 clock_idx; + s8 reset_idx; + const char *name; + const char *parent_name; + unsigned long flags; +}; + +/** + * struct aspeed_clk_gate - Aspeed specific clk_gate structure + * @hw: handle between common and hardware-specific interfaces + * @reg: register controlling gate + * @clock_idx: bit used to gate this clock in the clock register + * @reset_idx: bit used to reset this IP in the reset register. -1 if no + * reset is required when enabling the clock + * @flags: hardware-specific flags + * @lock: register lock + * + * Some of the clocks in the Aspeed SoC must be put in reset before enabling. + * This modified version of clk_gate allows an optional reset bit to be + * specified. + */ +struct aspeed_clk_gate { + struct clk_hw hw; + struct regmap *map; + u8 clock_idx; + s8 reset_idx; + u8 flags; + spinlock_t *lock; +}; + +#define to_aspeed_clk_gate(_hw) container_of(_hw, struct aspeed_clk_gate, hw) + +/* TODO: ask Aspeed about the actual parent data */ +static const struct aspeed_gate_data aspeed_gates[] __initconst = { + /* clk rst name parent flags */ + [ASPEED_CLK_GATE_ECLK] = { 0, -1, "eclk-gate", "eclk", 0 }, /* Video Engine */ + [ASPEED_CLK_GATE_GCLK] = { 1, 7, "gclk-gate", NULL, 0 }, /* 2D engine */ + [ASPEED_CLK_GATE_MCLK] = { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */ + [ASPEED_CLK_GATE_VCLK] = { 3, 6, "vclk-gate", NULL, 0 }, /* Video Capture */ + [ASPEED_CLK_GATE_BCLK] = { 4, 10, "bclk-gate", "bclk", 0 }, /* PCIe/PCI */ + [ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, 0 }, /* DAC */ + [ASPEED_CLK_GATE_REFCLK] = { 6, -1, "refclk-gate", "clkin", CLK_IS_CRITICAL }, + [ASPEED_CLK_GATE_USBPORT2CLK] = { 7, 3, "usb-port2-gate", NULL, 0 }, /* USB2.0 Host port 2 */ + [ASPEED_CLK_GATE_LCLK] = { 8, 5, "lclk-gate", NULL, 0 }, /* LPC */ + [ASPEED_CLK_GATE_USBUHCICLK] = { 9, 15, "usb-uhci-gate", NULL, 0 }, /* USB1.1 (requires port 2 enabled) */ + [ASPEED_CLK_GATE_D1CLK] = { 10, 13, "d1clk-gate", NULL, 0 }, /* GFX CRT */ + [ASPEED_CLK_GATE_YCLK] = { 13, 4, "yclk-gate", NULL, 0 }, /* HAC */ + [ASPEED_CLK_GATE_USBPORT1CLK] = { 14, 14, "usb-port1-gate", NULL, 0 }, /* USB2 hub/USB2 host port 1/USB1.1 dev */ + [ASPEED_CLK_GATE_UART1CLK] = { 15, -1, "uart1clk-gate", "uart", 0 }, /* UART1 */ + [ASPEED_CLK_GATE_UART2CLK] = { 16, -1, "uart2clk-gate", "uart", 0 }, /* UART2 */ + [ASPEED_CLK_GATE_UART5CLK] = { 17, -1, "uart5clk-gate", "uart", 0 }, /* UART5 */ + [ASPEED_CLK_GATE_ESPICLK] = { 19, -1, "espiclk-gate", NULL, 0 }, /* eSPI */ + [ASPEED_CLK_GATE_MAC1CLK] = { 20, 11, "mac1clk-gate", "mac", 0 }, /* MAC1 */ + [ASPEED_CLK_GATE_MAC2CLK] = { 21, 12, "mac2clk-gate", "mac", 0 }, /* MAC2 */ + [ASPEED_CLK_GATE_RSACLK] = { 24, -1, "rsaclk-gate", NULL, 0 }, /* RSA */ + [ASPEED_CLK_GATE_UART3CLK] = { 25, -1, "uart3clk-gate", "uart", 0 }, /* UART3 */ + [ASPEED_CLK_GATE_UART4CLK] = { 26, -1, "uart4clk-gate", "uart", 0 }, /* UART4 */ + [ASPEED_CLK_GATE_SDCLKCLK] = { 27, 16, "sdclk-gate", NULL, 0 }, /* SDIO/SD */ + [ASPEED_CLK_GATE_LHCCLK] = { 28, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */ +}; + +static void __init aspeed_cc_init(struct device_node *np) +{ + struct regmap *map; + u32 val; + int ret; + int i; + + scu_base = of_iomap(np, 0); + if (IS_ERR(scu_base)) + return; + + aspeed_clk_data = kzalloc(sizeof(*aspeed_clk_data) + + sizeof(*aspeed_clk_data->hws) * ASPEED_NUM_CLKS, + GFP_KERNEL); + if (!aspeed_clk_data) + return; + + /* + * This way all clocks fetched before the platform device probes, + * except those we assign here for early use, will be deferred. + */ + for (i = 0; i < ASPEED_NUM_CLKS; i++) + aspeed_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER); + + map = syscon_node_to_regmap(np); + if (IS_ERR(map)) { + pr_err("no syscon regmap\n"); + return; + } + /* + * We check that the regmap works on this very first access, + * but as this is an MMIO-backed regmap, subsequent regmap + * access is not going to fail and we skip error checks from + * this point. + */ + ret = regmap_read(map, ASPEED_STRAP, &val); + if (ret) { + pr_err("failed to read strapping register\n"); + return; + } + + aspeed_clk_data->num = ASPEED_NUM_CLKS; + ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_clk_data); + if (ret) + pr_err("failed to add DT provider: %d\n", ret); +}; +CLK_OF_DECLARE_DRIVER(aspeed_cc_g5, "aspeed,ast2500-scu", aspeed_cc_init); +CLK_OF_DECLARE_DRIVER(aspeed_cc_g4, "aspeed,ast2400-scu", aspeed_cc_init); diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h new file mode 100644 index 000000000000..4a99421d77c8 --- /dev/null +++ b/include/dt-bindings/clock/aspeed-clock.h @@ -0,0 +1,42 @@ +#ifndef DT_BINDINGS_ASPEED_CLOCK_H +#define DT_BINDINGS_ASPEED_CLOCK_H + +#define ASPEED_CLK_GATE_ECLK 0 +#define ASPEED_CLK_GATE_GCLK 1 +#define ASPEED_CLK_GATE_MCLK 2 +#define ASPEED_CLK_GATE_VCLK 3 +#define ASPEED_CLK_GATE_BCLK 4 +#define ASPEED_CLK_GATE_DCLK 5 +#define ASPEED_CLK_GATE_REFCLK 6 +#define ASPEED_CLK_GATE_USBPORT2CLK 7 +#define ASPEED_CLK_GATE_LCLK 8 +#define ASPEED_CLK_GATE_USBUHCICLK 9 +#define ASPEED_CLK_GATE_D1CLK 10 +#define ASPEED_CLK_GATE_YCLK 11 +#define ASPEED_CLK_GATE_USBPORT1CLK 12 +#define ASPEED_CLK_GATE_UART1CLK 13 +#define ASPEED_CLK_GATE_UART2CLK 14 +#define ASPEED_CLK_GATE_UART5CLK 15 +#define ASPEED_CLK_GATE_ESPICLK 16 +#define ASPEED_CLK_GATE_MAC1CLK 17 +#define ASPEED_CLK_GATE_MAC2CLK 18 +#define ASPEED_CLK_GATE_RSACLK 19 +#define ASPEED_CLK_GATE_UART3CLK 20 +#define ASPEED_CLK_GATE_UART4CLK 21 +#define ASPEED_CLK_GATE_SDCLKCLK 22 +#define ASPEED_CLK_GATE_LHCCLK 23 +#define ASPEED_CLK_HPLL 24 +#define ASPEED_CLK_AHB 25 +#define ASPEED_CLK_APB 26 +#define ASPEED_CLK_UART 27 +#define ASPEED_CLK_SDIO 28 +#define ASPEED_CLK_ECLK 29 +#define ASPEED_CLK_ECLK_MUX 30 +#define ASPEED_CLK_LHCLK 31 +#define ASPEED_CLK_MAC 32 +#define ASPEED_CLK_BCLK 33 +#define ASPEED_CLK_MPLL 34 + +#define ASPEED_NUM_CLKS 35 + +#endif From patchwork Wed Sep 27 06:26:59 2017 Content-Type: text/plain; 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[209.132.180.67]) by mx.google.com with ESMTP id p33si6971536pld.231.2017.09.26.23.27.49; Tue, 26 Sep 2017 23:27:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=YFIi9+O+; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752088AbdI0G1s (ORCPT + 26 others); Wed, 27 Sep 2017 02:27:48 -0400 Received: from mail-pf0-f193.google.com ([209.85.192.193]:38366 "EHLO mail-pf0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750805AbdI0G1p (ORCPT ); Wed, 27 Sep 2017 02:27:45 -0400 Received: by mail-pf0-f193.google.com with SMTP id a7so6001544pfj.5; Tue, 26 Sep 2017 23:27:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=7E/V83b8Xtyr0Zzys3yxvbZfJd5zamnBK7X22z3EPls=; b=YFIi9+O+4IN6U/xdbrRN9kILzWtvpz0VIXXf9YFS1J+SuOKCyIVdsMdkvMGUK3TGqY noaIGc0S3ouRU/4Tjgz8XlJkZLj4fMje5ETAtVM28u1tfRxq1FUtopTZrd2NNnYSR/Yc TrWn0FR0w90dFBw6bdUgba/wcoYWO241aUxQ5K+Kpoi5FFX4/KcVdCL3HYXLxWwdDxBE ImqDGAF6oZ+ZfNeGMAywkT2DLnO0EE+r8AYtsbHfGuANVyvv6lYH6EK/vuP/NmjCcSAL DQQvkWHiEGI+Fdpez5rwVUYwo2l05XbjXX7ehIP21WXUY/vgqo6eEtjSNFWitbN96v1F /PKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=7E/V83b8Xtyr0Zzys3yxvbZfJd5zamnBK7X22z3EPls=; b=kYIl1OarS9+JNhGFlqX5WMPL+E0kDAz9bvX31/B+Mkz1677Mw+CiZcd5VypVyz9tFO UiUHX8LdtIYoxDI6VJ07lI7cYxMkGvHSJd3+RboRqNmTPxB0jauC1pKPNwVvWC/ap0f4 shGQAiRMF8dZ1+L0slVhVhJbiKPkPLLg9WKhUNfQU5WoymqQN0h4Yhpsc65NmuX4XbLl XAHpfhvvvB7tcXiPU/mNprEVLl9cDR3WnNc6BEVUm9g/gQ9R2fmW4K0GSKbY9hWLS6EB qKeJEwu41hHWuVgu/xKlTbZ6JgTwTr+JZsFYED5xPlqT4oymk4Db8DXR5qhP3LOOLvYu 4sfg== X-Gm-Message-State: AHPjjUgaLbogwEDetDATuJN/rKjYF7Vq3398WRgLmguGBsfnt9XECPTV 7gm1b6MrYJpPYwQHkf0XGW8= X-Google-Smtp-Source: AOwi7QC+QUu95zX1hSZA/l9Ey5spLJ4bLTKBE1Bu04EB8TFnCOxm3MO5D2WGPdl/1CprtLUWbV3qug== X-Received: by 10.99.121.129 with SMTP id u123mr389020pgc.246.1506493664380; Tue, 26 Sep 2017 23:27:44 -0700 (PDT) Received: from aurora.jms.id.au ([203.0.153.9]) by smtp.gmail.com with ESMTPSA id q23sm18880446pfk.182.2017.09.26.23.27.38 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 26 Sep 2017 23:27:43 -0700 (PDT) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Wed, 27 Sep 2017 15:57:35 +0930 From: Joel Stanley To: Lee Jones , Michael Turquette , Stephen Boyd Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Andrew Jeffery , Benjamin Herrenschmidt , Jeremy Kerr , Rick Altherr , Ryan Chen , Arnd Bergmann Subject: [PATCH v3 2/5] clk: aspeed: Register core clocks Date: Wed, 27 Sep 2017 15:56:59 +0930 Message-Id: <20170927062702.11350-3-joel@jms.id.au> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170927062702.11350-1-joel@jms.id.au> References: <20170927062702.11350-1-joel@jms.id.au> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This registers the core clocks; those which are required to calculate the rate of the timer peripheral so the system can load a clocksource driver. Signed-off-by: Joel Stanley --- v3: - Fix ast2400 ahb calculation - Remove incorrect 'this is wrong' comment - Separate out clkin calc to be per platform - Support 48MHz clkin on ast2400 --- drivers/clk/clk-aspeed.c | 164 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 164 insertions(+) -- 2.14.1 diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c index 36b79a378f73..14387055554f 100644 --- a/drivers/clk/clk-aspeed.c +++ b/drivers/clk/clk-aspeed.c @@ -29,6 +29,9 @@ #define ASPEED_STRAP 0x70 #define ASPEED_CLK_SELECTION_2 0xd8 +/* Globally visible clocks */ +static DEFINE_SPINLOCK(aspeed_clk_lock); + /* Keeps track of all clocks */ static struct clk_hw_onecell_data *aspeed_clk_data; @@ -105,6 +108,160 @@ static const struct aspeed_gate_data aspeed_gates[] __initconst = { [ASPEED_CLK_GATE_LHCCLK] = { 28, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */ }; +static const struct clk_div_table ast2400_div_table[] = { + { 0x0, 2 }, + { 0x1, 4 }, + { 0x2, 6 }, + { 0x3, 8 }, + { 0x4, 10 }, + { 0x5, 12 }, + { 0x6, 14 }, + { 0x7, 16 }, + { 0 } +}; + +static const struct clk_div_table ast2500_div_table[] = { + { 0x0, 4 }, + { 0x1, 8 }, + { 0x2, 12 }, + { 0x3, 16 }, + { 0x4, 20 }, + { 0x5, 24 }, + { 0x6, 28 }, + { 0x7, 32 }, + { 0 } +}; + +static struct clk_hw *aspeed_ast2400_calc_pll(const char *name, u32 val) +{ + unsigned int mult, div; + + if (val & BIT(17)) { + /* Pass through mode */ + mult = div = 1; + } else { + /* F = 24Mhz * (2-OD) * [(N + 2) / (D + 1)] */ + u32 n = (val >> 5) & 0x3f; + u32 od = (val >> 4) & 0x1; + u32 d = val & 0xf; + + mult = (2 - od) * (n + 2); + div = d + 1; + } + return clk_hw_register_fixed_factor(NULL, name, "clkin", 0, + mult, div); +}; + +static struct clk_hw *aspeed_ast2500_calc_pll(const char *name, u32 val) +{ + unsigned int mult, div; + + if (val & BIT(20)) { + /* Pass through mode */ + mult = div = 1; + } else { + /* F = clkin * [(M+1) / (N+1)] / (P + 1) */ + u32 p = (val >> 13) & 0x3f; + u32 m = (val >> 5) & 0xff; + u32 n = val & 0x1f; + + mult = (m + 1) / (n + 1); + div = p + 1; + } + + return clk_hw_register_fixed_factor(NULL, name, "clkin", 0, + mult, div); +} + +static void __init aspeed_ast2400_cc(struct regmap *map) +{ + struct clk_hw *hw; + u32 val, freq, div; + + /* + * CLKIN is the crystal oscillator, 24, 48 or 25MHz selected by + * strapping + */ + regmap_read(map, ASPEED_STRAP, &val); + if (val & BIT(23)) + freq = 25000000; + else if (val & BIT(18)) + freq = 48000000; + else + freq = 24000000; + hw = clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, freq); + pr_debug("clkin @%u MHz\n", freq / 1000000); + + /* + * High-speed PLL clock derived from the crystal. This the CPU clock, + * and we assume that it is enabled + */ + regmap_read(map, ASPEED_HPLL_PARAM, &val); + WARN(val & BIT(18), "hpll is strapped not configured"); + aspeed_clk_data->hws[ASPEED_CLK_HPLL] = aspeed_ast2400_calc_pll("hpll", val); + + /* + * Strap bits 11:10 define the CPU/AHB clock frequency ratio (aka HCLK) + * 00: Select CPU:AHB = 1:1 + * 01: Select CPU:AHB = 2:1 + * 10: Select CPU:AHB = 4:1 + * 11: Select CPU:AHB = 3:1 + */ + regmap_read(map, ASPEED_STRAP, &val); + val = (val >> 10) & 0x3; + div = val + 1; + if (div == 3) + div = 4; + else if (div == 4) + div = 3; + hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, div); + aspeed_clk_data->hws[ASPEED_CLK_AHB] = hw; + + /* APB clock clock selection register SCU08 (aka PCLK) */ + hw = clk_hw_register_divider_table(NULL, "apb", "hpll", 0, + scu_base + ASPEED_CLK_SELECTION, 23, 3, 0, + ast2400_div_table, + &aspeed_clk_lock); + aspeed_clk_data->hws[ASPEED_CLK_APB] = hw; +} + +static void __init aspeed_ast2500_cc(struct regmap *map) +{ + struct clk_hw *hw; + u32 val, freq, div; + + /* CLKIN is the crystal oscillator, 24 or 25MHz selected by strapping */ + regmap_read(map, ASPEED_STRAP, &val); + if (val & BIT(23)) + freq = 25000000; + else + freq = 24000000; + hw = clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, freq); + pr_debug("clkin @%u MHz\n", freq / 1000000); + + /* + * High-speed PLL clock derived from the crystal. This the CPU clock, + * and we assume that it is enabled + */ + regmap_read(map, ASPEED_HPLL_PARAM, &val); + aspeed_clk_data->hws[ASPEED_CLK_HPLL] = aspeed_ast2500_calc_pll("hpll", val); + + /* Strap bits 11:9 define the AXI/AHB clock frequency ratio (aka HCLK)*/ + regmap_read(map, ASPEED_STRAP, &val); + val = (val >> 9) & 0x7; + WARN(val == 0, "strapping is zero: cannot determine ahb clock"); + div = 2 * (val + 1); + hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, div); + aspeed_clk_data->hws[ASPEED_CLK_AHB] = hw; + + /* APB clock clock selection register SCU08 (aka PCLK) */ + regmap_read(map, ASPEED_CLK_SELECTION, &val); + val = (val >> 23) & 0x7; + div = 4 * (val + 1); + hw = clk_hw_register_fixed_factor(NULL, "apb", "hpll", 0, 1, div); + aspeed_clk_data->hws[ASPEED_CLK_APB] = hw; +}; + static void __init aspeed_cc_init(struct device_node *np) { struct regmap *map; @@ -146,6 +303,13 @@ static void __init aspeed_cc_init(struct device_node *np) return; } + if (of_device_is_compatible(np, "aspeed,ast2400-scu")) + aspeed_ast2400_cc(map); + else if (of_device_is_compatible(np, "aspeed,ast2500-scu")) + aspeed_ast2500_cc(map); + else + pr_err("unknown platform, failed to add clocks\n"); + aspeed_clk_data->num = ASPEED_NUM_CLKS; ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_clk_data); if (ret) From patchwork Wed Sep 27 06:27:00 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 114350 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp4673865qgf; Tue, 26 Sep 2017 23:28:00 -0700 (PDT) X-Received: by 10.99.149.24 with SMTP id p24mr374636pgd.406.1506493680857; Tue, 26 Sep 2017 23:28:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506493680; cv=none; d=google.com; s=arc-20160816; b=gvBuaRXLdT+tbHwtHL7Qe9AYksoUDeQaIbCEyqWFpQiDOjRwAApMb3uZh5whJZ85C8 s+hREmVQxxynsQmRHidFjhja2LRiobIRYd6llg5nBQH3S6k/li2CEIYstOBEIsgL4Wwv EGxt7eaHT0/LeyrYKtnJEA1Oib7Mr8bUYCtfxz2TgKY/fwPC3ar1C9/RutNYIgZpGOqa FJO+SUdq+kXdH50bQuSJB656+6d4+FtpcJ9bQt2yC4x73cObYwR3et+zZZJARIxR3SYm VygLwCpqhOTL3jcd5DFvJdRHZ07u+X5U6tSd3ma/+iHwuA+rc+PKlEYjgyNMdKocjox2 faag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=BPULn7yKIJDVGVtQFe5shA3XgLvVoAxeDDXnIyJxITA=; b=lr5PoNschxYQOzmdN92Z51sxoYiBz6O7mn+f5ZtZARSPdenrw8iswxaU0OSTiXdRDV /V3j2z0VIiZosX7LAMcRQP1Gf6a1C13j6CbuePdpqnmyFB9+YfrDJIBWvd0qOeWTr9/J wpCh/m8WsoqU6SlPX784EMUHFVuESVbA3jM5eVI32c0P5K3KbZSxWQzo2lMEMiO7c3bx NpiRU1Wn2eOAc2voSv6yLcmMDw83fTSHbfBdmLD2ozn5vHF0YWsUl/DAK3EpehMKzwuN 3jHFkOh3DduIXjJVtxAkTIEPic/qDBBsJPeXouMblpHbeXFMc1Xiqqji3lWOgM1RYEXz WZ4w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=LRV36CLf; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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The clocks that have configurable rates are now registered. Signed-off-by: Joel Stanley -- v3: - Fix bclk and eclk calculation - Seperate out ast2400 and ast25000 for pll calculation Signed-off-by: Joel Stanley --- drivers/clk/clk-aspeed.c | 127 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 127 insertions(+) -- 2.14.1 diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c index 14387055554f..e43016ea82cd 100644 --- a/drivers/clk/clk-aspeed.c +++ b/drivers/clk/clk-aspeed.c @@ -14,6 +14,8 @@ #include #include #include +#include +#include #include #include #include @@ -108,6 +110,20 @@ static const struct aspeed_gate_data aspeed_gates[] __initconst = { [ASPEED_CLK_GATE_LHCCLK] = { 28, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */ }; +static const char * const eclk_parents[] = {"d1pll", "hpll", "mpll"}; + +static const struct clk_div_table ast2500_mac_div_table[] = { + { 0x0, 4 }, /* Yep, really. Aspeed confirmed this is correct */ + { 0x1, 4 }, + { 0x2, 6 }, + { 0x3, 8 }, + { 0x4, 10 }, + { 0x5, 12 }, + { 0x6, 14 }, + { 0x7, 16 }, + { 0 } +}; + static const struct clk_div_table ast2400_div_table[] = { { 0x0, 2 }, { 0x1, 4 }, @@ -173,6 +189,117 @@ static struct clk_hw *aspeed_ast2500_calc_pll(const char *name, u32 val) mult, div); } +struct aspeed_clk_soc_data { + const struct clk_div_table *div_table; + const struct clk_div_table *mac_div_table; + struct clk_hw *(*calc_pll)(const char *name, u32 val); +}; + +static const struct aspeed_clk_soc_data ast2500_data = { + .div_table = ast2500_div_table, + .mac_div_table = ast2500_mac_div_table, + .calc_pll = aspeed_ast2500_calc_pll, +}; + +static const struct aspeed_clk_soc_data ast2400_data = { + .div_table = ast2400_div_table, + .mac_div_table = ast2400_div_table, + .calc_pll = aspeed_ast2400_calc_pll, +}; + +static int __init aspeed_clk_probe(struct platform_device *pdev) +{ + const struct aspeed_clk_soc_data *soc_data; + struct device *dev = &pdev->dev; + struct regmap *map; + struct clk_hw *hw; + u32 val, rate; + + map = syscon_node_to_regmap(dev->of_node); + if (IS_ERR(map)) { + dev_err(dev, "no syscon regmap\n"); + return PTR_ERR(map); + } + + /* SoC generations share common layouts but have different divisors */ + soc_data = of_device_get_match_data(&pdev->dev); + + /* UART clock div13 setting */ + regmap_read(map, ASPEED_MISC_CTRL, &val); + if (val & BIT(12)) + rate = 24000000 / 13; + else + rate = 24000000; + /* TODO: Find the parent data for the uart clock */ + hw = clk_hw_register_fixed_rate(NULL, "uart", NULL, 0, rate); + aspeed_clk_data->hws[ASPEED_CLK_UART] = hw; + + /* + * Memory controller (M-PLL) PLL. This clock is configured by the + * bootloader, and is exposed to Linux as a read-only clock rate. + */ + regmap_read(map, ASPEED_MPLL_PARAM, &val); + aspeed_clk_data->hws[ASPEED_CLK_MPLL] = soc_data->calc_pll("mpll", val); + + /* SD/SDIO clock divider (TODO: There's a gate too) */ + hw = clk_hw_register_divider_table(NULL, "sdio", "hpll", 0, + scu_base + ASPEED_CLK_SELECTION, 12, 3, 0, + soc_data->div_table, + &aspeed_clk_lock); + aspeed_clk_data->hws[ASPEED_CLK_SDIO] = hw; + + /* MAC AHB bus clock divider */ + hw = clk_hw_register_divider_table(NULL, "mac", "hpll", 0, + scu_base + ASPEED_CLK_SELECTION, 16, 3, 0, + soc_data->mac_div_table, + &aspeed_clk_lock); + aspeed_clk_data->hws[ASPEED_CLK_MAC] = hw; + + /* LPC Host (LHCLK) clock divider */ + hw = clk_hw_register_divider_table(NULL, "lhclk", "hpll", 0, + scu_base + ASPEED_CLK_SELECTION, 20, 3, 0, + soc_data->div_table, + &aspeed_clk_lock); + aspeed_clk_data->hws[ASPEED_CLK_LHCLK] = hw; + + /* Video Engine (ECLK) mux and clock divider */ + hw = clk_hw_register_mux(NULL, "eclk_mux", + eclk_parents, ARRAY_SIZE(eclk_parents), 0, + scu_base + ASPEED_CLK_SELECTION, 2, 2, + 0, &aspeed_clk_lock); + aspeed_clk_data->hws[ASPEED_CLK_ECLK_MUX] = hw; + hw = clk_hw_register_divider_table(NULL, "eclk", "eclk_mux", 0, + scu_base + ASPEED_CLK_SELECTION, 28, 3, 0, + soc_data->div_table, + &aspeed_clk_lock); + aspeed_clk_data->hws[ASPEED_CLK_ECLK] = hw; + + /* P-Bus (BCLK) clock divider */ + hw = clk_hw_register_divider_table(NULL, "bclk", "hpll", 0, + scu_base + ASPEED_CLK_SELECTION_2, 0, 2, 0, + soc_data->div_table, + &aspeed_clk_lock); + aspeed_clk_data->hws[ASPEED_CLK_BCLK] = hw; + + return 0; +}; + +static const struct of_device_id aspeed_clk_dt_ids[] = { + { .compatible = "aspeed,ast2400-scu", .data = &ast2400_data }, + { .compatible = "aspeed,ast2500-scu", .data = &ast2500_data }, + { }, +}; + +static struct platform_driver aspeed_clk_driver = { + .probe = aspeed_clk_probe, + .driver = { + .name = "aspeed-clk", + .of_match_table = aspeed_clk_dt_ids, + .suppress_bind_attrs = true, + }, +}; +builtin_platform_driver(aspeed_clk_driver); + static void __init aspeed_ast2400_cc(struct regmap *map) { struct clk_hw *hw; From patchwork Wed Sep 27 06:27:01 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 114351 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp4673967qgf; Tue, 26 Sep 2017 23:28:09 -0700 (PDT) X-Received: by 10.84.244.6 with SMTP id g6mr346354pll.223.1506493689249; Tue, 26 Sep 2017 23:28:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506493689; cv=none; d=google.com; s=arc-20160816; b=KssrrWk7lBfjs7uY6n27leQxuhLt6b0R45ZXbKZG/9Jv4ifhvmWAEsP5QEDddk+L+W 36vMu2xNdDSAiTv9k4fRIE5Xnzyn8nHCeNj6NYQk70tJq+unl/fZWyO7UiNsUgJgnvE8 ClauNMgC2XiHlEES5h/BXrKhupRleV3uzQyuN4NLDQpbdg9/Es6fJX1EOq1EstxB9ZcP x4uuD9njde8FAHqioTU/9JM06qlFKt+W0ey4hNJKAr/wXf1fgT+mVpvUTSvEJE2I+hfo oUxI01Yx2mulbDXAzQw4lR2xhLQeGNvvb1vu2UYuwayLwHlYX/13UzaS4sI3uMpjK4WK iYGg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=G5XTmFmLjm8m02fUeC0jL1eiDTE1nYAhHWdOxGxhi3s=; b=UhzpvRPXJFnFXROeKe5a0lJuCI03CAMmRcPuoF0lCwV8Q678RYRNV3JW621AR88S8p ltymTILuQ+auN3BiL5DBgVwQWuUK3501+0jGJ1WyhQYH2mTMBlSg5HvnhxpM8OAPhIvX 8hYQ03KoG80EZipw/kb+HRL3zZTTis5xcAMrGaaZXY8sZx0w6E+5Jus4e5z3xPC3uXRI A47glatl6Y0mllhxqAlZ6HFOyPTeiCp+57vG50Lvz2bYWt5FMU3uBTW2y2XSImnplT2F 16guM8OWD/x8K2owPOpZ1mBW7qOJOKQjLSXdOWSONxVlXqusD9nbkbN9TYpqkkVvDQ5c NTOw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=Nd1oq+ax; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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This borrows from clk_hw_register_gate, but registers two 'gates', one to control the clock enable register and the other to control the reset IP. This allows us to enforce the ordering: 1. Place IP in reset 2. Enable clock 3. Delay 4. Release reset There are some gates that do not have an associated reset; these are handled by using -1 as the index for the reset. Signed-off-by: Joel Stanley --- V3: - Remove gates offset as gates are now at the start of the list --- drivers/clk/clk-aspeed.c | 128 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 128 insertions(+) -- 2.14.1 diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c index e43016ea82cd..42a69839d86e 100644 --- a/drivers/clk/clk-aspeed.c +++ b/drivers/clk/clk-aspeed.c @@ -207,6 +207,108 @@ static const struct aspeed_clk_soc_data ast2400_data = { .calc_pll = aspeed_ast2400_calc_pll, }; +static int aspeed_clk_enable(struct clk_hw *hw) +{ + struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw); + unsigned long flags; + u32 clk = BIT(gate->clock_idx); + u32 rst = BIT(gate->reset_idx); + + spin_lock_irqsave(gate->lock, flags); + + if (gate->reset_idx >= 0) { + /* Put IP in reset */ + regmap_update_bits(gate->map, ASPEED_RESET_CTRL, rst, rst); + + /* Delay 100us */ + udelay(100); + } + + /* Enable clock */ + regmap_update_bits(gate->map, ASPEED_CLK_STOP_CTRL, clk, 0); + + if (gate->reset_idx >= 0) { + /* Delay 10ms */ + /* TODO: can we sleep here? */ + msleep(10); + + /* Take IP out of reset */ + regmap_update_bits(gate->map, ASPEED_RESET_CTRL, rst, 0); + } + + spin_unlock_irqrestore(gate->lock, flags); + + return 0; +} + +static void aspeed_clk_disable(struct clk_hw *hw) +{ + struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw); + unsigned long flags; + u32 clk = BIT(gate->clock_idx); + + spin_lock_irqsave(gate->lock, flags); + + /* Disable clock */ + regmap_update_bits(gate->map, ASPEED_CLK_STOP_CTRL, clk, clk); + + spin_unlock_irqrestore(gate->lock, flags); +} + +static int aspeed_clk_is_enabled(struct clk_hw *hw) +{ + struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw); + u32 clk = BIT(gate->clock_idx); + u32 reg; + + regmap_read(gate->map, ASPEED_CLK_STOP_CTRL, ®); + + return (reg & clk) ? 0 : 1; +} + +static const struct clk_ops aspeed_clk_gate_ops = { + .enable = aspeed_clk_enable, + .disable = aspeed_clk_disable, + .is_enabled = aspeed_clk_is_enabled, +}; + +static struct clk_hw *aspeed_clk_hw_register_gate(struct device *dev, + const char *name, const char *parent_name, unsigned long flags, + struct regmap *map, u8 clock_idx, u8 reset_idx, + u8 clk_gate_flags, spinlock_t *lock) +{ + struct aspeed_clk_gate *gate; + struct clk_init_data init; + struct clk_hw *hw; + int ret; + + gate = kzalloc(sizeof(*gate), GFP_KERNEL); + if (!gate) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.ops = &aspeed_clk_gate_ops; + init.flags = flags | CLK_IS_BASIC; + init.parent_names = parent_name ? &parent_name : NULL; + init.num_parents = parent_name ? 1 : 0; + + gate->map = map; + gate->clock_idx = clock_idx; + gate->reset_idx = reset_idx; + gate->flags = clk_gate_flags; + gate->lock = lock; + gate->hw.init = &init; + + hw = &gate->hw; + ret = clk_hw_register(dev, hw); + if (ret) { + kfree(gate); + hw = ERR_PTR(ret); + } + + return hw; +} + static int __init aspeed_clk_probe(struct platform_device *pdev) { const struct aspeed_clk_soc_data *soc_data; @@ -214,6 +316,7 @@ static int __init aspeed_clk_probe(struct platform_device *pdev) struct regmap *map; struct clk_hw *hw; u32 val, rate; + int i; map = syscon_node_to_regmap(dev->of_node); if (IS_ERR(map)) { @@ -281,6 +384,31 @@ static int __init aspeed_clk_probe(struct platform_device *pdev) &aspeed_clk_lock); aspeed_clk_data->hws[ASPEED_CLK_BCLK] = hw; + /* There are a number of clocks that not included in this driver as + * more information is required: + * D2-PLL + * D-PLL + * YCLK + * RGMII + * RMII + * UART[1..5] clock source mux + */ + + for (i = 0; i < ARRAY_SIZE(aspeed_gates); i++) { + const struct aspeed_gate_data *gd; + + gd = &aspeed_gates[i]; + aspeed_clk_data->hws[i] = aspeed_clk_hw_register_gate(NULL, + gd->name, + gd->parent_name, + gd->flags, + map, + gd->clock_idx, + gd->reset_idx, + CLK_GATE_SET_TO_DISABLE, + &aspeed_clk_lock); + } + return 0; }; From patchwork Wed Sep 27 06:27:02 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 114352 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp4674063qgf; Tue, 26 Sep 2017 23:28:18 -0700 (PDT) X-Received: by 10.99.109.71 with SMTP id i68mr384142pgc.252.1506493698892; Tue, 26 Sep 2017 23:28:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506493698; cv=none; d=google.com; s=arc-20160816; b=ZSba4F2D4hv3xpSpvitmxPBo2yf7Lf+fhFn4IeWapq5y/eaW7c3YkEt6IJa271LonW xpQepecPLiXnt8qD5WRBLyjA8fd3Nn0A3zu8TAsjTLObtb6vs02plwwJ/J2cnRaMJ0kN 4Na29QA6mo4OarZXT842bAyLV/DKTOtPaBw7JF70E2IlSGG4m9/JrQyzu6AkyG7E8yNi AoHf1nBXAIp++0/NrwJDiXOoFBtKeR2HX1jzMEskrxNhbyeauXdlhWVWHuNXhTLC9tEe FFTNlwYQVtEr9bu1EbsiSrRuIdT9ApUbzjaBULUuFAhisxgou0Ov7HFHbtWHUc4/k297 wdtg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=tabUEba9bihTTYuienB300wIGl8uqcC+QFp6tat38BY=; b=Y4KeDRcfThif7ogumFOYffHEeGhq6zEvpAt//UAqWkA++5WOQb9KDP5vFad8CWqOWq TmXOfjKX7eHq5Cs05IDQd1boxOCACVhYsfTfyQ8uFeyb7sE5bwzVcdSBd8l42LHG2ECE WW8U/18hjC+iN7SwkFi6GM34KYwOtxiG84pDh5kivy+QkJRdehSwrOC+nZi9xY68GLI0 bEKrHxWd5Fp80cM6hCVT4R0HrMUgagMXNAozC811zQy24rWXdQlCiqHOUelqevI9whmK vFAhnFitwYBokYlPG39JoPMHc+bNwBmK1kKfgIpiy+PqGE5pToLagRFm66p5j6grMVGf Nt0g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=GcnMaiT1; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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These are represented by a reset controller. Signed-off-by: Joel Stanley --- v3: - Add named initalisers for the reset defines - Add define for ADC --- drivers/clk/clk-aspeed.c | 82 +++++++++++++++++++++++++++++++- include/dt-bindings/clock/aspeed-clock.h | 10 ++++ 2 files changed, 91 insertions(+), 1 deletion(-) -- 2.14.1 diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c index 42a69839d86e..4b08ad3b7960 100644 --- a/drivers/clk/clk-aspeed.c +++ b/drivers/clk/clk-aspeed.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include @@ -272,6 +273,68 @@ static const struct clk_ops aspeed_clk_gate_ops = { .is_enabled = aspeed_clk_is_enabled, }; +/** + * struct aspeed_reset - Aspeed reset controller + * @map: regmap to access the containing system controller + * @rcdev: reset controller device + */ +struct aspeed_reset { + struct regmap *map; + struct reset_controller_dev rcdev; +}; + +#define to_aspeed_reset(p) container_of((p), struct aspeed_reset, rcdev) + +static const u8 aspeed_resets[] = { + [ASPEED_RESET_XDMA] = 25, + [ASPEED_RESET_MCTP] = 24, + [ASPEED_RESET_ADC] = 23, + [ASPEED_RESET_JTAG_MASTER] = 22, + [ASPEED_RESET_MIC] = 18, + [ASPEED_RESET_PWM] = 9, + [ASPEED_RESET_PCIVGA] = 8, + [ASPEED_RESET_I2C] = 2, + [ASPEED_RESET_AHB] = 1, +}; + +static int aspeed_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct aspeed_reset *ar = to_aspeed_reset(rcdev); + u32 rst = BIT(aspeed_resets[id]); + + return regmap_update_bits(ar->map, ASPEED_RESET_CTRL, rst, 0); +} + +static int aspeed_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct aspeed_reset *ar = to_aspeed_reset(rcdev); + u32 rst = BIT(aspeed_resets[id]); + + return regmap_update_bits(ar->map, ASPEED_RESET_CTRL, rst, rst); +} + +static int aspeed_reset_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct aspeed_reset *ar = to_aspeed_reset(rcdev); + u32 val, rst = BIT(aspeed_resets[id]); + int ret; + + ret = regmap_read(ar->map, ASPEED_RESET_CTRL, &val); + if (ret) + return ret; + + return !!(val & rst); +} + +static const struct reset_control_ops aspeed_reset_ops = { + .assert = aspeed_reset_assert, + .deassert = aspeed_reset_deassert, + .status = aspeed_reset_status, +}; + static struct clk_hw *aspeed_clk_hw_register_gate(struct device *dev, const char *name, const char *parent_name, unsigned long flags, struct regmap *map, u8 clock_idx, u8 reset_idx, @@ -313,10 +376,11 @@ static int __init aspeed_clk_probe(struct platform_device *pdev) { const struct aspeed_clk_soc_data *soc_data; struct device *dev = &pdev->dev; + struct aspeed_reset *ar; struct regmap *map; struct clk_hw *hw; u32 val, rate; - int i; + int i, ret; map = syscon_node_to_regmap(dev->of_node); if (IS_ERR(map)) { @@ -324,6 +388,22 @@ static int __init aspeed_clk_probe(struct platform_device *pdev) return PTR_ERR(map); } + ar = devm_kzalloc(dev, sizeof(*ar), GFP_KERNEL); + if (!ar) + return -ENOMEM; + + ar->map = map; + ar->rcdev.owner = THIS_MODULE; + ar->rcdev.nr_resets = ARRAY_SIZE(aspeed_resets); + ar->rcdev.ops = &aspeed_reset_ops; + ar->rcdev.of_node = dev->of_node; + + ret = devm_reset_controller_register(dev, &ar->rcdev); + if (ret) { + dev_err(dev, "could not register reset controller\n"); + return ret; + } + /* SoC generations share common layouts but have different divisors */ soc_data = of_device_get_match_data(&pdev->dev); diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h index 4a99421d77c8..8e19646d8025 100644 --- a/include/dt-bindings/clock/aspeed-clock.h +++ b/include/dt-bindings/clock/aspeed-clock.h @@ -39,4 +39,14 @@ #define ASPEED_NUM_CLKS 35 +#define ASPEED_RESET_XDMA 0 +#define ASPEED_RESET_MCTP 1 +#define ASPEED_RESET_ADC 2 +#define ASPEED_RESET_JTAG_MASTER 3 +#define ASPEED_RESET_MIC 4 +#define ASPEED_RESET_PWM 5 +#define ASPEED_RESET_PCIVGA 6 +#define ASPEED_RESET_I2C 7 +#define ASPEED_RESET_AHB 8 + #endif