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Add Drivers/SasPlatform; 2. Add Drivers/Net/SnpPlatform; Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Signed-off-by: Heyi Guo Reviewed-by: Leif Lindholm --- Platform/Hisilicon/D05/D05.dsc | 5 ----- Platform/Hisilicon/D05/D05.fdf | 4 +++- 2 files changed, 3 insertions(+), 6 deletions(-) -- 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc index 3cdb1b1..7cd5758 100644 --- a/Platform/Hisilicon/D05/D05.dsc +++ b/Platform/Hisilicon/D05/D05.dsc @@ -538,11 +538,6 @@ Platform/Hisilicon/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.inf - # - #network - # - Platform/Hisilicon/D05/Drivers/Net/SnpPV660Dxe/SnpPV600Dxe.inf - MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf index b6d0e42..a5e6546 100644 --- a/Platform/Hisilicon/D05/D05.fdf +++ b/Platform/Hisilicon/D05/D05.fdf @@ -247,7 +247,8 @@ READ_LOCK_STATUS = TRUE #Network # - INF Platform/Hisilicon/D05/Drivers/Net/SnpPV660Dxe/SnpPV600Dxe.inf + INF Platform/Hisilicon/D05/Drivers/Net/SnpPlatform/SnpPlatform.inf + INF Platform/Hisilicon/D05/Drivers/Net/SnpPV600Dxe/SnpPV600Dxe.inf INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf @@ -292,6 +293,7 @@ READ_LOCK_STATUS = TRUE # INF Platform/Hisilicon/D05/Drivers/Sm750Dxe/UefiSmi.inf INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + INF Platform/Hisilicon/D05/Drivers/SasPlatform/SasPlatform.inf INF Platform/Hisilicon/D05/Drivers/Sas/SasDxeDriver.inf # From patchwork Fri Sep 29 03:19:41 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 114477 Delivered-To: patch@linaro.org Received: by 10.140.104.133 with SMTP id a5csp312142qgf; Thu, 28 Sep 2017 20:26:54 -0700 (PDT) X-Received: by 10.98.61.156 with SMTP id x28mr6104166pfj.295.1506655614285; Thu, 28 Sep 2017 20:26:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506655614; cv=none; d=google.com; s=arc-20160816; b=0ysXKY5asw6qQDL/bDVm/1uSZ7d5ZXB0hOejHN3mVQ3Uo53klvnouzfQLuhclmslUF rp9IAQ/rBNfRTemYzWfHeLeN/7U8H+ajGWUE395urnvJOj3j4wYMVI19BLeMJgCb85zi US/orZKjqhBBbiK+xarxdxdIxYWe90SD2yOhwg6CulSDjg4afnib6PXnQOQPCBC0vaaP c+GA3f9u028wHnep8iwR+Zj5ma51bq9eP47uxt0iZfOsE/G7rAc5tVeJiwbpzWsvDuyZ 7+fFm5tXPxv0OxWKQ0+NR0f1AmyBYm18jd3RnnDMkYkt/Gsh1c3GTirkk5KzQ6KFpPz4 ZTvQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=TqbDyXK0JOZXOSfLYZUqtM7AnRjyNPpRULhcIR07raE=; b=UU8Sb0llVqlljOHASWPlVJz141HlB1ayahou0bmtMkz66kvnEaGAUivBP6Jpb+WAul k9zdm+aZ4pVfB50EDgQO6KfrXRVt6i04oRqK+ysJrEvHtIigGh86JFSnxg6jzlobxz6g bY5dWcGtX5IOXM1G85VGaEzXaRK4jdbd5d0o4v2BCZUkAQq+fDpM1dscfI/q++4PyOHX B8Hsh6UmYnvczgH6vpDWwrkS0QZe4WTLBxDcOe6VixEpGoC3mP6pOTmy7C0IprCOhApC loMK++cWrNPlRVrTBkaNDmm7OtANbisnczmZqL/EXOEeYM2VMl2HPkhuto/5tzv6acRq Gk/g== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=XVRD/dvX; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. 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Add Drivers/SasPlatform; 2. Add Drivers/Net/SnpPlatform; Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Signed-off-by: Heyi Guo --- Platform/Hisilicon/D03/D03.dsc | 5 ----- Platform/Hisilicon/D03/D03.fdf | 4 +++- 2 files changed, 3 insertions(+), 6 deletions(-) -- 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/Hisilicon/D03/D03.dsc b/Platform/Hisilicon/D03/D03.dsc index afea162..7e25ffb 100644 --- a/Platform/Hisilicon/D03/D03.dsc +++ b/Platform/Hisilicon/D03/D03.dsc @@ -418,11 +418,6 @@ Platform/Hisilicon/D03/Drivers/Ipmi/ipmiInterfaceDxe/IpmiInterfaceDxe.inf - # - #network - # - Platform/Hisilicon/D03/Drivers/Net/SnpPV660Dxe/SnpPV600Dxe.inf - MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf diff --git a/Platform/Hisilicon/D03/D03.fdf b/Platform/Hisilicon/D03/D03.fdf index b62b908..37a7e28 100644 --- a/Platform/Hisilicon/D03/D03.fdf +++ b/Platform/Hisilicon/D03/D03.fdf @@ -242,7 +242,8 @@ READ_LOCK_STATUS = TRUE #Network # - INF Platform/Hisilicon/D03/Drivers/Net/SnpPV660Dxe/SnpPV600Dxe.inf + INF Platform/Hisilicon/D03/Drivers/Net/SnpPlatform/SnpPlatform.inf + INF Platform/Hisilicon/D03/Drivers/Net/SnpPV600Dxe/SnpPV600Dxe.inf INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf @@ -271,6 +272,7 @@ READ_LOCK_STATUS = TRUE # INF Platform/Hisilicon/D03/Drivers/Sm750Dxe/UefiSmi.inf + INF Platform/Hisilicon/D03/Drivers/SasPlatform/SasPlatform.inf INF Platform/Hisilicon/D03/Drivers/Sas/SasDxeDriver.inf # From patchwork Fri Sep 29 03:19:42 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 114478 Delivered-To: patch@linaro.org Received: by 10.140.104.133 with SMTP id a5csp312183qgf; Thu, 28 Sep 2017 20:26:58 -0700 (PDT) X-Received: by 10.84.253.131 with SMTP id a3mr5709814plm.244.1506655618362; Thu, 28 Sep 2017 20:26:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506655618; cv=none; d=google.com; s=arc-20160816; b=ZyQmogGwf9qxIW4biX8/kkZQcoCFV2/2ZsKPX7rcYgQuMN7CX3StLpA9XYnw8+Cocy YsN3qzMowLJVoYNVzO+/OFJ7i/YkLQJvgpQkZXsZYKXrxzW9OBPdQwVKoxFtZ/N4an5y BruX8GRZI5y17FmPEj4g7ZDBZMfvy8Z4h4MOQzF6ITslhx+61a8ETjFhICsc6vHf32Ln 6XBPG4UqaKCY4Ph/15TtAFZdQG8jkMR3nfHuc7xSKIZHvx2PGZ6RspBKd1l1jIVlHS/f KmlCWz4rc/AKIXYEsqUjJoGHKrd+iVFNEHhrn0w4IQ7hf6CbjnZ4kOe2x1IwFogDwP4A Yy9g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=/t60J+0+5uPNhNfvx92mkOCPis00e4dfuAHXKCtiFAE=; b=kM+lsbSo5Etn1+WAwkpyBjSN6r7fdz2xRrH7EnE9QQNSzBRqyF2OmKEB5LDp+HQMJW ddcIdzMbFDxVyu6HdzbpXCsVl9qUpXWrH6Kp5JupozEA0xQ3ktiHSnbaahlnMWnXj5Fm yKYX+8wK4ABI453lHDibtnvs49np60UFNGOsuNiSpFxAdgaotGVsYhmtsqKp948eegZk qLw6Phr6Xf5062Kg7yxQuMMKavhi/hxI6a6rrBqCO/QtIAyg95ILcMyHmlAdtYBTIx5/ Q+i91nFS461dFWSDpWZS5SMVZchf8HDwvPYzzopfOV5gdneAyxJ+rwTZ+mxg/zvP8gfF J+6A== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=fW+WCIRW; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [198.145.21.10]) by mx.google.com with ESMTPS id o30si2510371pli.229.2017.09.28.20.26.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 28 Sep 2017 20:26:58 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=fW+WCIRW; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 965032095E53A; Thu, 28 Sep 2017 20:23:41 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c05::231; helo=mail-pg0-x231.google.com; envelope-from=heyi.guo@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pg0-x231.google.com (mail-pg0-x231.google.com [IPv6:2607:f8b0:400e:c05::231]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 863AE20945B68 for ; Thu, 28 Sep 2017 20:23:40 -0700 (PDT) Received: by mail-pg0-x231.google.com with SMTP id c137so57811pga.11 for ; Thu, 28 Sep 2017 20:26:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=WEV+hrb4bbm4u6fweFmJ/lTQeqC8UWXcZhGGSfcIQbo=; b=fW+WCIRW5t+k8toPFs5u2FR70+tJWDWxa2JpbEvLRkcq9b2io8GGX2KnSFLnFGCniE 3mBS9HFbYQX3x4f5qh69EdXeeuG33EPHLYxtiVBHua2xbMWBXA2+U40Q27pBn8lz/g3X low1gnOb89KJOpbneUsKxf2tR/zVXc95esGHQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=WEV+hrb4bbm4u6fweFmJ/lTQeqC8UWXcZhGGSfcIQbo=; b=ZNuglsIasw7/xmKabVyGgNprIikIP5iZ9qmc68TiPBxwatkNcGOdWYpy/CqqIsGM1a Ur4rvM+P863kVnnoYQpj12cBmM6QhmDoAW757w7X1wuACUNLttNZ9LFUI0zEs4mmLwNA C4KxNTeL9GbaCmvKkkXwNt2svhJAZRapbwNr4rWd+pwCbvUx79NXRwhOvy4Ybs8CZBv/ sJk6Nr1q3fdRqMxHbFIc5OBL1XX45NjX1ZywrOlEhUoFnf8KQNjRMYP7NbrhCBsx8ogS 5dCD1M6+gW+DKM3wjFmi7JPaPKPVGRxF8F79+fkNOcIcMXPzg0L39X/0yjHwHEVUA1/h qulA== X-Gm-Message-State: AHPjjUjw3bqA6QnL2adwWg82LXdxlJeAsqiv+TL3xdDmg4KRX77wKunY tJFab4iurrjWh2wb/UXaVhKkPg== X-Google-Smtp-Source: AOwi7QDlkgt3biCMUMxkFztB/O52N8PdMJQtzGk3u/+wJ49if8Qw/XXnwmMwewgfcuT3vCgfU8m/dw== X-Received: by 10.84.173.4 with SMTP id o4mr5661504plb.150.1506655615669; Thu, 28 Sep 2017 20:26:55 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id g16sm5094376pfd.6.2017.09.28.20.26.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 28 Sep 2017 20:26:55 -0700 (PDT) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Fri, 29 Sep 2017 11:19:42 +0800 Message-Id: <1506655190-56231-4-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1506655190-56231-1-git-send-email-heyi.guo@linaro.org> References: <1506655190-56231-1-git-send-email-heyi.guo@linaro.org> Subject: [edk2] [PATCH edk2-platforms v5 03/11] Hisilicon: Fix the drivers use the same GUID issue X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, ard.biesheuvel@linaro.org, zhangjinsong2@huawei.com, Heyi Guo , wanghuiqiang@huawei.com, guoheyi@huawei.com, waip23@126.com, mengfanrong@huawei.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" The drivers build from separate sources, their GUID should be different. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Heyi Guo Reviewed-by: Leif Lindholm --- Platform/Hisilicon/D02/EarlyConfigPeim/EarlyConfigPeim.inf | 2 +- Platform/Hisilicon/D02/FdtUpdateLibD02/FdtUpdateLib.inf | 2 +- Platform/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.inf | 2 +- Platform/Hisilicon/D02/OemNicConfigD02/OemNicConfigD02.inf | 2 +- Platform/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.inf | 2 +- Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf | 2 +- Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf | 2 +- Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf | 2 +- Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf | 2 +- Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf | 2 +- Silicon/Hisilicon/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf | 2 +- Silicon/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf | 2 +- Silicon/Hisilicon/Library/I2CLib/I2CLib.inf | 2 +- Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf | 2 +- 14 files changed, 14 insertions(+), 14 deletions(-) -- 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/Hisilicon/D02/EarlyConfigPeim/EarlyConfigPeim.inf b/Platform/Hisilicon/D02/EarlyConfigPeim/EarlyConfigPeim.inf index 5506a58..3f3f81c 100644 --- a/Platform/Hisilicon/D02/EarlyConfigPeim/EarlyConfigPeim.inf +++ b/Platform/Hisilicon/D02/EarlyConfigPeim/EarlyConfigPeim.inf @@ -16,7 +16,7 @@ [Defines] INF_VERSION = 0x00010005 BASE_NAME = EarlyConfigPeim - FILE_GUID = A181AD33-E64A-4084-A54A-A69DF1FB0ABF + FILE_GUID = ECAE8400-9CCE-4BA5-9B44-74CAABE4DA79 MODULE_TYPE = PEIM VERSION_STRING = 1.0 ENTRY_POINT = EarlyConfigEntry diff --git a/Platform/Hisilicon/D02/FdtUpdateLibD02/FdtUpdateLib.inf b/Platform/Hisilicon/D02/FdtUpdateLibD02/FdtUpdateLib.inf index c952414..e881899 100644 --- a/Platform/Hisilicon/D02/FdtUpdateLibD02/FdtUpdateLib.inf +++ b/Platform/Hisilicon/D02/FdtUpdateLibD02/FdtUpdateLib.inf @@ -16,7 +16,7 @@ [Defines] INF_VERSION = 0x00010005 BASE_NAME = FdtUpdateLib - FILE_GUID = 02CF1727-E697-47fc-8CC2-5DCB81B26DD9 + FILE_GUID = 0F9ADE24-46B4-4506-8802-60C519B56133 MODULE_TYPE = BASE VERSION_STRING = 1.0 LIBRARY_CLASS = FdtUpdateLib diff --git a/Platform/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.inf b/Platform/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.inf index 4d2dbba..ab3b62b 100644 --- a/Platform/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.inf +++ b/Platform/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.inf @@ -16,7 +16,7 @@ [Defines] INF_VERSION = 0x00010005 BASE_NAME = PlatformPciLib - FILE_GUID = 61b7276a-fc67-11e5-82fd-47ea9896dd5d + FILE_GUID = 128F1E1E-A921-4277-A796-A4A47B96B7D2 MODULE_TYPE = BASE VERSION_STRING = 1.0 diff --git a/Platform/Hisilicon/D02/OemNicConfigD02/OemNicConfigD02.inf b/Platform/Hisilicon/D02/OemNicConfigD02/OemNicConfigD02.inf index df5adf1..4c5955f 100644 --- a/Platform/Hisilicon/D02/OemNicConfigD02/OemNicConfigD02.inf +++ b/Platform/Hisilicon/D02/OemNicConfigD02/OemNicConfigD02.inf @@ -16,7 +16,7 @@ [Defines] INF_VERSION = 0x00010005 BASE_NAME = OemNicConfig - FILE_GUID = 3A23A929-1F38-4d04-8A01-38AD993EB2CE + FILE_GUID = BF422A22-CA90-4C34-95B9-3D147AF09E70 MODULE_TYPE = DXE_DRIVER VERSION_STRING = 1.0 ENTRY_POINT = OemNicConfigEntry diff --git a/Platform/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.inf b/Platform/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.inf index 9569b91..2d9d53d 100755 --- a/Platform/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.inf +++ b/Platform/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.inf @@ -16,7 +16,7 @@ [Defines] INF_VERSION = 0x00010005 BASE_NAME = FdtUpdateLib - FILE_GUID = 02CF1727-E697-47fc-8CC2-5DCB81B26DD9 + FILE_GUID = B80B9FF1-FAB9-4BE5-B602-5ABAA6B7A3D4 MODULE_TYPE = BASE VERSION_STRING = 1.0 LIBRARY_CLASS = FdtUpdateLib diff --git a/Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf b/Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf index 9d8ea7e..0f6b68d 100644 --- a/Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf +++ b/Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf @@ -17,7 +17,7 @@ [Defines] INF_VERSION = 0x00010019 BASE_NAME = EarlyConfigPeimD05 - FILE_GUID = A181AD33-E64A-4084-A54A-A69DF1FB0ABF + FILE_GUID = 13525B94-06F0-41AC-8CAF-724B149FD259 MODULE_TYPE = PEIM VERSION_STRING = 1.0 ENTRY_POINT = EarlyConfigEntry diff --git a/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf b/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf index 4fe7ac6..bf44ff7 100644 --- a/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf +++ b/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf @@ -16,7 +16,7 @@ [Defines] INF_VERSION = 0x00010019 BASE_NAME = OemMiscLibHi1616Evb - FILE_GUID = B9CE7465-21A2-4ecd-B347-BBDDBD098CEE + FILE_GUID = 751C7627-D5F8-499C-AEEEE-C87858759612 MODULE_TYPE = BASE VERSION_STRING = 1.0 LIBRARY_CLASS = OemMiscLib diff --git a/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf b/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf index cd64193..21bb33a 100644 --- a/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf +++ b/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf @@ -16,7 +16,7 @@ [Defines] INF_VERSION = 0x00010019 BASE_NAME = PlatformPciLib - FILE_GUID = 61b7276a-fc67-11e5-82fd-47ea9896dd5d + FILE_GUID = B94B8A3A-AD7D-4F26-B140-1E699682176B MODULE_TYPE = BASE VERSION_STRING = 1.0 diff --git a/Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf b/Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf index 174e967..89447cc 100644 --- a/Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf +++ b/Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf @@ -16,7 +16,7 @@ [Defines] INF_VERSION = 0x00010005 BASE_NAME = IoInitDxe - FILE_GUID = e99c606a-5626-11e5-b09e-bb93f4e4c400 + FILE_GUID = 28C9B7DE-AAD6-4E9B-811B-050AD3DAB9A3 MODULE_TYPE = DXE_DRIVER VERSION_STRING = 1.0 diff --git a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf index 686d041..ee9dbed 100644 --- a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf +++ b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf @@ -17,7 +17,7 @@ [Defines] INF_VERSION = 0x00010005 BASE_NAME = PcieInitDxe - FILE_GUID = 2D53A704-A544-4A82-83DF-FFECF4B4AA97 + FILE_GUID = 8EB6E216-BA47-4B30-B68A-2B371F7232A6 MODULE_TYPE = DXE_DRIVER VERSION_STRING = 1.0 ENTRY_POINT = PcieInitEntry diff --git a/Silicon/Hisilicon/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf b/Silicon/Hisilicon/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf index 6faefb1..17d59ee 100644 --- a/Silicon/Hisilicon/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf +++ b/Silicon/Hisilicon/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf @@ -20,7 +20,7 @@ [Defines] INF_VERSION = 0x00010005 BASE_NAME = DS3231RealTimeClockLib - FILE_GUID = 470DFB96-E205-4515-A75E-2E60F853E79D + FILE_GUID = 5FD8127D-11E1-488F-8CF1-A143157D6BF0 MODULE_TYPE = BASE VERSION_STRING = 1.0 LIBRARY_CLASS = RealTimeClockLib diff --git a/Silicon/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf b/Silicon/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf index d7957ea..df65d4b 100644 --- a/Silicon/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf +++ b/Silicon/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf @@ -17,7 +17,7 @@ [Defines] INF_VERSION = 0x00010005 BASE_NAME = Dw8250SerialPortLib - FILE_GUID = 16D53E86-7EA6-47bd-861F-511ED9B8ABE0 + FILE_GUID = 78337705-D2A8-4EA7-9C18-27FC4A8A2C6E MODULE_TYPE = BASE VERSION_STRING = 1.0 LIBRARY_CLASS = SerialPortLib diff --git a/Silicon/Hisilicon/Library/I2CLib/I2CLib.inf b/Silicon/Hisilicon/Library/I2CLib/I2CLib.inf index 7f95124..9bca88f 100644 --- a/Silicon/Hisilicon/Library/I2CLib/I2CLib.inf +++ b/Silicon/Hisilicon/Library/I2CLib/I2CLib.inf @@ -16,7 +16,7 @@ [Defines] INF_VERSION = 0x00010005 BASE_NAME = I2CLib - FILE_GUID = FC5651CA-55D8-4fd2-B6D3-A284D993ABA2 + FILE_GUID = 162F2DF1-DBF8-41E6-9792-92A96ADEAB40 MODULE_TYPE = BASE VERSION_STRING = 1.0 LIBRARY_CLASS = I2CLib diff --git a/Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf b/Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf index 4990072..1bb4f5c 100644 --- a/Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf +++ b/Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf @@ -16,7 +16,7 @@ [Defines] INF_VERSION = 0x00010005 BASE_NAME = I2CLibRuntime - FILE_GUID = FC5651CA-55D8-4fd2-B6D3-A284D993ABA2 + FILE_GUID = 2E602B32-9203-44A4-BF28-1FF98BD89523 MODULE_TYPE = DXE_RUNTIME_DRIVER VERSION_STRING = 1.0 LIBRARY_CLASS = I2CLib From patchwork Fri Sep 29 03:19:43 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 114479 Delivered-To: patch@linaro.org Received: by 10.140.104.133 with SMTP id a5csp312214qgf; Thu, 28 Sep 2017 20:27:01 -0700 (PDT) X-Received: by 10.99.182.78 with SMTP id v14mr6180171pgt.325.1506655620956; Thu, 28 Sep 2017 20:27:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506655620; cv=none; d=google.com; s=arc-20160816; b=SyUyhot2NH/tOBAASzfdEiTVqUVbpeCtfqHbkxveLNfXi+xzYJVRHK/11hGRKFtWEt 0oaEV+cmbbnhyKreqxfCLQ9kj1wYE3WE8mZRPsZW0CKOHpsj/q2wQdTGSY/kQVDwc6M0 8U68h0pz7k/GXVpAg5REQem5ERuX1XrxUVmykLltyetSvsR8XLdVYcikaLWsqr+rJWiW AwHmRiJjJqosGHgzwmBOKQc/r/Ma34gxigoMCQEquFmhnzNECUQpsG1YSH5Jqw4dpn4M EpQoer+podk4j40eGZ+iYq/dKh7iDRO/m7EdFHd0u/qHQl+y2b4UUGMcgJ0bz98gyELD ajLA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=7DmlylXB+XCzzdMemNwg6Psouq/15q9tYeCES9MeC40=; b=QQ90uoNPNdAcvW4aAZOs+7Fxnc8FjMJfcGCy25m3RUUcbmCKE597iNVKC9yCJVJbcZ 3kZ3pKwJTW2pWob8Sr31NaJAaqiAEdf+/3hGT6m4xje+uCUTS5j93itysvLIBq32X4Qf ABi6Bw6TS8vsd52xBDxQP99jAyqu3wJeL4C+mG6MdZ7wf4w7GU72gfbnK9QQSDcXyXhP xuyKnmDo0T5jcA3Y1l3UyGkLnANRWZLuuMylX7DFwIGbcXe9iL/Pma0J6Dm6LF/1uURG oe1ZQ8sSRkMmpS8TI4g3V/rQcFpeKboXxkjFhMD7+u5DnoPHhfrQjXwuJ8yynNlnbRxe EQig== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=ODG3TqAF; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [198.145.21.10]) by mx.google.com with ESMTPS id r13si2446054plj.97.2017.09.28.20.27.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 28 Sep 2017 20:27:00 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=ODG3TqAF; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id D3E692095E534; Thu, 28 Sep 2017 20:23:44 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c05::236; helo=mail-pg0-x236.google.com; envelope-from=heyi.guo@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pg0-x236.google.com (mail-pg0-x236.google.com [IPv6:2607:f8b0:400e:c05::236]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 7BFF420945BD0 for ; Thu, 28 Sep 2017 20:23:43 -0700 (PDT) Received: by mail-pg0-x236.google.com with SMTP id v23so76358pgc.5 for ; Thu, 28 Sep 2017 20:26:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=j4F0TkCDviqlktS2yhOWzo1gIOr/MjOUf/5kz5fkhvI=; b=ODG3TqAFgRNypoJPwlTjeeQlmf8vfLNaDbsWYxV0RfzIDnSqrY2x2xYpZ3A354YRoH +F8HuKzwIybOvwRaTCl9C+lJQUshbinOY6794ac6FHW3ofyUs0hUMGBfl5dv6Wpo02v4 wyNQNTtSzfGp/K0YLKaOX9w/ffD9vA6QSaUT0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=j4F0TkCDviqlktS2yhOWzo1gIOr/MjOUf/5kz5fkhvI=; b=WHcldzh/QjWa29ERxLfe0ZUiS2vg+l4frzQcmdXMNdoabRU2vhz7TUItVmdhHkyH4i L1K9AucfPKO+SZfKMBqAFkXO8Kl+rj4YuOhFFVvxIwb6HIbznysdj+uu6N1Qm6lP54Qo tohCu+OjB5V7fR/4ru3uFIO+j4n0ZVBu8/bf0Cr9k/6EQM5EEWemVlFkU2deb4KtVkw4 g9crSpl+6gzPePCGLBSW53Y6jpmWCQYDoLycIO1YcYedyWOI+TODFusamdYBQEf5HGNY 1ujdocfKupj62Y6gdAReHmukC0wFxOBUkCNqyr7PM28WRg/wveow60JwFUphE45FkzUZ 970A== X-Gm-Message-State: AHPjjUhEuSSVOjStRpDwgq9LUu/jeKyKawSEGuoP51TJMAW1WVB6gCHP Sc+Z57QCWL6WfJ85er5oCih/Eg== X-Google-Smtp-Source: AOwi7QBy9wK9BxViS68HK9bUixPZJO/kBFnTICFjgu2ue5lbmIXulZMquJ3S77jNuuxtXXnOWmpf0g== X-Received: by 10.84.133.98 with SMTP id 89mr5674740plf.294.1506655618663; Thu, 28 Sep 2017 20:26:58 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id g16sm5094376pfd.6.2017.09.28.20.26.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 28 Sep 2017 20:26:58 -0700 (PDT) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Fri, 29 Sep 2017 11:19:43 +0800 Message-Id: <1506655190-56231-5-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1506655190-56231-1-git-send-email-heyi.guo@linaro.org> References: <1506655190-56231-1-git-send-email-heyi.guo@linaro.org> Subject: [edk2] [PATCH edk2-platforms v5 04/11] Hisilicon D03/D05: get firmware version from FIRMWARE_VER X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, ard.biesheuvel@linaro.org, zhangjinsong2@huawei.com, Heyi Guo , Ming Huang , wanghuiqiang@huawei.com, guoheyi@huawei.com, waip23@126.com, mengfanrong@huawei.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" From: Ming Huang Value of the environment variable FIRMWARE_VER is GIT SHA by default, and you can add the environment variable FIRMWARE_VER to EXTRA_OPTIONS at build time to specify something else, eg. "16.12-". Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Signed-off-by: Heyi Guo Reviewed-by: Leif Lindholm --- Platform/Hisilicon/D03/D03.dsc | 6 +++++- Platform/Hisilicon/D05/D05.dsc | 6 +++++- 2 files changed, 10 insertions(+), 2 deletions(-) -- 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/Hisilicon/D03/D03.dsc b/Platform/Hisilicon/D03/D03.dsc index 7e25ffb..fca6781 100644 --- a/Platform/Hisilicon/D03/D03.dsc +++ b/Platform/Hisilicon/D03/D03.dsc @@ -170,7 +170,11 @@ gHisiTokenSpaceGuid.PcdAlgSmmuBaseAddress|0xd0040000 - gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Hisilicon D03 UEFI 16.12 Release" + !ifdef $(FIRMWARE_VER) + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_VER)" + !else + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Development build base on Hisilicon D03 UEFI 17.10 Release" + !endif gHisiTokenSpaceGuid.PcdBiosVersionString|L"10.01.01T18" diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc index 7cd5758..aa61c0e 100644 --- a/Platform/Hisilicon/D05/D05.dsc +++ b/Platform/Hisilicon/D05/D05.dsc @@ -188,7 +188,11 @@ gHisiTokenSpaceGuid.PcdIsMPBoot|1 gHisiTokenSpaceGuid.PcdSocketMask|0x3 - gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Hisilicon D05 UEFI 16.12 Release" + !ifdef $(FIRMWARE_VER) + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_VER)" + !else + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Development build base on Hisilicon D05 UEFI 17.10 Release" + !endif gHisiTokenSpaceGuid.PcdBiosVersionString|L"10.01.01T18" From patchwork Fri Sep 29 03:19:44 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 114480 Delivered-To: patch@linaro.org Received: by 10.140.104.133 with SMTP id a5csp312268qgf; Thu, 28 Sep 2017 20:27:04 -0700 (PDT) X-Received: by 10.101.82.8 with SMTP id o8mr5870053pgp.261.1506655624069; Thu, 28 Sep 2017 20:27:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506655624; cv=none; d=google.com; s=arc-20160816; b=MYJASa2oRS+gzLQTUrXotMQnX/ajOyq0/UwCohlQc7vhEBG+Ecgl/z4ffBCx7+hu7M BACSIWkJVy8oQNHJNadYp9RZBO1p2mdIU9z5FlSxf+yhM8BGaTr0BPbo512h9i7395u0 DnyDnPJozdjlBZEntwuivmfwEb7iZMVzIA6oM3ThAmFMaFb/8lQWwt8AHaB4wW2sVlg5 aKvtjQjhHL81veShi9NVN2kHsUO7AaYgBy01z6b+67ZXuxSypykZaS5zD3N/06Xqlorx tCdY+MNGNC0oy8nK626zNvnK7TILUvw1RgikQE3CzR25VaVjpLvRsyAOhBxhi6po/vXs X04g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=1L5lhGiHtMwzaKYSQlkDGEuyZDVt7A+7YRcV240Y6rI=; b=wm1WGRgmF/pGvnwP63Od0ACp9/441BBAC2Xwfu93mmm21BLr3aFDQaokBRq9WP2mJv ZkoJKj9qSURMRUH/BZd0q9uN5qEZylWzHcv4USqwGj1AsvOT53nQa1NrZcmzw4cd0TDK 26j/1Xkb786MTbXF4jPdu9HysW9/4IbWtmqC2zs8SfkDrN2RAhb1ROxnLxSKHv8pTNsJ G+HeTlgWFy+Zutc7uT5Q7VcaoJpWhTOXvZ2sdsj1AGZ3wrufDwz+XPXAl0Lkiv+ml915 /KNMFf4l2RobII3Yy4J27AZG2XLQYptzgR335iz65A3Yyp/lV5xERSQAO705ZKjGG7Tv W/bA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Xhy9zX6X; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [198.145.21.10]) by mx.google.com with ESMTPS id b83si2568965pfj.113.2017.09.28.20.27.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 28 Sep 2017 20:27:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Xhy9zX6X; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 2239B21E1B76C; Thu, 28 Sep 2017 20:23:48 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c00::22c; helo=mail-pf0-x22c.google.com; envelope-from=heyi.guo@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pf0-x22c.google.com (mail-pf0-x22c.google.com [IPv6:2607:f8b0:400e:c00::22c]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 57DCA20945B68 for ; Thu, 28 Sep 2017 20:23:46 -0700 (PDT) Received: by mail-pf0-x22c.google.com with SMTP id e1so79408pfk.1 for ; Thu, 28 Sep 2017 20:27:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=hhdUB09fTVAnEDB3I7Lq1XdPfQusT+nJTQexSJ2LpVY=; b=Xhy9zX6X1x7m/gBf1/mxpsV13cyMXvVJHIF/5s+i+xa3PxJDErepZQaWyC4VjZodVJ Tv353tqdu8B71s66/TkmzwmfLjRN/gojbRx7XwqaVmF0AxGnSLrva3zlXnkWLTB9TcYH 4WSPbafoHkV2s5cAXa4PwABH0p3ItnQaAw7NE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hhdUB09fTVAnEDB3I7Lq1XdPfQusT+nJTQexSJ2LpVY=; b=hfzgOQcVOkjv97sjr3Y1n7BnwkewsFk2UDEfG/vNe8I0ogrulCf4XWSMtP/6mxyJ/J RGC/Otzu6/jHG2nVC514Ybez1QLnTfZ3FWHZ4CqaY35YpTqKwFFz7mZWALdYxtnhXJ/v FkDIRErdvPyGyP1x1mzPgPoee4JDdTKxWf+cIOmKQoiY3H5C6+gUW5zquUR0ZdWIhmfI rSaaYG8mez/Te5TKgmCAXIG/SOrVwI68F9Y8EcNQDGsljkzMIKJqP2hX/sQakHILZYnR VRP5LAKAXjTPMn3gxUOy4KfzO2oGfx6+TguRt5JeF87n8mmTULTznzA5s5lpCw1JdrG5 Yu0g== X-Gm-Message-State: AHPjjUjwOncVjElF7RR3WpuzJR7sa5DVUJsW2lPmEUEucxOwE+T/nZ3k papGDYZ1y/1VZFYLImhFc/d8Bw== X-Google-Smtp-Source: AOwi7QAMETEsIKNsfJafq+7MWGeozc3QPX46TmljFh2gVGh5S8j9VeUgeGWnmgmBc40OtNeb13d6Ww== X-Received: by 10.159.204.141 with SMTP id t13mr5683495plo.129.1506655621458; Thu, 28 Sep 2017 20:27:01 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id g16sm5094376pfd.6.2017.09.28.20.26.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 28 Sep 2017 20:27:00 -0700 (PDT) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Fri, 29 Sep 2017 11:19:44 +0800 Message-Id: <1506655190-56231-6-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1506655190-56231-1-git-send-email-heyi.guo@linaro.org> References: <1506655190-56231-1-git-send-email-heyi.guo@linaro.org> Subject: [edk2] [PATCH edk2-platforms v5 05/11] Hisilicon/PciHostBridgeDxe: Assign BAR resource from PciRegionBase X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, ard.biesheuvel@linaro.org, zhangjinsong2@huawei.com, Heyi Guo , wanghuiqiang@huawei.com, guoheyi@huawei.com, waip23@126.com, mengfanrong@huawei.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Io BAR should be based IoBase and Mem BAR should be based PciRegionBase. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Signed-off-by: Heyi Guo Reviewed-by: Leif Lindholm --- Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c | 37 ++++++++++++-------- Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 15 ++++++-- 2 files changed, 35 insertions(+), 17 deletions(-) -- 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c index a970da6..e3d3988 100644 --- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c +++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c @@ -1410,9 +1410,8 @@ SetResource( Ptr->ResType = 1; Ptr->GenFlag = 0; Ptr->SpecificFlag = 0; - /* This is PCIE Device Bus which start address is the low 32bit of mem base*/ - Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) + - (RootBridgeInstance->MemBase & 0xFFFFFFFF); + /* PCIE Device Iobar address should be based on IoBase */ + Ptr->AddrRangeMin = RootBridgeInstance->IoBase; Ptr->AddrRangeMax = 0; Ptr->AddrTranslationOffset = \ (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS; @@ -1429,9 +1428,13 @@ SetResource( Ptr->GenFlag = 0; Ptr->SpecificFlag = 0; Ptr->AddrSpaceGranularity = 32; - /* This is PCIE Device Bus which start address is the low 32bit of mem base*/ - Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) + - (RootBridgeInstance->MemBase & 0xFFFFFFFF); + /* PCIE device Bar should be based on PciRegionBase */ + if (RootBridgeInstance->PciRegionBase > MAX_UINT32) { + DEBUG((DEBUG_ERROR, "PCIE Res(TypeMem32) unsupported.\n")); + return EFI_UNSUPPORTED; + } + Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase + + RootBridgeInstance->PciRegionBase; Ptr->AddrRangeMax = 0; Ptr->AddrTranslationOffset = \ (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS; @@ -1448,9 +1451,13 @@ SetResource( Ptr->GenFlag = 0; Ptr->SpecificFlag = 6; Ptr->AddrSpaceGranularity = 32; - /* This is PCIE Device Bus which start address is the low 32bit of mem base*/ - Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) + - (RootBridgeInstance->MemBase & 0xFFFFFFFF); + /* PCIE device Bar should be based on PciRegionBase */ + if (RootBridgeInstance->PciRegionBase > MAX_UINT32) { + DEBUG((DEBUG_ERROR, "PCIE Res(TypePMem32) unsupported.\n")); + return EFI_UNSUPPORTED; + } + Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase + + RootBridgeInstance->PciRegionBase; Ptr->AddrRangeMax = 0; Ptr->AddrTranslationOffset = \ (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS; @@ -1467,9 +1474,9 @@ SetResource( Ptr->GenFlag = 0; Ptr->SpecificFlag = 0; Ptr->AddrSpaceGranularity = 64; - /* This is PCIE Device Bus which start address is the low 32bit of mem base*/ - Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) + - (RootBridgeInstance->MemBase & 0xFFFFFFFFFFFFFFFF); + /* PCIE device Bar should be based on PciRegionBase */ + Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase + + RootBridgeInstance->PciRegionBase; Ptr->AddrRangeMax = 0; Ptr->AddrTranslationOffset = \ (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS; @@ -1486,9 +1493,9 @@ SetResource( Ptr->GenFlag = 0; Ptr->SpecificFlag = 6; Ptr->AddrSpaceGranularity = 64; - /* This is PCIE Device Bus which start address is the low 32bit of mem base*/ - Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) + - (RootBridgeInstance->MemBase & 0xFFFFFFFFFFFFFFFF); + /* PCIE device Bar should be based on PciRegionBase */ + Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase + + RootBridgeInstance->PciRegionBase; Ptr->AddrRangeMax = 0; Ptr->AddrTranslationOffset = \ (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS; diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c index 03edcf1..10d766a 100644 --- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c @@ -2301,8 +2301,19 @@ RootBridgeIoConfiguration ( PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This); for (Index = 0; Index < TypeMax; Index++) { if (PrivateData->ResAllocNode[Index].Status == ResAllocated) { - Configuration.SpaceDesp[Index].AddrRangeMin = PrivateData->ResAllocNode[Index].Base; - Configuration.SpaceDesp[Index].AddrRangeMax = PrivateData->ResAllocNode[Index].Base + PrivateData->ResAllocNode[Index].Length - 1; + switch (Index) { + case TypeIo: + Configuration.SpaceDesp[Index].AddrRangeMin = PrivateData->IoBase; + break; + case TypeBus: + Configuration.SpaceDesp[Index].AddrRangeMin = PrivateData->ResAllocNode[Index].Base; + break; + default: + /* PCIE Device bar address should be base on PciRegionBase */ + Configuration.SpaceDesp[Index].AddrRangeMin = PrivateData->ResAllocNode[Index].Base - PrivateData->MemBase + + PrivateData->PciRegionBase; + } + Configuration.SpaceDesp[Index].AddrRangeMax = Configuration.SpaceDesp[Index].AddrRangeMin + PrivateData->ResAllocNode[Index].Length - 1; Configuration.SpaceDesp[Index].AddrLen = PrivateData->ResAllocNode[Index].Length; } } From patchwork Fri Sep 29 03:19:45 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 114481 Delivered-To: patch@linaro.org Received: by 10.140.104.133 with SMTP id a5csp312289qgf; Thu, 28 Sep 2017 20:27:06 -0700 (PDT) X-Received: by 10.84.135.34 with SMTP id 31mr5698989pli.306.1506655626353; Thu, 28 Sep 2017 20:27:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506655626; cv=none; d=google.com; s=arc-20160816; b=cokvD0hu610fmlxw1ix75FOGeWCr6cZMZ3XpgqNMpWp5fKvmuoj61OKLxxh4oWpkTH I9CPlYuD0JPgl73yRvR+K0QkKyvLDcuWeDRRrjMjBVub97sg7xEK25JS+Wgz4roTroU8 6jWhvqDJrl7nxsXcmrYUa73DAvdRF90AkUoenSqchv+gSvZAW3YDDoalYECPvJflq8kN zqi1B4mPydto8KMLI1+FtK3W82ITZ8t44v3dS27L4b6VoXvjq2rGp1eEpKevNjTJPzj3 RYJ+znZhWjsQ1Yz7ebCKK6kHpSSqz4VjD95W0/mwUJL9Px7flgAbkofKVZSKb6LRnm1+ y9MQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=SWte4aLN0QO+trRfmkjfqT10FxKCDfwtmT2rWVB3SNs=; b=JRqhKsxCe8b+ubd9aWTRdhyTr0DW4gk6to/ZDsuBTdo2Va/5rCRPR4Z1In7yTkEpUT M8iw4vu6zFRihdseZntHi1LR5yeAtZC3oY6oIzpBUFGKLCJb7ZCrcY4fOtEmCAdoGatT kc8O60jUSxHghuQ8Wl604VGxR40pfeVSLtXlTCpbjNBGmeuo1s/y1FeJgjGeQyOUYvBc 3GQfEkc92uXH6Ra/ZODS+0s85L9LWOuqg+ULuKqNvCibioag2C5CX393kJSPdtb6enOE f+0Ce+58uObGC/hKCn6WHtv36j3TJ0zDEPkwlZUApXk6x2QzTa5gkT5j/EBxplnU/2US iU8A== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=NIzO2zB+; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [2001:19d0:306:5::1]) by mx.google.com with ESMTPS id 3si2493020pli.141.2017.09.28.20.27.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 28 Sep 2017 20:27:06 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=NIzO2zB+; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 5FE4921E87968; Thu, 28 Sep 2017 20:23:50 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c00::22e; helo=mail-pf0-x22e.google.com; envelope-from=heyi.guo@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pf0-x22e.google.com (mail-pf0-x22e.google.com [IPv6:2607:f8b0:400e:c00::22e]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 2505F20945B68 for ; Thu, 28 Sep 2017 20:23:49 -0700 (PDT) Received: by mail-pf0-x22e.google.com with SMTP id z84so63787pfi.2 for ; Thu, 28 Sep 2017 20:27:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=udYeIXv3R7C2OZFve0o4J9I0UAexPYc3+7ZkDhkVR/E=; b=NIzO2zB+EXh55eCsIjbqVQvaDbGhqfi2npUYmDTZWwow+5Roa6XgtFrkQ5CempdbRj 1Qg00PEajnG4gMOkRFevF7r+WnP8/dDR0qLMIkg5iX1+66C4p6HEomfF1vpShhuj8MGF 4IZn1Ekus/21lq19JAuHeojepiS+Z7/ofVJAo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=udYeIXv3R7C2OZFve0o4J9I0UAexPYc3+7ZkDhkVR/E=; b=oIOkfE0+FjMedu5173GUWV1NteHU/FOgG+aMIZA/P+McsUptdSScvZGknbCnAF0/mB DumfoqWE8WHkrWDNPqttUj+aSi3uMLGGEqfjF93mq294G0c1KT11RSBx0wGcfvBZmimM zUR6I6PxMmGHTf1X5tfPH+Zln5+UYjhYd0/qchcDuYASzlM2YIbcWUn1qYLlrCxditQL WRcYLgZIK88TxPvcqedFpU8d9wiLnYk5PrKcugo0MC5DHr5qbrQhZz8Yv8+GR9bThcZl KptOv4fcvdkYV2gZkKHBJVMbL7pI6vyo0HN4G8eCEonOKbZWfdxcWm7c+zCA2a3r2/ZG MhUQ== X-Gm-Message-State: AHPjjUhoRbFGpDL1yKujsShIofgBfTNjnbH1n81UuTlAjK1YCDoDmBw1 Pv8OKeafpX5kwYw9AR3CBSSiNA== X-Google-Smtp-Source: AOwi7QBwGghu0PakzxfL54+EeMJW8M7qD4SEi8QIEehTjd9inDK7Eev44sDuvQBnQtn9inkHuQiYLQ== X-Received: by 10.98.59.193 with SMTP id w62mr6022331pfj.7.1506655624168; Thu, 28 Sep 2017 20:27:04 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id g16sm5094376pfd.6.2017.09.28.20.27.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 28 Sep 2017 20:27:03 -0700 (PDT) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Fri, 29 Sep 2017 11:19:45 +0800 Message-Id: <1506655190-56231-7-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1506655190-56231-1-git-send-email-heyi.guo@linaro.org> References: <1506655190-56231-1-git-send-email-heyi.guo@linaro.org> Subject: [edk2] [PATCH edk2-platforms v5 06/11] Hisilicon/D05/Pcie: fix bug of size definition X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, ard.biesheuvel@linaro.org, zhangjinsong2@huawei.com, Heyi Guo , wanghuiqiang@huawei.com, guoheyi@huawei.com, waip23@126.com, mengfanrong@huawei.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" From: Ming Huang Fix bug of PcieRegion size definition and IO size definition. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Signed-off-by: Heyi Guo Reviewed-by: Leif Lindholm --- Platform/Hisilicon/D05/D05.dsc | 64 ++++++++++---------- 1 file changed, 32 insertions(+), 32 deletions(-) -- 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc index aa61c0e..01defe0 100644 --- a/Platform/Hisilicon/D05/D05.dsc +++ b/Platform/Hisilicon/D05/D05.dsc @@ -310,37 +310,37 @@ gHisiTokenSpaceGuid.PciHb1Rb7Base|0x700a00b0000 gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress|0xa8400000 - gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize|0xbeffff + gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize|0xbf0000 gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress|0xa9400000 - gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize|0xbeffff + gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize|0xbf0000 gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress|0xa8800000 - gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize|0x77effff + gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize|0x77f0000 gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress|0xab400000 - gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize|0xbeffff + gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize|0xbf0000 gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress|0xa9000000 - gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize|0x2feffff + gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize|0x2ff0000 gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress|0xb0800000 - gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize|0x77effff + gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize|0x77f0000 gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress|0xac900000 - gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize|0x36effff + gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize|0x36f0000 gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionBaseAddress|0xb9800000 - gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize|0x67effff + gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize|0x67f0000 gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionBaseAddress|0x400a8400000 - gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize|0xbeffff + gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize|0xbf0000 gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress|0x400a9400000 - gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize|0xbeffff + gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize|0xbf0000 gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress|0x20000000 - gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize|0xcfffffff + gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize|0xd0000000 gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress|0x400ab400000 - gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize|0xbeffff + gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize|0xbf0000 gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress|0x30000000 - gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize|0xbfffffff + gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize|0xc0000000 gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress|0x40000000 - gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize|0xafffffff + gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize|0xb0000000 gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress|0x408aa400000 - gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize|0xbeffff + gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize|0xbf0000 gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionBaseAddress|0x408ab400000 - gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize|0xbeffff + gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize|0xbf0000 gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase|0xA8400000 gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase|0xA9400000 @@ -377,52 +377,52 @@ gHisiTokenSpaceGuid.PcdHb1Rb7CpuIoRegionBase|0x408abff0000 gHisiTokenSpaceGuid.PcdHb0Rb0IoBase|0 - gHisiTokenSpaceGuid.PcdHb0Rb0IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb0Rb0IoSize|0x10000 #64K gHisiTokenSpaceGuid.PcdHb0Rb1IoBase|0 - gHisiTokenSpaceGuid.PcdHb0Rb1IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb0Rb1IoSize|0x10000 #64K gHisiTokenSpaceGuid.PcdHb0Rb2IoBase|0 - gHisiTokenSpaceGuid.PcdHb0Rb2IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb0Rb2IoSize|0x10000 #64K gHisiTokenSpaceGuid.PcdHb0Rb3IoBase|0 - gHisiTokenSpaceGuid.PcdHb0Rb3IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb0Rb3IoSize|0x10000 #64K gHisiTokenSpaceGuid.PcdHb0Rb4IoBase|0 - gHisiTokenSpaceGuid.PcdHb0Rb4IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb0Rb4IoSize|0x10000 #64K gHisiTokenSpaceGuid.PcdHb0Rb5IoBase|0 - gHisiTokenSpaceGuid.PcdHb0Rb5IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb0Rb5IoSize|0x10000 #64K gHisiTokenSpaceGuid.PcdHb0Rb6IoBase|0 - gHisiTokenSpaceGuid.PcdHb0Rb6IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb0Rb6IoSize|0x10000 #64K gHisiTokenSpaceGuid.PcdHb0Rb7IoBase|0 - gHisiTokenSpaceGuid.PcdHb0Rb7IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb0Rb7IoSize|0x10000 #64K gHisiTokenSpaceGuid.PcdHb1Rb0IoBase|0 - gHisiTokenSpaceGuid.PcdHb1Rb0IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb1Rb0IoSize|0x10000 #64K gHisiTokenSpaceGuid.PcdHb1Rb1IoBase|0 - gHisiTokenSpaceGuid.PcdHb1Rb1IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb1Rb1IoSize|0x10000 #64K gHisiTokenSpaceGuid.PcdHb1Rb2IoBase|0 - gHisiTokenSpaceGuid.PcdHb1Rb2IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb1Rb2IoSize|0x10000 #64K gHisiTokenSpaceGuid.PcdHb1Rb3IoBase|0 - gHisiTokenSpaceGuid.PcdHb1Rb3IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb1Rb3IoSize|0x10000 #64K gHisiTokenSpaceGuid.PcdHb1Rb4IoBase|0 - gHisiTokenSpaceGuid.PcdHb1Rb4IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb1Rb4IoSize|0x10000 #64K gHisiTokenSpaceGuid.PcdHb1Rb5IoBase|0 - gHisiTokenSpaceGuid.PcdHb1Rb5IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb1Rb5IoSize|0x10000 #64K gHisiTokenSpaceGuid.PcdHb1Rb6IoBase|0 - gHisiTokenSpaceGuid.PcdHb1Rb6IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb1Rb6IoSize|0x10000 #64K gHisiTokenSpaceGuid.PcdHb1Rb7IoBase|0 - gHisiTokenSpaceGuid.PcdHb1Rb7IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb1Rb7IoSize|0x10000 #64K gHisiTokenSpaceGuid.Pcdsoctype|0x1610 From patchwork Fri Sep 29 03:19:46 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 114482 Delivered-To: patch@linaro.org Received: by 10.140.104.133 with SMTP id a5csp312337qgf; Thu, 28 Sep 2017 20:27:09 -0700 (PDT) X-Received: by 10.99.124.87 with SMTP id l23mr5979820pgn.351.1506655629450; Thu, 28 Sep 2017 20:27:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506655629; cv=none; d=google.com; s=arc-20160816; b=YTubSJf27e5uXqmyPlvZRA6Tdk2IK1obq8ygTXplNbUl66RmYr1siZmd1/3X+qulu6 iAu3Gg+gauYTGKmWb5r2645pDoRPusRgRuOlRpKujFLETpKsv4tmPBo/CKfI59Q3G9cc 8PM9bkJLtlmQ5M0pPCi/frXhFNOXeKxATzrIe0nkUMHudMv6Z1JQtLmi7cRfhp+QOikR J+/0S0zOSR4ZwJP0hI1iCojzQdZkBZU540VyN5s9O+UW11QD7MhTyCTTsppMDLp4RsUZ tD1f7FEeWBkc/uFMMKBfM/JkAHq6Mp4kE9+DjNtx7f7EMSvgDyeJDaLxa7L1h1jykmTL AuAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=Q/mjy2uV3z6H/gFHrDJLmYe9bOJoJ16tHEQ5n7voTc8=; b=IhP+aRoZimY6hDtANY1TItKbHdhyvoajQFArs1OvL1X70mpIuOAquoYOs9cPZVxM0q zQga/JoDYxy+fscS/gD8bcTcbQonGg/MIpKFBxjoXwbShHe2KkGDAT+pfEJWkpzByJdv wAdwkj5dd0NZxbxsouEWu4gyhRj9H7DjoDNZ3IDz58TB5kCrgq05d0Vsl8qSk8y/6mS0 QmZaoxWgPyS4ZscR0IwO2F6L0kJvpgm2QgaL3CI4PghF42QulF07jNSZdByb8wYb5Roe naksEVO3vWmAG25sDk560Q7Fw3lnK3Vqu14+6K9sem56SsQF/Ax3s1Bn13L4CQIekidg dQHA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=FRlPxKHv; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [2001:19d0:306:5::1]) by mx.google.com with ESMTPS id 1si2501160plk.689.2017.09.28.20.27.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 28 Sep 2017 20:27:09 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=FRlPxKHv; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 99F1D21F2AF65; Thu, 28 Sep 2017 20:23:52 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c00::22d; helo=mail-pf0-x22d.google.com; envelope-from=heyi.guo@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pf0-x22d.google.com (mail-pf0-x22d.google.com [IPv6:2607:f8b0:400e:c00::22d]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id DC1FE20945BD0 for ; Thu, 28 Sep 2017 20:23:51 -0700 (PDT) Received: by mail-pf0-x22d.google.com with SMTP id l188so58877pfc.6 for ; Thu, 28 Sep 2017 20:27:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=SONwR6b3hI7RT3XsR+jXry8c29U1r5xWCBJ7Konsg0M=; b=FRlPxKHv8WiDiBAVUJMEf+pDKh+CBMsC/YGURfRl6eAA7ezqz+3kbroSfOkFHjb49j VggZ7AwfuJ38NN2Oddm1CNLPfk9rfq7+49tnqCMT0KC/nw33bquk6qt9i4iphIC/TVIY BZKiN7gVJ2dsZT8jveSbNrmhJ3Eok6uZ0F29o= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=SONwR6b3hI7RT3XsR+jXry8c29U1r5xWCBJ7Konsg0M=; b=pqeDG2TAK/yjgx4kQikvEklUpIQTOs+I/k5RP6QPDVOiQ82VKNUwDmzcxsBCMr+gfX gS1uc5YBpuSZyCpEw80Z4282oBXjCXwEXRHFTeWVesBv9xGNuDmyHxFqKSvU2aOMa8fc S1I1SbJBnATke19BTrDSpCKOlubR4Gsqp7f5pnsRR6kbTdX8x3pjxThGc5XDUP2Id3Gk AUP0Bhr7S6tfmFkmGU8NBxagNvMqEHfdHIknZsdJktAdls9CC/N8o3Zu8P6Gkh/yfQxK 8OZT8LEEP4AoKIoAjBrWnbm6bBd2KhB8dG8CoxH5XcDtkJp5qJG9KxLHPUvIMG6A+7Yt O4Qw== X-Gm-Message-State: AHPjjUgkDxwA+ZvVtzqy9Ygw0iz2ErM9ZHx79jPbvN/bLPlcPooDwHJI jxJwIXmlaTS1gFQC37DCcloL5QgZf5A= X-Google-Smtp-Source: AOwi7QDgjaGB2Zcs7LgMkavUFlvW76mwCJMEyt6CkhbFreU+LtbODPKDFofc6F7lFNzMhwM+4DrmIA== X-Received: by 10.98.18.199 with SMTP id 68mr6228368pfs.94.1506655626943; Thu, 28 Sep 2017 20:27:06 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id g16sm5094376pfd.6.2017.09.28.20.27.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 28 Sep 2017 20:27:06 -0700 (PDT) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Fri, 29 Sep 2017 11:19:46 +0800 Message-Id: <1506655190-56231-8-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1506655190-56231-1-git-send-email-heyi.guo@linaro.org> References: <1506655190-56231-1-git-send-email-heyi.guo@linaro.org> Subject: [edk2] [PATCH edk2-platforms v5 07/11] D05/PCIe: Modify PcieRegionBase of secondary chip X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, ard.biesheuvel@linaro.org, zhangjinsong2@huawei.com, Heyi Guo , wanghuiqiang@huawei.com, guoheyi@huawei.com, waip23@126.com, mengfanrong@huawei.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" From: Ming Huang On D05 PCIe now, 2p NA PCIe2 and 2p NB PCIe0's pci domain addresses are 0x20000000 and 0x30000000 based. These addresses overlap with the DDR memory range 0-1G. In this situation, on the inbound direction, our pcie will drop the DDR address access that are located in the pci range window and lead to a dataflow error. Modify 2p NA PCIe2 and 2p NB PCIe0's pci domain addresses to 0x40000000 and decrease PciRegion Size accordingly. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Signed-off-by: Heyi Guo Reviewed-by: Leif Lindholm --- Platform/Hisilicon/D05/D05.dsc | 12 ++++++------ Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 8 ++++---- 2 files changed, 10 insertions(+), 10 deletions(-) -- 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc index 01defe0..64101a7 100644 --- a/Platform/Hisilicon/D05/D05.dsc +++ b/Platform/Hisilicon/D05/D05.dsc @@ -329,12 +329,12 @@ gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize|0xbf0000 gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress|0x400a9400000 gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize|0xbf0000 - gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress|0x20000000 - gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize|0xd0000000 + gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress|0x40000000 + gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize|0xb0000000 gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress|0x400ab400000 gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize|0xbf0000 - gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress|0x30000000 - gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize|0xc0000000 + gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress|0x40000000 + gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize|0xb0000000 gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress|0x40000000 gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize|0xb0000000 gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress|0x408aa400000 @@ -352,9 +352,9 @@ gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase|0x8B9800000 gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase|0x400A8400000 gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase|0x400A9400000 - gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase|0x65020000000 + gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase|0x65040000000 gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase|0x400AB400000 - gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase|0x75030000000 + gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase|0x75040000000 gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase|0x79040000000 gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase|0x408AA400000 gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase|0x408AB400000 diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl index 79267e5..55c7f50 100644 --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl @@ -646,10 +646,10 @@ Scope(_SB) Cacheable, ReadWrite, 0x0, // Granularity - 0x20000000, // Min Base Address + 0x40000000, // Min Base Address 0xefffffff, // Max Base Address 0x65000000000, // Translate - 0xd0000000 // Length + 0xb0000000 // Length ) QWordIO ( ResourceProducer, @@ -766,10 +766,10 @@ Scope(_SB) Cacheable, ReadWrite, 0x0, // Granularity - 0x30000000, // Min Base Address + 0x40000000, // Min Base Address 0xefffffff, // Max Base Address 0x75000000000, // Translate - 0xc0000000 // Length + 0xb0000000 // Length ) QWordIO ( ResourceProducer, From patchwork Fri Sep 29 03:19:47 2017 Content-Type: text/plain; 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[198.145.21.10]) by mx.google.com with ESMTPS id o12si2559374plk.182.2017.09.28.20.27.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 28 Sep 2017 20:27:12 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Z/eK1ta0; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id D4F1921E87967; Thu, 28 Sep 2017 20:23:55 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c00::229; helo=mail-pf0-x229.google.com; envelope-from=heyi.guo@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pf0-x229.google.com (mail-pf0-x229.google.com [IPv6:2607:f8b0:400e:c00::229]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id CC76720945B68 for ; Thu, 28 Sep 2017 20:23:54 -0700 (PDT) Received: by mail-pf0-x229.google.com with SMTP id d187so54313pfg.11 for ; Thu, 28 Sep 2017 20:27:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=axAqhG06bhdicOPruvqAk8NM/FW/iZgSUPSvmGntTrM=; b=Z/eK1ta0ktS3PNG4wd8mB4Ybks9LmoCTCOVfHj965o+/jhNjOxTfGigEAHKzNmM/bB KmaDT67le6CUYjRA1VdWql5eJS9x9TTMWMcKWuWhZ2dgogbdtejYMKGL44FemqTzzwm4 PZuYxlPYmqp+UVn//+BGFvH7WdPUxDuegJBV4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=axAqhG06bhdicOPruvqAk8NM/FW/iZgSUPSvmGntTrM=; b=gDTCYKPzL6LTRR6FJH6TlZs1Ks8vKq6ijQKblMRmAHcUXRjYClf9lu39LObPwJT/1B GIgiESdVid8bH03F6DnYjHI8ddZd1gMy+BYSg/ZWyQWRvhGREs/CVCg6B/Mh36TzjDO8 K7+SVSEhN5uWW11NvZuU2HXISzvVE7MUTxT/TX8PA9B3iF1aoWp1TQ5LrEaevOQnGc3v yfsOe/slRo7z5MN7uOHLkwNpLvKqGe+2EGIXh/rDEtHc2Sz7B18yt+2m9kGhlOmF/2k9 gK9Pa12bewqoL8vpsFLMb4lOAQ6FtEKz3/d3T8G6yv8yn1RGjddRxpldabwzteDAmjKg wV+A== X-Gm-Message-State: AHPjjUjxK+lCC2jv2R1d3E1EJbg1/lVCVHlTAy8sIA8IKlVnTbqvujhm eLUS309BYdkSeRqHKDxA8oufnA== X-Google-Smtp-Source: AOwi7QCsVZEuukZLYtnJLIME9Kz2A15Laot6mXLwFZ3FaYGDLQp0ssFQTTFytM/MMMtNqEON+sBMMA== X-Received: by 10.99.56.78 with SMTP id h14mr6039582pgn.192.1506655629864; Thu, 28 Sep 2017 20:27:09 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id g16sm5094376pfd.6.2017.09.28.20.27.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 28 Sep 2017 20:27:09 -0700 (PDT) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Fri, 29 Sep 2017 11:19:47 +0800 Message-Id: <1506655190-56231-9-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1506655190-56231-1-git-send-email-heyi.guo@linaro.org> References: <1506655190-56231-1-git-send-email-heyi.guo@linaro.org> Subject: [edk2] [PATCH edk2-platforms v5 08/11] Hisilicon/D03: Disable the function of PerfTuning X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, ard.biesheuvel@linaro.org, Chenhui Sun , zhangjinsong2@huawei.com, Heyi Guo , wanghuiqiang@huawei.com, guoheyi@huawei.com, waip23@126.com, mengfanrong@huawei.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" From: Chenhui Sun The PerTuning function is not stable, it will cause the LSI SAS 3008/3108 crash, disable this function first. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chenhui Sun Signed-off-by: Heyi Guo --- Platform/Hisilicon/D03/D03.dsc | 1 - Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf | 1 - Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 50 -------------------- Silicon/Hisilicon/HisiPkg.dec | 1 - 4 files changed, 53 deletions(-) -- 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/Hisilicon/D03/D03.dsc b/Platform/Hisilicon/D03/D03.dsc index fca6781..f2a120e 100644 --- a/Platform/Hisilicon/D03/D03.dsc +++ b/Platform/Hisilicon/D03/D03.dsc @@ -112,7 +112,6 @@ # It could be set FALSE to save size. gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE gHisiTokenSpaceGuid.PcdIsItsSupported|TRUE - gHisiTokenSpaceGuid.PcdIsPciPerfTuningEnable|TRUE [PcdsFixedAtBuild.common] gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"D03" diff --git a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf index ee9dbed..61b091f 100644 --- a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf +++ b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf @@ -55,7 +55,6 @@ [FeaturePcd] gHisiTokenSpaceGuid.PcdIsItsSupported - gHisiTokenSpaceGuid.PcdIsPciPerfTuningEnable [depex] TRUE diff --git a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c index 8ab7fa3..f420c91 100644 --- a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c +++ b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c @@ -315,50 +315,6 @@ PcieEnableItssm ( } -STATIC EFI_STATUS PciPerfTuning(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) -{ - UINT32 Value; - UINTN RegSegmentOffset; - - if (Port >= PCIE_MAX_ROOTBRIDGE) { - DEBUG((DEBUG_ERROR, "Invalid port number: %d\n", Port)); - return EFI_INVALID_PARAMETER; - } - - RegSegmentOffset = PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_SYS_REG_OFFSET; - - //Enable SMMU bypass for translation - RegRead(RegSegmentOffset + PCIE_SYS_CTRL13_REG, Value); - //BIT13: controller master read SMMU bypass - //BIT12: controller master write SMMU bypass - //BIT10: SMMU bypass enable - Value |= (BIT13 | BIT12 | BIT10); - RegWrite(RegSegmentOffset + PCIE_SYS_CTRL13_REG, Value); - - //Switch strongly order (SO) to relaxed order (RO) for write transaction - RegRead(RegSegmentOffset + PCIE_CTRL_6_REG, Value); - //BIT13 | BIT12: Enable write merge and SMMU streaming ordered write acknowledge - Value |= (BIT13 | BIT12); - //BIT29 | BIT27 | BIT25 | BIT23 | BIT21 | BIT19 | BIT17: Enable RO for all types of write transaction - Value |= (BIT29 | BIT27 | BIT25 | BIT23 | BIT21 | BIT19 | BIT17); - RegWrite(RegSegmentOffset + PCIE_CTRL_6_REG, Value); - - //Force streamID for controller read operation - RegRead(RegSegmentOffset + PCIE_SYS_CTRL54_REG, Value); - //Force using streamID in PCIE_SYS_CTRL54_REG - Value &= ~(BIT30); - //Set streamID to 0, bit[0:15] is for request ID and should be kept - Value &= ~(0xff << 16); - RegWrite(RegSegmentOffset + PCIE_SYS_CTRL54_REG, Value); - - //Enable read and write snoopy - RegRead(RegSegmentOffset + PCIE_SYS_CTRL19_REG, Value); - Value |= (BIT30 | BIT28); - RegWrite(RegSegmentOffset + PCIE_SYS_CTRL19_REG, Value); - - return EFI_SUCCESS; -} - EFI_STATUS PcieDisableItssm(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) { PCIE_CTRL_7_U pcie_ctrl7; @@ -1141,12 +1097,6 @@ PciePortInit ( DisableRcOptionRom (soctype, HostBridgeNum, PortIndex, PcieCfg->PortInfo.PortType); /* assert LTSSM enable */ (VOID)PcieEnableItssm (soctype, HostBridgeNum, PortIndex, PcieCfg); - if (FeaturePcdGet(PcdIsPciPerfTuningEnable)) { - //PCIe will still work even if performance tuning fails, - //and there is warning message inside the function to print - //detailed error if there is. - (VOID)PciPerfTuning(soctype, HostBridgeNum, PortIndex); - } PcieConfigContextHi1610(soctype, HostBridgeNum, PortIndex); /* diff --git a/Silicon/Hisilicon/HisiPkg.dec b/Silicon/Hisilicon/HisiPkg.dec index 2c02e14..81ba3be 100644 --- a/Silicon/Hisilicon/HisiPkg.dec +++ b/Silicon/Hisilicon/HisiPkg.dec @@ -274,7 +274,6 @@ [PcdsFeatureFlag] gHisiTokenSpaceGuid.PcdIsItsSupported|FALSE|BOOLEAN|0x00000065 - gHisiTokenSpaceGuid.PcdIsPciPerfTuningEnable|FALSE|BOOLEAN|0x00000066 From patchwork Fri Sep 29 03:19:48 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 114484 Delivered-To: patch@linaro.org Received: by 10.140.104.133 with SMTP id a5csp312443qgf; Thu, 28 Sep 2017 20:27:15 -0700 (PDT) X-Received: by 10.84.216.75 with SMTP id f11mr5730422plj.236.1506655635696; Thu, 28 Sep 2017 20:27:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506655635; cv=none; d=google.com; s=arc-20160816; b=a1o9YEYY7W0/+8TzTJwjPkjryRuvsfuT3KtRMbBVCAmzp0GimSC4aQJxuYKdsFHrVz LtLscg5rlUQxivjoijkbmtEuA68PweXQ+3pmhSMSJzKkUkkvFdkuDwAkBpYYB15sOWqB FLUOpJbJV9PAbawzozdEYbNpdZv2o/0M2kyo9iIw1JQl4tXWxP6xsLxnCfRismpFTFNo 84M4btdJC4iHMaU8a/6j0v3VnqewVAc2lCvt0uH84VZXh72DHvUOWxuSa5SEc7WwCYBX uUz3wWlIUr4Bb2G6g0/hWT+jm9cKd5WlvnY/j+ekTCbo4lQWsVuEoK/+JQHgZscbDLfM CMPQ== ARC-Message-Signature: i=1; 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[198.145.21.10]) by mx.google.com with ESMTPS id p14si2498730pgq.58.2017.09.28.20.27.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 28 Sep 2017 20:27:15 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=N0vLRWTa; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 1B49221F2AF6F; Thu, 28 Sep 2017 20:23:59 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c05::230; helo=mail-pg0-x230.google.com; envelope-from=heyi.guo@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pg0-x230.google.com (mail-pg0-x230.google.com [IPv6:2607:f8b0:400e:c05::230]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 90FB120945B68 for ; Thu, 28 Sep 2017 20:23:57 -0700 (PDT) Received: by mail-pg0-x230.google.com with SMTP id v3so78611pgv.3 for ; Thu, 28 Sep 2017 20:27:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=exre81a1AbEQtMN4xKwQBYjPZ5EuS2E53io48RpM9dU=; b=N0vLRWTa59S2x4qcOTMm9njiDoeX8+QvT7ZXIh7Q5ONPQwtAmBDAw6UXuNPn3d9QjI 5TSfY/vvnRADmIpW9CUQs5ZhR0mCa3NCvPMLgiPAbYU856hQ4vvxN5C22or/7XQusa4J MNqtAuGg30MCzAy2Jkm3EoqzrKMMfbvLnlxBk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=exre81a1AbEQtMN4xKwQBYjPZ5EuS2E53io48RpM9dU=; b=JI7l25lE6cfANqoqBVKvWXOFeu3iX4la9sQMSLIGty7+qxGMTx1lVzVntmPLdD8DtN 8dsWfG7uv0KINxe7duRQji8BHB1BLHLWEkgPjhvYG5CnwQtQ4q2j4mHPux7daSXlxJ30 jmpnLXaILZfpjXLtAGNedSVN9KVsKOayYmMM1vOlAHxJ/kr5o1H49/uGOJBx4qbPmYOs POZ3Uxvb0w2eMekN5TBLxbBzBx6FhsGQXoBbbrxfdXl1HiPlBd+Fjra9qB3s5Rk5Yliv wf/69fOiAtyZvF7AJJpHZaNt3e9SZ+8MRuBqAw06eh8XZqOIz8u+klB8/fUJEBkLzIkG 5r4g== X-Gm-Message-State: AHPjjUhB9JuHmbbR8nI4egxFJeNbVStZGy+0fQ2szitUgXlnbdp/kG1c RDAZmpyeEEKPVM4qHQIlnrT7+fexznM= X-Google-Smtp-Source: AOwi7QBjLDy/M5jsmisp+js8AkgNO82gwGtHH7WujfVN6Z6gvZou/c4YeChZ938r7izv+v1WUNy3ZQ== X-Received: by 10.84.179.65 with SMTP id a59mr5758165plc.162.1506655632709; Thu, 28 Sep 2017 20:27:12 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id g16sm5094376pfd.6.2017.09.28.20.27.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 28 Sep 2017 20:27:12 -0700 (PDT) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Fri, 29 Sep 2017 11:19:48 +0800 Message-Id: <1506655190-56231-10-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1506655190-56231-1-git-send-email-heyi.guo@linaro.org> References: <1506655190-56231-1-git-send-email-heyi.guo@linaro.org> Subject: [edk2] [PATCH edk2-platforms v5 09/11] D05/ACPI: Disable D05 SAS0 and SAS2 X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, ard.biesheuvel@linaro.org, zhangjinsong2@huawei.com, Heyi Guo , wanghuiqiang@huawei.com, guoheyi@huawei.com, waip23@126.com, mengfanrong@huawei.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" From: Ming Huang There is no interface from SAS0 or SAS2 controller on D05, so SAS0 and SAS2 can't be used. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Signed-off-by: Heyi Guo --- Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl | 10 ++++++++++ 1 file changed, 10 insertions(+) -- 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl index 93beb95..6455130 100644 --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl @@ -88,6 +88,11 @@ Scope(_SB) Store(0x7ffff, CLK) Sleep(1) } + + Method (_STA, 0, NotSerialized) + { + Return (0x0) + } } Device(SAS1) { @@ -239,6 +244,11 @@ Scope(_SB) Store(0x7ffff, CLK) Sleep(1) } + + Method (_STA, 0, NotSerialized) + { + Return (0x0) + } } } From patchwork Fri Sep 29 03:19:49 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 114485 Delivered-To: patch@linaro.org Received: by 10.140.104.133 with SMTP id a5csp312476qgf; Thu, 28 Sep 2017 20:27:19 -0700 (PDT) X-Received: by 10.99.109.13 with SMTP id i13mr6131020pgc.349.1506655638953; Thu, 28 Sep 2017 20:27:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506655638; cv=none; d=google.com; s=arc-20160816; b=pRbvgabOnGGgU2TydVkE2fvpPaQroHZCAyYaJ+pYH2HlMnm6dhBRqI+ZywXOdg6xvX v43nw7s1pX4EcqdbDDTVcs/NDl7q5+uh+x0FNBHusa7sS4mlFaIRQyCYBfUe6c9hlq5/ wejUTs3oP0YiZkMhlAt5FpbCwr6bs0toFzTiZS91b7F3nSOv6lgLDt+u968oDt/hs52+ f9nXBD0e2r3/13YbEpTmjve5JsoT6GYsB35/im5GWg17QbZ4iqZJb9eMxk4yLpRZz1Ts 3Uxl23QnOJGjucifmfN2qXxHK6EhtMBdOAd5XtZbneZvxsbpq7ybH0zaTEjEs1D3V/RT AM7w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=w8MVonfqXE6IQ31ajNaCxe+QY2WsBtk+1kSFw3Wxp9Q=; b=UNQS3gF8UlBdA/wj5QCoeCDExFDPVh3Qbah+qhkqpdWZHIjVLuTMJEzh74CB8cvt1U JhROIC9QJqYp9/xTd31FWzL9Snlpn3AHLDBlgxYBd1Wnz67qbxOhoi6tKcpCwQM3VSgk DkJTsFanfZMQrjHCM1mXzP0LiwtUcndpls4t5l40+zzVM97S0j2G+JfMEDMPi2Gi36hj BOZUQk6O3pOWGpCmzO+3ZzVFJk/5WlwUOiIhd+zqKD5As+DJQZih/J8oAYmqtZvJZE+U hrL+W3SXEHHNM7mO8lQ2BQUrx5hUcMzglb/iamtDN34+UmRcxJuej/udSCAnWbOf/146 s03A== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=NdIwH3ie; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [2001:19d0:306:5::1]) by mx.google.com with ESMTPS id z5si559069plh.373.2017.09.28.20.27.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 28 Sep 2017 20:27:18 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=NdIwH3ie; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 551D121F2AF74; Thu, 28 Sep 2017 20:24:02 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c05::234; helo=mail-pg0-x234.google.com; envelope-from=heyi.guo@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pg0-x234.google.com (mail-pg0-x234.google.com [IPv6:2607:f8b0:400e:c05::234]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 42E0020945B68 for ; Thu, 28 Sep 2017 20:24:00 -0700 (PDT) Received: by mail-pg0-x234.google.com with SMTP id j16so81519pga.1 for ; Thu, 28 Sep 2017 20:27:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=osmWHjelq3fYM3lm8AbMvOO1rb3nAbS0MjB+HfsJ3b0=; b=NdIwH3iek/ahE7+886T3I97Xv8tnOWn0VcXoM9IqwXFijrNi0jrNjygQrRz9OCGOXD QNwrvk52z2NCkY7JtdRuSKLDoTVpJKLKtz6FOUn3iGaAHNSLHJV4nlrhg/rRmoS4Jylu PVq0ZuOJy+q5N8WZBANXGcBRvHJvt5TuYw5RM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=osmWHjelq3fYM3lm8AbMvOO1rb3nAbS0MjB+HfsJ3b0=; b=lN+rWUCm5vj9ZqoH53wUWpFHHaWPH3XRJZagJIMxjQjbIPcYuH7eVDGIV4Ly9blbn4 owRqWQHj1Fd64T8BgljmZJvJXW6mulBZW/o27kMKxFvxTG/Qlq9PKXeOt6hrl1HyJ1AQ ++rn2fcOf7VRnsjtGcTSPK1D0k6RI6/Tk4ekB/jPJWJZZaPzr2x8EtM62bhaMbGRG2Bk Eeu2yidsZo7r0P9hHWlNP3oZuNzyqnhWbuR2GGUxIplo0WXZSZSMt/cR4rw5evfnpEer L2TvSvH20ih0aGeIdUL5qQiyEr+HBiUvQ/sNp4qiXKmbSjzTly69im6J2AUJjwfMu3li jpNQ== X-Gm-Message-State: AHPjjUiClD6iri+8gTcEoRig45+2zvaCrst0OUEdiiiYVA2u2345UfRf WfqNPAxQQroN/Qg4mOJ4IUEqwg== X-Google-Smtp-Source: AOwi7QCeeXXr5vYeprRYeCuEj5WKdkpa3Ps9rp+bLb+xarH+qt7W8LonrVnKA0Y6teEYXWqUeHC6ZQ== X-Received: by 10.84.215.22 with SMTP id k22mr5527819pli.284.1506655635466; Thu, 28 Sep 2017 20:27:15 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id g16sm5094376pfd.6.2017.09.28.20.27.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 28 Sep 2017 20:27:14 -0700 (PDT) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Fri, 29 Sep 2017 11:19:49 +0800 Message-Id: <1506655190-56231-11-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1506655190-56231-1-git-send-email-heyi.guo@linaro.org> References: <1506655190-56231-1-git-send-email-heyi.guo@linaro.org> Subject: [edk2] [PATCH edk2-platforms v5 10/11] D05/ACPI: Modify I2C device X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, ard.biesheuvel@linaro.org, zhangjinsong2@huawei.com, Heyi Guo , wanghuiqiang@huawei.com, guoheyi@huawei.com, waip23@126.com, mengfanrong@huawei.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" From: Ming Huang 1. Disable I2C0 device avoiding access conflict in OS, for it is used by UEFI to access DS3231 RTC chip and provide time services; 2. Modify _HID of I2C2 for matching the string in OS driver; Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Signed-off-by: Heyi Guo --- Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl | 20 +------------------- 1 file changed, 1 insertion(+), 19 deletions(-) -- 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl index eb906ef..3cc60d1 100644 --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl @@ -18,26 +18,8 @@ Scope(_SB) { - Device(I2C0) { - Name(_HID, "APMC0D0F") - Name(_CID, "APMC0D0F") - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xd00e0000, 0x10000) - Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI6") { 705 } - }) - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"clock-frequency", 100000}, - Package () {"i2c-sda-falling-time-ns", 913}, - Package () {"i2c-scl-falling-time-ns", 303}, - Package () {"i2c-sda-hold-time-ns", 0x9c2}, - } - }) - } - Device(I2C2) { - Name(_HID, "APMC0D0F") + Name(_HID, "HISI02A1") Name(_CID, "APMC0D0F") Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xd0100000, 0x10000) From patchwork Fri Sep 29 03:19:50 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 114486 Delivered-To: patch@linaro.org Received: by 10.140.104.133 with SMTP id a5csp312511qgf; Thu, 28 Sep 2017 20:27:22 -0700 (PDT) X-Received: by 10.101.66.74 with SMTP id d10mr6024375pgq.435.1506655642235; Thu, 28 Sep 2017 20:27:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506655642; cv=none; d=google.com; s=arc-20160816; b=nqrAwd1mNA2V0RkX082KtpboO8CcRkambxe+o3iJNr1wd1gMEuq7PbzJ2Z4QNeaGrS 8E5L86KAcAmUkgS5ohq6CTkpihWHn5gQzpcUOmC4dEQgWR9CbdtQNcMYHCaUj01fB1aM NXPV/DpD56kXEzY9WXXzZK01rH9ZzHJBD+yhFfPRdERcdfXPZLFyPxDuUMVapPVBJqST UNAvJH8bB8GaO4iWfAsj+GWk5aMNAbwWj/XBnizH9KqYk8B9f2v5EL4HFLGKL5UttpqK G8w7jHPbwcw47FKkH8CrAjjcAVgvs8i6GGDxmW3KkfaxAV7XsuzEP22YBGYxQngNQ3uh lCHA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=y3+WX/dqiracxQ1N1KtFmrBTkpXQUcjcLCVj1Wmx10Q=; b=Wbn2qwXisBp7JSmxf8J1lBdyGA2mOSLe22c+YsxPulAXCHfs5U38D331iG2iv2Ac0K mepTxd3YlSe1WU+XYC3zjvppiBwB6Z2U0EjrGYHxswjK/sxELFlV4vachHCcNcOBB+Vx H01pZeDH99+rGj6ZTjOJE5cTc1TgB+aIY6aPqtoD2/Ihg1sdnfwpVZhqtaPOH8cRTrKJ tnCwDGiFA1SQGZSKo9nq8ARlntJ4siwZSszKJU8PBdse4dE8ZRQU8gAbnlxNR4LMzjcm PfogOsi32bXuhIW7BKUElvEMmgqlKCOAzUmwWZq7FlpI5JpfsHPin2VWvzm3/2DmH50S JaLg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=HFSOwsVb; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. 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X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, ard.biesheuvel@linaro.org, zhangjinsong2@huawei.com, Heyi Guo , wanghuiqiang@huawei.com, guoheyi@huawei.com, waip23@126.com, mengfanrong@huawei.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" From: Jason zhang 1. Because Hi161x chip doesn't support "ARI Forwarding Enable" function, BIOS will enumerate 32 same devices (Device Number 0~31) when a Non-ARI capable device attached in the RP. Hi161x chip will not fix it, need BIOS patch. 2. Just enlarge iatu for those root port with ARI capable device attached, Non-ARI capable device's RP, keep iatu limitation. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jason zhang Signed-off-by: Heyi Guo --- Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c | 1 + Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h | 7 ++ Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 79 ++++++++++++++++++++ 3 files changed, 87 insertions(+) -- 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c index e3d3988..9fa3f84 100644 --- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c +++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c @@ -839,6 +839,7 @@ NotifyPhase( case EfiPciHostBridgeEndEnumeration: PCIE_DEBUG("Case EfiPciHostBridgeEndEnumeration\n"); + EnlargeAtuConfig0 (This); break; case EfiPciHostBridgeBeginBusAllocation: diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h index cddda6b..c04361f 100644 --- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h +++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h @@ -401,6 +401,9 @@ PreprocessController ( #define EFI_RESOURCE_NONEXISTENT 0xFFFFFFFFFFFFFFFFULL #define EFI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL +#define INVALID_CAPABILITY_00 0x00 +#define INVALID_CAPABILITY_FF 0xFF +#define PCI_CAPABILITY_POINTER_MASK 0xFC // // Driver Instance Data Prototypes @@ -518,4 +521,8 @@ RootBridgeConstructor ( IN UINT32 Seg ); +VOID +EnlargeAtuConfig0 ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This + ); #endif diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c index 10d766a..b57bd51 100644 --- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c @@ -14,6 +14,7 @@ **/ #include "PciHostBridge.h" +#include #include #include #include @@ -2322,3 +2323,81 @@ RootBridgeIoConfiguration ( return EFI_SUCCESS; } +BOOLEAN +PcieCheckAriFwdEn ( + UINTN PciBaseAddr + ) +{ + UINT8 PciPrimaryStatus; + UINT8 CapabilityOffset; + UINT8 CapId; + UINT8 TempData; + + PciPrimaryStatus = MmioRead16 (PciBaseAddr + PCI_PRIMARY_STATUS_OFFSET); + + if (PciPrimaryStatus & EFI_PCI_STATUS_CAPABILITY) { + CapabilityOffset = MmioRead8 (PciBaseAddr + PCI_CAPBILITY_POINTER_OFFSET); + CapabilityOffset &= PCI_CAPABILITY_POINTER_MASK; + + while ((CapabilityOffset != INVALID_CAPABILITY_00) && (CapabilityOffset != INVALID_CAPABILITY_FF)) { + CapId = MmioRead8 (PciBaseAddr + CapabilityOffset); + if (CapId == EFI_PCI_CAPABILITY_ID_PCIEXP) { + break; + } + CapabilityOffset = MmioRead8 (PciBaseAddr + CapabilityOffset + 1); + CapabilityOffset &= PCI_CAPABILITY_POINTER_MASK; + } + } else { + PCIE_DEBUG ("[%a:%d] - No PCIE Capability.\n", __FUNCTION__, __LINE__); + return FALSE; + } + + if ((CapabilityOffset == INVALID_CAPABILITY_FF) || (CapabilityOffset == INVALID_CAPABILITY_00)) { + PCIE_DEBUG ("[%a:%d] - No PCIE Capability.\n", __FUNCTION__, __LINE__); + return FALSE; + } + + TempData = MmioRead16 (PciBaseAddr + CapabilityOffset + + EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET); + TempData &= EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING; + + if (TempData == EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING) { + return TRUE; + } else { + return FALSE; + } +} + +VOID +EnlargeAtuConfig0 ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This + ) +{ + UINTN RbPciBase; + UINT64 MemLimit; + LIST_ENTRY *List; + PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance; + PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; + + PCIE_DEBUG ("In Enlarge RP iatu Config 0.\n"); + + HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); + List = HostBridgeInstance->Head.ForwardLink; + + while (List != &HostBridgeInstance->Head) { + PCIE_DEBUG ("HostBridge has data.\n"); + RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List); + + RbPciBase = RootBridgeInstance->RbPciBar; + + // Those ARI FWD Enable Root Bridge, need enlarge iatu window. + if (PcieCheckAriFwdEn (RbPciBase)) { + MemLimit = GetPcieCfgAddress (RootBridgeInstance->Ecam, + RootBridgeInstance->BusBase + 2, 0, 0, 0) + - 1; + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, 1); + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit); + } + List = List->ForwardLink; + } +}