From patchwork Fri Jul 3 20:13:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Antonio Tessarolo X-Patchwork-Id: 240726 List-Id: U-Boot discussion From: anthonytexdev at gmail.com (Antonio Tessarolo) Date: Fri, 3 Jul 2020 22:13:41 +0200 Subject: [PATCH 1/1] arm-freescale-mx6sx: Fix imx6sx UART5 wrong iomux register configuration Message-ID: This patch fixes a wrong IOMUX configuration for UART5_TX of NXP?s IMX6SX --- arch/arm/include/asm/arch-mx6/mx6sx_pins.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) IOMUX_PAD(0x05DC, 0x0294, 2, 0x0000, 0, 0), MX6_PAD_SD4_DATA5__ECSPI3_MOSI = IOMUX_PAD(0x05DC, 0x0294, 3, 0x0738, 0, 0), MX6_PAD_SD4_DATA5__LCDIF2_DATA_7 = IOMUX_PAD(0x05DC, 0x0294, 4, 0x0000, 0, 0), MX6_PAD_SD4_DATA5__GPIO6_IO_19 = IOMUX_PAD(0x05DC, 0x0294, 5, 0x0000, 0, 0), diff --git a/arch/arm/include/asm/arch-mx6/mx6sx_pins.h b/arch/arm/include/asm/arch-mx6/mx6sx_pins.h index a18e08f65c..f5c8bbf0a1 100644 --- a/arch/arm/include/asm/arch-mx6/mx6sx_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6sx_pins.h @@ -1615,7 +1615,7 @@ enum { MX6_PAD_SD4_DATA5__USDHC4_DATA5 = IOMUX_PAD(0x05DC, 0x0294, 0, 0x0000, 0, 0), MX6_PAD_SD4_DATA5__RAWNAND_CE2_B = IOMUX_PAD(0x05DC, 0x0294, 1, 0x0000, 0, 0), - MX6_PAD_SD4_DATA5__UART5_TX = IOMUX_PAD(0x05DC, 0x0294, 2, 0x0850, 1, 0), + MX6_PAD_SD4_DATA5__UART5_TX =