From patchwork Fri Jun 5 08:20:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Tan, Ley Foon" X-Patchwork-Id: 241767 List-Id: U-Boot discussion From: ley.foon.tan at intel.com (Ley Foon Tan) Date: Fri, 5 Jun 2020 16:20:09 +0800 Subject: [PATCH] arm: socfpga: gen5: Enable cache driver in SPL Message-ID: <20200605082009.175720-1-ley.foon.tan@intel.com> Adding "u-boot,dm-pre-reloc" and enable CONFIG_SPL_CACHE to enable cache driver in SPL. This fixed error below in SPL: cache controller driver NOT found! Signed-off-by: Ley Foon Tan --- arch/arm/dts/socfpga-common-u-boot.dtsi | 4 ++++ arch/arm/mach-socfpga/Kconfig | 1 + 2 files changed, 5 insertions(+) diff --git a/arch/arm/dts/socfpga-common-u-boot.dtsi b/arch/arm/dts/socfpga-common-u-boot.dtsi index d55460755fe3..f65aca6ebaba 100644 --- a/arch/arm/dts/socfpga-common-u-boot.dtsi +++ b/arch/arm/dts/socfpga-common-u-boot.dtsi @@ -14,6 +14,10 @@ u-boot,dm-pre-reloc; }; +&L2 { + u-boot,dm-pre-reloc; +}; + &rst { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index a3699e82a19e..1173422b8f28 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -67,6 +67,7 @@ config TARGET_SOCFPGA_CYCLONE5 config TARGET_SOCFPGA_GEN5 bool select SPL_ALTERA_SDRAM + select SPL_CACHE if SPL imply FPGA_SOCFPGA imply SPL_SIZE_LIMIT_SUBTRACT_GD imply SPL_SIZE_LIMIT_SUBTRACT_MALLOC