From patchwork Thu Jun 11 11:03:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 242124 List-Id: U-Boot discussion From: andre.przywara at arm.com (Andre Przywara) Date: Thu, 11 Jun 2020 12:03:15 +0100 Subject: [PATCH 1/7] arm: vexpress64: Fix counter frequency In-Reply-To: <20200611110321.9574-1-andre.przywara@arm.com> References: <20200611110321.9574-1-andre.przywara@arm.com> Message-ID: <20200611110321.9574-2-andre.przywara@arm.com> The arch timer on 64-bit Arm Ltd. platforms is driven by a 24 MHz crystal oscillator, so the frequency is not 25165824 MHz, as the current code suggests. Signed-off-by: Andre Przywara Reviewed-by: Linus Walleij --- include/configs/vexpress_aemv8a.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h index 09cdd3dab5..e63c335f85 100644 --- a/include/configs/vexpress_aemv8a.h +++ b/include/configs/vexpress_aemv8a.h @@ -68,7 +68,7 @@ #define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8) /* Generic Timer Definitions */ -#define COUNTER_FREQUENCY (0x1800000) /* 24MHz */ +#define COUNTER_FREQUENCY 24000000 /* 24MHz */ /* Generic Interrupt Controller Definitions */ #ifdef CONFIG_GICV3 From patchwork Thu Jun 11 11:03:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 242125 List-Id: U-Boot discussion From: andre.przywara at arm.com (Andre Przywara) Date: Thu, 11 Jun 2020 12:03:16 +0100 Subject: [PATCH 2/7] net: dm: Remove warning about EEPROM provided MAC address In-Reply-To: <20200611110321.9574-1-andre.przywara@arm.com> References: <20200611110321.9574-1-andre.przywara@arm.com> Message-ID: <20200611110321.9574-3-andre.przywara@arm.com> Similar to patch 821fec0ceb3e ("net: remove scary warning about EEPROM provided MAC address") this removes the somewhat awkward "warning" on boards using DM_ETH: In many parts of the computing world having a unique MAC address sitting in some on-NIC storage is considered the normal case. If there is a properly provided MAC address (either from ROM or from DT), remove the warning to not scare the user unnecessarily. Signed-off-by: Andre Przywara Reviewed-By: Ramon Fried Reviewed-by: Linus Walleij --- net/eth-uclass.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/net/eth-uclass.c b/net/eth-uclass.c index 7f89f65c92..0d9b75a9a2 100644 --- a/net/eth-uclass.c +++ b/net/eth-uclass.c @@ -560,8 +560,6 @@ static int eth_post_probe(struct udevice *dev) memcpy(pdata->enetaddr, env_enetaddr, ARP_HLEN); } else if (is_valid_ethaddr(pdata->enetaddr)) { eth_env_set_enetaddr_by_index("eth", dev->seq, pdata->enetaddr); - printf("\nWarning: %s using MAC address from %s\n", - dev->name, source); } else if (is_zero_ethaddr(pdata->enetaddr) || !is_valid_ethaddr(pdata->enetaddr)) { #ifdef CONFIG_NET_RANDOM_ETHADDR From patchwork Thu Jun 11 11:03:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 242126 List-Id: U-Boot discussion From: andre.przywara at arm.com (Andre Przywara) Date: Thu, 11 Jun 2020 12:03:17 +0100 Subject: [PATCH 3/7] net: smc911x: Properly handle EEPROM MAC address In-Reply-To: <20200611110321.9574-1-andre.przywara@arm.com> References: <20200611110321.9574-1-andre.przywara@arm.com> Message-ID: <20200611110321.9574-4-andre.przywara@arm.com> When compiled as a DM_ETH driver, the scm911x driver was reading the MAC address from the optional EEPROM storage, but failed to copy this to the platdata struct. Since it was also missing a definition of the read_rom_hwaddr() function, the generic Ethernet code was dismissing this MAC address, falling back to a random address or denying to start at all. Add an implementation of .read_rom_hwaddr, and refactor the function reading the ROM address to be called by all interested parties. This fixes MAC address issues when using the driver in DM_ETH "mode". Signed-off-by: Andre Przywara Reviewed-By: Ramon Fried Reviewed-by: Linus Walleij --- drivers/net/smc911x.c | 60 ++++++++++++++++++++++++++----------------- 1 file changed, 36 insertions(+), 24 deletions(-) diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c index 9d2790e561..053ff9f4ff 100644 --- a/drivers/net/smc911x.c +++ b/drivers/net/smc911x.c @@ -187,6 +187,26 @@ static void smc911x_handle_mac_address(struct smc911x_priv *priv) printf(DRIVERNAME ": MAC %pM\n", m); } +static bool smc911x_read_mac_address(struct smc911x_priv *priv) +{ + u32 addrh, addrl; + + /* address is obtained from optional eeprom */ + addrh = smc911x_get_mac_csr(priv, ADDRH); + addrl = smc911x_get_mac_csr(priv, ADDRL); + if (addrl == 0xffffffff && addrh == 0x0000ffff) + return false; + + priv->enetaddr[0] = addrl; + priv->enetaddr[1] = addrl >> 8; + priv->enetaddr[2] = addrl >> 16; + priv->enetaddr[3] = addrl >> 24; + priv->enetaddr[4] = addrh; + priv->enetaddr[5] = addrh >> 8; + + return true; +} + static int smc911x_eth_phy_read(struct smc911x_priv *priv, u8 phy, u8 reg, u16 *val) { @@ -471,7 +491,6 @@ static int smc911x_recv(struct eth_device *dev) int smc911x_initialize(u8 dev_num, int base_addr) { - unsigned long addrl, addrh; struct smc911x_priv *priv; int ret; @@ -489,18 +508,8 @@ int smc911x_initialize(u8 dev_num, int base_addr) goto err_detect; } - addrh = smc911x_get_mac_csr(priv, ADDRH); - addrl = smc911x_get_mac_csr(priv, ADDRL); - if (!(addrl == 0xffffffff && addrh == 0x0000ffff)) { - /* address is obtained from optional eeprom */ - priv->enetaddr[0] = addrl; - priv->enetaddr[1] = addrl >> 8; - priv->enetaddr[2] = addrl >> 16; - priv->enetaddr[3] = addrl >> 24; - priv->enetaddr[4] = addrh; - priv->enetaddr[5] = addrh >> 8; + if (smc911x_read_mac_address(priv)) memcpy(priv->dev.enetaddr, priv->enetaddr, 6); - } priv->dev.init = smc911x_init; priv->dev.halt = smc911x_halt; @@ -565,6 +574,19 @@ static int smc911x_recv(struct udevice *dev, int flags, uchar **packetp) return ret ? ret : -EAGAIN; } +static int smc911x_read_rom_hwaddr(struct udevice *dev) +{ + struct smc911x_priv *priv = dev_get_priv(dev); + struct eth_pdata *pdata = dev_get_platdata(dev); + + if (!smc911x_read_mac_address(priv)) + return -ENODEV; + + memcpy(pdata->enetaddr, priv->enetaddr, sizeof(pdata->enetaddr)); + + return 0; +} + static int smc911x_bind(struct udevice *dev) { return device_set_name(dev, dev->name); @@ -573,7 +595,6 @@ static int smc911x_bind(struct udevice *dev) static int smc911x_probe(struct udevice *dev) { struct smc911x_priv *priv = dev_get_priv(dev); - unsigned long addrh, addrl; int ret; /* Try to detect chip. Will fail if not present. */ @@ -581,17 +602,7 @@ static int smc911x_probe(struct udevice *dev) if (ret) return ret; - addrh = smc911x_get_mac_csr(priv, ADDRH); - addrl = smc911x_get_mac_csr(priv, ADDRL); - if (!(addrl == 0xffffffff && addrh == 0x0000ffff)) { - /* address is obtained from optional eeprom */ - priv->enetaddr[0] = addrl; - priv->enetaddr[1] = addrl >> 8; - priv->enetaddr[2] = addrl >> 16; - priv->enetaddr[3] = addrl >> 24; - priv->enetaddr[4] = addrh; - priv->enetaddr[5] = addrh >> 8; - } + smc911x_read_rom_hwaddr(dev); return 0; } @@ -612,6 +623,7 @@ static const struct eth_ops smc911x_ops = { .send = smc911x_send, .recv = smc911x_recv, .stop = smc911x_stop, + .read_rom_hwaddr = smc911x_read_rom_hwaddr, }; static const struct udevice_id smc911x_ids[] = { From patchwork Thu Jun 11 11:03:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 242127 List-Id: U-Boot discussion From: andre.przywara at arm.com (Andre Przywara) Date: Thu, 11 Jun 2020 12:03:18 +0100 Subject: [PATCH 4/7] arm: juno: Enable DM_ETH In-Reply-To: <20200611110321.9574-1-andre.przywara@arm.com> References: <20200611110321.9574-1-andre.przywara@arm.com> Message-ID: <20200611110321.9574-5-andre.przywara@arm.com> The smc911X driver is now DM enabled, so we can switch the Juno board over to use DM_ETH for the on-board Fast Ethernet device. Works out of the box by using the DT. Signed-off-by: Andre Przywara Reviewed-by: Linus Walleij --- arch/arm/Kconfig | 2 +- board/armltd/vexpress64/vexpress64.c | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 21df1c415f..09a819c5fa 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1169,7 +1169,7 @@ config TARGET_VEXPRESS64_JUNO select DM_SERIAL select ARM_PSCI_FW select PSCI_RESET - select DM + select DM_ETH select BLK select USB select DM_USB diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c index fbfa7a18f1..5932a4a0c7 100644 --- a/board/armltd/vexpress64/vexpress64.c +++ b/board/armltd/vexpress64/vexpress64.c @@ -152,11 +152,13 @@ void reset_cpu(ulong addr) int board_eth_init(bd_t *bis) { int rc = 0; +#ifndef CONFIG_DM_ETH #ifdef CONFIG_SMC91111 rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); #endif #ifdef CONFIG_SMC911X rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); +#endif #endif return rc; } From patchwork Thu Jun 11 11:03:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 242129 List-Id: U-Boot discussion From: andre.przywara at arm.com (Andre Przywara) Date: Thu, 11 Jun 2020 12:03:19 +0100 Subject: [PATCH 5/7] sata_sil: Enable DM_PCI operation In-Reply-To: <20200611110321.9574-1-andre.przywara@arm.com> References: <20200611110321.9574-1-andre.przywara@arm.com> Message-ID: <20200611110321.9574-6-andre.przywara@arm.com> Even though the sata_sil driver was converted over to the driver model, it still assumed that the PCI controller is using the legacy interface. Allow the "devno" member to be a struct udevice pointer and use DM_PCI_COMPAT to covert the rest of the interface. Signed-off-by: Andre Przywara Reviewed-by: Linus Walleij --- drivers/ata/sata_sil.c | 11 ++++++++++- drivers/ata/sata_sil.h | 6 +++++- 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/ata/sata_sil.c b/drivers/ata/sata_sil.c index 6896fa8771..d5ba94c172 100644 --- a/drivers/ata/sata_sil.c +++ b/drivers/ata/sata_sil.c @@ -27,7 +27,11 @@ #include "sata_sil.h" +#ifdef CONFIG_DM_PCI +#define virt_to_bus(devno, v) dm_pci_virt_to_mem(devno, (void *) (v)) +#else #define virt_to_bus(devno, v) pci_virt_to_mem(devno, (void *) (v)) +#endif /* just compatible ahci_ops */ struct sil_ops { @@ -608,13 +612,18 @@ static int sil_init_sata(struct udevice *uc_dev, int dev) /* Save the private struct to block device struct */ #if !CONFIG_IS_ENABLED(BLK) sata_dev_desc[dev].priv = (void *)sata; + sata->devno = sata_info.devno; #else priv->sil_sata_desc[dev] = sata; priv->port_num = dev; +#ifdef CONFIG_DM_PCI + sata->devno = uc_dev->parent; +#else + sata->devno = sata_info.devno; +#endif /* CONFIG_DM_PCI */ #endif sata->id = dev; sata->port = port; - sata->devno = sata_info.devno; sprintf(sata->name, "SATA#%d", dev); sil_cmd_soft_reset(sata); tmp = readl(port + PORT_SSTATUS); diff --git a/drivers/ata/sata_sil.h b/drivers/ata/sata_sil.h index ef41e8259a..a300c0c388 100644 --- a/drivers/ata/sata_sil.h +++ b/drivers/ata/sata_sil.h @@ -21,7 +21,11 @@ struct sil_sata { u16 pio; u16 mwdma; u16 udma; - pci_dev_t devno; +#ifdef CONFIG_DM_PCI + struct udevice *devno; +#else + pci_dev_t devno; +#endif int wcache; int flush; int flush_ext; From patchwork Thu Jun 11 11:03:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 242130 List-Id: U-Boot discussion From: andre.przywara at arm.com (Andre Przywara) Date: Thu, 11 Jun 2020 12:03:20 +0100 Subject: [PATCH 6/7] arm: juno: Enable PCI In-Reply-To: <20200611110321.9574-1-andre.przywara@arm.com> References: <20200611110321.9574-1-andre.przywara@arm.com> Message-ID: <20200611110321.9574-7-andre.przywara@arm.com> The ARM Juno boards in their -r1 and -r2 variants sport a PCIe controller, which we configure already in board specific code to be ECAM compliant. Hence we can just enable the generic ECAM driver to let U-Boot use PCIe devices. Add the respective options to the Juno defconfig to enable the PCI framework and the generic ECAM driver, and initialise the driver upon loading U-Boot. Make some functions in the Juno PCIe init code static on the way. Signed-off-by: Andre Przywara Reviewed-by: Linus Walleij --- board/armltd/vexpress64/pcie.c | 14 +++++++++----- configs/vexpress_aemv8a_juno_defconfig | 5 +++++ 2 files changed, 14 insertions(+), 5 deletions(-) diff --git a/board/armltd/vexpress64/pcie.c b/board/armltd/vexpress64/pcie.c index 02de58b360..733b190e59 100644 --- a/board/armltd/vexpress64/pcie.c +++ b/board/armltd/vexpress64/pcie.c @@ -72,9 +72,9 @@ JUNO_RESET_STATUS_PHY | \ JUNO_RESET_STATUS_RC) -void xr3pci_set_atr_entry(unsigned long base, unsigned long src_addr, - unsigned long trsl_addr, int window_size, - int trsl_param) +static void xr3pci_set_atr_entry(unsigned long base, unsigned long src_addr, + unsigned long trsl_addr, int window_size, + int trsl_param) { /* X3PCI_ATR_SRC_ADDR_LOW: - bit 0: enable entry, @@ -94,7 +94,7 @@ void xr3pci_set_atr_entry(unsigned long base, unsigned long src_addr, ((u64)1) << window_size, trsl_param); } -void xr3pci_setup_atr(void) +static void xr3pci_setup_atr(void) { /* setup PCIe to CPU address translation tables */ unsigned long base = XR3_CONFIG_BASE + XR3PCI_ATR_PCIE_WIN0; @@ -141,7 +141,7 @@ void xr3pci_setup_atr(void) XR3_PCI_MEMSPACE64_SIZE, XR3PCI_ATR_TRSLID_PCIE_MEMORY); } -void xr3pci_init(void) +static void xr3pci_init(void) { u32 val; int timeout = 200; @@ -193,5 +193,9 @@ void xr3pci_init(void) void vexpress64_pcie_init(void) { + /* Initialise and configure the PCIe host bridge. */ xr3pci_init(); + + /* Register the now ECAM complaint PCIe host controller with U-Boot. */ + pci_init(); } diff --git a/configs/vexpress_aemv8a_juno_defconfig b/configs/vexpress_aemv8a_juno_defconfig index 49acb34310..4866a0e9d5 100644 --- a/configs/vexpress_aemv8a_juno_defconfig +++ b/configs/vexpress_aemv8a_juno_defconfig @@ -32,6 +32,11 @@ CONFIG_CMD_UBI=y # CONFIG_ISO_PARTITION is not set # CONFIG_EFI_PARTITION is not set CONFIG_OF_BOARD=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_PCIE_ECAM_GENERIC=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_CMD_PCI=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0xBFC0000 # CONFIG_MMC is not set From patchwork Thu Jun 11 11:03:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 242128 List-Id: U-Boot discussion From: andre.przywara at arm.com (Andre Przywara) Date: Thu, 11 Jun 2020 12:03:21 +0100 Subject: [PATCH 7/7] arm: juno: Enable SATA controller In-Reply-To: <20200611110321.9574-1-andre.przywara@arm.com> References: <20200611110321.9574-1-andre.przywara@arm.com> Message-ID: <20200611110321.9574-8-andre.przywara@arm.com> The ARM Juno boards (-r1 and -r2) feature a Silicon Image 3132 PCIe SATA controller soldered on the board, providing two SATA ports. Enable the driver and the sata command in the defconfig, to be able to load images from SATA disks. Tested by loading kernels and Grub/EFI from an SSD and successfully booting a Linux system (with and without using UEFI). Signed-off-by: Andre Przywara Reviewed-by: Linus Walleij --- configs/vexpress_aemv8a_juno_defconfig | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/configs/vexpress_aemv8a_juno_defconfig b/configs/vexpress_aemv8a_juno_defconfig index 4866a0e9d5..4654c529e8 100644 --- a/configs/vexpress_aemv8a_juno_defconfig +++ b/configs/vexpress_aemv8a_juno_defconfig @@ -29,14 +29,15 @@ CONFIG_CMD_USB=y CONFIG_CMD_CACHE=y # CONFIG_CMD_MISC is not set CONFIG_CMD_UBI=y -# CONFIG_ISO_PARTITION is not set -# CONFIG_EFI_PARTITION is not set CONFIG_OF_BOARD=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_PCIE_ECAM_GENERIC=y CONFIG_DM_PCI_COMPAT=y CONFIG_CMD_PCI=y +CONFIG_LIBATA=y +CONFIG_SATA_SIL=y +CONFIG_CMD_SATA=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0xBFC0000 # CONFIG_MMC is not set