From patchwork Fri Jun 26 12:39:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sagar Shrikant Kadam X-Patchwork-Id: 243011 List-Id: U-Boot discussion From: sagar.kadam at sifive.com (Sagar Shrikant Kadam) Date: Fri, 26 Jun 2020 05:39:18 -0700 Subject: [PATCH v6 1/4] riscv: dts: hifive-unleashed-a00: add cpu aliases In-Reply-To: <1593175161-26278-1-git-send-email-sagar.kadam@sifive.com> References: <1593175161-26278-1-git-send-email-sagar.kadam@sifive.com> Message-ID: <1593175161-26278-2-git-send-email-sagar.kadam@sifive.com> Add cpu aliases to U-Boot specific dtsi for hifive-unleashed. Without aliases we see that the CPU device sequence numbers are set randomly and the cpu list/detail command will show it as follows: => cpu list 1: cpu at 1 rv64imafdc 2: cpu at 2 rv64imafdc 3: cpu at 3 rv64imafdc 0: cpu at 4 rv64imafdc Seems like CPU probing with dm-model also relies on aliases as observed in case spi. The fu540-c000-u-boot.dtsi has cpu nodes and so adding corresponding aliases we can ensure that cpu devices are assigned proper sequence as follows: => cpu list 1: cpu at 1 rv64imafdc 2: cpu at 2 rv64imafdc 3: cpu at 3 rv64imafdc 4: cpu at 4 rv64imafdc Signed-off-by: Sagar Shrikant Kadam Reviewed-by: Pragnesh Patel Reviewed-by: Bin Meng --- arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi index 3038064..e037150 100644 --- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi +++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi @@ -8,6 +8,10 @@ / { aliases { + cpu1 = &cpu1; + cpu2 = &cpu2; + cpu3 = &cpu3; + cpu4 = &cpu4; spi0 = &qspi0; spi2 = &qspi2; }; From patchwork Fri Jun 26 12:39:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sagar Shrikant Kadam X-Patchwork-Id: 243012 List-Id: U-Boot discussion From: sagar.kadam at sifive.com (Sagar Shrikant Kadam) Date: Fri, 26 Jun 2020 05:39:19 -0700 Subject: [PATCH v6 2/4] uclass: cpu: fix to display proper CPU features In-Reply-To: <1593175161-26278-1-git-send-email-sagar.kadam@sifive.com> References: <1593175161-26278-1-git-send-email-sagar.kadam@sifive.com> Message-ID: <1593175161-26278-3-git-send-email-sagar.kadam@sifive.com> The cmd "cpu detail" fetches uninitialized cpu feature information and thus displays wrong / inconsitent details as below. For eg: FU540-C000 doesn't have any microcode, yet the cmd display's it. => cpu detail 1: cpu at 1 rv64imafdc ID = 1, freq = 999.100 MHz: L1 cache, MMU, Microcode, Device ID Microcode version 0x0 Device ID 0x0 2: cpu at 2 rv64imafdc ID = 2, freq = 999.100 MHz: L1 cache, MMU, Microcode, Device ID Microcode version 0x0 Device ID 0x0 3: cpu at 3 rv64imafdc ID = 3, freq = 999.100 MHz: L1 cache, MMU, Microcode, Device ID Microcode version 0x0 Device ID 0x0 4: cpu at 4 rv64imafdc ID = 4, freq = 999.100 MHz: L1 cache, MMU, Microcode, Device ID Microcode version 0x0 Device ID 0x0 The L1 cache or MMU entry seen above is also displayed inconsistently. So initialize cpu information to zero into cpu-uclass itself so that similar issues can be avoided for other CPU drivers. We now see correct features as: => cpu detail 1: cpu at 1 rv64imafdc ID = 1, freq = 999.100 MHz 2: cpu at 2 rv64imafdc ID = 2, freq = 999.100 MHz 3: cpu at 3 rv64imafdc ID = 3, freq = 999.100 MHz 4: cpu at 4 rv64imafdc ID = 4, freq = 999.100 MHz Signed-off-by: Sagar Shrikant Kadam Reviewed-by: Pragnesh Patel Reviewed-by: Bin Meng --- drivers/cpu/cpu-uclass.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/cpu/cpu-uclass.c b/drivers/cpu/cpu-uclass.c index 7418c26..9f4a8fd 100644 --- a/drivers/cpu/cpu-uclass.c +++ b/drivers/cpu/cpu-uclass.c @@ -83,6 +83,9 @@ int cpu_get_info(struct udevice *dev, struct cpu_info *info) { struct cpu_ops *ops = cpu_get_ops(dev); + /* Init cpu_info to 0 */ + memset(info, 0, sizeof(struct cpu_info)); + if (!ops->get_info) return -ENOSYS; From patchwork Fri Jun 26 12:39:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sagar Shrikant Kadam X-Patchwork-Id: 243013 List-Id: U-Boot discussion From: sagar.kadam at sifive.com (Sagar Shrikant Kadam) Date: Fri, 26 Jun 2020 05:39:20 -0700 Subject: [PATCH v6 3/4] riscv: cpu: correctly handle the setting of CPU_FEAT_MMU bit In-Reply-To: <1593175161-26278-1-git-send-email-sagar.kadam@sifive.com> References: <1593175161-26278-1-git-send-email-sagar.kadam@sifive.com> Message-ID: <1593175161-26278-4-git-send-email-sagar.kadam@sifive.com> The conditional check to read "mmu-type" from the device tree is not rightly handled due to which the cpu feature doesn't include CPU_FEAT_MMU even if it's corresponding entry is present in the device tree. The initialization of cpu features is now taken care in cpu-uclass driver, so no need to zero out cpu_freq in riscv_cpu driver and can be removed. Signed-off-by: Sagar Shrikant Kadam Reviewed-by: Pragnesh Patel Reviewed-by: Bin Meng --- drivers/cpu/riscv_cpu.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c index 76b0489..112690f 100644 --- a/drivers/cpu/riscv_cpu.c +++ b/drivers/cpu/riscv_cpu.c @@ -36,9 +36,6 @@ static int riscv_cpu_get_info(struct udevice *dev, struct cpu_info *info) struct clk clk; const char *mmu; - /* Zero out the frequency, in case sizeof(ulong) != sizeof(u32) */ - info->cpu_freq = 0; - /* First try getting the frequency from the assigned clock */ ret = clk_get_by_index(dev, 0, &clk); if (!ret) { @@ -52,7 +49,7 @@ static int riscv_cpu_get_info(struct udevice *dev, struct cpu_info *info) dev_read_u32(dev, "clock-frequency", (u32 *)&info->cpu_freq); mmu = dev_read_string(dev, "mmu-type"); - if (!mmu) + if (mmu) info->features |= BIT(CPU_FEAT_MMU); return 0; From patchwork Fri Jun 26 12:39:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sagar Shrikant Kadam X-Patchwork-Id: 243014 List-Id: U-Boot discussion From: sagar.kadam at sifive.com (Sagar Shrikant Kadam) Date: Fri, 26 Jun 2020 05:39:21 -0700 Subject: [PATCH v6 4/4] riscv: cpu: check and append L1 cache to cpu features In-Reply-To: <1593175161-26278-1-git-send-email-sagar.kadam@sifive.com> References: <1593175161-26278-1-git-send-email-sagar.kadam@sifive.com> Message-ID: <1593175161-26278-5-git-send-email-sagar.kadam@sifive.com> All cpu cores within FU540-C000 having split I/D caches. Set the L1 cache feature bit using the i-cache-size or d-cache-size as one of the property from device tree indicating that L1 cache is present on the cpu core. => cpu detail 1: cpu at 1 rv64imafdc ID = 1, freq = 999.100 MHz: L1 cache, MMU 2: cpu at 2 rv64imafdc ID = 2, freq = 999.100 MHz: L1 cache, MMU 3: cpu at 3 rv64imafdc ID = 3, freq = 999.100 MHz: L1 cache, MMU 4: cpu at 4 rv64imafdc ID = 4, freq = 999.100 MHz: L1 cache, MMU Signed-off-by: Sagar Shrikant Kadam Reviewed-by: Pragnesh Patel Reviewed-by: Bin Meng --- drivers/cpu/riscv_cpu.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c index 112690f..100fe55 100644 --- a/drivers/cpu/riscv_cpu.c +++ b/drivers/cpu/riscv_cpu.c @@ -35,6 +35,8 @@ static int riscv_cpu_get_info(struct udevice *dev, struct cpu_info *info) int ret; struct clk clk; const char *mmu; + u32 i_cache_size; + u32 d_cache_size; /* First try getting the frequency from the assigned clock */ ret = clk_get_by_index(dev, 0, &clk); @@ -52,6 +54,16 @@ static int riscv_cpu_get_info(struct udevice *dev, struct cpu_info *info) if (mmu) info->features |= BIT(CPU_FEAT_MMU); + /* check if I cache is present */ + ret = dev_read_u32(dev, "i-cache-size", &i_cache_size); + if (ret) + /* if not found check if d-cache is present */ + ret = dev_read_u32(dev, "d-cache-size", &d_cache_size); + + /* if either I or D cache is present set L1 cache feature */ + if (!ret) + info->features |= BIT(CPU_FEAT_L1_CACHE); + return 0; }