From patchwork Thu Oct 5 20:54:07 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Ripard X-Patchwork-Id: 115001 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp1015007qgn; Thu, 5 Oct 2017 13:54:40 -0700 (PDT) X-Google-Smtp-Source: AOwi7QDlCetKExsc9ctkW3a9I8s0DOf6gJXCkbDKfikNcWbThNfJP5FjgYtCVt8k1IX5XO9U5F2W X-Received: by 10.98.1.76 with SMTP id 73mr9898837pfb.314.1507236880032; Thu, 05 Oct 2017 13:54:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507236880; cv=none; d=google.com; s=arc-20160816; b=t0Y07V4J0Ywtsd8Yi3CrZnB68fNwk0ObKLp7OrrBCsQe53tsPx/ENz8j6Xklcg0fjO F8z/kOT798SQqc9OSU4Wq8gdLlV9yWCitJ2bRLcY+nqaLQ4qmZ2bT/sbncdTRIZUFSSc 3R7FbU6fZ+Tq6Q5N9WwkkQCWOrz+pherhQsZ1QWU2vc/Vfj4f4H8qILl8G2k0dQitkqT n3BtdROEzUjH/w86rAQM4DGJvL0Uq/sNVla9CbdhSDLSEAQAavLa4pwGtkWLKNjFKF6n UYucGxfu7CWBLOXkzFZ1YIAbZpVdm1J0kcrsMj7waPZvJEUdnWSofNXByElAM8kY+Wjo SiDg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=wMYYnu0q7XRlwRuoS0aLyKS6pXzP6s0x04DI3j1gxCU=; b=UNAFqFT3Pgakd+TSY0+Vu7wKsI2gRfhS2hAfqW7pTYFyWqqDwtjlEjpa9menhdYgWQ IHQPx7+C43Dq/xTE6iQG+pLxUX8noKucVO8QUebm/T80siMihz2PgMLzES8xqedu4Gde pRft9Tiv9rjyAB+NPRviOt7dAXWjmZcm5vsdfotF0QEgVAqCqkgfEjd61poVZN6pfjK7 omsJQS2VS+T0zQqEK0sCgEK7JNZnVNu3B++ZJBLLmWOwEZrppJSuKUNz22EAs+mY9WGD 9vJRYvF7b1843oJkXmEZJrk5gsl/iZ4Jb0m5YKMroSmbU7iSqU+OBYWM4aRu3JC2swqz oUfA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u59si6871954plb.707.2017.10.05.13.54.39; Thu, 05 Oct 2017 13:54:40 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752180AbdJEUyi (ORCPT + 26 others); Thu, 5 Oct 2017 16:54:38 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:32862 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751695AbdJEUyP (ORCPT ); Thu, 5 Oct 2017 16:54:15 -0400 Received: by mail.free-electrons.com (Postfix, from userid 110) id 3EAC82097B; Thu, 5 Oct 2017 22:54:13 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost (unknown [91.126.32.14]) by mail.free-electrons.com (Postfix) with ESMTPSA id 09FEA20914; Thu, 5 Oct 2017 22:54:13 +0200 (CEST) From: Maxime Ripard To: Chen-Yu Tsai , Maxime Ripard , linus.walleij@linaro.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org Subject: [PATCH 2/3] pinctrl: sunxi: Disable strict mode for old pinctrl drivers Date: Thu, 5 Oct 2017 22:54:07 +0200 Message-Id: X-Mailer: git-send-email 2.13.5 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Old pinctrl drivers will need to disable strict mode for various reasons, among which: - Some DT will still have a pinctrl group for each GPIO used, which will be rejected by pin_request. While we could remove those nodes, we still have to deal with old DTs. - Some GPIOs on these boards need to have their pin configuration changed (for bias or current), and there's no clear migration path Let's disable the strict mode on those SoCs so that there's no breakage. Signed-off-by: Maxime Ripard --- drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c | 1 + drivers/pinctrl/sunxi/pinctrl-sun5i.c | 1 + drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c | 1 + drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c | 1 + drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c | 1 + drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c | 3 ++- drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c | 1 + 7 files changed, 8 insertions(+), 1 deletion(-) -- git-series 0.9.1 diff --git a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c index f763d8d62d6e..295e48fc94bc 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c @@ -1289,6 +1289,7 @@ static const struct sunxi_pinctrl_desc sun4i_a10_pinctrl_data = { .npins = ARRAY_SIZE(sun4i_a10_pins), .irq_banks = 1, .irq_read_needs_mux = true, + .disable_strict_mode = true, }; static int sun4i_a10_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun5i.c b/drivers/pinctrl/sunxi/pinctrl-sun5i.c index 47afd558b114..27ec99e81c4c 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun5i.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun5i.c @@ -713,6 +713,7 @@ static const struct sunxi_pinctrl_desc sun5i_pinctrl_data = { .pins = sun5i_pins, .npins = ARRAY_SIZE(sun5i_pins), .irq_banks = 1, + .disable_strict_mode = true, }; static int sun5i_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c index 951a25c18815..82ffaf466892 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c @@ -965,6 +965,7 @@ static const struct sunxi_pinctrl_desc sun6i_a31_pinctrl_data = { .pins = sun6i_a31_pins, .npins = ARRAY_SIZE(sun6i_a31_pins), .irq_banks = 4, + .disable_strict_mode = true, }; static int sun6i_a31_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c index 721b6935baf3..402fd7d21e7b 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c @@ -563,6 +563,7 @@ static const struct sunxi_pinctrl_desc sun8i_a23_pinctrl_data = { .pins = sun8i_a23_pins, .npins = ARRAY_SIZE(sun8i_a23_pins), .irq_banks = 3, + .disable_strict_mode = true, }; static int sun8i_a23_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c index ef1e0bef4099..da387211a75e 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c @@ -486,6 +486,7 @@ static const struct sunxi_pinctrl_desc sun8i_a33_pinctrl_data = { .npins = ARRAY_SIZE(sun8i_a33_pins), .irq_banks = 2, .irq_bank_base = 1, + .disable_strict_mode = true, }; static int sun8i_a33_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c index 518a92df4418..d1719a738c20 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c @@ -491,7 +491,8 @@ static const struct sunxi_pinctrl_desc sun8i_h3_pinctrl_data = { .pins = sun8i_h3_pins, .npins = ARRAY_SIZE(sun8i_h3_pins), .irq_banks = 2, - .irq_read_needs_mux = true + .irq_read_needs_mux = true, + .disable_strict_mode = true, }; static int sun8i_h3_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c index bc14e954d7a2..472ef0d91b99 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c @@ -721,6 +721,7 @@ static const struct sunxi_pinctrl_desc sun9i_a80_pinctrl_data = { .pins = sun9i_a80_pins, .npins = ARRAY_SIZE(sun9i_a80_pins), .irq_banks = 5, + .disable_strict_mode = true, }; static int sun9i_a80_pinctrl_probe(struct platform_device *pdev) From patchwork Thu Oct 5 20:54:08 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Ripard X-Patchwork-Id: 115000 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp1014831qgn; Thu, 5 Oct 2017 13:54:26 -0700 (PDT) X-Google-Smtp-Source: AOwi7QBOUKGi39p8LQvKHBTT4O729Ax7vii5d30GtP3xYFXqXlaOOm0e7LpLtwH1KcSe8Nqp4lQp X-Received: by 10.99.119.206 with SMTP id s197mr13371757pgc.83.1507236866290; Thu, 05 Oct 2017 13:54:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507236866; cv=none; d=google.com; s=arc-20160816; b=GoUezxrqT7qsr4JsT/23jQwW30VlFwIjk9ey8LMF2szJc8RVbQtCPmjN8KVCiStFVJ 9Oc/mdUgdtS70sir1AcDpKowvTK6WvopF/4NPN5ng/AMgJDbAku/6pK+t9scix5hTGu0 mEuYvHlJk5ox8e2lRPnI0S9K7eUhbU6LsbqrMDIMGrrmBJ87BU2t4AeQqWyoOm8kZrvL QcABZPTWGkoqyzLkf3X3r0ok141Qf1hpN4ca5jdN6gtpTA3Lm9I2GKFeMAc6C7xORUWx A7Mqusxd33/4QK8tmeAh5jzSHFlLA4ZZivzzcVZbFkZtMJQu6ho5QDK48O36Ilw8IAMK cz5w== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id w128si8550842pfw.112.2017.10.05.13.54.25; Thu, 05 Oct 2017 13:54:26 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752065AbdJEUyY (ORCPT + 26 others); Thu, 5 Oct 2017 16:54:24 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:32864 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751774AbdJEUyQ (ORCPT ); Thu, 5 Oct 2017 16:54:16 -0400 Received: by mail.free-electrons.com (Postfix, from userid 110) id BBBF920982; Thu, 5 Oct 2017 22:54:13 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost (unknown [91.126.32.14]) by mail.free-electrons.com (Postfix) with ESMTPSA id 8C9B020914; Thu, 5 Oct 2017 22:54:13 +0200 (CEST) From: Maxime Ripard To: Chen-Yu Tsai , Maxime Ripard , linus.walleij@linaro.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org Subject: [PATCH 3/3] pinctrl: sunxi: Enforce the strict mode by default Date: Thu, 5 Oct 2017 22:54:08 +0200 Message-Id: <817a66704d6c8f3caa034a526db11e25a9152a65.1507236823.git-series.maxime.ripard@free-electrons.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The strict mode should always have been enabled on our driver, and leaving it unchecked just makes it harder to find a migration path as time passes. Let's enable it by default now so that hopefully the new SoCs should be safe. Signed-off-by: Maxime Ripard --- drivers/pinctrl/sunxi/pinctrl-sunxi.c | 1 + 1 file changed, 1 insertion(+) -- git-series 0.9.1 diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index 1753a5b1573f..2313c3b8931a 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -696,6 +696,7 @@ static struct pinmux_ops sunxi_pmx_ops = { .get_function_groups = sunxi_pmx_get_func_groups, .set_mux = sunxi_pmx_set_mux, .gpio_set_direction = sunxi_pmx_gpio_set_direction, + .strict = true, }; static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip,