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X-Host: pioneer.tdc.vzwcorp.com Received: from ohtwi1exh001.uswin.ad.vzwcorp.com ([10.144.218.43]) by eris.verizonwireless.com with ESMTP/TLS/AES128-SHA256; 07 Oct 2017 22:36:51 +0000 Received: from tbwexch12apd.uswin.ad.vzwcorp.com (153.114.162.36) by OHTWI1EXH001.uswin.ad.vzwcorp.com (10.144.218.43) with Microsoft SMTP Server (TLS) id 14.3.248.2; Sat, 7 Oct 2017 18:36:51 -0400 Received: from OMZP1LUMXCA17.uswin.ad.vzwcorp.com (144.8.22.195) by tbwexch12apd.uswin.ad.vzwcorp.com (153.114.162.36) with Microsoft SMTP Server (TLS) id 15.0.1263.5; Sat, 7 Oct 2017 18:36:51 -0400 Received: from OMZP1LUMXCA17.uswin.ad.vzwcorp.com (144.8.22.195) by OMZP1LUMXCA17.uswin.ad.vzwcorp.com (144.8.22.195) with Microsoft SMTP Server (TLS) id 15.0.1263.5; Sat, 7 Oct 2017 17:36:50 -0500 Received: from OMZP1LUMXCA17.uswin.ad.vzwcorp.com ([144.8.22.195]) by OMZP1LUMXCA17.uswin.ad.vzwcorp.com ([144.8.22.195]) with mapi id 15.00.1263.000; Sat, 7 Oct 2017 17:36:50 -0500 To: "linux-kernel@vger.kernel.org" , "stable@vger.kernel.org" Subject: [PATCH review for 4.9 07/50] mmc: s3cmci: include linux/interrupt.h for tasklet_struct Thread-Topic: [PATCH review for 4.9 07/50] mmc: s3cmci: include linux/interrupt.h for tasklet_struct Thread-Index: AQHTP7zCm1b1UN/ZQkKYiJs8J31SkA== Date: Sat, 7 Oct 2017 22:36:47 +0000 Message-ID: <20171007223636.24797-7-alexander.levin@verizon.com> References: <20171007223636.24797-1-alexander.levin@verizon.com> In-Reply-To: <20171007223636.24797-1-alexander.levin@verizon.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-messagesentrepresentingtype: 1 x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.144.60.250] MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Arnd Bergmann [ Upstream commit e1c6ec26b853e9062f0b3daaf695c546d0702953 ] I got this new build error on today's linux-next drivers/mmc/host/s3cmci.h:69:24: error: field 'pio_tasklet' has incomplete type struct tasklet_struct pio_tasklet; drivers/mmc/host/s3cmci.c: In function 's3cmci_enable_irq': drivers/mmc/host/s3cmci.c:390:4: error: implicit declaration of function 'enable_irq';did you mean 'enable_imask'? [-Werror=implicit-function-declaration] While I haven't found out why this happened now and not earlier, the solution is obvious, we should include the header that defines the structure. Signed-off-by: Arnd Bergmann Signed-off-by: Ulf Hansson Signed-off-by: Sasha Levin --- drivers/mmc/host/s3cmci.c | 1 + 1 file changed, 1 insertion(+) -- 2.11.0 diff --git a/drivers/mmc/host/s3cmci.c b/drivers/mmc/host/s3cmci.c index c531deef3258..8f27fe35e8af 100644 --- a/drivers/mmc/host/s3cmci.c +++ b/drivers/mmc/host/s3cmci.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include From patchwork Sat Oct 7 22:36:51 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Levin, Alexander \(Sasha Levin\)" X-Patchwork-Id: 115151 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp1036411qgn; Sat, 7 Oct 2017 15:48:05 -0700 (PDT) X-Google-Smtp-Source: AOwi7QDsMJtcPMeQWZVX2LKTsuFdSndIQGzmgd8gnICxtJa4KbPcw8V1DF+tijbfCOjQP81o63f6 X-Received: by 10.99.38.7 with SMTP id m7mr5527999pgm.53.1507416485012; Sat, 07 Oct 2017 15:48:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507416485; cv=none; d=google.com; s=arc-20160816; b=ZNzPI3AcTxE5FcmMWyr4TcP2BawnJXRPspWPx9kbkypQbK3rn+5EAF/SMOMZfaw0Mk RWUTi1/4ILASe5R/X6g5K2vSA9U33vl2jkEnW3GplLF6DrViI5qkBAu9CpNjY4fjoBcr C8MoWOA93d8GoQfMZL1aLVSon58lZ59Euna2VKnF0Kv1j8PGJVsl9RC1e4+a0KfdXRxS jxpBEfTsdCUNZRPb8KrSddOLCzHqP36vIAyv/QE2G3SIAD57++Ir7+2NlAutcU861hQE P6Ty59hmMTH8VNy3PwNhD6YTPa6avWKRwDoj4KIZqvi/Yh4Isf4PqnRvD++cvq+BbuNQ ovQw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:content-transfer-encoding :content-language:accept-language:in-reply-to:references:message-id :date:thread-index:thread-topic:subject:to:dkim-signature :dkim-signature:cc:from:dkim-signature:arc-authentication-results; bh=o+mgSzSF7RPOvS8eojkWGAZj69yMCDXj/F5cQoyxGJw=; b=p0Y7CDmaobjjFm0/CD/sT5W/Vu/VsTp2KIGo617f4ViJBCpFfbJUESSFWA+PhqC069 nrERXzK47XSuXjwLMdzGVz88u5DLGDZeY5zeqemhXQ8kPHlwxuJdr0DMMGgosdUovBMF m5m8GH9iV3SUnXFSP8ZVT0KMJfoKutk3a7R4ROjM6+4c+riyiWHlIOxfilSq2In6Qg2k 1Nr2i6hYFtwBCMNjecrANmYEXVd91LcGj6cAZ3YBXW24vTRI6a/iioqc8P2lU4+ckfSb TDAmOZWACP//Xaeeqt1TKXCVlEdpeL/vI51YyS4Mcej2lmcsHvJ6tn8HNFYRDr0A/3nM zs9g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@verizon.com header.s=corp header.b=qMjGfkBE; dkim=fail header.i=@verizon.com header.s=corp header.b=Gwx9ucre; dkim=fail header.i=@verizon.com header.s=corp header.b=Gwx9ucre; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=verizon.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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X-Host: mariner.tdc.vzwcorp.com Received: from ohtwi1exh002.uswin.ad.vzwcorp.com ([10.144.218.44]) by eris.verizonwireless.com with ESMTP/TLS/AES128-SHA256; 07 Oct 2017 22:37:00 +0000 Received: from tbwexch16apd.uswin.ad.vzwcorp.com (153.114.162.40) by OHTWI1EXH002.uswin.ad.vzwcorp.com (10.144.218.44) with Microsoft SMTP Server (TLS) id 14.3.248.2; Sat, 7 Oct 2017 18:37:01 -0400 Received: from OMZP1LUMXCA13.uswin.ad.vzwcorp.com (144.8.22.188) by tbwexch16apd.uswin.ad.vzwcorp.com (153.114.162.40) with Microsoft SMTP Server (TLS) id 15.0.1263.5; Sat, 7 Oct 2017 18:37:00 -0400 Received: from OMZP1LUMXCA17.uswin.ad.vzwcorp.com (144.8.22.195) by OMZP1LUMXCA13.uswin.ad.vzwcorp.com (144.8.22.188) with Microsoft SMTP Server (TLS) id 15.0.1263.5; Sat, 7 Oct 2017 17:36:59 -0500 Received: from OMZP1LUMXCA17.uswin.ad.vzwcorp.com ([144.8.22.195]) by OMZP1LUMXCA17.uswin.ad.vzwcorp.com ([144.8.22.195]) with mapi id 15.00.1263.000; Sat, 7 Oct 2017 17:36:59 -0500 To: "linux-kernel@vger.kernel.org" , "stable@vger.kernel.org" Subject: [PATCH review for 4.9 22/50] clocksource/drivers/arm_arch_timer: Add dt binding for hisilicon-161010101 erratum Thread-Topic: [PATCH review for 4.9 22/50] clocksource/drivers/arm_arch_timer: Add dt binding for hisilicon-161010101 erratum Thread-Index: AQHTP7zEUehRdGYDtU+qNiyFI1uQRA== Date: Sat, 7 Oct 2017 22:36:51 +0000 Message-ID: <20171007223636.24797-22-alexander.levin@verizon.com> References: <20171007223636.24797-1-alexander.levin@verizon.com> In-Reply-To: <20171007223636.24797-1-alexander.levin@verizon.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-messagesentrepresentingtype: 1 x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.144.60.250] MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ding Tianhong [ Upstream commit 729e55225b1f6225ee7a2a358d5141a3264627c4 ] This erratum describes a bug in logic outside the core, so MIDR can't be used to identify its presence, and reading an SoC-specific revision register from common arch timer code would be awkward. So, describe it in the device tree. Signed-off-by: Ding Tianhong Acked-by: Rob Herring Signed-off-by: Mark Rutland Signed-off-by: Daniel Lezcano Signed-off-by: Sasha Levin --- Documentation/devicetree/bindings/arm/arch_timer.txt | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.11.0 diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt index ad440a2b8051..e926aea1147d 100644 --- a/Documentation/devicetree/bindings/arm/arch_timer.txt +++ b/Documentation/devicetree/bindings/arm/arch_timer.txt @@ -31,6 +31,12 @@ to deliver its interrupts via SPIs. This also affects writes to the tval register, due to the implicit counter read. +- hisilicon,erratum-161010101 : A boolean property. Indicates the + presence of Hisilicon erratum 161010101, which says that reading the + counters is unreliable in some cases, and reads may return a value 32 + beyond the correct value. This also affects writes to the tval + registers, due to the implicit counter read. + ** Optional properties: - arm,cpu-registers-not-fw-configured : Firmware does not initialize