From patchwork Wed May 13 19:15:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Urja Rannikko X-Patchwork-Id: 245747 List-Id: U-Boot discussion From: urjaman at gmail.com (Urja Rannikko) Date: Wed, 13 May 2020 19:15:20 +0000 Subject: [PATCH 1/4] rockchip: spl: veyron speedy boots from SPI In-Reply-To: <20200513191523.3141-1-urjaman@gmail.com> References: <20200513191523.3141-1-urjaman@gmail.com> Message-ID: <20200513191523.3141-2-urjaman@gmail.com> Apparently speedy was forgotten from this list of veyron devices. Fixes: 49105fb7ed ("rockchip: add common spl board file") Signed-off-by: Urja Rannikko Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/spl.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c index 0b76af6080..2c2b4ea5c0 100644 --- a/arch/arm/mach-rockchip/spl.c +++ b/arch/arm/mach-rockchip/spl.c @@ -49,7 +49,8 @@ u32 spl_boot_device(void) #if defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \ defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \ - defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) + defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) || \ + defined(CONFIG_TARGET_CHROMEBOOK_SPEEDY) return BOOT_DEVICE_SPI; #endif if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)) From patchwork Wed May 13 19:15:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Urja Rannikko X-Patchwork-Id: 245748 List-Id: U-Boot discussion From: urjaman at gmail.com (Urja Rannikko) Date: Wed, 13 May 2020 19:15:21 +0000 Subject: [PATCH 2/4] rockchip: veyron: move board_early_init_f to _r (after reloc) In-Reply-To: <20200513191523.3141-1-urjaman@gmail.com> References: <20200513191523.3141-1-urjaman@gmail.com> Message-ID: <20200513191523.3141-3-urjaman@gmail.com> Previously veyron_init() was called in board_init() context, which is called after relocation. Moving it to veyron.c used board_early_init_f which is called way earlier, and causes veyron_init to hang. Using board_early_init_r instead fixes this. Fixes: b678f2790c ("rockchip: rk3288: Move veyron_init() back to veyron.c") Signed-off-by: Urja Rannikko Reviewed-by: Kever Yang --- board/google/veyron/veyron.c | 2 +- configs/chromebit_mickey_defconfig | 1 + configs/chromebook_jerry_defconfig | 2 +- configs/chromebook_minnie_defconfig | 1 + configs/chromebook_speedy_defconfig | 2 +- 5 files changed, 5 insertions(+), 3 deletions(-) diff --git a/board/google/veyron/veyron.c b/board/google/veyron/veyron.c index 6b9c34818b..04321094ef 100644 --- a/board/google/veyron/veyron.c +++ b/board/google/veyron/veyron.c @@ -68,7 +68,7 @@ static int veyron_init(void) } #endif -int board_early_init_f(void) +int board_early_init_r(void) { struct udevice *dev; int ret; diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig index b1ad7bdd1d..b290f0fcb9 100644 --- a/configs/chromebit_mickey_defconfig +++ b/configs/chromebit_mickey_defconfig @@ -19,6 +19,7 @@ CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-mickey.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index 16eee2238b..f6bdf80aee 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -20,7 +20,7 @@ CONFIG_LOG=y CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-jerry.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig index 2c0415431f..c229177f64 100644 --- a/configs/chromebook_minnie_defconfig +++ b/configs/chromebook_minnie_defconfig @@ -20,6 +20,7 @@ CONFIG_SILENT_CONSOLE=y CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-minnie.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 diff --git a/configs/chromebook_speedy_defconfig b/configs/chromebook_speedy_defconfig index b4116a34e6..be434871ff 100644 --- a/configs/chromebook_speedy_defconfig +++ b/configs/chromebook_speedy_defconfig @@ -20,7 +20,7 @@ CONFIG_SILENT_CONSOLE=y CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-speedy.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_EARLY_INIT_R=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 From patchwork Wed May 13 19:15:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Urja Rannikko X-Patchwork-Id: 245749 List-Id: U-Boot discussion From: urjaman at gmail.com (Urja Rannikko) Date: Wed, 13 May 2020 19:15:22 +0000 Subject: [PATCH 3/4] rockchip: spl-boot-order: do not attempt to access fdt if OF_PLATDATA In-Reply-To: <20200513191523.3141-1-urjaman@gmail.com> References: <20200513191523.3141-1-urjaman@gmail.com> Message-ID: <20200513191523.3141-4-urjaman@gmail.com> gd->fdt_blob is null if using OF_PLATDATA in SPL, which causes a hang after f0921f5098 ("fdt: Sync up to the latest libfdt"). We use the same test that is used in spl_common_init on whether to call fdtdec_setup to unconditionally avoid linking in the fdt-using code when not necessary and thus reduce SPL size. Signed-off-by: Urja Rannikko Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/spl-boot-order.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/mach-rockchip/spl-boot-order.c b/arch/arm/mach-rockchip/spl-boot-order.c index c147d5821e..d23829a789 100644 --- a/arch/arm/mach-rockchip/spl-boot-order.c +++ b/arch/arm/mach-rockchip/spl-boot-order.c @@ -98,6 +98,12 @@ __weak const char *board_spl_was_booted_from(void) void board_boot_order(u32 *spl_boot_list) { + /* In case of no fdt (or only platdata), use spl_boot_device() */ + if (!CONFIG_IS_ENABLED(OF_CONTROL) || CONFIG_IS_ENABLED(OF_PLATDATA)) { + spl_boot_list[0] = spl_boot_device(); + return; + } + const void *blob = gd->fdt_blob; int chosen_node = fdt_path_offset(blob, "/chosen"); int idx = 0; From patchwork Wed May 13 19:15:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Urja Rannikko X-Patchwork-Id: 245750 List-Id: U-Boot discussion From: urjaman at gmail.com (Urja Rannikko) Date: Wed, 13 May 2020 19:15:23 +0000 Subject: [PATCH 4/4] defconfig: veyron: no need for CONFIG_SPL_PINCTRL_FULL In-Reply-To: <20200513191523.3141-1-urjaman@gmail.com> References: <20200513191523.3141-1-urjaman@gmail.com> Message-ID: <20200513191523.3141-5-urjaman@gmail.com> Veyrons do not need full pinctrl support for SPL. The full pinctrl support does nothing when enabled with OF_PLATDATA, thus was already unused. This frees about 4kB of SPL size. Signed-off-by: Urja Rannikko Reviewed-by: Kever Yang --- configs/chromebit_mickey_defconfig | 3 +-- configs/chromebook_jerry_defconfig | 3 +-- configs/chromebook_minnie_defconfig | 3 +-- configs/chromebook_speedy_defconfig | 1 + 4 files changed, 4 insertions(+), 6 deletions(-) diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig index b290f0fcb9..23efafb0d2 100644 --- a/configs/chromebit_mickey_defconfig +++ b/configs/chromebit_mickey_defconfig @@ -73,8 +73,7 @@ CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_PINCTRL=y CONFIG_PINCONF=y CONFIG_SPL_PINCTRL=y -# CONFIG_SPL_PINMUX is not set -CONFIG_SPL_PINCONF=y +# CONFIG_SPL_PINCTRL_FULL is not set CONFIG_DM_PMIC=y # CONFIG_SPL_PMIC_CHILDREN is not set CONFIG_PMIC_RK8XX=y diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index f6bdf80aee..443e3cdace 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -75,8 +75,7 @@ CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_PINCTRL=y CONFIG_PINCONF=y CONFIG_SPL_PINCTRL=y -# CONFIG_SPL_PINMUX is not set -CONFIG_SPL_PINCONF=y +# CONFIG_SPL_PINCTRL_FULL is not set CONFIG_DM_PMIC=y # CONFIG_SPL_PMIC_CHILDREN is not set CONFIG_PMIC_RK8XX=y diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig index c229177f64..99ac0e0674 100644 --- a/configs/chromebook_minnie_defconfig +++ b/configs/chromebook_minnie_defconfig @@ -75,8 +75,7 @@ CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_PINCTRL=y CONFIG_PINCONF=y CONFIG_SPL_PINCTRL=y -# CONFIG_SPL_PINMUX is not set -CONFIG_SPL_PINCONF=y +# CONFIG_SPL_PINCTRL_FULL is not set CONFIG_DM_PMIC=y # CONFIG_SPL_PMIC_CHILDREN is not set CONFIG_PMIC_RK8XX=y diff --git a/configs/chromebook_speedy_defconfig b/configs/chromebook_speedy_defconfig index be434871ff..5a5152541b 100644 --- a/configs/chromebook_speedy_defconfig +++ b/configs/chromebook_speedy_defconfig @@ -74,6 +74,7 @@ CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_PINCTRL=y CONFIG_PINCONF=y CONFIG_SPL_PINCTRL=y +# CONFIG_SPL_PINCTRL_FULL is not set CONFIG_DM_PMIC=y # CONFIG_SPL_PMIC_CHILDREN is not set CONFIG_PMIC_RK8XX=y