From patchwork Wed May 27 01:31:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 246653 List-Id: U-Boot discussion From: judge.packham at gmail.com (Chris Packham) Date: Wed, 27 May 2020 13:31:29 +1200 Subject: [PATCH 1/2] mv_ddr: ddr3: Use correct bitmask for read sample delay In-Reply-To: <20200527013131.1663-1-judge.packham@gmail.com> References: <20200527013131.1663-1-judge.packham@gmail.com> Message-ID: <20200527013131.1663-2-judge.packham@gmail.com> From: Chris Packham In the Armada 385 functional spec (MV-S109094-00 Rev. C) the read sample delay fields are 5 bits wide. Use the correct bitmask of 0x1f when extracting the value. Signed-off-by: Chris Packham [upstream https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/22] Signed-off-by: Chris Packham Reviewed-by: Stefan Roese --- drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c b/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c index df832ac6dce0..ce9a47fc2ce0 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c +++ b/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c @@ -11,7 +11,7 @@ #define VREF_MAX_INDEX 7 #define MAX_VALUE (1024 - 1) #define MIN_VALUE (-MAX_VALUE) -#define GET_RD_SAMPLE_DELAY(data, cs) ((data >> rd_sample_mask[cs]) & 0xf) +#define GET_RD_SAMPLE_DELAY(data, cs) ((data >> rd_sample_mask[cs]) & 0x1f) u32 ca_delay; int ddr3_tip_centr_skip_min_win_check = 0; From patchwork Wed May 27 01:31:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 246654 List-Id: U-Boot discussion From: judge.packham at gmail.com (Chris Packham) Date: Wed, 27 May 2020 13:31:30 +1200 Subject: [PATCH 2/2] mv_ddr: ddr3: Update {min,max}_read_sample calculation In-Reply-To: <20200527013131.1663-1-judge.packham@gmail.com> References: <20200527013131.1663-1-judge.packham@gmail.com> Message-ID: <20200527013131.1663-3-judge.packham@gmail.com> From: Chris Packham Measurements on actual hardware shown that the read ODT is early by 3 clocks. Adjust the calculation to avoid this. Signed-off-by: Chris Packham [upstream https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/22] Signed-off-by: Chris Packham Tested-by: Baruch Siach Reviewed-by: Stefan Roese --- drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c b/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c index ce9a47fc2ce0..58ffb205072e 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c +++ b/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c @@ -91,8 +91,8 @@ int ddr3_tip_write_additional_odt_setting(u32 dev_num, u32 if_id) min_read_sample = read_sample[cs_num]; } - min_read_sample = min_read_sample - 1; - max_read_sample = max_read_sample + 4 + (max_phase + 1) / 2 + 1; + min_read_sample = min_read_sample + 2; + max_read_sample = max_read_sample + 7 + (max_phase + 1) / 2 + 1; if (min_read_sample >= 0xf) min_read_sample = 0xf; if (max_read_sample >= 0x1f)