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Also move it out of mfd as it is not and has never been related to mfd. Signed-off-by: Alexandre Belloni Reviewed-by: Rob Herring Signed-off-by: Daniel Lezcano Link: https://lore.kernel.org/r/20200710230813.1005150-2-alexandre.belloni@bootlin.com --- .../devicetree/bindings/mfd/atmel-tcb.txt | 56 -------- .../soc/microchip/atmel,at91rm9200-tcb.yaml | 131 ++++++++++++++++++ 2 files changed, 131 insertions(+), 56 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mfd/atmel-tcb.txt create mode 100644 Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml -- 2.25.1 Acked-by: Lee Jones diff --git a/Documentation/devicetree/bindings/mfd/atmel-tcb.txt b/Documentation/devicetree/bindings/mfd/atmel-tcb.txt deleted file mode 100644 index c4a83e364cb6..000000000000 --- a/Documentation/devicetree/bindings/mfd/atmel-tcb.txt +++ /dev/null @@ -1,56 +0,0 @@ -* Device tree bindings for Atmel Timer Counter Blocks -- compatible: Should be "atmel,-tcb", "simple-mfd", "syscon". - can be "at91rm9200" or "at91sam9x5" -- reg: Should contain registers location and length -- #address-cells: has to be 1 -- #size-cells: has to be 0 -- interrupts: Should contain all interrupts for the TC block - Note that you can specify several interrupt cells if the TC - block has one interrupt per channel. -- clock-names: tuple listing input clock names. - Required elements: "t0_clk", "slow_clk" - Optional elements: "t1_clk", "t2_clk" -- clocks: phandles to input clocks. - -The TCB can expose multiple subdevices: - * a timer - - compatible: Should be "atmel,tcb-timer" - - reg: Should contain the TCB channels to be used. If the - counter width is 16 bits (at91rm9200-tcb), two consecutive - channels are needed. Else, only one channel will be used. - -Examples: - -One interrupt per TC block: - tcb0: timer@fff7c000 { - compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xfff7c000 0x100>; - interrupts = <18 4>; - clocks = <&tcb0_clk>, <&clk32k>; - clock-names = "t0_clk", "slow_clk"; - - timer@0 { - compatible = "atmel,tcb-timer"; - reg = <0>, <1>; - }; - - timer@2 { - compatible = "atmel,tcb-timer"; - reg = <2>; - }; - }; - -One interrupt per TC channel in a TC block: - tcb1: timer@fffdc000 { - compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xfffdc000 0x100>; - interrupts = <26 4>, <27 4>, <28 4>; - clocks = <&tcb1_clk>, <&clk32k>; - clock-names = "t0_clk", "slow_clk"; - }; - - diff --git a/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml b/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml new file mode 100644 index 000000000000..9d680e0b9109 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml @@ -0,0 +1,131 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/soc/microchip/atmel,at91rm9200-tcb.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Atmel Timer Counter Block + +maintainers: + - Alexandre Belloni + +description: | + The Atmel (now Microchip) SoCs have timers named Timer Counter Block. Each + timer has three channels with two counters each. + +properties: + compatible: + items: + - enum: + - atmel,at91rm9200-tcb + - atmel,at91sam9x5-tcb + - const: simple-mfd + - const: syscon + + reg: + maxItems: 1 + + interrupts: + description: + List of interrupts. One interrupt per TCB channel if available or one + interrupt for the TC block + minItems: 1 + maxItems: 3 + + clock-names: + description: + List of clock names. Always includes t0_clk and slow clk. Also includes + t1_clk and t2_clk if a clock per channel is available. + oneOf: + - items: + - const: t0_clk + - const: slow_clk + - items: + - const: t0_clk + - const: t1_clk + - const: t2_clk + - const: slow_clk + minItems: 2 + maxItems: 4 + + clocks: + minItems: 2 + maxItems: 4 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +patternProperties: + "^timer@[0-2]$": + description: The timer block channels that are used as timers. + type: object + properties: + compatible: + const: atmel,tcb-timer + reg: + description: + List of channels to use for this particular timer. + minItems: 1 + maxItems: 3 + + required: + - compatible + - reg + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - '#address-cells' + - '#size-cells' + +additionalProperties: false + +examples: + - | + /* One interrupt per TC block: */ + tcb0: timer@fff7c000 { + compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfff7c000 0x100>; + interrupts = <18 4>; + clocks = <&tcb0_clk>, <&clk32k>; + clock-names = "t0_clk", "slow_clk"; + + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>, <1>; + }; + + timer@2 { + compatible = "atmel,tcb-timer"; + reg = <2>; + }; + }; + + /* One interrupt per TC channel in a TC block: */ + tcb1: timer@fffdc000 { + compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfffdc000 0x100>; + interrupts = <26 4>, <27 4>, <28 4>; + clocks = <&tcb1_clk>, <&clk32k>; + clock-names = "t0_clk", "slow_clk"; + + timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; + }; From patchwork Thu Jul 23 15:26:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 247087 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp1587002ilg; Thu, 23 Jul 2020 08:26:59 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw3ZoVSDec8dERNCwvkQgcmb0hSBAi4nJTYI7hV65dpMK2bwtUEM0AqTjp3Llu6iAep/Ozg X-Received: by 2002:a50:f0c6:: with SMTP id a6mr4518142edm.374.1595518019271; Thu, 23 Jul 2020 08:26:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1595518019; cv=none; d=google.com; s=arc-20160816; b=AH7e/G9uxmPoJVWd8bqa+fU1L75TpFBGEHBFM7MthzBCQGEryCl1aPFcm7SF5ARV+y gt5/G1lq/cyq1AKW5nmCll30kJsfVQrXufO607mMHffTOwqWlqQpjK292m2XI0OQ9J+0 pnTkL6ijrDqDoyFYalvWcnLvcqk9M7FIvdhvUarj1Nvt9p7E5g8O00GgQDzTgvvBOW8e DEb+rP67Qv50QyZs3yNhBtH/c3qg2QeLaQ72n9D8FagKFzAjAsl1vfIpDF8+qr2HN9qH ibY+L1/hsAMJDgn27ls1973ENNOK4CtOyoY+hTkZUILPpMBC8wejdlObEJH04RngV4ow 4z3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=8/f3+aWQD6jv0BacPrlT71wq4KzB+QZIhzZYF2sQn5E=; b=LnJkpyrSItfYrjU4sLbdQlCN6AxqDGjeDWVLSsQTtUTfvaYSdWlom53I1MKzxgwELe QfcxqkFTEfbb/L+MiTQhC8GycwoU+rA2dIMEbssrqKg7LjyTvCchCV21SrqOCc6bT0Sc ME6E67dspyzCubWgRY4tTp/bvjrDBGMO+cSMN/C36Z3o+IpxlXH12LVFPPs6lWD1cMi0 k36pElUc4A6h4ZT4Nrsi+Qqre736P0VvvXP4raqnFz3qdlhLGpXncj4RNmMNQUnreRaJ dobYLK+OXY4lhNFWIJuxFfJXBhEBKkeX3+77RfTJ+Wit8U5fDD96amTABFkp/yYaX4BQ yoew== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZibBjkqe; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Instead of being MCK / 2, it is the TCB GCLK. Reviewed-by: Rob Herring Signed-off-by: Alexandre Belloni Signed-off-by: Daniel Lezcano Link: https://lore.kernel.org/r/20200710230813.1005150-3-alexandre.belloni@bootlin.com --- .../soc/microchip/atmel,at91rm9200-tcb.yaml | 42 +++++++++++++++---- 1 file changed, 33 insertions(+), 9 deletions(-) -- 2.25.1 diff --git a/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml b/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml index 9d680e0b9109..d226fd7d5258 100644 --- a/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml +++ b/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml @@ -19,6 +19,7 @@ properties: - enum: - atmel,at91rm9200-tcb - atmel,at91sam9x5-tcb + - atmel,sama5d2-tcb - const: simple-mfd - const: syscon @@ -36,15 +37,6 @@ properties: description: List of clock names. Always includes t0_clk and slow clk. Also includes t1_clk and t2_clk if a clock per channel is available. - oneOf: - - items: - - const: t0_clk - - const: slow_clk - - items: - - const: t0_clk - - const: t1_clk - - const: t2_clk - - const: slow_clk minItems: 2 maxItems: 4 @@ -75,6 +67,38 @@ patternProperties: - compatible - reg +allOf: + - if: + properties: + compatible: + contains: + const: atmel,sama5d2-tcb + then: + properties: + clocks: + minItems: 3 + maxItems: 3 + clock-names: + items: + - const: t0_clk + - const: gclk + - const: slow_clk + else: + properties: + clocks: + minItems: 2 + maxItems: 4 + clock-names: + oneOf: + - items: + - const: t0_clk + - const: slow_clk + - items: + - const: t0_clk + - const: t1_clk + - const: t2_clk + - const: slow_clk + required: - compatible - reg From patchwork Thu Jul 23 15:26:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 247088 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp1587035ilg; Thu, 23 Jul 2020 08:27:02 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwDUIKDdd9Qei1+pJWAF34EJWKt14HRQGWv009z1mPebWwqIFOh5DGtB2FtvCVuNGjD1q5U X-Received: by 2002:a17:906:488b:: with SMTP id v11mr5011356ejq.173.1595518022579; Thu, 23 Jul 2020 08:27:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1595518022; cv=none; d=google.com; s=arc-20160816; b=ilELSvE+BjgTQzAkvmivq7F+xn5CINuzzkd+hoMJZRQ7q92/6wygmIHlnrmEzMdvtu UsFZ3RgeUbOw4QXqd28au18OJaT8g928ymRFJ38GdyG8StoYpbYN431e5jSE14ZvWmos 61jo3r9rPaJsedKB67Cgl5xwBuDUwfGTY3II3v+i/xU/IMbMF2hWYGUAeu3iZeS7pVfQ 3QwdjJar1wPLGiqDd9mVeCAJmaEzjHKa3w7yMkrpMfhyv0RBxCflW++Xu1j1Q7wCMBeX imu1miNOtWn/X8CBeXsRH16DnNJt5Drcs+oxAjlh6dvYAMQ5qhAqlH5Nd51RpId1azXE cYVg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=R3Az9OepR2BdTDAPEdWN7LwMsA5P61TmIGuTZB4zgG8=; b=QfqP71HS/pQpOalQEZhpQJ0WWS8tA8Mv7wljl3E1Rc5O4Q4FzZNaKyCpAjXAyj5loF ChNDl0ZfvmSIQHfz/IVaiG1egldcfdkiVaXj2VE+qvDuK7NxMGLpj0NCgWO9dPpSrhQI 2uJOKmOBmsdLGp7R35gsIIigPANtL1I9hqJWl2hG58EJAcgGbjR14hZmYw/c+q8vo+VS IR4nRK7lNGoz3m3VBx9Fi4maRTYhPtilgguIEr7iD1ZjqiUYpPKLOL7VwQNs4LLx+Mb2 q5yF/VbNKT6MX0BeE4l6bjyUKd5ltzw5C7LGeeXYLLFqyM9oumZEGzY5dfaN2EB6qvn3 ykJw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dQ0bNcNH; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Alexandre Belloni Signed-off-by: Daniel Lezcano Link: https://lore.kernel.org/r/20200710230813.1005150-4-alexandre.belloni@bootlin.com --- arch/arm/boot/dts/sama5d2.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) -- 2.25.1 diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index ab550d69db91..996143e966d8 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -499,23 +499,23 @@ macb0: ethernet@f8008000 { }; tcb0: timer@f800c000 { - compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; + compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; #address-cells = <1>; #size-cells = <0>; reg = <0xf800c000 0x100>; interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&clk32k>; - clock-names = "t0_clk", "slow_clk"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_GCK 35>, <&clk32k>; + clock-names = "t0_clk", "gclk", "slow_clk"; }; tcb1: timer@f8010000 { - compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; + compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; #address-cells = <1>; #size-cells = <0>; reg = <0xf8010000 0x100>; interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 36>, <&clk32k>; - clock-names = "t0_clk", "slow_clk"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 36>, <&pmc PMC_TYPE_GCK 36>, <&clk32k>; + clock-names = "t0_clk", "gclk", "slow_clk"; }; hsmc: hsmc@f8014000 { From patchwork Thu Jul 23 15:26:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 247090 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp1587408ilg; Thu, 23 Jul 2020 08:27:30 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwtmCDfDaYxv5vrcLUCj33VFrxg59SesENFS0k2CPKZuRJCCNxG90zoLfgi/EjgNevsaMSS X-Received: by 2002:a17:906:c0ce:: with SMTP id bn14mr4982489ejb.129.1595518049906; Thu, 23 Jul 2020 08:27:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1595518049; cv=none; d=google.com; s=arc-20160816; b=YKqJCsiYsSw1Wixz7GIz06uJxYaceLJWhcI79NjUszMuNNsBQwOzZkyWtAWdQ4i9uH pkT61hOAbjZo9kHKFg3Fdbtm4gXZdMlMPahhEeMeBnxNZdnEO0xyYpo0tJCZ6Tr5TXot pb66yNx7q4CV/lt2FiqMhStv6rAJsPrzOQmInutBewKPBUia+kCsaXgEyDsXiTAZ8nop Asuh+UVwHZyz+3hXOCcDI9R1iGoqn7QDdV5SEvBwbkhBcHK54hHhS6YoUsmY6GWpg9vh VUu4cDbpKD+tl4S0Ow7mk5KpJJRIOIGyFV3GmqSfq1IXHGCrTm2sJ5UBJhA9XPtJ16Ph KaWQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=kHJ+XeVbi6Fqf64rZGsvMfPCwEnJl/mkyREvWYHyzSs=; b=a1+3ypBgAxNJ+ORzXPgygqXbbSPwbCHpFkShdW2ZLkRhUZGT66m0ifYWGDDPD/KbVU eFKK4cUE3DFzL8GvUFokAXBw+urqv1kdxyMwwPcDeLjOCGZpbKJUSeKEOhhfS4iRJKrh z0a2u+T03vvA6HC8XU10ZB0zbXVyEkPfzbm+Gpk9cIGLtmMjSXTMMzPGK+fZYbjnuDMP tA8wWzQA3pSGlKt7VDZ9s3nBsBUgO3ddO8L89UtwsZ/7tCNv1D6JlyaMrUrpL70nj0RW 5RxUZKT1jh6XHMhiDaxTJaQau4xyFBPxW3FWvDZv1Tfs2YaOO+9NC+Rcf0Jw1kOADK/X NviQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=P+0A1dF9; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Klimov" , Rob Herring , Rob Herring , linux-kernel@vger.kernel.org (open list:CLOCKSOURCE, CLOCKEVENT DRIVERS), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS) Subject: [PATCH 14/16] clocksource/drivers: Replace HTTP links with HTTPS ones Date: Thu, 23 Jul 2020 17:26:34 +0200 Message-Id: <20200723152639.639771-14-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200723152639.639771-1-daniel.lezcano@linaro.org> References: <1b1122f4-bce9-f349-e602-ed8e14cbb501@linaro.org> <20200723152639.639771-1-daniel.lezcano@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: "Alexander A. Klimov" Rationale: Reduces attack surface on kernel devs opening the links for MITM as HTTPS traffic is much harder to manipulate. Deterministic algorithm: For each file: If not .svg: For each line: If doesn't contain `\bxmlns\b`: For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`: If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`: If both the HTTP and HTTPS versions return 200 OK and serve the same content: Replace HTTP with HTTPS. Signed-off-by: Alexander A. Klimov Acked-by: Rob Herring Signed-off-by: Daniel Lezcano Link: https://lore.kernel.org/r/20200708165856.15322-1-grandmaster@al2klimov.de --- Documentation/devicetree/bindings/timer/ti,keystone-timer.txt | 2 +- drivers/clocksource/timer-ti-32k.c | 2 +- drivers/clocksource/timer-ti-dm.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) -- 2.25.1 diff --git a/Documentation/devicetree/bindings/timer/ti,keystone-timer.txt b/Documentation/devicetree/bindings/timer/ti,keystone-timer.txt index 5fbe361252b4..d3905a5412b8 100644 --- a/Documentation/devicetree/bindings/timer/ti,keystone-timer.txt +++ b/Documentation/devicetree/bindings/timer/ti,keystone-timer.txt @@ -10,7 +10,7 @@ It is global timer is a free running up-counter and can generate interrupt when the counter reaches preset counter values. Documentation: -http://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf +https://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf Required properties: diff --git a/drivers/clocksource/timer-ti-32k.c b/drivers/clocksource/timer-ti-32k.c index ae12bbf3d68c..59b0be482f32 100644 --- a/drivers/clocksource/timer-ti-32k.c +++ b/drivers/clocksource/timer-ti-32k.c @@ -21,7 +21,7 @@ * Roughly modelled after the OMAP1 MPU timer code. * Added OMAP4 support - Santosh Shilimkar * - * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2015 Texas Instruments Incorporated - https://www.ti.com */ #include diff --git a/drivers/clocksource/timer-ti-dm.c b/drivers/clocksource/timer-ti-dm.c index 60aff087947a..33eeabf9c3d1 100644 --- a/drivers/clocksource/timer-ti-dm.c +++ b/drivers/clocksource/timer-ti-dm.c @@ -4,7 +4,7 @@ * * OMAP Dual-Mode Timers * - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/ * Tarun Kanti DebBarma * Thara Gopinath * From patchwork Thu Jul 23 15:26:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 247089 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp1587253ilg; Thu, 23 Jul 2020 08:27:19 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwzfvRj4sbOUwVPFjsYvJblsW72P46/ZcSCTf3Ef7Tv2xmEwt/wMmqIIZt9Cg6oXdteoFIX X-Received: by 2002:a17:906:b313:: with SMTP id n19mr4725429ejz.325.1595518039440; Thu, 23 Jul 2020 08:27:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1595518039; cv=none; d=google.com; s=arc-20160816; b=lmXbJF7s3ZHtBivIuUGbMM3xzDSv1m/OuWC+lLb6OdrzwGELJgWbVKoR5zW8q2Eyzd ys6q2C9ARzxXn96Vwq0ur+JlG7eSCp7rDtA0/NMfyiAj7G/5fR4y33slfsgYZyy4+b9u TzpF3QZD87ZaBMUS2njDSGx2BxlYS84Qmwif2Za5PuoFvibdZTBha7toLfyRNzSqmzzo KC9zzP0Ojwkf0VW/HzXXaqDbmQyWpT0VU7qk/3XepCE9MAzydVk1HteKMwwYUoL2/KkD WSHSwvLljriMsHEpj91223HaZmvVUhOZqxLOATvEQ9OOQ2yqbiA5LdetPKvHjv3oC1pK ZUow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=tsnEVgbRFSFGMlt+VQiCkCrNIR6sMOUDqSqxuXgPGHg=; b=gnrKxgENR/3TTyvwDW9blijYzbNfMDT4LauSCn7WNun2XzqIqvJ0MGKcQhoC0RUuoR 0cwTYSav6kJisoUP0WLnF2gQbx4LYWsGJQFsfmx4PN3XmHvbPUq3kpJfae+YKX6ZmWUU 0t6U/PuOYTYsBOytRfsllAEcXPgVduPVeN9UzMl1HMSAh2qlOuUmbTMUCfSTvZ0R06cQ 0F75Z7yAKaYM9gni2X3nQ2W3zqdXqbWQQruoHxQ5w4QYTiuikCwvoM9eFJVRo4Xbt+MC jb+vccyCiBO1tOwyblBxF52dc1q6j8RWfNoaVNz9wRFqz+BijR3W6Gmj7U4PpFbOmcbU pLQQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Cr23JDMp; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Date: Thu, 23 Jul 2020 17:26:35 +0200 Message-Id: <20200723152639.639771-15-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200723152639.639771-1-daniel.lezcano@linaro.org> References: <1b1122f4-bce9-f349-e602-ed8e14cbb501@linaro.org> <20200723152639.639771-1-daniel.lezcano@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: 周琰杰 (Zhou Yanjie) Add the OST bindings for the X1000 SoC from Ingenic. Tested-by: 周正 (Zhou Zheng) Signed-off-by: 周琰杰 (Zhou Yanjie) Reviewed-by: Paul Cercueil Reviewed-by: Rob Herring Signed-off-by: Daniel Lezcano Link: https://lore.kernel.org/r/20200722171804.97559-2-zhouyanjie@wanyeetech.com --- .../bindings/timer/ingenic,sysost.yaml | 63 +++++++++++++++++++ include/dt-bindings/clock/ingenic,sysost.h | 12 ++++ 2 files changed, 75 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/ingenic,sysost.yaml create mode 100644 include/dt-bindings/clock/ingenic,sysost.h -- 2.25.1 diff --git a/Documentation/devicetree/bindings/timer/ingenic,sysost.yaml b/Documentation/devicetree/bindings/timer/ingenic,sysost.yaml new file mode 100644 index 000000000000..df3eb76045e0 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/ingenic,sysost.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/ingenic,sysost.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Bindings for SYSOST in Ingenic XBurst family SoCs + +maintainers: + - 周琰杰 (Zhou Yanjie) + +description: + The SYSOST in an Ingenic SoC provides one 64bit timer for clocksource + and one or more 32bit timers for clockevent. + +properties: + "#clock-cells": + const: 1 + + compatible: + enum: + - ingenic,x1000-ost + - ingenic,x2000-ost + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: ost + + interrupts: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-names + - interrupts + +additionalProperties: false + +examples: + - | + #include + + ost: timer@12000000 { + compatible = "ingenic,x1000-ost"; + reg = <0x12000000 0x3c>; + + #clock-cells = <1>; + + clocks = <&cgu X1000_CLK_OST>; + clock-names = "ost"; + + interrupt-parent = <&cpuintc>; + interrupts = <3>; + }; +... diff --git a/include/dt-bindings/clock/ingenic,sysost.h b/include/dt-bindings/clock/ingenic,sysost.h new file mode 100644 index 000000000000..9ac88e90babf --- /dev/null +++ b/include/dt-bindings/clock/ingenic,sysost.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides clock numbers for the ingenic,tcu DT binding. + */ + +#ifndef __DT_BINDINGS_CLOCK_INGENIC_OST_H__ +#define __DT_BINDINGS_CLOCK_INGENIC_OST_H__ + +#define OST_CLK_PERCPU_TIMER 0 +#define OST_CLK_GLOBAL_TIMER 1 + +#endif /* __DT_BINDINGS_CLOCK_INGENIC_OST_H__ */