From patchwork Tue Jul 28 03:14:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahisa Kojima X-Patchwork-Id: 247208 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp161643ilg; Mon, 27 Jul 2020 20:15:12 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyiVER1cYesbw1HR6Qd9krwEgzQBNaE22ky9yqxt4ozAjkXs1R76Oz8v5i4eaMBR5r71gAO X-Received: by 2002:a05:6402:3113:: with SMTP id dc19mr23899653edb.20.1595906112124; Mon, 27 Jul 2020 20:15:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1595906112; cv=none; d=google.com; s=arc-20160816; b=uErscnB0YfS4k2Mg10EcdCuW3QoS5u/iDnwoAHkbdFBpL6bqU8r4vBz0ZcaZQSUuZk e9TLPbb9pivGD2eXjNTqByo6oux9GjcLR+YNy7POwgH7i2HzEp47N5ONQ9omff+hA2S1 EOUQRH2vD1eEO8wwh6UbWKy75BCJNJA2jk2g2pRmqoXqDvCC1Tp72g9Eyo3JqL5p0/Kf 0TlsNBGWU/DllAAGdSyKqaZ1JP2XHoADmexqM2ld8gf5GLJuyrorvBXS5F9XNJGV9OpQ CcJd7SdGrH7SL7mt7l0gFiAc5AqDMouzB5jmu8AcAFVMIrjV4CxcWuC24C6adPIMGHcw MzUA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=/t4x1lE/ln+iWxTd0oAMxFTi1bLACFMxmDNz8ZnbyNc=; b=H5XmDMT0V9I/z/TtQx7wffmIaXVbJyOp/ATpl44J0X1NNR6mQDJaIgVmOfUt6Fb8aH YXWRSxaWf/b+Vl+wt+HV0i2q4ILiHUQxVM/SQs/fR9aj6EiaXIjcpXlXIdPqLBJfGzR6 tbl6U76ReMm/Pcdg1FrMm4yXpHYZDv7Wx7IMUVCbEepKjJi6aBG2apjOE+ANSz5fy1vz BRQa2+azlYWIuhXp5cM8WY3YVT18tNRBl9mEJ3KM7Qt6i3qVKVPOL5qUHGkv/UJbBN/F Haf5Y0Zsrr8GWf4IKg7HsaROvGHyRCIaMo/W4cmDYJuAg/EGLQIs8i7Z5Ojf0gQQ4pB4 DQbg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CyZOFqJg; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id t15si1960015eje.543.2020.07.27.20.15.11; Mon, 27 Jul 2020 20:15:12 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CyZOFqJg; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726947AbgG1DPL (ORCPT + 6 others); Mon, 27 Jul 2020 23:15:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44344 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726944AbgG1DPK (ORCPT ); Mon, 27 Jul 2020 23:15:10 -0400 Received: from mail-pl1-x644.google.com (mail-pl1-x644.google.com [IPv6:2607:f8b0:4864:20::644]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1E6ECC0619D2 for ; Mon, 27 Jul 2020 20:15:10 -0700 (PDT) Received: by mail-pl1-x644.google.com with SMTP id w17so9158686ply.11 for ; Mon, 27 Jul 2020 20:15:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/t4x1lE/ln+iWxTd0oAMxFTi1bLACFMxmDNz8ZnbyNc=; b=CyZOFqJgDYD4ZLKir402Lq/oR5tQffh77J7UFxTayeAClA0cXIEjPFG+ZUXbPGjCmL itx7Uk+8Q9GtxvHWGW6rv+/v2en8qJmsTQMp9h129EXR4TxsXXI+cQ0lu9SjlQUjKqdK ESbUe1lywvJqLryHSi5WgpBOdXl2N5/eerL7bUNyqpwQyQDLWGJdHBnw0BiTZm1yOF79 D94pBWr3p5usy+xvNa1Ah+x2JI4cG+YR9Ji5Roe1mSHYMVUAnFqRbvRsNEeFi2WW4Oad N3S98BoQVyi+RZt/m90mSpEiMv6wyA2kn4o6fnh6nWeGn/tzjsgrk/w9oyNC9AtoZJ0d 9lYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/t4x1lE/ln+iWxTd0oAMxFTi1bLACFMxmDNz8ZnbyNc=; b=VBqAJFpUwuHknA80YAFq4i5EylfJvNE5X038MONYL46BHqqj/TzJzNi6IXiEVtXowE zISORh3y7+TeGOl+BFL8ER3Tw3ZsMkl1HDAyFN78+/DrJFYvLpv62/iRXnW+xnWZpyCz HU0vk2A0Qas61M/rU8GtbvAlaIXjbOKqQuIH6t99x5j9ZxczrK/T+aDncc3pBf/o/MLq 70UeE7vXfYCOHeZA7B1k2CT7vgVZxuxEh6+87wTeeYa+wUGCDLhdsi76DSM8YeKUcPM/ AxeV03rkCVHxJhofElkX5WoK1YaPtOiFa9IJ/qmBKXENW/hKjPHSC4Sh78v1Hj9YwF7F KE4Q== X-Gm-Message-State: AOAM530dk/jeiYZd+6h4a36jOTLdE+ZQrzK4hGVdRAYYJzLIMmgdjZZm rjLv2Lj0oUwQ9E/l6nBu/9ZyDwnDtUVhMA== X-Received: by 2002:a17:902:7791:: with SMTP id o17mr21600872pll.224.1595906109557; Mon, 27 Jul 2020 20:15:09 -0700 (PDT) Received: from debian.flets-east.jp ([2400:2411:502:a100:c84b:19e2:9b53:48bb]) by smtp.gmail.com with ESMTPSA id s10sm3895285pjf.3.2020.07.27.20.15.06 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 27 Jul 2020 20:15:08 -0700 (PDT) From: Masahisa Kojima To: linux-kernel@vger.kernel.org Cc: masahisa.kojima@linaro.org, jarkko.sakkinen@linux.intel.com, linux-arm-kernel@lists.infradead.org, ardb@kernel.org, devicetree@vger.kernel.org, linux-integrity@vger.kernel.org, peterhuewe@gmx.de, jgg@ziepe.ca Subject: [PATCH v5 1/2] tpm: tis: add support for MMIO TPM on SynQuacer Date: Tue, 28 Jul 2020 12:14:31 +0900 Message-Id: <20200728031433.3370-2-masahisa.kojima@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200728031433.3370-1-masahisa.kojima@linaro.org> References: <20200728031433.3370-1-masahisa.kojima@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org When fitted, the SynQuacer platform exposes its SPI TPM via a MMIO window that is backed by the SPI command sequencer in the SPI bus controller. This arrangement has the limitation that only byte size accesses are supported, and so we'll need to provide a separate module that take this into account. Signed-off-by: Ard Biesheuvel Signed-off-by: Masahisa Kojima --- drivers/char/tpm/Kconfig | 12 ++ drivers/char/tpm/Makefile | 1 + drivers/char/tpm/tpm_tis_synquacer.c | 208 +++++++++++++++++++++++++++ 3 files changed, 221 insertions(+) create mode 100644 drivers/char/tpm/tpm_tis_synquacer.c -- 2.20.1 Reviewed-by: Jarkko Sakkinen diff --git a/drivers/char/tpm/Kconfig b/drivers/char/tpm/Kconfig index 58b4c573d176..a18c314da211 100644 --- a/drivers/char/tpm/Kconfig +++ b/drivers/char/tpm/Kconfig @@ -74,6 +74,18 @@ config TCG_TIS_SPI_CR50 If you have a H1 secure module running Cr50 firmware on SPI bus, say Yes and it will be accessible from within Linux. +config TCG_TIS_SYNQUACER + tristate "TPM Interface Specification 1.2 Interface / TPM 2.0 FIFO Interface (MMIO - SynQuacer)" + depends on ARCH_SYNQUACER + select TCG_TIS_CORE + help + If you have a TPM security chip that is compliant with the + TCG TIS 1.2 TPM specification (TPM1.2) or the TCG PTP FIFO + specification (TPM2.0) say Yes and it will be accessible from + within Linux on Socionext SynQuacer platform. + To compile this driver as a module, choose M here; + the module will be called tpm_tis_synquacer. + config TCG_TIS_I2C_ATMEL tristate "TPM Interface Specification 1.2 Interface (I2C - Atmel)" depends on I2C diff --git a/drivers/char/tpm/Makefile b/drivers/char/tpm/Makefile index 9567e5197f74..84db4fb3a9c9 100644 --- a/drivers/char/tpm/Makefile +++ b/drivers/char/tpm/Makefile @@ -21,6 +21,7 @@ tpm-$(CONFIG_EFI) += eventlog/efi.o tpm-$(CONFIG_OF) += eventlog/of.o obj-$(CONFIG_TCG_TIS_CORE) += tpm_tis_core.o obj-$(CONFIG_TCG_TIS) += tpm_tis.o +obj-$(CONFIG_TCG_TIS_SYNQUACER) += tpm_tis_synquacer.o obj-$(CONFIG_TCG_TIS_SPI) += tpm_tis_spi.o tpm_tis_spi-y := tpm_tis_spi_main.o diff --git a/drivers/char/tpm/tpm_tis_synquacer.c b/drivers/char/tpm/tpm_tis_synquacer.c new file mode 100644 index 000000000000..e47bdd272704 --- /dev/null +++ b/drivers/char/tpm/tpm_tis_synquacer.c @@ -0,0 +1,208 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Linaro Ltd. + * + * This device driver implements MMIO TPM on SynQuacer Platform. + */ +#include +#include +#include +#include +#include +#include +#include +#include "tpm.h" +#include "tpm_tis_core.h" + +/* + * irq > 0 means: use irq $irq; + * irq = 0 means: autoprobe for an irq; + * irq = -1 means: no irq support + */ +struct tpm_tis_synquacer_info { + struct resource res; + int irq; +}; + +struct tpm_tis_synquacer_phy { + struct tpm_tis_data priv; + void __iomem *iobase; +}; + +static inline struct tpm_tis_synquacer_phy *to_tpm_tis_tcg_phy(struct tpm_tis_data *data) +{ + return container_of(data, struct tpm_tis_synquacer_phy, priv); +} + +static int tpm_tis_synquacer_read_bytes(struct tpm_tis_data *data, u32 addr, + u16 len, u8 *result) +{ + struct tpm_tis_synquacer_phy *phy = to_tpm_tis_tcg_phy(data); + + while (len--) + *result++ = ioread8(phy->iobase + addr); + + return 0; +} + +static int tpm_tis_synquacer_write_bytes(struct tpm_tis_data *data, u32 addr, + u16 len, const u8 *value) +{ + struct tpm_tis_synquacer_phy *phy = to_tpm_tis_tcg_phy(data); + + while (len--) + iowrite8(*value++, phy->iobase + addr); + + return 0; +} + +static int tpm_tis_synquacer_read16_bw(struct tpm_tis_data *data, + u32 addr, u16 *result) +{ + struct tpm_tis_synquacer_phy *phy = to_tpm_tis_tcg_phy(data); + + /* + * Due to the limitation of SPI controller on SynQuacer, + * 16/32 bits access must be done in byte-wise and descending order. + */ + *result = (ioread8(phy->iobase + addr + 1) << 8) | + (ioread8(phy->iobase + addr)); + + return 0; +} + +static int tpm_tis_synquacer_read32_bw(struct tpm_tis_data *data, + u32 addr, u32 *result) +{ + struct tpm_tis_synquacer_phy *phy = to_tpm_tis_tcg_phy(data); + + /* + * Due to the limitation of SPI controller on SynQuacer, + * 16/32 bits access must be done in byte-wise and descending order. + */ + *result = (ioread8(phy->iobase + addr + 3) << 24) | + (ioread8(phy->iobase + addr + 2) << 16) | + (ioread8(phy->iobase + addr + 1) << 8) | + (ioread8(phy->iobase + addr)); + + return 0; +} + +static int tpm_tis_synquacer_write32_bw(struct tpm_tis_data *data, + u32 addr, u32 value) +{ + struct tpm_tis_synquacer_phy *phy = to_tpm_tis_tcg_phy(data); + + /* + * Due to the limitation of SPI controller on SynQuacer, + * 16/32 bits access must be done in byte-wise and descending order. + */ + iowrite8(value >> 24, phy->iobase + addr + 3); + iowrite8(value >> 16, phy->iobase + addr + 2); + iowrite8(value >> 8, phy->iobase + addr + 1); + iowrite8(value, phy->iobase + addr); + + return 0; +} + +static const struct tpm_tis_phy_ops tpm_tcg_bw = { + .read_bytes = tpm_tis_synquacer_read_bytes, + .write_bytes = tpm_tis_synquacer_write_bytes, + .read16 = tpm_tis_synquacer_read16_bw, + .read32 = tpm_tis_synquacer_read32_bw, + .write32 = tpm_tis_synquacer_write32_bw, +}; + +static int tpm_tis_synquacer_init(struct device *dev, + struct tpm_tis_synquacer_info *tpm_info) +{ + struct tpm_tis_synquacer_phy *phy; + + phy = devm_kzalloc(dev, sizeof(struct tpm_tis_synquacer_phy), GFP_KERNEL); + if (phy == NULL) + return -ENOMEM; + + phy->iobase = devm_ioremap_resource(dev, &tpm_info->res); + if (IS_ERR(phy->iobase)) + return PTR_ERR(phy->iobase); + + return tpm_tis_core_init(dev, &phy->priv, tpm_info->irq, &tpm_tcg_bw, + ACPI_HANDLE(dev)); +} + +static SIMPLE_DEV_PM_OPS(tpm_tis_synquacer_pm, tpm_pm_suspend, tpm_tis_resume); + +static int tpm_tis_synquacer_probe(struct platform_device *pdev) +{ + struct tpm_tis_synquacer_info tpm_info = {}; + struct resource *res; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) { + dev_err(&pdev->dev, "no memory resource defined\n"); + return -ENODEV; + } + tpm_info.res = *res; + + tpm_info.irq = -1; + + return tpm_tis_synquacer_init(&pdev->dev, &tpm_info); +} + +static int tpm_tis_synquacer_remove(struct platform_device *pdev) +{ + struct tpm_chip *chip = dev_get_drvdata(&pdev->dev); + + tpm_chip_unregister(chip); + tpm_tis_remove(chip); + + return 0; +} + +#ifdef CONFIG_OF +static const struct of_device_id tis_synquacer_of_platform_match[] = { + {.compatible = "socionext,synquacer-tpm-mmio"}, + {}, +}; +MODULE_DEVICE_TABLE(of, tis_synquacer_of_platform_match); +#endif + +#ifdef CONFIG_ACPI +static const struct acpi_device_id tpm_synquacer_acpi_tbl[] = { + { "SCX0009" }, + {}, +}; +MODULE_DEVICE_TABLE(acpi, tpm_synquacer_acpi_tbl); +#endif + +static struct platform_driver tis_synquacer_drv = { + .probe = tpm_tis_synquacer_probe, + .remove = tpm_tis_synquacer_remove, + .driver = { + .name = "tpm_tis_synquacer", + .pm = &tpm_tis_synquacer_pm, + .of_match_table = of_match_ptr(tis_synquacer_of_platform_match), + .acpi_match_table = ACPI_PTR(tpm_synquacer_acpi_tbl), + }, +}; + +static int __init tpm_tis_synquacer_module_init(void) +{ + int rc; + + rc = platform_driver_register(&tis_synquacer_drv); + if (rc) + return rc; + + return 0; +} + +static void __exit tpm_tis_synquacer_module_exit(void) +{ + platform_driver_unregister(&tis_synquacer_drv); +} + +module_init(tpm_tis_synquacer_module_init); +module_exit(tpm_tis_synquacer_module_exit); +MODULE_DESCRIPTION("TPM MMIO Driver for Socionext SynQuacer platform"); +MODULE_LICENSE("GPL"); From patchwork Tue Jul 28 03:14:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahisa Kojima X-Patchwork-Id: 247209 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp161708ilg; Mon, 27 Jul 2020 20:15:18 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw9NjTn3p3eM4oS9oJipdZIpqf2mXJFBkwXgyZyjjVpfSJ6LSHrjxfbQ4tH/rQYkLM6fv9C X-Received: by 2002:a05:6402:31a3:: with SMTP id dj3mr8568559edb.73.1595906118528; Mon, 27 Jul 2020 20:15:18 -0700 (PDT) ARC-Seal: i=1; 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[23.128.96.18]) by mx.google.com with ESMTP id t15si1960015eje.543.2020.07.27.20.15.18; Mon, 27 Jul 2020 20:15:18 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EjwAA3KC; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726998AbgG1DPR (ORCPT + 6 others); Mon, 27 Jul 2020 23:15:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44368 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726989AbgG1DPR (ORCPT ); Mon, 27 Jul 2020 23:15:17 -0400 Received: from mail-pj1-x1041.google.com (mail-pj1-x1041.google.com [IPv6:2607:f8b0:4864:20::1041]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4E8EBC061794 for ; Mon, 27 Jul 2020 20:15:17 -0700 (PDT) Received: by mail-pj1-x1041.google.com with SMTP id ha11so3387905pjb.1 for ; Mon, 27 Jul 2020 20:15:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PD2ZLQCvLaWVcoV1PzZsr55F59ipm51nH9LfNuI1BWE=; b=EjwAA3KCQnsgyym83+P1cOxkyODRcSK9IpoGYOEK8mo9VSqUL4M+G3WzSpNJSRYQA9 y586nY0JjXTtfFnWhUCaxaE/0h4A5BMb85AH2INGsMulbg6VPaM/sY6p2gGS3DSzIqlX boAOW4/CtUL/7SK30IKifPmDizDBLglxmwmJh9IqHU/TYIA5Ru0CPlWcQ3nU0eQhDO5T Gtx4lpvl0TnG/jCP92EzfoGeSIQRbklRXSZmbE92OyLda3zwF7BtF6C/OB5EweH1I6e7 qKnPgAMoeLt4IVhHIvneIRBJkhNGkLh9ClXVIslrK10smMjWzOTuc4hyJddRtz3Q2vDv XdyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PD2ZLQCvLaWVcoV1PzZsr55F59ipm51nH9LfNuI1BWE=; b=lZZUxA9bl9rIZoyYQ+nmiVP2HjGoYFiKZ64L4pRbBfgYxu3JaDLufpsufJpgKfI9P4 SCxnCS2B6LH2E1lzLp3tLKqPm6xLsIi5+ipIq8m4+cPU5mvvYEnrlVhnRtvPMJVTdM3T /Xvvyb9sKCzm0KBYjumj7NHhnsiEiRxxTOaDGVhQwP2aw/bxDZDRkbB5fRrBKsjhy14S cTbZW1yzOqIQPbnRdqFcyF3c13+61wS0AUIrVllRChWg7X3u3XPMcrV7Tpup3ChflGOA o/hbudxRKnwQf9jTRneCr/kMt+r/luXjtcR2z6SPaqlarCXTb99eyhMIUCv6VDt9J4pT Cflw== X-Gm-Message-State: AOAM531NNWZOG7pidixEJadBFwkYiz2vE4ff3xUm8SJ445d+sROGgRfr 0N1aVKdk9LFWaNZ3tXeB6HsOUA== X-Received: by 2002:a17:90a:7805:: with SMTP id w5mr2362904pjk.192.1595906116854; Mon, 27 Jul 2020 20:15:16 -0700 (PDT) Received: from debian.flets-east.jp ([2400:2411:502:a100:c84b:19e2:9b53:48bb]) by smtp.gmail.com with ESMTPSA id s10sm3895285pjf.3.2020.07.27.20.15.13 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 27 Jul 2020 20:15:15 -0700 (PDT) From: Masahisa Kojima To: linux-kernel@vger.kernel.org Cc: masahisa.kojima@linaro.org, jarkko.sakkinen@linux.intel.com, linux-arm-kernel@lists.infradead.org, ardb@kernel.org, devicetree@vger.kernel.org, linux-integrity@vger.kernel.org, peterhuewe@gmx.de, jgg@ziepe.ca, Rob Herring , Rob Herring Subject: [PATCH v5 2/2] dt-bindings: Add SynQucer TPM MMIO as a trivial device Date: Tue, 28 Jul 2020 12:14:32 +0900 Message-Id: <20200728031433.3370-3-masahisa.kojima@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200728031433.3370-1-masahisa.kojima@linaro.org> References: <20200728031433.3370-1-masahisa.kojima@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a compatible string for the SynQuacer TPM to the binding for a TPM exposed via a memory mapped TIS frame. The MMIO window behaves slightly differently on this hardware, so it requires its own identifier. Cc: Rob Herring Cc: Ard Biesheuvel Acked-by: Rob Herring Signed-off-by: Masahisa Kojima --- Documentation/devicetree/bindings/trivial-devices.yaml | 2 ++ 1 file changed, 2 insertions(+) -- 2.20.1 Acked-by: Jarkko Sakkinen diff --git a/Documentation/devicetree/bindings/trivial-devices.yaml b/Documentation/devicetree/bindings/trivial-devices.yaml index 4165352a590a..814148939e5a 100644 --- a/Documentation/devicetree/bindings/trivial-devices.yaml +++ b/Documentation/devicetree/bindings/trivial-devices.yaml @@ -328,6 +328,8 @@ properties: - silabs,si7020 # Skyworks SKY81452: Six-Channel White LED Driver with Touch Panel Bias Supply - skyworks,sky81452 + # Socionext SynQuacer TPM MMIO module + - socionext,synquacer-tpm-mmio # i2c serial eeprom (24cxx) - st,24c256 # Ambient Light Sensor with SMBUS/Two Wire Serial Interface