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[209.51.188.17]) by mx.google.com with ESMTPS id n134si5093914yba.4.2020.08.21.22.55.19 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 21 Aug 2020 22:55:19 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@wdc.com header.s=dkim.wdc.com header.b=Q5JxoOCS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=wdc.com Received: from localhost ([::1]:60728 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1k9MUo-0008UC-Hc for patch@linaro.org; Sat, 22 Aug 2020 01:55:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33872) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1k9MR0-0001i8-Su for qemu-devel@nongnu.org; Sat, 22 Aug 2020 01:51:22 -0400 Received: from esa1.hgst.iphmx.com ([68.232.141.245]:23553) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1k9MQy-0000Ci-SQ for qemu-devel@nongnu.org; Sat, 22 Aug 2020 01:51:22 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1598075480; x=1629611480; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=yfYyKBsl1n2peeasbFsM3w2uLXt3XUd/TnbAhB/W+jI=; b=Q5JxoOCSnqwJ5Yuhoe3YnHibhMTSyUDewsHrzRaUWZYDKcmmMvux2ZvB T6kc8jDmjN91wpGEWK+5Z0KJ8vEahlxa45Rv7iLnpAgHwa0rz5Q38QOfS fZHFka0Or52EBEH+vcmhPrI0iYRaj76F39CRkdjLeRDvTnU699aIhJ0EH fObVMHAb2Pd2iBd8a6zdBzGX1tzlubxJb5JQRM7tBOUzB8J26EfMBf4Sc VKXZ9tNDUfP6Umoo7bJQL3dLP+9E9Zo9oqnZuL4v2ULkgdkPglHRxzNJM GDTxpDsISWsNPJ4IQSRISDe8bhrAPH1FLiLq2LRl5aEdAO9Lu5bMXvzdQ A==; IronPort-SDR: FBhnscrMybKtN4LLAN9BZS9r2+RcHwGHq/lZ4YmUoN97/lZZD0/u130QzIDBr16qc8u5z/zK7V AQe8JzO6+4mD/7M/xO8mPKr1UN1UolyuiJt3J34+3fu/CvmNjkwVgMaaFqAdnLk6xD4RYjWJd7 Bf0Z9QWZiIH8DDKiihBA+LYeyBkOWCxPe+yMo4J5zsyl+v2luR7ZcXc66WsqJR9CyCSmPmpYOA lJpKtPALPTXjKYiITBtEQ2lvibxsy5IhkLOM8JNEDpZICbGXL5ci0pk/bR56zRVM39xB+fcHBh lz4= X-IronPort-AV: E=Sophos;i="5.76,339,1592841600"; d="scan'208";a="255030528" Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 22 Aug 2020 13:51:15 +0800 IronPort-SDR: 1x5CSp5dxztqLguduQA6S5EEvQsgR3ucA/Fl0BT/oSzuh2gTFtCMerZkepsTTW4GDD2sU/BSqI ZEWbO+AwMySg== Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2020 22:38:56 -0700 IronPort-SDR: 5dIOCnC0Wn3hvMltJ8f10Md6ng3u/ob8cmAyWDDKCoZj2cvvAXBhA2W7N6EslxREwBfmURuxA7 m6xaObqfkPDA== WDCIronportException: Internal Received: from 5zn13g2.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.59.90]) by uls-op-cesaip02.wdc.com with ESMTP; 21 Aug 2020 22:51:16 -0700 From: Alistair Francis To: qemu-devel@nongnu.org Subject: [PULL v3 01/20] target/riscv: Generate nanboxed results from fp helpers Date: Fri, 21 Aug 2020 22:40:42 -0700 Message-Id: <20200822054101.1202175-2-alistair.francis@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200822054101.1202175-1-alistair.francis@wdc.com> References: <20200822054101.1202175-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=49637c5a7=alistair.francis@wdc.com; helo=esa1.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/22 01:51:16 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Richard Henderson , alistair.francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Make sure that all results from single-precision scalar helpers are properly nan-boxed to 64-bits. Signed-off-by: Richard Henderson Reviewed-by: LIU Zhiwei Message-Id: <20200724002807.441147-2-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/internals.h | 5 +++++ target/riscv/fpu_helper.c | 42 +++++++++++++++++++++------------------ 2 files changed, 28 insertions(+), 19 deletions(-) -- 2.28.0 diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 37d33820ad..9f4ba7d617 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -38,4 +38,9 @@ target_ulong fclass_d(uint64_t frs1); #define SEW32 2 #define SEW64 3 +static inline uint64_t nanbox_s(float32 f) +{ + return f | MAKE_64BIT_MASK(32, 32); +} + #endif diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c index 4379756dc4..72541958a7 100644 --- a/target/riscv/fpu_helper.c +++ b/target/riscv/fpu_helper.c @@ -81,10 +81,16 @@ void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm) set_float_rounding_mode(softrm, &env->fp_status); } +static uint64_t do_fmadd_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2, + uint64_t frs3, int flags) +{ + return nanbox_s(float32_muladd(frs1, frs2, frs3, flags, &env->fp_status)); +} + uint64_t helper_fmadd_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2, uint64_t frs3) { - return float32_muladd(frs1, frs2, frs3, 0, &env->fp_status); + return do_fmadd_s(env, frs1, frs2, frs3, 0); } uint64_t helper_fmadd_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2, @@ -96,8 +102,7 @@ uint64_t helper_fmadd_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2, uint64_t helper_fmsub_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2, uint64_t frs3) { - return float32_muladd(frs1, frs2, frs3, float_muladd_negate_c, - &env->fp_status); + return do_fmadd_s(env, frs1, frs2, frs3, float_muladd_negate_c); } uint64_t helper_fmsub_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2, @@ -110,8 +115,7 @@ uint64_t helper_fmsub_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2, uint64_t helper_fnmsub_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2, uint64_t frs3) { - return float32_muladd(frs1, frs2, frs3, float_muladd_negate_product, - &env->fp_status); + return do_fmadd_s(env, frs1, frs2, frs3, float_muladd_negate_product); } uint64_t helper_fnmsub_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2, @@ -124,8 +128,8 @@ uint64_t helper_fnmsub_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2, uint64_t helper_fnmadd_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2, uint64_t frs3) { - return float32_muladd(frs1, frs2, frs3, float_muladd_negate_c | - float_muladd_negate_product, &env->fp_status); + return do_fmadd_s(env, frs1, frs2, frs3, + float_muladd_negate_c | float_muladd_negate_product); } uint64_t helper_fnmadd_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2, @@ -137,37 +141,37 @@ uint64_t helper_fnmadd_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2, uint64_t helper_fadd_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2) { - return float32_add(frs1, frs2, &env->fp_status); + return nanbox_s(float32_add(frs1, frs2, &env->fp_status)); } uint64_t helper_fsub_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2) { - return float32_sub(frs1, frs2, &env->fp_status); + return nanbox_s(float32_sub(frs1, frs2, &env->fp_status)); } uint64_t helper_fmul_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2) { - return float32_mul(frs1, frs2, &env->fp_status); + return nanbox_s(float32_mul(frs1, frs2, &env->fp_status)); } uint64_t helper_fdiv_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2) { - return float32_div(frs1, frs2, &env->fp_status); + return nanbox_s(float32_div(frs1, frs2, &env->fp_status)); } uint64_t helper_fmin_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2) { - return float32_minnum(frs1, frs2, &env->fp_status); + return nanbox_s(float32_minnum(frs1, frs2, &env->fp_status)); } uint64_t helper_fmax_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2) { - return float32_maxnum(frs1, frs2, &env->fp_status); + return nanbox_s(float32_maxnum(frs1, frs2, &env->fp_status)); } uint64_t helper_fsqrt_s(CPURISCVState *env, uint64_t frs1) { - return float32_sqrt(frs1, &env->fp_status); + return nanbox_s(float32_sqrt(frs1, &env->fp_status)); } target_ulong helper_fle_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2) @@ -209,23 +213,23 @@ uint64_t helper_fcvt_lu_s(CPURISCVState *env, uint64_t frs1) uint64_t helper_fcvt_s_w(CPURISCVState *env, target_ulong rs1) { - return int32_to_float32((int32_t)rs1, &env->fp_status); + return nanbox_s(int32_to_float32((int32_t)rs1, &env->fp_status)); } uint64_t helper_fcvt_s_wu(CPURISCVState *env, target_ulong rs1) { - return uint32_to_float32((uint32_t)rs1, &env->fp_status); + return nanbox_s(uint32_to_float32((uint32_t)rs1, &env->fp_status)); } #if defined(TARGET_RISCV64) uint64_t helper_fcvt_s_l(CPURISCVState *env, uint64_t rs1) { - return int64_to_float32(rs1, &env->fp_status); + return nanbox_s(int64_to_float32(rs1, &env->fp_status)); } uint64_t helper_fcvt_s_lu(CPURISCVState *env, uint64_t rs1) { - return uint64_to_float32(rs1, &env->fp_status); + return nanbox_s(uint64_to_float32(rs1, &env->fp_status)); } #endif @@ -266,7 +270,7 @@ uint64_t helper_fmax_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2) uint64_t helper_fcvt_s_d(CPURISCVState *env, uint64_t rs1) { - return float64_to_float32(rs1, &env->fp_status); + return nanbox_s(float64_to_float32(rs1, &env->fp_status)); } uint64_t helper_fcvt_d_s(CPURISCVState *env, uint64_t rs1) From patchwork Sat Aug 22 05:40:43 2020 Content-Type: text/plain; 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[209.51.188.17]) by mx.google.com with ESMTPS id k9si4643026ybf.433.2020.08.21.22.51.47 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 21 Aug 2020 22:51:47 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@wdc.com header.s=dkim.wdc.com header.b=AZcyokCC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=wdc.com Received: from localhost ([::1]:44074 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1k9MRO-0001nk-Vi for patch@linaro.org; Sat, 22 Aug 2020 01:51:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33900) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1k9MR1-0001jW-LJ for qemu-devel@nongnu.org; Sat, 22 Aug 2020 01:51:23 -0400 Received: from esa1.hgst.iphmx.com ([68.232.141.245]:23559) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1k9MQz-0000DF-En for qemu-devel@nongnu.org; Sat, 22 Aug 2020 01:51:23 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1598075481; x=1629611481; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=s+Qui1yOY/DT0/NEtJwMy6JHTS2A8SdJ6rIojxXUwmA=; b=AZcyokCCpiilTAV2BdVyGQ2xaGieuNto19xdDknWHmElxxLbHslLu5nm BRvIuX2YdViyKgtTF/fVGWx260ER4prxC7JEgxIjIFBnHJjQBIBOVZEfC kPORqUn3/MobdH4hohmX7ya+kg+Ql1qBH+UoQGH95N6fiFpic4oXnrsCw DV/PLuv9XTDz88Y8TxIEbKFHWuajqjR13RS/uMs9X4FfGNkUSuyVdVrUW R7CN4tXsvqxlrpJN+LqsfYxtkejl9r3cVfdMNOwk3RZw8oJQ7aVqyLufu xcE59Oi6xwU39UmLjqOTZIKIE+n1Q4v63qh+VbQqUbXpKuxVcmgZ64j4p A==; IronPort-SDR: 2U7UhLOu6S2hS/Gj215hYTrdFY/VIOSbN/SjATPyVBwAcI2OJq8BbmMc2YrfUdWPWtuohFwNFV ow3ogFD0S77PsrywzgcVfMeKPM1tXyLdc9xlHAr2T54dccJrkKm+y0+pvGY3tCJhWILTkDrJqL uK5yDCboNsrlAOE2+gLfxuSwFMMmRJrIMLTntKHtWVvLtsnJ3loACuLHE3DVg+dmK6NMp+3pgf niDG3VTcbyoqqj84aPNDvGRCj2Y2/k+gbqSngfEQfnWGxWKX0AC1qnmow9Q7nkUbnd5hU2F0b9 dWo= X-IronPort-AV: E=Sophos;i="5.76,339,1592841600"; d="scan'208";a="255030529" Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 22 Aug 2020 13:51:16 +0800 IronPort-SDR: VNipglq2fUV82pVKZL0QSXA1Dv0wXIUYFTg1p9DyO1QGLL9L5tYChBkF3kuTR0AghkCbWlOE2o FstzthWqNkng== Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2020 22:38:56 -0700 IronPort-SDR: weEKyVdaZIleEyCJLwMABkCmcTHNAWpBusvqDu9RD1aLrA8oRIgL+iDOsDmewU/8bVuBgaB7BR 2TRNbKcA5vsQ== WDCIronportException: Internal Received: from 5zn13g2.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.59.90]) by uls-op-cesaip02.wdc.com with ESMTP; 21 Aug 2020 22:51:17 -0700 From: Alistair Francis To: qemu-devel@nongnu.org Subject: [PULL v3 02/20] target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_s Date: Fri, 21 Aug 2020 22:40:43 -0700 Message-Id: <20200822054101.1202175-3-alistair.francis@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200822054101.1202175-1-alistair.francis@wdc.com> References: <20200822054101.1202175-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=49637c5a7=alistair.francis@wdc.com; helo=esa1.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/22 01:51:16 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Richard Henderson , alistair.francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Do not depend on the RVD extension, take input and output via TCGv_i64 instead of fpu regno. Move the function to translate.c so that it can be used in multiple trans_*.inc.c files. Signed-off-by: Richard Henderson Reviewed-by: LIU Zhiwei Message-Id: <20200724002807.441147-3-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/translate.c | 11 +++++++++++ target/riscv/insn_trans/trans_rvf.c.inc | 16 +--------------- 2 files changed, 12 insertions(+), 15 deletions(-) -- 2.28.0 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index d0485c0750..1290faddda 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -90,6 +90,17 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext) return ctx->misa & ext; } +/* + * RISC-V requires NaN-boxing of narrower width floating point values. + * This applies when a 32-bit value is assigned to a 64-bit FP register. + * For consistency and simplicity, we nanbox results even when the RVD + * extension is not present. + */ +static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) +{ + tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); +} + static void generate_exception(DisasContext *ctx, int excp) { tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc index 3bfd8881e7..c7057482e8 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -23,20 +23,6 @@ return false; \ } while (0) -/* - * RISC-V requires NaN-boxing of narrower width floating - * point values. This applies when a 32-bit value is - * assigned to a 64-bit FP register. Thus this does not - * apply when the RVD extension is not present. - */ -static void gen_nanbox_fpr(DisasContext *ctx, int regno) -{ - if (has_ext(ctx, RVD)) { - tcg_gen_ori_i64(cpu_fpr[regno], cpu_fpr[regno], - MAKE_64BIT_MASK(32, 32)); - } -} - static bool trans_flw(DisasContext *ctx, arg_flw *a) { TCGv t0 = tcg_temp_new(); @@ -46,7 +32,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a) tcg_gen_addi_tl(t0, t0, a->imm); tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL); - gen_nanbox_fpr(ctx, a->rd); + gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]); tcg_temp_free(t0); mark_fs_dirty(ctx); From patchwork Sat Aug 22 05:40:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 248142 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:522:0:0:0:0 with SMTP id h2csp942911ils; Fri, 21 Aug 2020 22:53:20 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy5AoIqJCQSXU8bGx50EgtfLBgrOzuSAO+a5VRj9WMDuWMWcSHnm5VVxxfLXa14DgQi9m/G X-Received: by 2002:a25:ae43:: with SMTP id g3mr8428356ybe.459.1598075600726; Fri, 21 Aug 2020 22:53:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598075600; cv=none; d=google.com; s=arc-20160816; b=bbapBU+lB9kSDEzSkY2U+gNKt/KyNgFDkzakdp0nH+Gll3TnsvrgYmTQZBfm7X9z7d EHeNnqFOr/i1QR9j/rc/cRiOiItlfuAjRxBVdEWjAVGA1rhmaSiS8hWpa1iYxtz8DdQX /8yxgnww2pmFkSjNF1NgQ4hS1mGrU4KAk8O08UXrY4Ui6bEfN0UvsMD9cArQBZjnR04y iBJuHFoKfJuhgHI1uiEvLABfiasFapatBNhQbxn8I/uYGxtXc4tibdm3vXPP+x+ZlDQb l3IP6rzY9cHlN4oq7I9DuhSWkCOOxT5Ll6GQZLR5CUW9ndwTa9tP6P4FYeOXgAenOQd4 uZkg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :wdcironportexception:ironport-sdr:ironport-sdr:ironport-sdr :dkim-signature; bh=r7eTwJR9kuw0jUk+7t5cxfKawU46fdeKANZvYVejs2k=; b=k1qSWnh1b2fZOy7guJTM7tgf1aJxvVPpRBOVHqz33BDndjDWJlQLVBNTlapD2Ou9VM fklIJBGcgQQEftRK1ccO/q1rlOV5ygvi0sRKXj7J0N7xLdfBBgfR3a68fRUArMvpDBiy MSQS7cyZw90OMAnKvJbgFENcTH0WTCyuaVHyO5eByqwOafZTTTCNHdym6IoHJK+x9cmN XciB0BekngFDl825bUyDCI2xzYBKRNDQ3XGK+4yRYJxCMAWaBXnxYo8TDYGp6olJS12Q Mi48+L2xYNdYNEtoKnrkMh/Tgu9N7jEqifu8nN1Gl1QrT4E8iGMctdIzSa/mu41hAbwp 71tw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@wdc.com header.s=dkim.wdc.com header.b=fwY9H120; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson Reviewed-by: LIU Zhiwei Message-Id: <20200724002807.441147-4-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvf.c.inc | 4 ++++ 1 file changed, 4 insertions(+) -- 2.28.0 diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc index c7057482e8..264d3139f1 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -167,6 +167,7 @@ static bool trans_fsgnj_s(DisasContext *ctx, arg_fsgnj_s *a) tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rs2], cpu_fpr[a->rs1], 0, 31); } + gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]); mark_fs_dirty(ctx); return true; } @@ -183,6 +184,7 @@ static bool trans_fsgnjn_s(DisasContext *ctx, arg_fsgnjn_s *a) tcg_gen_deposit_i64(cpu_fpr[a->rd], t0, cpu_fpr[a->rs1], 0, 31); tcg_temp_free_i64(t0); } + gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]); mark_fs_dirty(ctx); return true; } @@ -199,6 +201,7 @@ static bool trans_fsgnjx_s(DisasContext *ctx, arg_fsgnjx_s *a) tcg_gen_xor_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], t0); tcg_temp_free_i64(t0); } + gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]); mark_fs_dirty(ctx); return true; } @@ -369,6 +372,7 @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a) #else tcg_gen_extu_i32_i64(cpu_fpr[a->rd], t0); #endif + gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]); mark_fs_dirty(ctx); tcg_temp_free(t0); From patchwork Sat Aug 22 05:40:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 248143 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:522:0:0:0:0 with SMTP id h2csp943401ils; Fri, 21 Aug 2020 22:54:48 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwt0p+TYe5GuiwQkVd7VHJ68sgF3PNzjYPLtHslg6VrHRZvjwANaRuUD9ysXBjJ9XsKXnrG X-Received: by 2002:a25:ca85:: with SMTP id a127mr7871517ybg.369.1598075688858; Fri, 21 Aug 2020 22:54:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598075688; cv=none; d=google.com; s=arc-20160816; b=rmX0VK1ru9YOXCZTtauq/pdMwRw3qetIlx0NVIJLBPTbSg3LhaHA9BSRQEYZEbRfhK 2MQdgYTAhop4twvU6WHZPvNTjfZ8fd/hxlZLXn9hcIt54o4K9XwWIcBnTvIKD4FnVVDI AmQTzhptFEcCVcQ28jJCR/YeAUBxRJ4c3ozXGAqDqrtAhhrMWy91xIprBM/at5jdW12M eHnWI0pMLu2s+eyB0JZDoBwsdmLCL9k1iXcYNmrc33fgirld21MijkkpPzXWjWPK5bVP nzFFwCcRXo+w7l5dEL8yFP49bZTo+rYkysgslzX8lm83P6g2jsqSOnzrcV80HaQStQa2 7nlA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :wdcironportexception:ironport-sdr:ironport-sdr:ironport-sdr :dkim-signature; bh=40q0SSqklbOe9KdZnS0JT2pIcfF6uW8ie6wwfkuT45M=; b=UX8BE1tVlBMu/RdKFhq4uXsgDc8PD3UB1FqXrxjmyJeHH6FjG1DoA4c0yi/GZoQjvL CsmmVYigxGX7psatKR84a9C2/nCi3RaE9fmI8OvmSuXe8t3paC6FoJUrNUpp+4yAyc8F +3FOoFHuToXPhIVZ780m+KjelbosTrlMQnby3HlesiS3DXDVdvSnIZI24kLBGCsWjWRS 3CuMgwXFU8xD2z+Wwhd/QSn0warBcDmRHO1peBL1g4AsyX9LhX9D0aArAO1Z4JeMDVJN zMV/FbZ3AZ6Ub049XBoeveSq9kkLdUirrgkmlbbJRLWuL5KfdBjabFhaxz9Q2WeWVk7z hFBw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@wdc.com header.s=dkim.wdc.com header.b=ojjbGnRH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id h63si4447640ybg.488.2020.08.21.22.54.48 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 21 Aug 2020 22:54:48 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@wdc.com header.s=dkim.wdc.com header.b=ojjbGnRH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=wdc.com Received: from localhost ([::1]:32784 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1k9MUK-0000B4-Ai for patch@linaro.org; Sat, 22 Aug 2020 01:54:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33988) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1k9MR6-0001uT-46 for qemu-devel@nongnu.org; Sat, 22 Aug 2020 01:51:28 -0400 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:62896) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1k9MR3-0000E7-Se for qemu-devel@nongnu.org; Sat, 22 Aug 2020 01:51:27 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1598075503; x=1629611503; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=sFvFvjNjpUCti0g6dQBNn6K8GaHBoa/jE4d+xGvVp5E=; b=ojjbGnRHZVNFu5mOVT0Q7bS74anThPSpcL4rOCFF6baa0A8JXeKEHAAG pMGGUOFQm7yIUPGnBFm4J46JVRVeTKuldbX/h5X+VsuqX88RyKR1tHFUA PA0q3XtkNkRAzbJp7gIYXgMnv3Il4SiJJ/pj6FWPENMIUBFUzyozw9VsS NjEIif8sDGak8WVOMn0J0Nueo+TeEsmvYJcMpWW5ew8fSd6bZz5ZzSowp U2Q/vypPBAQjjYh3STbml7dcyUauc1pauwVuueIfaJhdbZYZ7WMKg0INI Nq31eOps7d+EcNjxqiGO4D77eIeaezHOCIXbHPDb5gsDFUb82RoOwIIdU g==; IronPort-SDR: FVO892yeTC7NCK3hgV8WIbEfAl9xBxkIJykZEdBCU6z26Y2pdLggDIEq8xdeqmCdBiuJo3YeZD 3UiRe3jmZ6capucll/+VNBzyyRJvYqzvdyJKLSpa6bMgW8OKz1ZMNqE8SgCo6n4/AjTH/8/yla pbYFxcC5NVKBo/lFVpIOXmcZmZHeS/wC/BYWfQ2/Or+V2UC0lzYCW+FBf5BfaGOYOWKZKZacTs iEcX3LkBGUYXafxBQZ4VJuGsA74FGPkbVz55lPc7xUgI6mKY+Sc7NfXtjOiSLVnKSf4+wNg4Kj sfI= X-IronPort-AV: E=Sophos;i="5.76,339,1592841600"; d="scan'208";a="248764773" Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 22 Aug 2020 13:51:29 +0800 IronPort-SDR: qK+6Utd7VEpRT0Eb3N+sKtjRBrsYtcqrV2g8Q+FoJ/hOJNorZHGl91EPOD994bInVx5ihE3QYe R85zxlvGPoXQ== Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2020 22:38:56 -0700 IronPort-SDR: OTO316WXzKiZTHzemN+SHnREg48czRNP8JgcBzXYQqje9kM0PwYYV0bgcAWebJ5tCg+jiABtEH 2L3tRhSRPEGA== WDCIronportException: Internal Received: from 5zn13g2.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.59.90]) by uls-op-cesaip02.wdc.com with ESMTP; 21 Aug 2020 22:51:17 -0700 From: Alistair Francis To: qemu-devel@nongnu.org Subject: [PULL v3 04/20] target/riscv: Check nanboxed inputs to fp helpers Date: Fri, 21 Aug 2020 22:40:45 -0700 Message-Id: <20200822054101.1202175-5-alistair.francis@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200822054101.1202175-1-alistair.francis@wdc.com> References: <20200822054101.1202175-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=49637c5a7=alistair.francis@wdc.com; helo=esa2.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/22 01:51:23 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Richard Henderson , alistair.francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson If a 32-bit input is not properly nanboxed, then the input is replaced with the default qnan. Signed-off-by: Richard Henderson Reviewed-by: LIU Zhiwei Message-Id: <20200724002807.441147-5-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/internals.h | 11 +++++++ target/riscv/fpu_helper.c | 64 ++++++++++++++++++++++++++++----------- 2 files changed, 57 insertions(+), 18 deletions(-) -- 2.28.0 diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 9f4ba7d617..f1a546dba6 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -43,4 +43,15 @@ static inline uint64_t nanbox_s(float32 f) return f | MAKE_64BIT_MASK(32, 32); } +static inline float32 check_nanbox_s(uint64_t f) +{ + uint64_t mask = MAKE_64BIT_MASK(32, 32); + + if (likely((f & mask) == mask)) { + return (uint32_t)f; + } else { + return 0x7fc00000u; /* default qnan */ + } +} + #endif diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c index 72541958a7..bb346a8249 100644 --- a/target/riscv/fpu_helper.c +++ b/target/riscv/fpu_helper.c @@ -81,9 +81,12 @@ void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm) set_float_rounding_mode(softrm, &env->fp_status); } -static uint64_t do_fmadd_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2, - uint64_t frs3, int flags) +static uint64_t do_fmadd_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2, + uint64_t rs3, int flags) { + float32 frs1 = check_nanbox_s(rs1); + float32 frs2 = check_nanbox_s(rs2); + float32 frs3 = check_nanbox_s(rs3); return nanbox_s(float32_muladd(frs1, frs2, frs3, flags, &env->fp_status)); } @@ -139,74 +142,97 @@ uint64_t helper_fnmadd_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2, float_muladd_negate_product, &env->fp_status); } -uint64_t helper_fadd_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2) +uint64_t helper_fadd_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) { + float32 frs1 = check_nanbox_s(rs1); + float32 frs2 = check_nanbox_s(rs2); return nanbox_s(float32_add(frs1, frs2, &env->fp_status)); } -uint64_t helper_fsub_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2) +uint64_t helper_fsub_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) { + float32 frs1 = check_nanbox_s(rs1); + float32 frs2 = check_nanbox_s(rs2); return nanbox_s(float32_sub(frs1, frs2, &env->fp_status)); } -uint64_t helper_fmul_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2) +uint64_t helper_fmul_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) { + float32 frs1 = check_nanbox_s(rs1); + float32 frs2 = check_nanbox_s(rs2); return nanbox_s(float32_mul(frs1, frs2, &env->fp_status)); } -uint64_t helper_fdiv_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2) +uint64_t helper_fdiv_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) { + float32 frs1 = check_nanbox_s(rs1); + float32 frs2 = check_nanbox_s(rs2); return nanbox_s(float32_div(frs1, frs2, &env->fp_status)); } -uint64_t helper_fmin_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2) +uint64_t helper_fmin_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) { + float32 frs1 = check_nanbox_s(rs1); + float32 frs2 = check_nanbox_s(rs2); return nanbox_s(float32_minnum(frs1, frs2, &env->fp_status)); } -uint64_t helper_fmax_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2) +uint64_t helper_fmax_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) { + float32 frs1 = check_nanbox_s(rs1); + float32 frs2 = check_nanbox_s(rs2); return nanbox_s(float32_maxnum(frs1, frs2, &env->fp_status)); } -uint64_t helper_fsqrt_s(CPURISCVState *env, uint64_t frs1) +uint64_t helper_fsqrt_s(CPURISCVState *env, uint64_t rs1) { + float32 frs1 = check_nanbox_s(rs1); return nanbox_s(float32_sqrt(frs1, &env->fp_status)); } -target_ulong helper_fle_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2) +target_ulong helper_fle_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) { + float32 frs1 = check_nanbox_s(rs1); + float32 frs2 = check_nanbox_s(rs2); return float32_le(frs1, frs2, &env->fp_status); } -target_ulong helper_flt_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2) +target_ulong helper_flt_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) { + float32 frs1 = check_nanbox_s(rs1); + float32 frs2 = check_nanbox_s(rs2); return float32_lt(frs1, frs2, &env->fp_status); } -target_ulong helper_feq_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2) +target_ulong helper_feq_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) { + float32 frs1 = check_nanbox_s(rs1); + float32 frs2 = check_nanbox_s(rs2); return float32_eq_quiet(frs1, frs2, &env->fp_status); } -target_ulong helper_fcvt_w_s(CPURISCVState *env, uint64_t frs1) +target_ulong helper_fcvt_w_s(CPURISCVState *env, uint64_t rs1) { + float32 frs1 = check_nanbox_s(rs1); return float32_to_int32(frs1, &env->fp_status); } -target_ulong helper_fcvt_wu_s(CPURISCVState *env, uint64_t frs1) +target_ulong helper_fcvt_wu_s(CPURISCVState *env, uint64_t rs1) { + float32 frs1 = check_nanbox_s(rs1); return (int32_t)float32_to_uint32(frs1, &env->fp_status); } #if defined(TARGET_RISCV64) -uint64_t helper_fcvt_l_s(CPURISCVState *env, uint64_t frs1) +uint64_t helper_fcvt_l_s(CPURISCVState *env, uint64_t rs1) { + float32 frs1 = check_nanbox_s(rs1); return float32_to_int64(frs1, &env->fp_status); } -uint64_t helper_fcvt_lu_s(CPURISCVState *env, uint64_t frs1) +uint64_t helper_fcvt_lu_s(CPURISCVState *env, uint64_t rs1) { + float32 frs1 = check_nanbox_s(rs1); return float32_to_uint64(frs1, &env->fp_status); } #endif @@ -233,8 +259,9 @@ uint64_t helper_fcvt_s_lu(CPURISCVState *env, uint64_t rs1) } #endif -target_ulong helper_fclass_s(uint64_t frs1) +target_ulong helper_fclass_s(uint64_t rs1) { + float32 frs1 = check_nanbox_s(rs1); return fclass_s(frs1); } @@ -275,7 +302,8 @@ uint64_t helper_fcvt_s_d(CPURISCVState *env, uint64_t rs1) uint64_t helper_fcvt_d_s(CPURISCVState *env, uint64_t rs1) { - return float32_to_float64(rs1, &env->fp_status); + float32 frs1 = check_nanbox_s(rs1); + return float32_to_float64(frs1, &env->fp_status); } uint64_t helper_fsqrt_d(CPURISCVState *env, uint64_t frs1) From patchwork Sat Aug 22 05:40:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 248141 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:522:0:0:0:0 with SMTP id h2csp942549ils; Fri, 21 Aug 2020 22:52:24 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwYf9g4+Kh2k2g1fdKyDpzrX6k66bt6HnDRu+qKjmm6FEO7aPOEDrp0Bt1r0Wlh3/lSsG84 X-Received: by 2002:a25:3a81:: with SMTP id h123mr7490695yba.427.1598075544402; Fri, 21 Aug 2020 22:52:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1598075544; cv=none; d=google.com; s=arc-20160816; b=S4Nbup1ZtQW9V4wutBOtP8WUW8CEQRC/3GiiJ3H1gFPRSjX1lugQzx+/8rAPQPyC6u FZdZYFQjfBO0Tbae55MfnZiypcjwNioFdNBe36sdy2tIlRYSZWM6AE90gvRWUSIjZ14o v6JWBGTta/pus31YWPKSZFMnbcrMQSaTBSv725byoOYq2GOnJCTPOiUQUM9asDCWvi0b MmxERxMS4JzOY3kf/wFRXdD2csq6VKRxKCnJa08u/lcGWLQ5iDOBYL/Ucqkh1g1dXBib W0pXUdNsGNx5BJizG7wpdJapAO1fmTMk4nrUCM3Ts3YbdGGWCKV4S1AOH5t17giQ1mBi c9LA== ARC-Message-Signature: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id k137si4567538ybk.139.2020.08.21.22.52.24 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 21 Aug 2020 22:52:24 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@wdc.com header.s=dkim.wdc.com header.b=gek9GKaq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=wdc.com Received: from localhost ([::1]:43844 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1k9MRz-0001hc-RY for patch@linaro.org; Sat, 22 Aug 2020 01:52:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33822) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1k9MQz-0001go-4S for qemu-devel@nongnu.org; Sat, 22 Aug 2020 01:51:21 -0400 Received: from esa5.hgst.iphmx.com ([216.71.153.144]:26625) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1k9MQw-0000Cq-Fo for qemu-devel@nongnu.org; Sat, 22 Aug 2020 01:51:20 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1598075478; x=1629611478; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=QOEvjCXdTrn+yzhxdiLzckYSauafsPy96xz9Wgxo0EQ=; b=gek9GKaq/E5FJxRBO7mkqV/a7G/AmAFUfLpNapasIxnt1Iir/HaNaGP/ gKGYxxPsvV2NmWua3zIkd92yBl2jljHhjMvrFsPEkgbW40BO+mO4bAtF7 r4GJSWn43S1IUdR8y0PKoIM4vzv+u1+vuZljj5Uupiigo2kt7PoHQxdHa Ie7UnEwmABBUk96G3NJJaq9DFlnr/6doDJrCyt1jwCMHbsSX9xpAIfzhd hEWAa0eEMI3R7U/3CQQIoo5J7BhrLTvAKEwEUtbAwhUEX3JboPgOO849o JC8oDDRaeJlI1Q828TWNb1JU8cqsETs2o6vLM8SIKeB+6sdMo73ZJQcVu g==; IronPort-SDR: ChaYnD1e+X9zyQuNi5IhmiJz6l19oSVgFb5JK26WjhwLUPWXKX645c5aSdB4Ku6JtPO3nd8Yt9 3TPB0B//+01XoSqjVLTdLHTnwiQHjUGeC29NqMHLBN/Q9C1pUB2St7cUPnexJoXVvl0P57XYou Fz212JJFA8mU6F0kv+gwYWppDUmZ+EQbcX55Xr2JlTb6H8qCSqr8kVsQwSZR6203G/vyECPrIZ JCreKl98G0Imtj8nRqpNJsnZFhn2O17kwYiXYh/M9c2dkQ8pgsqQUSg5QiJ70ob88z+dDAZKop 9uQ= X-IronPort-AV: E=Sophos;i="5.76,339,1592841600"; d="scan'208";a="145571951" Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 22 Aug 2020 13:51:17 +0800 IronPort-SDR: 2hye634TuW8w0QOVO8nVQQxYJahC8oHTTnDEmM7+eT/7xHo0P9XmJvkn1CBTzTOu5pQ1iveK69 46VIx6GaZs1w== Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2020 22:38:57 -0700 IronPort-SDR: FpjkWDG6VDJug1jG0HTBdB8XmLWFODg5Fh3sR7mFr9H7eZpziHsKXlij6YIcZ+WrvZ7GmIXkNL zwg1G89pEdvw== WDCIronportException: Internal Received: from 5zn13g2.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.59.90]) by uls-op-cesaip02.wdc.com with ESMTP; 21 Aug 2020 22:51:17 -0700 From: Alistair Francis To: qemu-devel@nongnu.org Subject: [PULL v3 05/20] target/riscv: Check nanboxed inputs in trans_rvf.inc.c Date: Fri, 21 Aug 2020 22:40:46 -0700 Message-Id: <20200822054101.1202175-6-alistair.francis@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200822054101.1202175-1-alistair.francis@wdc.com> References: <20200822054101.1202175-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=49637c5a7=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/22 01:43:18 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Richard Henderson , alistair.francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson If a 32-bit input is not properly nanboxed, then the input is replaced with the default qnan. The only inline expansion is for the sign-changing set of instructions: FSGNJ.S, FSGNJX.S, FSGNJN.S. Signed-off-by: Richard Henderson Reviewed-by: LIU Zhiwei Message-Id: <20200724002807.441147-6-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/translate.c | 18 +++++++ target/riscv/insn_trans/trans_rvf.c.inc | 71 +++++++++++++++++++------ 2 files changed, 73 insertions(+), 16 deletions(-) -- 2.28.0 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 1290faddda..3919f570f7 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -101,6 +101,24 @@ static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); } +/* + * A narrow n-bit operation, where n < FLEN, checks that input operands + * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1. + * If so, the least-significant bits of the input are used, otherwise the + * input value is treated as an n-bit canonical NaN (v2.2 section 9.2). + * + * Here, the result is always nan-boxed, even the canonical nan. + */ +static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) +{ + TCGv_i64 t_max = tcg_const_i64(0xffffffff00000000ull); + TCGv_i64 t_nan = tcg_const_i64(0xffffffff7fc00000ull); + + tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); + tcg_temp_free_i64(t_max); + tcg_temp_free_i64(t_nan); +} + static void generate_exception(DisasContext *ctx, int excp) { tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc index 264d3139f1..832f01db6f 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -161,47 +161,86 @@ static bool trans_fsgnj_s(DisasContext *ctx, arg_fsgnj_s *a) { REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); + if (a->rs1 == a->rs2) { /* FMOV */ - tcg_gen_mov_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1]); + gen_check_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rs1]); } else { /* FSGNJ */ - tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rs2], cpu_fpr[a->rs1], - 0, 31); + TCGv_i64 rs1 = tcg_temp_new_i64(); + TCGv_i64 rs2 = tcg_temp_new_i64(); + + gen_check_nanbox_s(rs1, cpu_fpr[a->rs1]); + gen_check_nanbox_s(rs2, cpu_fpr[a->rs2]); + + /* This formulation retains the nanboxing of rs2. */ + tcg_gen_deposit_i64(cpu_fpr[a->rd], rs2, rs1, 0, 31); + tcg_temp_free_i64(rs1); + tcg_temp_free_i64(rs2); } - gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]); mark_fs_dirty(ctx); return true; } static bool trans_fsgnjn_s(DisasContext *ctx, arg_fsgnjn_s *a) { + TCGv_i64 rs1, rs2, mask; + REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); + + rs1 = tcg_temp_new_i64(); + gen_check_nanbox_s(rs1, cpu_fpr[a->rs1]); + if (a->rs1 == a->rs2) { /* FNEG */ - tcg_gen_xori_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], INT32_MIN); + tcg_gen_xori_i64(cpu_fpr[a->rd], rs1, MAKE_64BIT_MASK(31, 1)); } else { - TCGv_i64 t0 = tcg_temp_new_i64(); - tcg_gen_not_i64(t0, cpu_fpr[a->rs2]); - tcg_gen_deposit_i64(cpu_fpr[a->rd], t0, cpu_fpr[a->rs1], 0, 31); - tcg_temp_free_i64(t0); + rs2 = tcg_temp_new_i64(); + gen_check_nanbox_s(rs2, cpu_fpr[a->rs2]); + + /* + * Replace bit 31 in rs1 with inverse in rs2. + * This formulation retains the nanboxing of rs1. + */ + mask = tcg_const_i64(~MAKE_64BIT_MASK(31, 1)); + tcg_gen_nor_i64(rs2, rs2, mask); + tcg_gen_and_i64(rs1, mask, rs1); + tcg_gen_or_i64(cpu_fpr[a->rd], rs1, rs2); + + tcg_temp_free_i64(mask); + tcg_temp_free_i64(rs2); } - gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]); + tcg_temp_free_i64(rs1); + mark_fs_dirty(ctx); return true; } static bool trans_fsgnjx_s(DisasContext *ctx, arg_fsgnjx_s *a) { + TCGv_i64 rs1, rs2; + REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); + + rs1 = tcg_temp_new_i64(); + gen_check_nanbox_s(rs1, cpu_fpr[a->rs1]); + if (a->rs1 == a->rs2) { /* FABS */ - tcg_gen_andi_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], ~INT32_MIN); + tcg_gen_andi_i64(cpu_fpr[a->rd], rs1, ~MAKE_64BIT_MASK(31, 1)); } else { - TCGv_i64 t0 = tcg_temp_new_i64(); - tcg_gen_andi_i64(t0, cpu_fpr[a->rs2], INT32_MIN); - tcg_gen_xor_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], t0); - tcg_temp_free_i64(t0); + rs2 = tcg_temp_new_i64(); + gen_check_nanbox_s(rs2, cpu_fpr[a->rs2]); + + /* + * Xor bit 31 in rs1 with that in rs2. + * This formulation retains the nanboxing of rs1. + */ + tcg_gen_andi_i64(rs2, rs2, MAKE_64BIT_MASK(31, 1)); + tcg_gen_xor_i64(cpu_fpr[a->rd], rs1, rs2); + + tcg_temp_free_i64(rs2); } - gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]); + tcg_temp_free_i64(rs1); + mark_fs_dirty(ctx); return true; } From patchwork Sat Aug 22 05:40:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 275819 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6FF0CC433E1 for ; Sat, 22 Aug 2020 05:52:40 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3E83A2072D for ; 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d="scan'208";a="145571952" Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 22 Aug 2020 13:51:17 +0800 IronPort-SDR: AtYemhvaVSERlmmINXr2ChaGG2Y5u443iQcEKXkoRa+S9jV9CiDu4COd8Cdrvr/PXEKOIqOqat PZzhVlar+sOA== Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2020 22:38:57 -0700 IronPort-SDR: lRA6W0ftKK0qzQETO7ldNsI5Hjr930OCaj7HnFrRMB+vrdVzlMXnINNrjjrV/Z/BGB5CFMyOdn cReD2wOFSm+w== WDCIronportException: Internal Received: from 5zn13g2.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.59.90]) by uls-op-cesaip02.wdc.com with ESMTP; 21 Aug 2020 22:51:18 -0700 From: Alistair Francis To: qemu-devel@nongnu.org Subject: [PULL v3 06/20] target/riscv: Clean up fmv.w.x Date: Fri, 21 Aug 2020 22:40:47 -0700 Message-Id: <20200822054101.1202175-7-alistair.francis@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200822054101.1202175-1-alistair.francis@wdc.com> References: <20200822054101.1202175-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=49637c5a7=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/22 01:43:18 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Richard Henderson , alistair.francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: LIU Zhiwei Use tcg_gen_extu_tl_i64 to avoid the ifdef. Signed-off-by: LIU Zhiwei Signed-off-by: Richard Henderson Message-Id: <20200626205917.4545-7-zhiwei_liu@c-sky.com> Signed-off-by: Richard Henderson Message-Id: <20200724002807.441147-7-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvf.c.inc | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc index 832f01db6f..138e317723 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -406,11 +406,7 @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a) TCGv t0 = tcg_temp_new(); gen_get_gpr(t0, a->rs1); -#if defined(TARGET_RISCV64) - tcg_gen_mov_i64(cpu_fpr[a->rd], t0); -#else - tcg_gen_extu_i32_i64(cpu_fpr[a->rd], t0); -#endif + tcg_gen_extu_tl_i64(cpu_fpr[a->rd], t0); gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]); mark_fs_dirty(ctx); From patchwork Sat Aug 22 05:40:49 2020 Content-Type: text/plain; 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d="scan'208";a="145571955" Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 22 Aug 2020 13:51:18 +0800 IronPort-SDR: DBTeFb5aZ1dZ10sGhMxokZHHYyf1yLKYaSMmTFFLU+psm7zF6NNImXkypzwVcC9HbxzFI6WXkT buc7cHqRTP6A== Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2020 22:38:57 -0700 IronPort-SDR: QmOrKuM3Yh5wWuatjGpxS+jgjo+gbY/OdfUw+MtU88yTm421Gr1G7CceG8m4L7+QQVpLz8yxYk c1n3WtbWf7cg== WDCIronportException: Internal Received: from 5zn13g2.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.59.90]) by uls-op-cesaip02.wdc.com with ESMTP; 21 Aug 2020 22:51:18 -0700 From: Alistair Francis To: qemu-devel@nongnu.org Subject: [PULL v3 08/20] hw/riscv: sifive_u: Add a dummy L2 cache controller device Date: Fri, 21 Aug 2020 22:40:49 -0700 Message-Id: <20200822054101.1202175-9-alistair.francis@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200822054101.1202175-1-alistair.francis@wdc.com> References: <20200822054101.1202175-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=49637c5a7=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/22 01:43:18 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Bin Meng , alistair.francis@wdc.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng It is enough to simply map the SiFive FU540 L2 cache controller into the MMIO space using create_unimplemented_device(), with an FDT fragment generated, to make the latest upstream U-Boot happy. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Message-Id: <1595227748-24720-1-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis --- include/hw/riscv/sifive_u.h | 4 ++++ hw/riscv/sifive_u.c | 22 ++++++++++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index aba4d0181f..d3c0c00d10 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -71,6 +71,7 @@ enum { SIFIVE_U_DEBUG, SIFIVE_U_MROM, SIFIVE_U_CLINT, + SIFIVE_U_L2CC, SIFIVE_U_L2LIM, SIFIVE_U_PLIC, SIFIVE_U_PRCI, @@ -86,6 +87,9 @@ enum { }; enum { + SIFIVE_U_L2CC_IRQ0 = 1, + SIFIVE_U_L2CC_IRQ1 = 2, + SIFIVE_U_L2CC_IRQ2 = 3, SIFIVE_U_UART0_IRQ = 4, SIFIVE_U_UART1_IRQ = 5, SIFIVE_U_GPIO_IRQ0 = 7, diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index e5682c38a9..55b3383c31 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -72,6 +72,7 @@ static const struct MemmapEntry { [SIFIVE_U_DEBUG] = { 0x0, 0x100 }, [SIFIVE_U_MROM] = { 0x1000, 0xf000 }, [SIFIVE_U_CLINT] = { 0x2000000, 0x10000 }, + [SIFIVE_U_L2CC] = { 0x2010000, 0x1000 }, [SIFIVE_U_L2LIM] = { 0x8000000, 0x2000000 }, [SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 }, [SIFIVE_U_PRCI] = { 0x10000000, 0x1000 }, @@ -302,6 +303,24 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_string(fdt, nodename, "compatible", "gpio-restart"); g_free(nodename); + nodename = g_strdup_printf("/soc/cache-controller@%lx", + (long)memmap[SIFIVE_U_L2CC].base); + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop_cells(fdt, nodename, "reg", + 0x0, memmap[SIFIVE_U_L2CC].base, + 0x0, memmap[SIFIVE_U_L2CC].size); + qemu_fdt_setprop_cells(fdt, nodename, "interrupts", + SIFIVE_U_L2CC_IRQ0, SIFIVE_U_L2CC_IRQ1, SIFIVE_U_L2CC_IRQ2); + qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); + qemu_fdt_setprop(fdt, nodename, "cache-unified", NULL, 0); + qemu_fdt_setprop_cell(fdt, nodename, "cache-size", 2097152); + qemu_fdt_setprop_cell(fdt, nodename, "cache-sets", 1024); + qemu_fdt_setprop_cell(fdt, nodename, "cache-level", 2); + qemu_fdt_setprop_cell(fdt, nodename, "cache-block-size", 64); + qemu_fdt_setprop_string(fdt, nodename, "compatible", + "sifive,fu540-c000-ccache"); + g_free(nodename); + phy_phandle = phandle++; nodename = g_strdup_printf("/soc/ethernet@%lx", (long)memmap[SIFIVE_U_GEM].base); @@ -733,6 +752,9 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp) create_unimplemented_device("riscv.sifive.u.dmc", memmap[SIFIVE_U_DMC].base, memmap[SIFIVE_U_DMC].size); + + create_unimplemented_device("riscv.sifive.u.l2cc", + memmap[SIFIVE_U_L2CC].base, memmap[SIFIVE_U_L2CC].size); } static Property sifive_u_soc_props[] = { From patchwork Sat Aug 22 05:40:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 275812 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 660F7C433E1 for ; Sat, 22 Aug 2020 05:59:50 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3194F2072D for ; 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d="scan'208";a="145571956" Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 22 Aug 2020 13:51:18 +0800 IronPort-SDR: B39CM39cBOnHarEjNiteXQOGpIdp6aJe0SSQUjeUcO5MhVag19EEYYHn/dG/2qcMTiA/xMFYbO qp6MRoZz3EmQ== Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2020 22:38:58 -0700 IronPort-SDR: uXsIukbGmELCtOFEXY8qPU0zC+KIHeS8vcCWs5VKERpCPESo9k+qq7tZufhewIFnHl3D0lY7Dq gzQMLRM4TlnQ== WDCIronportException: Internal Received: from 5zn13g2.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.59.90]) by uls-op-cesaip02.wdc.com with ESMTP; 21 Aug 2020 22:51:18 -0700 From: Alistair Francis To: qemu-devel@nongnu.org Subject: [PULL v3 09/20] riscv: Fix bug in setting pmpcfg CSR for RISCV64 Date: Fri, 21 Aug 2020 22:40:50 -0700 Message-Id: <20200822054101.1202175-10-alistair.francis@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200822054101.1202175-1-alistair.francis@wdc.com> References: <20200822054101.1202175-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=49637c5a7=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/22 01:43:18 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Hou Weiying , alistair23@gmail.com, alistair.francis@wdc.com, Hongzheng-Li , Myriad-Dreamin Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Hou Weiying First, sizeof(target_ulong) equals to 4 on riscv32, so this change does not change the function on riscv32. Second, sizeof(target_ulong) equals to 8 on riscv64, and 'reg_index * 8 + i' is not a legal pmp_index (we will explain later), which should be 'reg_index * 4 + i'. If the parameter reg_index equals to 2 (means that we will change the value of pmpcfg2, or the second pmpcfg on riscv64), then pmpcfg_csr_write(env, 2, val) will map write tasks to pmp_write_cfg(env, 2 * 8 + [0...7], val). However, no cfg csr is indexed by value 16 or 23 on riscv64, so we consider it as a bug. We are looking for constant (e.g., define a new constant named RISCV_WORD_SIZE) in QEMU to help others understand code better, but none was found. A possible good explanation of this literal is it is the minimum word length on riscv is 4 bytes (32 bit). Signed-off-by: Hongzheng-Li Signed-off-by: Hou Weiying Signed-off-by: Myriad-Dreamin Reviewed-by: Alistair Francis Message-Id: Signed-off-by: Alistair Francis --- target/riscv/pmp.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 2a2b9f5363..b14feeb7da 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -320,8 +320,7 @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index, for (i = 0; i < sizeof(target_ulong); i++) { cfg_val = (val >> 8 * i) & 0xff; - pmp_write_cfg(env, (reg_index * sizeof(target_ulong)) + i, - cfg_val); + pmp_write_cfg(env, (reg_index * 4) + i, cfg_val); } } @@ -336,7 +335,7 @@ target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index) target_ulong val = 0; for (i = 0; i < sizeof(target_ulong); i++) { - val = pmp_read_cfg(env, (reg_index * sizeof(target_ulong)) + i); + val = pmp_read_cfg(env, (reg_index * 4) + i); cfg_val |= (val << (i * 8)); } trace_pmpcfg_csr_read(env->mhartid, reg_index, cfg_val); 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envelope-from=prvs=49637c5a7=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/22 01:43:18 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Bin Meng , alistair.francis@wdc.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Now we need to ship the OpenSBI fw_dynamic.elf image for the RISC-V Spike machine, it requires us to create symbolic links for pc-bios/*.elf files. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Message-Id: <1596439832-29238-2-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis --- configure | 1 + 1 file changed, 1 insertion(+) diff --git a/configure b/configure index 4e5fe33211..0a01802637 100755 --- a/configure +++ b/configure @@ -8129,6 +8129,7 @@ LINKS="$LINKS tests/qemu-iotests/check" LINKS="$LINKS python" for bios_file in \ $source_path/pc-bios/*.bin \ + $source_path/pc-bios/*.elf \ $source_path/pc-bios/*.lid \ $source_path/pc-bios/*.rom \ $source_path/pc-bios/*.dtb \ From patchwork Sat Aug 22 05:40:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 275816 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 09FC9C433E1 for ; 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d="scan'208";a="145571960" Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 22 Aug 2020 13:51:19 +0800 IronPort-SDR: 4emVatyYDkERDkie1ytUwhud3KfhWEjAMLmRplI8bc/XIdKDAjyxwtJJcFulBqwH8jBSIf1/xn Sl01BBOOGjxg== Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2020 22:38:58 -0700 IronPort-SDR: 30znCu4Eh1Z73m8ph7tri98M4D+2xY7xpO2qgUeC1NaRkzIA83dL62JAjxcfF9M6tBefxvUP/C HlX1q8gg7RaA== WDCIronportException: Internal Received: from 5zn13g2.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.59.90]) by uls-op-cesaip02.wdc.com with ESMTP; 21 Aug 2020 22:51:19 -0700 From: Alistair Francis To: qemu-devel@nongnu.org Subject: [PULL v3 11/20] roms/opensbi: Upgrade from v0.7 to v0.8 Date: Fri, 21 Aug 2020 22:40:52 -0700 Message-Id: <20200822054101.1202175-12-alistair.francis@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200822054101.1202175-1-alistair.francis@wdc.com> References: <20200822054101.1202175-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=49637c5a7=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/22 01:43:18 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Bin Meng , alistair.francis@wdc.com, Anup Patel Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Upgrade OpenSBI from v0.7 to v0.8. The v0.8 release includes the following commits: 1bb00ab lib: No need to provide default PMP region using platform callbacks a9eac67 include: sbi_platform: Combine reboot and shutdown into one callback 6585fab lib: utils: Add SiFive test device 4781545 platform: Add Nuclei UX600 platform 3a326af scripts: adapt binary archive script for Nuclei UX600 5bdf022 firmware: fw_base: Remove CSR_MTVEC update check e6c1345 lib: utils/serial: Skip baudrate config if input frequency is zero 01a8c8e lib: utils: Improve fdt_parse_uart8250() API 0a0093b lib: utils: Add fdt_parse_uart8250_node() function 243b0d0 lib: utils: Remove redundant clint_ipi_sync() declaration e3ad7c1 lib: utils: Rename fdt_parse_clint() to fdt_parse_compat_addr() a39cd6f lib: utils: Add FDT match table based node lookup dd33b9e lib: utils: Make fdt_get_node_addr_size() public function 66185b3 lib: utils: Add fdt_parse_sifive_uart_node() function 19e966b lib: utils: Add fdt_parse_hart_id() function 44dd7be lib: utils: Add fdt_parse_max_hart_id() API f0eb503 lib: utils: Add fdt_parse_plic_node() function 1ac794c include: Add array_size() macro 8ff2b94 lib: utils: Add simple FDT timer framework 76f0f81 lib: utils: Add simple FDT ipi framework 75322a6 lib: utils: Add simple FDT irqchip framework 76a8940 lib: utils: Add simple FDT serial framework 7cc6fa4 lib: utils: Add simple FDT reset framework 4d06353 firmware: fw_base: Introduce optional fw_platform_init() f1aa9e5 platform: Add generic FDT based platform support 1f21b99 lib: sbi: Print platform hart count at boot time 2ba7087 scripts: Add generic platform to create-binary-archive.sh 4f18c6e platform: generic: Add Sifive FU540 TLB flush range limit override 13717a8 platform: Remove qemu/virt directory 65c06b0 platform: Remove spike directory d626037 docs: Add missing links in platform.md 7993ca2 include: sbi: Remove redundant page table related defines 5338679 lib: sbi_tlb: Fix remote TLB HFENCE VVMA implementation dc38929 lib: sbi: Improve misa_string() implementation 433bac7 docs: platform/generic: Add details about stdout-path DT property b4efa70 docs: platform/generic: Add details about IPI and timer expectations dfd9dd6 docs: Add platform requirements document c2286b6 docs: Fix ordering of pages in table of contents 7be75f5 docs: Don't use italic text in page title 63a513e lib: Rename unprivileged trap handler aef9a60 lib: Add csr detect support 13ca20d lib: Create a separate math helper function file 79d0fad lib: utils: Update reserved memory fdt node even if PMP is not present 6a053f6 lib: Add support for hart specific features b2df751 platform: Move platform features to hart 4938024 platform: fpga: Remove redundant platform specific features ec0d2a7 lib: timer: Provide a hart based timer feature 1f235ec lib: Add platform features in boot time print 22c4334 lib: Add hart features in boot time print 36833ab lib: Optimize inline assembly for unprivilege access functions 38a4b54 firmware: Correct spelling mistakes 28b4052 lib: sbi: detect features before everything else in sbi_hart_init() 4984183 lib: sbi: Improve get_feature_str() implementation and usage 3aa1036 lib: sbi: Remove extra spaces from boot time prints 3a8fc81 lib: sbi: Print platform HART count just before boot HART id 63b0f5f include: sbi: Use scratch pointer as parmeter in HART feature APIs 2966510 lib: sbi: Few cosmetic improvements to HART feature detection a38bea9 lib: sbi_hart: Detect number of supported PMP regions 89ba634 include: sbi: Add firmware extension constants 73d6ef3 lib: utils: Remove redundant parameters from PLIC init functions 446a9c6 lib: utils: Allow PLIC functions to be used for multiple PLICs 2c685c2 lib: utils: Extend fdt_find_match() Implementation d30bb68 lib: utils/irqchip: Initialize all matching irqchip DT nodes a9a9751 lib: utils: Allow CLINT functions to be used for multiple CLINTs 569dd64 lib: utils: Add fdt_parse_clint_node() function 6956e83 lib: utils/ipi: Initialize all matching ipi DT nodes a63f05f lib: utils/timer: Initialize all matching timer DT nodes 30b6040 Makefile: Fix builtin DTB compilation for out-of-tree platforms 64f1408 firmware: fw_base: Make builtin DTB available to fw_platform_init() 4ce6b7a firmware: fw_base: Don't OR forced FW_OPTIONS 86ec534 firmware: Allow fw_platform_init() to return updated FDT location c6c65ee Makefile: Preprocess builtin DTS 4e3876d Makefile: Add mechanism for platforms to have multiple builtin DTBs 72019ee platform: kendryte/k210: Use new mechanism of builtin DTB 51f0e4a firmware: Remove FW_PAYLOAD_FDT and related documentation 1b8c012 lib: Add RISC-V hypervisor v0.6.1 support 79bfd67 docs: Use doxygen config to mark the main page 106b888 docs: Remove redundant documentation about combined payload use case 9802906 platform: Add AE350 platform specific SBI handler 32f87e5 platform: Add AE350 cache control SBIs e2c3f01 lib: Fix __sbi_hfence_gvma_vmid_gpa() and __sbi_hfence_vvma_asid_va() 6966ad0 platform/lib: Allow the OS to map the regions that are protected by PMP 518e85c platform: Update Nuclei ux600 platform support d5725c2 lib: Don't print delegation CSRs if there is no S-Mode 637b348 lib: Fix the SBI_HART_HAS_MCOUNTEREN feature check db56ef3 platform: Add support for Shakti C-class SoC from IIT-M 9bd5f8f lib: sbi: Fix 32/64 bits variable compatibility 2314101 lib: Don't return any invalid error from SBI ecall a98258d include: Bump-up version to 0.8 Signed-off-by: Bin Meng Reviewed-by: Anup Patel Reviewed-by: Alistair Francis Message-Id: <1596439832-29238-3-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis --- roms/opensbi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/roms/opensbi b/roms/opensbi index 9f1b72ce66..a98258d0b5 160000 --- a/roms/opensbi +++ b/roms/opensbi @@ -1 +1 @@ -Subproject commit 9f1b72ce66d659e91013b358939e832fb27223f5 +Subproject commit a98258d0b537a295f517bbc8d813007336731fa9 From patchwork Sat Aug 22 05:40:53 2020 Content-Type: text/plain; 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21 Aug 2020 22:40:53 -0700 Message-Id: <20200822054101.1202175-13-alistair.francis@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200822054101.1202175-1-alistair.francis@wdc.com> References: <20200822054101.1202175-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=49637c5a7=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/22 01:43:18 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Bin Meng , alistair.francis@wdc.com, Anup Patel Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng The RISC-V generic platform is a flattened device tree (FDT) based platform where all platform specific functionality is provided based on FDT passed by previous booting stage. The support was added in the upstream OpenSBI v0.8 release recently. Update our Makefile to build the generic platform instead of building virt and sifive_u separately for RISC-V OpenSBI firmware, and change to use fw_dynamic type images as well. Signed-off-by: Bin Meng Reviewed-by: Anup Patel Reviewed-by: Alistair Francis Message-Id: <1596439832-29238-4-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis --- roms/Makefile | 32 ++++++++++---------------------- 1 file changed, 10 insertions(+), 22 deletions(-) diff --git a/roms/Makefile b/roms/Makefile index f9acf39954..5d9f15b677 100644 --- a/roms/Makefile +++ b/roms/Makefile @@ -64,10 +64,8 @@ default help: @echo " u-boot.e500 -- update u-boot.e500" @echo " u-boot.sam460 -- update u-boot.sam460" @echo " efi -- update UEFI (edk2) platform firmware" - @echo " opensbi32-virt -- update OpenSBI for 32-bit virt machine" - @echo " opensbi64-virt -- update OpenSBI for 64-bit virt machine" - @echo " opensbi32-sifive_u -- update OpenSBI for 32-bit sifive_u machine" - @echo " opensbi64-sifive_u -- update OpenSBI for 64-bit sifive_u machine" + @echo " opensbi32-generic -- update OpenSBI for 32-bit generic machine" + @echo " opensbi64-generic -- update OpenSBI for 64-bit generic machine" @echo " bios-microvm -- update bios-microvm.bin (qboot)" @echo " clean -- delete the files generated by the previous" \ "build targets" @@ -170,29 +168,19 @@ skiboot: efi: edk2-basetools $(MAKE) -f Makefile.edk2 -opensbi32-virt: +opensbi32-generic: $(MAKE) -C opensbi \ CROSS_COMPILE=$(riscv32_cross_prefix) \ - PLATFORM="qemu/virt" - cp opensbi/build/platform/qemu/virt/firmware/fw_jump.bin ../pc-bios/opensbi-riscv32-virt-fw_jump.bin + PLATFORM="generic" + cp opensbi/build/platform/generic/firmware/fw_dynamic.bin ../pc-bios/opensbi-riscv32-generic-fw_dynamic.bin + cp opensbi/build/platform/generic/firmware/fw_dynamic.elf ../pc-bios/opensbi-riscv32-generic-fw_dynamic.elf -opensbi64-virt: +opensbi64-generic: $(MAKE) -C opensbi \ CROSS_COMPILE=$(riscv64_cross_prefix) \ - PLATFORM="qemu/virt" - cp opensbi/build/platform/qemu/virt/firmware/fw_jump.bin ../pc-bios/opensbi-riscv64-virt-fw_jump.bin - -opensbi32-sifive_u: - $(MAKE) -C opensbi \ - CROSS_COMPILE=$(riscv32_cross_prefix) \ - PLATFORM="sifive/fu540" - cp opensbi/build/platform/sifive/fu540/firmware/fw_jump.bin ../pc-bios/opensbi-riscv32-sifive_u-fw_jump.bin - -opensbi64-sifive_u: - $(MAKE) -C opensbi \ - CROSS_COMPILE=$(riscv64_cross_prefix) \ - PLATFORM="sifive/fu540" - cp opensbi/build/platform/sifive/fu540/firmware/fw_jump.bin ../pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin + PLATFORM="generic" + cp opensbi/build/platform/generic/firmware/fw_dynamic.bin ../pc-bios/opensbi-riscv64-generic-fw_dynamic.bin + cp opensbi/build/platform/generic/firmware/fw_dynamic.elf ../pc-bios/opensbi-riscv64-generic-fw_dynamic.elf bios-microvm: $(MAKE) -C qboot From patchwork Sat Aug 22 05:40:59 2020 Content-Type: text/plain; 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21 Aug 2020 22:39:01 -0700 IronPort-SDR: IoS6dcUFN3THfHjyK5PNkf31OMCcmwPHg5TAtGnYmlGDEqJZ+sqHeERpwz4s/3kQKQu3nwMDkb GZR41Eg3xf9A== WDCIronportException: Internal Received: from 5zn13g2.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.59.90]) by uls-op-cesaip02.wdc.com with ESMTP; 21 Aug 2020 22:51:22 -0700 From: Alistair Francis To: qemu-devel@nongnu.org Subject: [PULL v3 18/20] hw/intc: ibex_plic: Update the pending irqs Date: Fri, 21 Aug 2020 22:40:59 -0700 Message-Id: <20200822054101.1202175-19-alistair.francis@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200822054101.1202175-1-alistair.francis@wdc.com> References: <20200822054101.1202175-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=49637c5a7=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/22 01:43:18 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, alistair.francis@wdc.com, =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Jessica Clarke Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" After a claim or a priority change we need to update the pending interrupts. This is based on the same patch for the SiFive PLIC: 55765822804f5a58594e "riscv: plic: Add a couple of mising sifive_plic_update calls" Signed-off-by: Alistair Francis Cc: Jessica Clarke Reviewed-by: Philippe Mathieu-Daudé Message-Id: <0693aa700a4c67c49b3f1c973a82b257fdb7198d.1595655188.git.alistair.francis@wdc.com> --- hw/intc/ibex_plic.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c index 41079518c6..578edd2ce0 100644 --- a/hw/intc/ibex_plic.c +++ b/hw/intc/ibex_plic.c @@ -121,6 +121,9 @@ static uint64_t ibex_plic_read(void *opaque, hwaddr addr, s->pending[pending_num] &= ~(1 << (s->claim % 32)); ret = s->claim; + + /* Update the interrupt status after the claim */ + ibex_plic_update(s); } return ret; @@ -140,6 +143,7 @@ static void ibex_plic_write(void *opaque, hwaddr addr, } else if (addr_between(addr, s->priority_base, s->priority_num)) { uint32_t irq = ((addr - s->priority_base) >> 2) + 1; s->priority[irq] = value & 7; + ibex_plic_update(s); } else if (addr_between(addr, s->enable_base, s->enable_num)) { uint32_t enable_reg = (addr - s->enable_base) / 4; From patchwork Sat Aug 22 05:41:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 275810 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B045AC433DF for ; Sat, 22 Aug 2020 06:07:49 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 78EEC20724 for ; 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d="scan'208";a="145571974" Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 22 Aug 2020 13:51:22 +0800 IronPort-SDR: WVNir2vDJfZ46vmOCLJm3kbqlNFEjxbs+0cyL6C7ncPGd5TQJU3yYGgKamMKX8LLU/Q5nk3Xo/ dm27UZpU+isA== Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2020 22:39:01 -0700 IronPort-SDR: WGgeG07KdrQzkSXAeXTh6tiRoFOmkgbyYBMXoJeVJuwMXhl4FYliEJK7s0eRzvQYWg5AZulH1H ec0is5U0QkFg== WDCIronportException: Internal Received: from 5zn13g2.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.59.90]) by uls-op-cesaip02.wdc.com with ESMTP; 21 Aug 2020 22:51:22 -0700 From: Alistair Francis To: qemu-devel@nongnu.org Subject: [PULL v3 20/20] hw/intc: ibex_plic: Honour source priorities Date: Fri, 21 Aug 2020 22:41:01 -0700 Message-Id: <20200822054101.1202175-21-alistair.francis@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200822054101.1202175-1-alistair.francis@wdc.com> References: <20200822054101.1202175-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=49637c5a7=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/22 01:43:18 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, alistair.francis@wdc.com, =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Jessica Clarke Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This patch follows what commit aa4d30f6618dc "riscv: plic: Honour source priorities" does and ensures that the highest priority interrupt will be serviced first. Signed-off-by: Alistair Francis Cc: Jessica Clarke Reviewed-by: Philippe Mathieu-Daudé Message-Id: --- hw/intc/ibex_plic.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c index 669247ef08..f49fa67c91 100644 --- a/hw/intc/ibex_plic.c +++ b/hw/intc/ibex_plic.c @@ -57,6 +57,8 @@ static void ibex_plic_irqs_set_pending(IbexPlicState *s, int irq, bool level) static bool ibex_plic_irqs_pending(IbexPlicState *s, uint32_t context) { int i; + uint32_t max_irq = 0; + uint32_t max_prio = s->threshold; for (i = 0; i < s->pending_num; i++) { uint32_t irq_num = ctz64(s->pending[i]) + (i * 32); @@ -66,14 +68,17 @@ static bool ibex_plic_irqs_pending(IbexPlicState *s, uint32_t context) continue; } - if (s->priority[irq_num] > s->threshold) { - if (!s->claim) { - s->claim = irq_num; - } - return true; + if (s->priority[irq_num] > max_prio) { + max_irq = irq_num; + max_prio = s->priority[irq_num]; } } + if (max_irq) { + s->claim = max_irq; + return true; + } + return false; }