From patchwork Tue Sep 8 07:57:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 249282 Delivered-To: patch@linaro.org Received: by 2002:a92:5b9c:0:0:0:0:0 with SMTP id c28csp4330892ilg; Tue, 8 Sep 2020 01:04:58 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxOBnGPrJq46evc9G1UQFT1gsqLikRuqBdkN0W8/Wdk2u07/jIHZ0PVSY2Tl1FaBM2e04rQ X-Received: by 2002:a17:907:70cb:: with SMTP id yk11mr24186875ejb.312.1599552298191; Tue, 08 Sep 2020 01:04:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1599552298; cv=none; d=google.com; s=arc-20160816; b=fQE+u35C8tZ23RG360yWCxpEvm9Uw2EYNzY3a25c5SDqzv9CGQoM43cXrrRrdG37P0 45ycaXmq56+kKgHP/c/SbTBKtiDsX0z7kal0kSx/p/5Ubyn0W1NngVM4AAGOTpp6Cq63 rSlp4Ne7oA6JJnqPQhCcVspo7Jv/5C8X7IVxesMJltFgcji1NbCZMLimA3sL8hH6fJGc ECY+LlPadBna9c59gyl4/PS3YhizCH5vEpdENM4U6QHbAKKOOheoUmNLMHa2mLhhq3aA HzsriMi2Vzy+7ajtRnnQSwri+/1/Lt6AVJWDshkhPV8froy90c6CjVjkfgF2MOr9s7GT ruIA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=cDupOEGD43zOafkeHwpXvRZFRBLRl6C9wgjA2f07/F0=; b=04xKnKuPgGEz07KhLHOB3brqXRwJVXkzxMLelltc5X0khtscSEePFllWQiMO+1WM6x A1iHG0t4B/fwaNrs/HTQSsAVVkJyG8bX6Q5w5Atza4BLYyRNyb9o74661MnrgVvWv5rr aWt+kBsLMyuKTMc7ME2LRdH7DQXlnBbIyaxv/m0Rirzk16BPYRCR+EJeIeD9h9y+xZ55 O8Q8JGZSBiKhyYTuS/pQv0EM2bG9KRanD26QDR9njBYiTq66D1e5C1vjDlJNkOgIqfi3 NGepy7yI+UH7eB5vrZrtZWKj/N6Hvcy+Ox6PvXT3uE4mqDhgYA0ZvHkmGqrju2yNhcOc V69Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QQYLtPYQ; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id ec7si11269923ejb.359.2020.09.08.01.04.58; Tue, 08 Sep 2020 01:04:58 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QQYLtPYQ; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729670AbgIHIEp (ORCPT + 6 others); Tue, 8 Sep 2020 04:04:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36366 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729950AbgIHH5x (ORCPT ); Tue, 8 Sep 2020 03:57:53 -0400 Received: from mail-pg1-x541.google.com (mail-pg1-x541.google.com [IPv6:2607:f8b0:4864:20::541]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 46CD0C061757 for ; Tue, 8 Sep 2020 00:57:51 -0700 (PDT) Received: by mail-pg1-x541.google.com with SMTP id l191so9480482pgd.5 for ; Tue, 08 Sep 2020 00:57:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=cDupOEGD43zOafkeHwpXvRZFRBLRl6C9wgjA2f07/F0=; b=QQYLtPYQds66Aq5sAInDKeb1drvHJt9XVWKwoRjvuCeNkRGx5+rFQiX+dSbfnvmPUQ +EdJT883lIKsSbWKYABvFjZ5eK7DhOsF540AZTY3Lh/sCCiSuQ5sE9f71hfSjND1BrYb /fRUds+4A7kgOKaPGN6xeDdnBeDpzTIyfwwEuN19BFcyhxX492wBYzXnibWeszqb+k/M xNi0n0FYMAm/2j9zF4nudmkX9Ae3RxGQgX62hcWZScGUwk3kY39muYL1NykdmwhEU0cM gPvxnLyYSeo9NrzD5eMpuSoYDDRkruY7GDkUxtEyfX7IthGRRkpmCCbiufQhWithfewm briw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=cDupOEGD43zOafkeHwpXvRZFRBLRl6C9wgjA2f07/F0=; b=lq1roUmMdNdOb+YtXqVK47KUdE7uMuzYHmSl6PRSiwl+AiV88HiRU1bBOCal8Hy0nB kOVtScun+CbCAs8Zf7iIcRHj7h8S/nuH93pmahZ+2BBP6caFKU6R+iFXjSfwokboy/7H X3zFBsiU0SKEAkhsJYXbOr57MhIAXWZNdgge8LVDRi4ria1/Kge5QT6QsraUkL6wB2D+ aWK2wqkG43x0e2dRSLybZkBYhU7T2aSNMPWmNKCKVQn42Eov2DH8Ih94Zu9SMyFDnTNw 0D9CVYyWbbTeWNsR+NiaS01uXJavw/vesmsb3leh7nLPGaQkcdi/q/UwVU4v0wVodqcC WMCQ== X-Gm-Message-State: AOAM531nJlAwwe92w+DdFwTLLN50yXknBvK1PpewqHifS8g9AustkqVX fzg5HEggQuXv7FsIm7yEvUMJ X-Received: by 2002:a63:9d82:: with SMTP id i124mr19186323pgd.336.1599551870736; Tue, 08 Sep 2020 00:57:50 -0700 (PDT) Received: from localhost.localdomain ([103.59.133.81]) by smtp.googlemail.com with ESMTPSA id m21sm7560154pfo.13.2020.09.08.00.57.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Sep 2020 00:57:50 -0700 (PDT) From: Manivannan Sadhasivam To: rjw@rjwysocki.net, viresh.kumar@linaro.org, robh+dt@kernel.org, agross@kernel.org, bjorn.andersson@linaro.org Cc: amitk@kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dmitry.baryshkov@linaro.org, tdas@codeaurora.org, Manivannan Sadhasivam Subject: [PATCH 5/7] cpufreq: qcom-hw: Use regmap for accessing hardware registers Date: Tue, 8 Sep 2020 13:27:14 +0530 Message-Id: <20200908075716.30357-6-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200908075716.30357-1-manivannan.sadhasivam@linaro.org> References: <20200908075716.30357-1-manivannan.sadhasivam@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Use regmap for accessing cpufreq registers in hardware. Signed-off-by: Manivannan Sadhasivam --- drivers/cpufreq/qcom-cpufreq-hw.c | 55 ++++++++++++++++++++++++++----- 1 file changed, 47 insertions(+), 8 deletions(-) -- 2.17.1 diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c index 41853db7c9b8..de816bcafd33 100644 --- a/drivers/cpufreq/qcom-cpufreq-hw.c +++ b/drivers/cpufreq/qcom-cpufreq-hw.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #define LUT_MAX_ENTRIES 40U @@ -32,6 +33,7 @@ struct qcom_cpufreq_soc_data { struct qcom_cpufreq_data { void __iomem *base; + struct regmap *regmap; const struct qcom_cpufreq_soc_data *soc_data; }; @@ -85,8 +87,11 @@ static int qcom_cpufreq_hw_target_index(struct cpufreq_policy *policy, struct qcom_cpufreq_data *data = policy->driver_data; const struct qcom_cpufreq_soc_data *soc_data = data->soc_data; unsigned long freq = policy->freq_table[index].frequency; + int ret; - writel_relaxed(index, data->base + soc_data->reg_perf_state); + ret = regmap_write(data->regmap, soc_data->reg_perf_state, index); + if (ret) + return ret; if (icc_scaling_enabled) qcom_cpufreq_set_bw(policy, freq); @@ -102,6 +107,7 @@ static unsigned int qcom_cpufreq_hw_get(unsigned int cpu) const struct qcom_cpufreq_soc_data *soc_data; struct cpufreq_policy *policy; unsigned int index; + int ret; policy = cpufreq_cpu_get_raw(cpu); if (!policy) @@ -110,7 +116,10 @@ static unsigned int qcom_cpufreq_hw_get(unsigned int cpu) data = policy->driver_data; soc_data = data->soc_data; - index = readl_relaxed(data->base + soc_data->reg_perf_state); + ret = regmap_read(data->regmap, soc_data->reg_perf_state, &index); + if (ret) + return 0; + index = min(index, LUT_MAX_ENTRIES - 1); return policy->freq_table[index].frequency; @@ -123,9 +132,12 @@ static unsigned int qcom_cpufreq_hw_fast_switch(struct cpufreq_policy *policy, const struct qcom_cpufreq_soc_data *soc_data = data->soc_data; unsigned int index; unsigned long freq; + int ret; index = policy->cached_resolved_idx; - writel_relaxed(index, data->base + soc_data->reg_perf_state); + ret = regmap_write(data->regmap, soc_data->reg_perf_state, index); + if (ret) + return 0; freq = policy->freq_table[index].frequency; arch_set_freq_scale(policy->related_cpus, freq, @@ -171,14 +183,24 @@ static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev, } for (i = 0; i < LUT_MAX_ENTRIES; i++) { - data = readl_relaxed(drv_data->base + soc_data->reg_freq_lut + - i * soc_data->lut_row_size); + ret = regmap_read(drv_data->regmap, soc_data->reg_freq_lut + + i * soc_data->lut_row_size, &data); + if (ret) { + kfree(table); + return ret; + } + src = FIELD_GET(LUT_SRC, data); lval = FIELD_GET(LUT_L_VAL, data); core_count = FIELD_GET(LUT_CORE_COUNT, data); - data = readl_relaxed(drv_data->base + soc_data->reg_volt_lut + - i * soc_data->lut_row_size); + ret = regmap_read(drv_data->regmap, soc_data->reg_volt_lut + + i * soc_data->lut_row_size, &data); + if (ret) { + kfree(table); + return ret; + } + volt = FIELD_GET(LUT_VOLT, data) * 1000; if (src) @@ -248,6 +270,13 @@ static void qcom_get_related_cpus(int index, struct cpumask *m) } } +static struct regmap_config qcom_cpufreq_regmap = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .fast_io = true, +}; + static const struct qcom_cpufreq_soc_data qcom_soc_data = { .reg_enable = 0x0, .reg_freq_lut = 0x110, @@ -274,6 +303,7 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) struct qcom_cpufreq_data *data; const struct of_device_id *match; int ret, index; + u32 val; cpu_dev = get_cpu_device(policy->cpu); if (!cpu_dev) { @@ -316,9 +346,18 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) data->soc_data = match->data; data->base = base; + data->regmap = devm_regmap_init_mmio(dev, base, &qcom_cpufreq_regmap); + if (IS_ERR(data->regmap)) { + ret = PTR_ERR(data->regmap); + goto error; + } /* HW should be in enabled state to proceed */ - if (!(readl_relaxed(base + data->soc_data->reg_enable) & 0x1)) { + ret = regmap_read(data->regmap, data->soc_data->reg_enable, &val); + if (ret) + goto error; + + if (!(val & 0x1)) { dev_err(dev, "Domain-%d cpufreq hardware not enabled\n", index); ret = -ENODEV; goto error; From patchwork Tue Sep 8 07:57:15 2020 Content-Type: text/plain; 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Hence, add support for it in the driver with relevant of_match data. Signed-off-by: Manivannan Sadhasivam --- drivers/cpufreq/qcom-cpufreq-hw.c | 9 +++++++++ 1 file changed, 9 insertions(+) -- 2.17.1 diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c index de816bcafd33..c3c397cc3dc6 100644 --- a/drivers/cpufreq/qcom-cpufreq-hw.c +++ b/drivers/cpufreq/qcom-cpufreq-hw.c @@ -285,8 +285,17 @@ static const struct qcom_cpufreq_soc_data qcom_soc_data = { .lut_row_size = 32, }; +static const struct qcom_cpufreq_soc_data sm8250_soc_data = { + .reg_enable = 0x0, + .reg_freq_lut = 0x100, + .reg_volt_lut = 0x200, + .reg_perf_state = 0x320, + .lut_row_size = 4, +}; + static const struct of_device_id qcom_cpufreq_hw_match[] = { { .compatible = "qcom,cpufreq-hw", .data = &qcom_soc_data }, + { .compatible = "qcom,sm8250-epss", .data = &sm8250_soc_data }, {} }; MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match);